Circuit for detecting a single-bit flip in the generation of an internal clock for a memory

Abstract

Embodiments of the present disclosure relate to a circuit for detecting a single-bit flip in the generation of an internal clock for a memory. A fault determination circuit includes a latch circuit that receives an internal clock from a clock latch, the internal clock rising in response to a rising external clock. In response to a rising edge of the external clock, the circuit generates a rising edge of a fault flag. If a rising edge of the internal clock occurs, then in response to the rising edge of the internal clock, the fault flag falls. Then, the fault flag is latched. If the clock latch is in an active mode, then if a falling edge of the fault flag is not generated before latching, the latched fault flag indicates a single-bit flip in the clock latch, and if the clock latch is in an inactive mode, then if a falling edge of the fault flag is generated before latching, the latched fault flag indicates a single-bit flip in the clock latch.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 735,489, filed on September 24, 2018, the content of which is incorporated by reference to the maximum extent permitted by law. Technical Field

[0003] This application relates to the field of memory cells, and more particularly, to a circuit for detecting single-bit flips in a latch that generates an internal clock for self-timed memory cells. Background Art

[0004] Latches are used for a variety of functions in digital systems. Figure 1 A typical latch 1 is shown, and the latch 1 consists of a first tri-state inverter 2, an inverter 3, and a second tri-state inverter 4. The tri-state inverter 2 receives the input signal IN of the latch and is enabled by the clock signal CK. The inverter 3 is coupled to the output of the tri-state inverter 2 and generates the output OUT of the latch. The tri-state inverter 4 is coupled to the inverter 3 in a positive feedback arrangement and is enabled by the clock inverted signal CKB (the inversion of the clock signal CK).

[0005] When the clock signal CK is at a logic high level, the tri-state inverter 4 is disabled, and the tri-state inverter 2 is enabled, and the logic level is inverted at the input IN. Then, this logic level is returned to its initial state at the output OUT by the inverter 3. When the clock signal CK returns to a logic low level, the tri-state driver 2 is disabled, and the tri-state driver 4 is enabled. Due to the feedback loop of the inverter 3 and the tri-state inverter 4, this latches the input IN to the output OUT, thus effectively storing the logic level (bit) from the input IN until the clock signal CK returns to a logic high level.

[0006] If the latch 1 is hit by radiation, the stored single data bit can be inverted. This error can be referred to as a single-bit flip (SBU).

[0007] In a self-timed memory, in response to detecting a rising edge of an external clock signal, an internal clock signal is generated and latched until the memory completes a successful operation and generates a logic high internal reset signal.

[0008] Figure 2An example clock latch 5 for a memory is shown, and the clock latch 5 is composed of a NAND gate 6 and a tri-state inverter 7. The NAND gate 6 receives feedback as an input from its output (after being inverted by the tri-state inverter 7), as well as a reset signal RESET and a clock signal CK as inputs. The tri-state inverter 7 is coupled to the NAND gate 6 in a positive feedback arrangement and is enabled by a clock inverted signal CKB. The feedback arrangement and the NAND logic produce a set and auto-reset behavior, where an internal clock inverted signal INTCKB (the inversion of the internal clock signal INTCK) is generated at the output of the NAND gate 6.

[0009] During the operation of this clock latch 5, the occurrence of a single-bit flip error is particularly undesirable. Now, with additional reference to Figure 3 a discussion of this potential single-bit flip is presented.

[0010] A single-bit flip may occur during an active period (where the memory is enabled and the clock latch is to generate an internal clock signal INTCK in response to an external clock signal CK), as shown in the following cases: The rising edge of the clock signal CK pulse 10 and the auto-reset behavior appropriately generate an internal clock signal INTCK pulse 14, but due to a radiation strike, another internal clock signal INTCK pulse 15 is spuriously generated. Another example of a single-bit flip during the active period may occur when the rising edge of the clock signal CK pulse 12 starts to generate an internal clock signal INTCK pulse 17, but the pulse quickly drops to a logic low level without reaching a logic high level, resulting in a missing readable internal clock signal INTCK pulse. Another example of a single-bit flip during the active period may occur when the rising edge of the clock signal CK pulse 13 starts to generate an internal clock signal INTCK pulse 18, where the pulse reaches a logic high level but prematurely returns to a logic low level due to an inappropriate rise of the reset signal RESET.

[0011] These single-bit flips during the active period may cause read / write failures or spurious operations to be performed. Single-bit flips may also occur during an inactive period (where the memory is not enabled), as shown in the following case: The rising edge of the clock signal CK pulse 11 causes a spurious generation of an internal clock signal INTCK16 pulse.

[0012] These single-bit flips may cause damage to the memory itself and the data stored in the memory. Therefore, it is desirable to be able to detect such single-bit flips so that protective and corrective measures can be taken. Summary of the Invention

[0013] The first embodiment disclosed in this document is a fault determination circuit. The fault determination circuit includes a master-slave latch device, which in the active mode is configured to: receive an internal clock signal from a clock latch, the internal clock signal being intended to rise in response to the rising edge of an external clock signal; generate a rising edge of a fault flag signal in response to the rising edge of the external clock signal; if the rising edge of the internal clock signal occurs, generate a falling edge of the fault flag signal in response to the rising edge of the internal clock signal; and latch the fault flag signal in response to the falling edge of the internal clock signal. If the falling edge of the fault flag signal is not generated before latching, the latched fault signal indicates a single-bit flip in the clock latch.

[0014] The master-slave latch device in the inactive mode is configured to: generate a rising edge of the fault flag signal in response to the rising edge of the external clock signal; if the rising edge of the internal clock signal occurs, generate a falling edge of the fault flag signal in response to the rising edge of the internal clock signal; and if the rising edge of the internal clock signal occurs, latch the fault flag signal in response to the falling edge of the internal clock signal. If the falling edge of the fault flag signal is generated before latching, the latched fault signal indicates a single-bit flip in the clock latch.

[0015] The master-slave latch device includes a first latch having a first input receiving the inverted external clock signal, a second input receiving the internal clock signal, and an output; an inverter coupled to the output of the first latch; and a second latch having a non-inverted enable terminal receiving a signal based on the inverted external clock signal and the inverted output of the first latch, an inverted enable terminal receiving a signal based on the internal clock signal, an input coupled to receive the output from the inverter, and an output.

[0016] The first latch is composed of NOR logic, while the second latch is composed of NOT logic.

[0017] The second latch includes a first tri-state inverter having an inverted enable terminal receiving the inverted external clock signal, a non-inverted enable terminal receiving the internal clock signal, and an input coupled to receive the output from the inverter; a first inverter having an input coupled to the output of the first tri-state inverter; and a second tri-state inverter having an enable terminal, a non-inverted enable terminal, an input coupled to the output of the first inverter, and an output coupled to the input of the first inverter.

[0018] The second latch includes a PMOS transistor having a source coupled to a power supply node, a drain coupled to an inverting enable terminal of a second tri-state inverter, and a gate coupled to an internal clock signal; a first NMOS transistor having a drain coupled to a non-inverting enable terminal of the second tri-state inverter, a source coupled to ground, and a gate coupled to receive an output from an inverter that receives an output of the first latch; a second NMOS transistor having a drain coupled to the non-inverting enable terminal of the second tri-state inverter, a source coupled to ground, and a gate coupled to an inverted external clock signal; and an inverter that receives an input from the first inverter and generates a fault flag signal at its output.

[0019] A second embodiment relates to a fault determination circuit that detects a single bit flip in a clock latch. The clock latch receives an external clock signal and generates an internal clock signal therefrom. The fault determination circuit includes a first latch configured to generate a first signal of a logic high level when the internal clock signal is at a logic low level and the external clock signal is at a logic high level, and to generate a first signal of a logic low level when the internal clock signal is at a logic high level and the external clock signal is at a logic high level; a second latch configured to generate a fault flag signal of a logic high level when the first signal is at a logic high level, to generate a fault flag signal of a logic low level when the first signal is at a logic low level, and to latch when the internal clock signal is at a logic low level. A single bit flip in the clock latch is indicated by the fault flag signal being at a logic high level when latching the second latch and the clock latch being in an active mode. A single bit flip in the clock latch is indicated by the fault flag signal being at a logic low level when latching the second latch and the clock latch being in an inactive mode.

[0020] The second latch includes a first tri-state inverter having an inverted inverter enable terminal receiving an external clock signal, a non-inverted enable terminal receiving an internal clock signal, and an input coupled to receive an inverted version of a first signal; a first inverter having an input coupled to the output of the first tri-state inverter; a second tri-state inverter having an inverter enable terminal, a non-inverted enable terminal, an input coupled to the output of the first inverter, and an output coupled to the input of the first inverter; a PMOS transistor having a source coupled to a power supply node, a drain coupled to the inverter enable terminal of the second tri-state inverter, and a gate coupled to the internal clock signal; a first NMOS transistor having a drain coupled to the non-inverted enable terminal of the second tri-state inverter, a source coupled to ground, and a gate coupled to receive an output from an inverter that receives an output of the first latch; a second NMOS transistor having a drain coupled to the non-inverted enable terminal of the second tri-state inverter, a source coupled to ground, and a gate coupled to an inverted external clock signal; and an inverter receiving an input from the first inverter and generating a fault flag signal at its output.

[0021] The first latch includes a first NOR gate and a second NOR gate. The first NOR gate has an input coupled to an inverted external clock signal and an output of the second NOR gate, and an output. The second NOR gate has an input coupled to the internal clock signal and an output of the first NOR gate, and an output. A third inverter is coupled to receive an input from the output of the second NOR gate and provides an output to the second latch.

[0022] A third embodiment relates to a fault determination circuit that detects a single bit flip in a clock latch. The clock latch receives an external clock signal and generates an internal clock signal therefrom. The fault determination circuit includes an SR latch having a set input receiving an inverted external clock signal, a reset input receiving the internal clock signal, and an output; an inverter coupled to the output of the SR latch; and a static latch having an inverter enable terminal receiving an inverted signal based on an inverted external clock signal and an output of the SR latch, a non-inverted enable terminal receiving a signal based on the internal clock signal, an input coupled to receive an output from the inverter, and an output.

[0023] The inverter receives an input from the output of the static latch and generates a fault flag signal as an output. The fault flag signal is at a logic high level when the static latch is latched and the clock latch is in an active mode, indicating the presence of a single bit flip in the clock latch, and the fault flag signal is at a logic low level when the static latch is latched and the clock latch is in an inactive mode, indicating the presence of a single bit flip in the clock latch.

[0024] The SR latch is composed of NOR logic, while the static latch is composed of NOT logic.

[0025] The fourth embodiment relates to an electronic device having a first latch that receives, as an input, the inversion of an internal clock signal for a memory and an external clock signal, the internal clock signal being generated from the external clock signal; a first inverter having an input coupled to the output of the first latch; and a second latch. The second latch includes: a first tri-state inverter having an inverting enable terminal that receives the inversion of the external clock signal, a non-inverting enable terminal that receives the non-inverted internal clock signal, and an input coupled to the output of the first inverter; a second inverter having an input coupled to the output of the first tri-state inverter; a second tri-state inverter having an input coupled to the output of the second inverter and an output coupled to the input of the second inverter; a PMOS transistor having a source coupled to a power supply node, a drain coupled to the inverting enable terminal of the second tri-state inverter, and a gate coupled to the internal clock signal; a first NMOS transistor having a drain coupled to the non-inverting enable terminal of the second tri-state inverter, a source coupled to ground, and a gate coupled to the output of the first inverter; and a second NMOS transistor having a drain coupled to the non-inverting enable terminal of the second tri-state inverter, a source coupled to ground, and a gate coupled to the inversion of the external clock signal. A third inverter has an input coupled to the output of the second inverter and an output for the circuit.

[0026] The first latch includes a first NOR gate and a second NOR gate. The first NOR gate has an input coupled to the inversion of the external clock signal and the output of the second NOR gate, and an output. The second NOR gate has an input coupled to the internal clock signal and the output of the first NOR gate, and an output coupled to the input of the first inverter.

[0027] The second tri-state inverter has an inverting enable terminal coupled to a second node and a non-inverting enable terminal coupled to a first node.

[0028] The second latch further includes a first PMOS transistor having a source coupled to a power supply node, a drain coupled to the second node, and a gate coupled to receive the internal clock signal; a first NMOS transistor having a drain coupled to the first node, a source coupled to ground, and a gate coupled to the output of the first inverter; and a second NMOS transistor having a drain coupled to the first node, a source coupled to ground, and a gate coupled to receive the inversion of the external clock signal.

[0029] The fifth embodiment relates to a method for determining the presence of a single bit flip in a clock latch. The method includes: receiving a next rising edge of an external clock signal at the clock latch. In response to the rising edge of the external clock signal, the method includes: when the clock latch is in an active mode, aiming to generate a rising edge of an internal clock signal (and when the clock latch is in an inactive mode, not aiming to generate a rising edge of the internal clock signal), and generating a rising edge of a fault flag signal. If a rising edge of the internal clock signal occurs, in response to the rising edge of the internal clock signal, a falling edge of the fault flag signal is generated. The fault flag signal is latched. If the clock latch is in an active mode, if the falling edge of the fault flag signal is not generated before latching, the latched fault signal indicates a single bit flip in the clock latch. If the clock latch is in an inactive mode, if the falling edge of the fault flag signal is generated before latching, the latched fault signal indicates a single bit flip in the clock latch.

[0030] A circuit is also disclosed herein, having a first latch that receives, as an input, an inverted internal clock signal for a memory and an inverted external clock signal, the internal clock signal being generated from the external clock signal. A first inverter having an input coupled to the output of the first latch. A second latch including a first tri-state inverter having an inverting enable terminal receiving the inverted external clock signal, a non-inverting enable terminal receiving the non-inverted internal clock signal, and an input coupled to the output of the first inverter; a second inverter having an input coupled to the output of the first tri-state inverter; a second tri-state inverter having an input coupled to the output of the second inverter and an output coupled to the input of the second inverter; a first transistor having a first conductive terminal coupled to a power supply node, a second conductive terminal coupled to the inverting enable terminal of the second tri-state inverter, and a control terminal coupled to the internal clock signal; a second transistor having a first conductive terminal coupled to the non-inverting enable terminal of the second tri-state inverter, a second conductive terminal coupled to ground, and a control terminal coupled to the output of the first inverter; and a third transistor having a first conductive terminal coupled to the non-inverting enable terminal of the second tri-state inverter, a second conductive terminal coupled to ground, and a control terminal coupled to the inverted external clock signal.

[0031] The first latch may include a first logic gate and a second logic gate, the first logic gate having an input coupled to the inverted external clock signal and the output of the second logic gate, and an output. The second logic gate may have an input coupled to the internal clock signal and the output of the first logic gate, and an output coupled to the input of the first inverter.

[0032] The second three-state inverter may have an inverting enable terminal coupled to the second node and a non-inverting enable terminal coupled to the first node. The second latch may further include a fourth transistor having a second conduction terminal coupled to a power supply node, a first conduction terminal coupled to the second node, and a control terminal coupled to receive an internal clock signal; a fifth transistor having a first conduction terminal coupled to the first node, a second conduction terminal coupled to ground, and a control terminal coupled to the output of the first inverter; and a sixth transistor having a first conduction terminal coupled to the first node, a second conduction terminal coupled to ground, and a control terminal coupled to receive an inverted external clock signal.

[0033] The third inverter may have an input coupled to the output of the second inverter and an output for the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a schematic block diagram of a known latch.

[0035] Figure 2 is a schematic block diagram of a known clock latch for generating an internal clock signal for a self-timed memory.

[0036] Figure 3 shows Figure 2 the timing diagrams of proper and improper operations of the latch.

[0037] Figure 4 is a schematic block diagram of a known fault detection circuit for determining whether a clock latch is operating properly or improperly.

[0038] Figure 5 is Figure 4 the timing diagram of the fault detection circuit during an active period and when detecting a single bit flip.

[0039] Figure 6 is Figure 4 the timing diagram of the fault detection circuit during an inactive period and when detecting a single bit flip.

[0040] Figure 7 is a schematic block diagram of an improved fault detection circuit for determining whether a clock latch is operating properly or improperly.

[0041] Figure 8 is the timing diagram of the fault detection circuit operating while detecting a single bit flip during an active period Figure 7 of

[0042] Figure 9 shows the Figure 7Timing diagram of the fault detection circuit. Detailed implementation

[0043] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. Without departing from the spirit and scope of the present disclosure, the general principles described herein can be applied to embodiments and applications other than those detailed above. The present disclosure is not intended to be limited to the illustrated embodiments, but rather to be in line with the broadest scope consistent with the principles and features disclosed or suggested herein.

[0044] Fault detection circuit

[0045] Figure 4 A fault detection circuit 20 for detecting a single-bit flip in a clock latch is shown. Circuit 20 includes a master latch 28 and a slave latch 29. The master latch 28 includes a tri-state inverter 21, an inverter 22, and a tri-state inverter 23. The tri-state inverter 21 is enabled by the FIXINTCKB signal and the FIXINTCK signal, receives the internal clock inverted signal INTCKB (e.g., generated by Figure 3 the clock latch 5 of

[0046] as an input, and its output is coupled to the inverter 22. The tri-state inverter 23 is enabled by the FIXINTCK and FIXINTCKB signals and is coupled to the inverter 22 in a positive feedback arrangement.

[0047] The slave latch 29 includes a tri-state inverter 24, a NAND gate 25, and a tri-state inverter 26. The tri-state inverter 24 is enabled by the SLVCK signal and the SLVCKB signal, receives its input from the output of the master latch 28, and provides its output to the NAND gate 25. The NAND gate 25 receives the CKPULSE signal and generates a fault flag CSNSO at its output. The tri-state inverter 26 is enabled by the SLVCKB signal and the SLVCK signal and is coupled in a positive feedback arrangement between the output of the NAND gate 25 and the input of the NAND gate 25 coupled to the inverter 24.

[0047] Now, the generation of the FIXINTCK signal, the CKPULSE signal, and the SLVCK signal is described. The logic 50 for generating the FIXINTCK signal includes a delay chain 51, an inverter 52, a NAND gate 53, and an inverter 54. The delay chain 51 receives the INTCK signal and passes a delayed version of the INTCK signal to the inverter 52, which provides an inverted and delayed version of the INTCK signal to the NAND gate 53. The NAND gate 53 also receives the INTCK signal as an input and provides its output as the FIXINTCKB signal to the inverter 54, which inverts the FIXINTCKB signal to generate the FIXINTCK signal.

[0048] The logic 60 for generating the CKPULSE signal includes an inverter 61, a delay chain 62, an inverter 63, a NOR gate 64, and an inverter 65. The inverter 61 receives an external clock signal CK and provides its output to the NOR gate 64 and the delay chain 62. The inverter 63 receives the output from the delay chain 62 and inverts a delayed version of the external clock signal for input to the NOR gate 64. The output of the NOR gate 64 is inverted by the inverter 65 to generate the CKPULSE signal.

[0049] From Figure 5 's timing diagram, it can be understood that when the external clock signal CK transitions to a logic high level, the CKPULSE signal transitions to a logic low level and remains at the logic low level until the change in the logic level of the external clock signal CK propagates through the delay chain 62.

[0050] Referring again to Figure 4 , the logic 70 for generating the SLVCK signal includes a NAND gate 71 and an inverter 72. The NAND gate 71 receives the INTCK signal and the reset signal RESET as inputs and generates the SLVCKB signal as output. The inverter 72 inverts the SLVCKB signal for output as the SLVCK signal.

[0051] As can be pointed out in Figure 5 's timing diagram, when both the INTCK signal and the RESET signal are at a logic high level, the SLVCK signal is at a logic high level.

[0052] Now also referring to Figure 5 Regarding Figure 4 's operation of the circuit 20 during the active period is described. At the rising edge of CK, CKPULSE is pulled low by the logic 60 as shown by the arrow O1, and the internal clock signal INTCK is pulled high as shown by the arrow O2. Note that since SLVCK is at a logic low level at this time, data cannot be transferred from the inverter 22 to the NAND gate 25, so the output of the NAND gate 25 is controlled by CKPULSE. Therefore, CKPULSE is driven low to cause the NAND gate 25 to pull the fault flag CSNSO high as shown by the arrow O3 and maintain the fault flag CSNSO at a logic high level through the feedback of the tri-state inverter 26.

[0053] Shortly after INCK rises, FIXINTCK rises as shown by arrow O4. At this time, the tri-state inverter 21 is enabled because FIXINTCKB is at a logic low level and FIXINTCK is at a logic high level, and the tri-state inverter 23 is disabled because FIXINTCK is at a logic high level and FIXINTCKB is at a logic low level. Therefore, at this time, the logic level of the internal clock inverted signal INTCKB will be output by the inverter 22.

[0054] When RESET rises, since INTCK is still at a logic high level at this time, the SLVCK signal rises, enabling the tri-state inverter 24 and disabling the tri-state inverter 26. Therefore, the logic level of the internal clock inverted signal INTCKB will be received by the tri-state inverter 24. When FIXINTCK falls, the tri-state inverter 21 will be disabled and the tri-state inverter 23 will be enabled, thus latching the value of the internal clock inverted signal INTCKB. As a result, INTCKB is passed by the master latch 28 and then inverted by the tri-state inverter 24 to be received by the NAND gate 25, which then pulls the fault flag CSNSO low as shown by arrow O5.

[0055] When SLVCK falls due to the fall of INTCK, the tri-state inverter 24 is disabled and the tri-state inverter 26 is enabled, thus latching the fault flag CSNSO in its current state as shown by arrow O6. The fault flag CSNSO is at a logic low level in this example, indicating that there is no single-bit flip or fault when the clock latch generates INTCK (during the active period).

[0056] In Figure 5 In the next cycle shown, there is a single-bit flip in the clock latch, which causes the INTCK signal to not have an appropriate pulse width. Therefore, there is no time when both INTCK and RESET are high. As a result, the tri-state inverter 24 is not enabled to invert the internal clock inverted signal INTCKB signal. Therefore, once the fault flag CSNSO rises in response to the fall of CKPULSE, the fault flag CSNSO remains at a logic high level and remains latched. This latched logic high level value of the fault flag CSNSO (during this active period) indicates that a single flip has occurred.

[0057] Figure 6Shown is an inactive period during which the clock latch does not generate an internal clock signal INTCK in response to an external clock signal CK. Once CKPULSE (generated in response to the rising edge of the external clock CK as shown by arrow O7) falls, the fault flag CSNSO rises (as shown by arrow O8). Since SLVCK does not rise, the tri-state inverter 24 is not enabled and CSNSO remains latched at a logic high level to indicate proper operation (during this inactive period).

[0058] Since the internal clock signal INTCK will not be generated during the inactive period, an error occurs when a pulse of the internal clock signal INTCK is spuriously generated. As a result, the internal clock inverted signal INTCKB is propagated through the master latch 28, and when SLVCK rises, the tri-state inverter 24 is enabled, so CSNSO falls due to the NAND logic (as shown by arrow O9) and is then latched (as shown by arrow O10) to indicate the presence of a single bit flip.

[0059] Although Figure 4 the fault detection circuit 20 is able to determine the occurrence of a single bit flip in the clock latch, it has several drawbacks. For example, the use of multiple logic gates in the slave latch and in the generation of various control and timing signals may lead to pulse integrity problems. Additionally, the use of logic gates provides multiple possible race (metastable) conditions.

[0060] Fault detection circuit 30

[0061] Therefore, a fault detection circuit with improved performance has been developed. Referring to Figure 7 , a fault detection circuit 30 for determining a single bit flip in a clock latch 40 that generates an internal clock signal INTCK for use by a self-timed memory (not shown) will now be described. Note that when the self-timed memory is in an "active period", the internal clock signal INTCK is to be generated by the clock latch 40 in response to the external clock signal CK, and when the self-timed memory is in an "inactive period", it is not to be generated by the clock latch 40. The fault detection circuit 30 operates to generate a fault flag CSNSO that indicates the presence of a single bit flip when at a logic high level (during the active period of the self-timed memory) and indicates the presence of a single bit flip when at a logic low level (during the inactive period of the self-timed memory).

[0062] The fault detection circuit 30 includes a master latch 38 (which can be considered a set-reset SR latch) and a slave latch 39 (which can be considered a static latch). The master latch 38 includes a NOR gate 31 that receives as inputs the clock inverted signal CKB (the inversion of the external clock signal CK), and the output of NOR gate 32. NOR gate 32 receives as inputs the internal clock signal INTCK, and the output of NOR gate 31, and provides its output signal MCSNSOBB as an input to inverter 33, which provides its output to the slave latch 39 as an input.

[0063] The slave latch 39 includes a tri-state inverter 34 that receives the MCSNSOB signal as an input, and has an inverted enable input that receives the clock inverted signal CKB and a non-inverted enable input that receives the internal clock signal INTCK. Note that the tri-state inverter 34 is enabled when the clock inverted signal CKB is at a logic low level and / or when the internal clock signal INTCK is at a logic high level, and the tri-state inverter 34 is disabled when the clock inverted signal CKB is at a logic high level and the internal clock signal INTCK is at a logic low level. When enabled, the tri-state inverter 34 generates the SCSNSOBB signal as an input to inverter 35, which in turn generates the SCSNSOB signal. Inverter 35 provides the SCSNSOB signal to inverter 37, which generates the fault flag CSNSO.

[0064] The tri-state inverter 36 is coupled between the input and output of inverter 35 in a positive feedback arrangement. The tri-state inverter 36 has an inverted enable input coupled to the drain of PMOS transistor P1. The source of PMOS transistor P1 is coupled to the power supply node, and the gate of PMOS transistor P1 receives the internal clock signal INTCK. The tri-state inverter 36 has a non-inverted enable input coupled to the drains of NMOS transistors N1 and N2. The sources of NMOS transistors N1 and N2 are coupled to ground. NMOS transistor N1 receives the MCSNSOB signal at its gate, while NMOS transistor N2 receives the clock inverted signal CKB at its gate. Note that the tri-state inverter 36 is enabled when the internal clock signal INTCK is at a logic low level and when the clock inverted signal CKB and / or the MCSNSOB signal are at a logic high level. The tri-state inverter 36 is disabled when the internal clock signal INTCK is at a logic high level and / or when the clock inverted signal CKB and the MCSNSOB signal are both at a logic low level.

[0065] Also refer to Figures 8 to 9For the timing diagram, it should be known that (during correct operation) the internal clock signal INTCK rises in response to the rising edge of the external clock signal CK (marked by arrows E0 and E3), and falls when the self-timed memory completes its operation. First, a general discussion of the operation of the fault detection circuit 30 will be given, and then a detailed discussion will follow.

[0066] Operation of the fault detection circuit 30 during the active period of the self-timed memory

[0067] Further reference Figure 8 Referring further to, generally speaking, during the active period of the self-timed memory without a single-bit flip occurring, the internal clock signal INTCK is generated in response to the rising edge of the external clock signal CK (marked by arrow E0). The fault detection circuit 30 generates a rising edge of the fault flag CSNSO in response to the rising edge of the external clock signal CK (marked by arrow E1), and generates a falling edge of the fault flag CSNSO in response to the rising edge of the internal clock signal CK (marked by arrow E2). The fault flag CSNSO is latched at a logic low level, indicating no error.

[0068] However, if the internal clock signal INTCK should rise but does not rise (marked by arrow E3), then since the rising edge of the internal clock signal INTCK does not occur, the fault flag CSNSO still rises in response to the rising edge of the external clock signal CK (marked by arrow E4), and should fall (marked by arrow E5) but does not fall. Then, the fault flag CSNSO is latched at a logic high level, indicating that a single-bit flip has occurred.

[0069] Therefore, when operating during the active period of the self-timed memory, in the absence of an error, the fault flag CSNSO will be at a logic low level. Thus, the latched logic low level value of the fault flag CSNSO indicates proper operation within the clock latch 40 and no single-bit flip, while the latched logic high level value of the fault flag CSNSO indicates the occurrence of a fault and a single-bit flip within the clock latch 40.

[0070] Operation of the fault detection circuit 30 during the inactive period of the self-timed memory

[0071] Now refer to Figure 9, generally, during the inactive period of the self-timed memory, the fault detection circuit generates a rising edge of the fault flag CSNSO (assuming the fault flag CSNSO is not already high) in response to the rising edge of the external clock signal CK (marked by arrow E6), and the fault flag CSNSO is latched. Thus, since the internal clock signal INTCK is not intended to rise during the inactive period of the self-timed memory, the latched logic high value of the fault flag CSNSO indicates that no single bit flip occurs in the clock latch 40 during the inactive period.

[0072] However, if a rising edge of the internal clock signal INTCK is falsely and erroneously generated due to a single bit error in the clock latch 40, the fault flag CSNSO falls in response to the rising edge of the internal clock signal INTCK (marked by arrow E7) and is latched at a logic low level. Thus, since the internal clock signal INTCK is not intended to rise during the inactive period of the self-timed memory, the latched logic low level of the fault flag CSNSO indicates a single bit flip in the clock latch 40 during the inactive period.

[0073] Therefore, when operating during the inactive period of the self-timed memory, the latched logic high value of the fault flag CSNSO indicates correct operation, while the latched logic low value of the fault flag CSNSO indicates the occurrence of a fault within the clock latch 40 and a single bit flip.

[0074] Operation of the fault detection circuit 30 during the active period of the self-timed memory

[0075] Now, also referring to Figure 8 the timing diagram of, a detailed description of the operation when the self-timed memory is in the active period is given. A period without error is shown between times t0 - t6. It can be seen that the external clock signal CK rises to logic high at time t1. The external clock signal CK being at logic high means that its inverted CK B will be at logic low.

[0076] Since the external clock signal CK was previously at a logic low level, this means that its inverse CKB was previously at a logic high level, which means that when the external clock signal CK rises at time t1 (or its inverse CKB falls), the NOR gate 31 will output a logic low level. As a result, the NOR gate 32 outputs a logic high level as MCSNSOBB to the inverter 33, and the inverter 33 in turn outputs a logic low level of MCSNSOB. Note that since CKB is low, the tri-state inverter 34 is enabled at this time and will output a logic high level of SCNSOBB. In addition, at this time, the tri-state inverter 36 will remain enabled until the internal clock signal INTCK falls to a logic low level. The inverter 35 inverts SCSNSOBB to SCNSOB, and the inverter 37 inverts SCNSOB to CSNO, so the fault flag CSNO rises to a logic high level at time t3 (due to propagation delay).

[0077] At time t2, the internal clock signal INTCK rises in response to the rising edge of the external clock signal CK. The internal clock signal INTCK being at a high level means that the NOR gate 32 must output a logic low level as MCSNSOBB to the inverter 33, and the inverter 33 in turn inverts it to a logic high level as MCSNSOB to the tri-state inverter 34. At this time, the tri-state inverter 34 remains on because INTCK is at a high level, so it outputs a logic low level as SCSNSOBB to the inverter 35, which inverts it to SCSNSOB to the inverter 37, which will pull the fault flag CSNSO low at time t5 (due to propagation delay). Note that at this time, since the internal clock signal INTCK is at a logic high level, the tri-state inverter 36 will remain off.

[0078] At time t4, the internal clock signal INTCK falls. Here, since INTCK was just previously at a logic high level, the NOR gate 32 outputs a logic low level as MCSNSOBB, as a result of which the NOR gate 31 will output a logic high level (because CKB is at a logic low level), thus maintaining the output of the NOR gate 32 at a logic low level. Since MCSNSOBB is at a logic low level, the inverter 33 will output MCSNSOB as a logic high level. The tri-state inverter 34 remains enabled because CKB is at a logic low level and inverts MCSNSOB to produce SCSNSOBB as a logic low level, which is inverted by the inverter 35 to produce SCSNSOB as a logic high level, and is inverted again by the inverter 37 to produce a logic low level of the fault flag CSNSO. Note that at this time, because the internal clock signal INTCK is at a logic low level and because MCSNSOB is at a logic high level, the tri-state inverter 36 will be enabled.

[0079] At time t6, the external clock signal CK falls to a logic low level, as a result of which the tri-state inverter 34 is disabled, thereby latching the fault flag CSNSO in its current state. Since the clock inverted signal CKB rises to a logic high level when the external clock signal CK falls to a logic low level, and since the internal clock signal INTCK is already at a logic low level (having fallen to a logic low level at time t4), the tri-state inverter 34 is disabled at time t6. Also at this time, since INTCK is low, the tri-state inverter 36 is enabled, thereby latching the fault flag CSNSO in its logic low level.

[0080] Note that the latching of the fault flag CSNSO does not depend on the fall of the external clock signal CK. If the external clock signal CK does not fall to a logic low level, this means that the clock inverted signal CKB remains at a logic low level. If CKB is at a logic low level, the output of the NOR gate 31 is at a logic high level, and since the internal clock signal INTCK will be at a logic low level at this time, the output of the NOR gate 32 will generate MCSNSOBB as low level, and the inverter 33 will invert it to generate MCSNSOB as high level. MCSNSOB being high when the internal clock signal INTCK is at a logic low level will enable the tri-state inverter 36, thereby latching the fault flag CSNSO in its current state.

[0081] Since the fault flag CSNSO is at a logic low level at time t6 when the latch 39 latches the fault flag CSNSO, this logic low level is latched, indicating that there is no error during this cycle (which ends at time t6).

[0082] In this operation, it should be understood that the rise of the internal clock signal INTCK always causes the fault flag CSNSO to fall to a logic low level due to the logic of the fault detection circuit 30, thereby eliminating the possibility of metastability or a race condition.

[0083] The next cycle starts at time t6 and lasts until time t10. As can be seen, an error occurs during this cycle. Here, at time t7, a rising edge of the external clock signal CK occurs. The external clock signal CK being at a logic high level means that its inverted signal CKB will be at a logic low level.

[0084] Since the external clock signal CK was previously at logic low, this means that its inverse CKB was previously at logic high, which in turn means that when the external clock signal CK rises at time t7 (or its inverse CKB falls), the NOR gate 31 will output a logic low. As a result, the NOR gate 32 will output a logic high as MCSNSOBB to the inverter 33, and the inverter 33 in turn outputs a logic low MCSNSOB.

[0085] Note that at this time, since CKB is at logic low, the tri-state inverter 34 will be enabled and will output a logic high SCNSOBB. Also note that at this time, since the clock inverse signal CKB and MCNSOB are at logic low, the tri-state inverter 36 will be disabled.

[0086] SCNSOBB will be inverted by the inverter 35 and then again by the inverter 37 to produce a rising edge of the fault flag CSNSO at time t9. Due to the propagation delay in the fault detection circuit 30, the rising edge of the fault flag CSNSO rises at time t9.

[0087] It can be seen that at time t8, the rising edge of the internal clock signal INTCK should have occurred, but did not occur due to a single-bit flip in the clock latch 40. Therefore, the logical states of the various components of the fault detection circuit 30 do not change until time t10. At time t10, the external clock signal CK falls (and its inverse CKB rises), but the fault flag CSNSO is at logic high, so the result of disabling the tri-state inverter 34 by the internal clock signal INTCK remaining low and the clock inverse signal CKB rising to logic high is used to latch the fault flag CSNSO at logic high, indicating that a single-bit flip has occurred in the clock latch 40. The clock inverse signal CKB rising to logic high and the internal clock signal INTCK remaining at logic low are used to turn on the tri-state inverter 36 at this time to maintain the fault flag CSNSO in its current state.

[0088] Note that for an error where the internal clock signal INTCK does rise but not sufficiently (e.g., the signal does not reach logic high before falling back to logic low), the operation and results are the same as if the internal clock signal INTCK had never risen.

[0089] Note also that the latching of the fault flag CSNSO does not depend on the falling edge of the external clock signal CK. If the external clock signal CK does not fall to a logic low level, this means that the clock inverted signal CKB remains at a logic low level. If CKB is at a logic low level, the output of the NOR gate 31 will be at a logic high level, and since the internal clock signal INTCK will be at a logic low level at this time, the output of the NOR gate 32 will generate MCSNSOBB as a low level, and the inverter 33 will invert it to generate MCSNSOB as a high level. When MCSNSOB is at a high level when the internal clock signal INTCK is at a logic low, this will enable the tri-state inverter 36, thereby latching the fault flag CSNSO in its current state.

[0090] Operation of the fault detection circuit 30 during the inactive period of the self-timed memory

[0091] Now, also referring to Figure 9 the timing diagram of, the detailed operation when the self-timed memory is in the inactive period will be described. The period during which no error occurs is shown between times t11 - t14. It can be seen that the external clock signal CK rises to a logic high level at time t12. The external clock signal CK being at a logic high level means that CKB is at a logic low level.

[0092] Since the external clock signal CK was previously at a logic low level, this means that its inverted CKB was previously at a logic high level, which means that when the external clock signal CK rises at time t12 (or its inverted CKB falls), the NOR gate 31 will output a logic low level. As a result, the NOR gate 32 outputs a logic high level as MCSNSOBB to the inverter 33, and the inverter 33 in turn outputs a logic low level of MCSNSOB.

[0093] Note that at this time, since CKB is at a logic low level, the tri-state inverter 34 will be enabled and will output a logic high level of SCNSOBB. Also note that at this time, since CKB and MCSNSOB are at a logic low level, the tri-state inverter 36 will be disabled.

[0094] SCNSOBB will be inverted by the inverter 35 and then inverted again by the inverter 37 to generate a rising edge of the fault flag CSNSO at time t13. Due to the propagation delay in the fault detection circuit 30, the rising edge of the fault flag CSNSO rises at time t13.

[0095] At time t14, the external clock signal CK falls (and its inverse CKB rises), but the fault flag CSNSO is at logic high. Thus, the internal clock signal INTCK remains low and the rising of the clock inverse signal CKB to logic high and the resultant disabling of the tri-state inverter 34 are used to latch the fault flag CSNSO at logic high, indicating that no single-bit flip has occurred in the clock latch 40. At this time, since INTCK is at logic low and CKB rises to logic high, the tri-state inverter 36 is enabled, thereby maintaining the fault flag CSNSO at its current logic level. Again, the latching of the fault flag CSNSO does not depend on the falling of the external clock signal CK. If the external clock signal CK does not fall to logic low, this means that the clock inverse signal CKB remains at logic low. If CKB is at logic low, the output of the NOR gate 31 will be at logic high, and since the internal clock signal INTCK will be at logic low at this time, the output of the NOR gate 32 will generate MCSNSOBB as low, and the inverter 33 will invert it to generate MCSNSOB as high. When MCSNSOB is high while the internal clock signal INTCK is at logic low, this will enable the tri-state inverter 36, thereby latching the fault flag CSNSO in its current state.

[0096] Now, an inactive period during which an error occurs is shown between times t14 and t19. Since the external clock signal CK was previously at logic low, this means that CKB was previously at logic high, which means that when the external clock signal CK rises (and its inverse CKB falls) at time t15, the NOR gate 31 will output logic low. As a result, the NOR gate 32 outputs logic high as MCSNSOBB to the inverter 33, and the inverter 33 in turn outputs logic low MCSNSOB.

[0097] Note that at this time, since CKB is at logic low, the tri-state inverter 34 will be enabled and will output SCNSOBB at logic high. Also at this time, since MCSNSOB and CKB are at logic low, the tri-state inverter 36 will be disabled.

[0098] SCNSOBB will be inverted by the inverter 35 and then again by the inverter 37 to maintain the logic high state of the fault flag CSNSO at time t15.

[0099] At time t16, the internal clock signal INTCK wrongly and spuriously rises due to a single-bit error in the clock latch 40. Since the internal clock signal INTCK is now at a logic high level, the NOR gate 32 will output a logic low level as MCSNSOBB. Therefore, the logic low level represented by MCSNSOBB is inverted by the inverter 33 to generate MCSNSOB, which in turn is inverted by the tri-state inverter 34 to generate SCSNSOBB, which in turn is inverted by the inverter 35 to generate SCSNSOB, and the SCSNSOB itself is then inverted by the inverter 37, pulling the output of the inverter 37 to a low level, thereby generating a falling edge of the fault flag CSNSO. Due to the propagation delay, the falling edge of the fault flag CSNSO occurs at time t18.

[0100] At time t19, the external clock signal CK falls to a logic low level, as a result of which the tri-state inverter 34 is disabled, thus latching the fault flag CSNSO. Since the clock inverted signal CKB rises to a logic high level when the external clock signal CK falls to a logic low level, and since the internal clock signal INTCK is already at a logic low level (having fallen to a logic low level at time t17), the tri-state inverter 34 is disabled at time t19. Also note that the latching of the fault flag CSNSO does not depend on the external clock signal CK falling. If the external clock signal CK does not fall to a logic low level, this means that the clock inverted signal CKB remains at a logic low level. If CKB is at a logic low level, the output of the NOR gate 31 will be at a logic high level, and since the internal clock signal INTCK will be at a logic low level at this time, the output of the NOR gate 32 will generate MCSNSOBB as a low level, and the inverter 33 will invert it to generate MCSNSOB as a high level. When MCSNSOB is at a high level when the internal clock signal INTCK is at a logic low level, this will enable the tri-state inverter 36, thus latching the fault flag CSNSO in its current state.

[0101] Since the fault flag CSNSO is at a logic low level at time t19 when the latch 39 latches the fault flag CSNSO, this logic low level is latched and indicates the presence of a single-bit flip in the clock latch 40 error during this cycle (which ends at time t19). Also note that at this time, since INTCK is at a logic low level and CKB rises to a logic high level, the tri-state inverter 36 will be enabled, thus maintaining the fault flag CSNSO at its existing value.

[0102] Therefore, through the use of the fault detection circuit 30, a single-bit flip can be accurately determined without the possibility of metastable conditions as in the prior art.

[0103] Although the present disclosure has been described with respect to a limited number of embodiments, those skilled in the art having the benefit of this disclosure will appreciate that other embodiments can be contemplated that do not depart from the scope of the disclosure herein. Accordingly, the scope of the present disclosure is limited only by the appended claims.

Claims

1. A fault determination circuit, comprising: A master - slave latch device, which in the active mode is configured to: The slave clock latch directly receives an internal clock signal electrically, the internal clock signal being designed to rise in response to the rising edge of an external clock signal, wherein the internal clock signal is generated from the external clock signal; In response to the rising edge of the external clock signal, generate a rising edge of a fault flag signal; If the rising edge of the internal clock signal occurs, then in response to the rising edge of the internal clock signal, generate a falling edge of the fault flag signal; In response to the falling edge of the internal clock signal, latch the fault flag signal; and Wherein if the falling edge of the fault flag signal is not generated before latching, the latched fault flag signal indicates a single - bit flip in the clock latch.

2. The fault determination circuit according to claim 1, wherein the master - slave latch device in the inactive mode is configured to: In response to the rising edge of the external clock signal, generate a rising edge of a fault flag signal; If a rising edge of the internal clock signal occurs, a falling edge of the fault flag signal is generated in response to the rising edge of the internal clock signal; And If the rising edge of the internal clock signal occurs, then in response to the falling edge of the internal clock signal, latch the fault flag signal; Wherein if the falling edge of the fault flag signal is generated before latching, the latched fault flag signal indicates a single - bit flip in the clock latch.

3. The fault determination circuit according to claim 1, wherein the master - slave latch device comprises: A first latch, having a first input receiving the inverted external clock signal, a second input receiving the internal clock signal, and an output; An inverter, coupled to the output of the first latch; And A second latch, having a non - inverted enable terminal, an inverted enable terminal, an input, and an output, the inverted enable terminal receiving a signal based on the inversion of the external clock signal and the inversion of the output of the first latch, the non - inverted enable terminal receiving a signal based on the internal clock signal, and the input being coupled to receive the output from the inverter.

4. The fault determination circuit according to claim 3, wherein the first latch comprises a NOR logic circuit; and wherein the second latch comprises a NOT logic circuit.

5. The fault determination circuit according to claim 3, wherein the second latch comprises: A first tri - state inverter, having an inverted enable terminal receiving the inverted external clock signal, a non - inverted enable terminal receiving the internal clock signal, and an input coupled to receive the output from the inverter; A first inverter, having an input coupled to the output of the first tri - state inverter; And A second tri - state inverter, having an inverted enable terminal, a non - inverted enable terminal, an input coupled to the output of the first inverter, and an output coupled to the input of the first inverter.

6. The fault determination circuit according to claim 5, wherein the second latch further comprises: A PMOS transistor having a source coupled to a power supply node, a drain coupled to the inverting enable terminal of the second tri-state inverter, and a gate coupled to the internal clock signal; A first NMOS transistor having a drain coupled to the non-inverting enable terminal of the second tri-state inverter, a source coupled to ground, and a gate coupled to receive an output from the inverter that receives the output of the first latch; A second NMOS transistor having a drain coupled to the non-inverting enable terminal of the second tri-state inverter, a source coupled to ground, and a gate coupled to the inverted external clock signal; And A second inverter receiving an input from the first inverter and generating the fault flag signal at its output.

7. A fault determination circuit that detects a single bit flip in a clock latch that receives an external clock signal and generates an internal clock signal from the external clock signal, the fault determination circuit comprising: A first latch configured to generate a first signal at a logic high level when the internal clock signal is at a logic low level and the external clock signal is at a logic high level, and to generate the first signal at a logic low level when the internal clock signal is at a logic high level and the external clock signal is at a logic high level; And A second latch configured to generate a fault flag signal at a logic high level when the first signal is at a logic high level, to generate the fault flag signal at a logic low level when the first signal is at a logic low level, and to latch when the internal clock signal is at a logic low level; Wherein the presence of a single bit flip in the clock latch is indicated by the fault flag signal being at a logic high level when latching the second latch and the clock latch being in an active mode; and Wherein the presence of a single bit flip in the clock latch is indicated by the fault flag signal being at a logic low level when latching the second latch and the clock latch being in an inactive mode.

8. The fault determination circuit according to claim 7, wherein the second latch comprises: A first tri-state inverter having an inverting enable terminal receiving the inverted external clock signal, a non-inverting enable terminal receiving the internal clock signal, and an input coupled to receive an inverted version of the first signal; A first inverter having an input coupled to the output of the first tri-state inverter; A second tri-state inverter having an inverting enable terminal, a non-inverting enable terminal, an input coupled to the output of the first inverter, and an output coupled to the input of the first inverter; A PMOS transistor having a source coupled to a power supply node, a drain coupled to the inverting enable terminal of the second tri-state inverter, and a gate coupled to the internal clock signal; A first NMOS transistor having a drain coupled to the non-inverting enable terminal of the second tri-state inverter, a source coupled to ground, and a gate coupled to receive an output from a third inverter, the third inverter receiving the output of the first latch; A second NMOS transistor having a drain coupled to the non-inverting enable terminal of the second tri-state inverter, a source coupled to ground, and a gate coupled to the inverted external clock signal; And A second inverter receiving an input from the first inverter and generating the fault flag signal at its output.

9. The fault determination circuit according to claim 8, wherein the first latch comprises: A first NOR gate and a second NOR gate; Wherein the first NOR gate has an input coupled to the inverted external clock signal and the output of the second NOR gate, and an output; Wherein the second NOR gate has an input coupled to the internal clock signal and the output of the first NOR gate, and an output; and Wherein the third inverter is coupled to receive an input from the output of the second NOR gate and provides an output to the second latch.

10. A fault determination circuit that detects a single bit flip in a clock latch that receives an external clock signal and generates an internal clock signal from the external clock signal, the fault determination circuit comprising: A set-reset SR latch having a set input receiving the inverted external clock signal, a reset input receiving the internal clock signal, and an output; An inverter coupled to the output of the SR latch; And A static latch having an inverting enable terminal, a non-inverting enable terminal, an input, and an output, the inverting enable terminal receiving a signal based on the inverted external clock signal and the inverted output of the SR latch, the non-inverting enable terminal receiving a signal based on the internal clock signal, the input being coupled to receive an output from the inverter.

11. The fault determination circuit according to claim 10, further comprising a first inverter that receives an input from the output of the static latch and generates a fault flag signal as an output, wherein the fault flag signal is at a logic high level when the static latch is latched and the clock latch is in an active mode indicating the presence of a single bit flip in the clock latch; and wherein the fault flag signal is at a logic low level when the static latch is latched and the clock latch is in an inactive mode indicating the presence of a single bit flip in the clock latch.

12. The fault determination circuit according to claim 10, wherein the SR latch is formed of NOR logic.

13. The fault determination circuit according to claim 10, wherein the static latch is formed of NOT logic.

14. An electronic device comprising: A first latch that receives, as inputs, an inversion of an internal clock signal and an external clock signal for a memory, the internal clock signal being generated from the external clock signal; A first inverter having an input coupled to the output of the first latch; A second latch including: A first tri-state inverter having an inversion enable terminal receiving the inversion of the external clock signal, a non-inversion enable terminal receiving the internal clock signal, and an input coupled to the output of the first inverter; A second inverter having an input coupled to the output of the first tri-state inverter; A second tri-state inverter having an input coupled to the output of the second inverter and an output coupled to the input of the second inverter; A PMOS transistor having a source coupled to a power supply node, a drain coupled to the inversion enable terminal of the second tri-state inverter, and a gate coupled to the internal clock signal; A first NMOS transistor having a drain coupled to the non-inversion enable terminal of the second tri-state inverter, a source coupled to ground, and a gate coupled to the output of the first inverter; and A second NMOS transistor having a drain coupled to the non-inversion enable terminal of the second tri-state inverter, a source coupled to ground, and a gate coupled to the inversion of the external clock signal; and A third inverter having an input coupled to the output of the second inverter and an output for the electronic device.

15. The electronic device according to claim 14, wherein the first latch includes: A first NOR gate and a second NOR gate; wherein the first NOR gate has an input coupled to the inversion of the external clock signal and the output of the second NOR gate, and an output; and wherein the second NOR gate has an input coupled to the internal clock signal and the output of the first NOR gate, and an output coupled to the input of the first inverter.

16. The electronic device according to claim 14, wherein the second three-state inverter has an inverting enable terminal coupled to the second node and a non-inverting enable terminal coupled to the first node; wherein the second latch further includes: A first PMOS transistor having a source coupled to a power supply node, a drain coupled to the second node, and a gate coupled to receive the internal clock signal; A first NMOS transistor having a drain coupled to the first node, a source coupled to ground, and a gate coupled to the output of the first inverter; and A second NMOS transistor having a drain coupled to the first node, a source coupled to ground, and a gate coupled to receive the inversion of the external clock signal.

17. A method for determining the presence of a single bit flip in a clock latch, the method including: Directly electrically receiving, at the clock latch, the next rising edge of an external clock signal; In response to the next rising edge of the external clock signal: When the clock latch is in an active mode, generating a rising edge of an internal clock signal from the external clock signal, and when the clock latch is in an inactive mode, not generating the rising edge of the internal clock signal from the external clock signal; and generate a rising edge of a fault flag signal; if a rising edge of the internal clock signal occurs, generate a falling edge of the fault flag signal in response to the rising edge of the internal clock signal; and latch the fault flag signal.

18. The method according to claim 17, wherein if the clock latch is in the active mode, the latched fault flag signal indicates a single bit flip in the clock latch if the falling edge of the fault flag signal has not been generated before latching.

19. The method according to claim 17, wherein if the clock latch is in the inactive mode, the latched fault flag signal indicates a single bit flip in the clock latch if the falling edge of the fault flag signal has been generated before latching.

20. An electronic device, comprising: a first latch that receives, as an input, an inversion of an internal clock signal and an external clock signal for a memory, the internal clock signal being generated from the external clock signal; a first inverter having an input coupled to an output of the first latch; and a second latch, comprising: a first tri-state inverter having an inversion enable terminal that receives the inversion of the external clock signal, a non-inversion enable terminal that receives the non-inverted internal clock signal, and an input coupled to an output of the first inverter; a second inverter having an input coupled to an output of the first tri-state inverter; a second tri-state inverter having an input coupled to an output of the second inverter and an output coupled to an input of the second inverter; a first transistor having a first conduction terminal coupled to a power supply node, a second conduction terminal coupled to an inversion enable terminal of the second tri-state inverter, and a control terminal coupled to the internal clock signal; a second transistor having a first conduction terminal coupled to a non-inversion enable terminal of the second tri-state inverter, a second conduction terminal coupled to ground, and a control terminal coupled to the output of the first inverter; and a third transistor having a first conduction terminal coupled to the non-inversion enable terminal of the second tri-state inverter, a second conduction terminal coupled to ground, and a control terminal coupled to the inversion of the external clock signal.

21. The electronic device according to claim 20, wherein the first latch comprises: a first logic gate and a second logic gate; wherein the first logic gate has an input coupled to the inversion of the external clock signal and an output of the second logic gate, and an output; and wherein the second logic gate has an input coupled to the internal clock signal and an output of the first logic gate, and an output coupled to the input of the first inverter.

22. The electronic device according to claim 20, wherein the second tri-state inverter has an inversion enable terminal coupled to a second node and a non-inversion enable terminal coupled to a first node; wherein: The first transistor has a first conductive terminal coupled to a power supply node, a second conductive terminal coupled to the second node, and a control terminal coupled to receive the internal clock signal; The second transistor has a first conductive terminal coupled to the first node, a second conductive terminal coupled to ground, and a control terminal coupled to the output of the first inverter; and The third transistor has a first conductive terminal coupled to the first node, a second conductive terminal coupled to ground, and a control terminal coupled to receive the inverted external clock signal.

23. The electronic device according to claim 20, further comprising a third inverter having an input coupled to the output of the second inverter and an output for the electronic device.

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