A rail-to-rail ultra-low mismatch charge pump circuit powered by a floating power supply

Abstract

The present invention discloses a rail-to-rail ultra-low mismatch charge pump circuit powered by a floating power supply, the rail-to-rail ultra-low mismatch charge pump circuit includes a charge pump, a floating power supply circuit and a level conversion circuit, the floating power supply circuit generates a positive floating power supply and a negative floating power supply that maintain a constant difference with the voltage VC at the output end of the charge pump and follow the change of the voltage VC, and provides floating power supply access and floating ground access for the charge pump, wherein the aforementioned constant difference is configured according to the difference between the corresponding power supply and power ground and the voltage VC when the charging current and the discharging current of the charge pump are equal, when the voltage VC changes, the positive floating power supply and the negative floating power supply both follow the change of the voltage VC and maintain a constant difference, thereby widening the charge pump working range to 0-3.3V, and ensuring that the charge pump works in a state close to zero current mismatch in the full working range. At the same time, the burr problem caused by charge sharing is avoided, and the circuit structure inside the existing charge pump is simplified.

Description

Technical Field

[0001] The invention belongs to the technical field of charge pump circuits in phase-locked loops, and in particular relates to a rail-to-rail ultra-low mismatch charge pump circuit powered by a floating power supply. Background Art

[0002] The phase-locked loop (PLL) is a very important functional system with a wide range of applications, such as providing a clock signal of one or more frequencies in a chip system to which it belongs, generating a local oscillator signal in a receiver to which it belongs, and maintaining synchronization in a communication system to which it belongs. Low charge pump mismatch current and wide voltage control oscillator control voltage adjustment range are very important design indicators.

[0003] The charge pump phase-locked loop system (CPPLL) is widely used, mainly including a phase frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), a voltage-controlled oscillator (VCO) and a frequency divider (N); the phase frequency detector receives the feedback clock of the phase-locked loop and compares the phase with the input reference clock to generate phase error signals UP and DN. These two phase error signals are used to control the charge pump to charge and discharge the low-pass filter, thereby adjusting the control voltage VC output by the low-pass filter; the control voltage VC is used as the control voltage input to the voltage-controlled oscillator to change the frequency of the clock signal output by the voltage-controlled oscillator, and then the clock signal output by the voltage-controlled oscillator is divided by the frequency divider and input as the feedback clock to the phase frequency detector, thereby adjusting the control signal output by the phase frequency detector, and the cycle continues until the phase lock is stable and the clock signal output by the voltage-controlled oscillator is synchronized with the locally generated reference clock. In a charge pump phase-locked loop system, the charge pump outputs charging current and discharging current to the low-pass filter to control the low-pass filter to generate a control voltage VC for the voltage-controlled oscillator, thereby adjusting the frequency of the clock signal output by the voltage-controlled oscillator. However, when the control voltage VC is too high or too low, the charge pump will have a serious current mismatch. Therefore, the control voltage VC can only be adjusted within a certain range, so that the frequency range of the clock signal output by the voltage-controlled oscillator is limited. If the voltage-controlled oscillator needs to generate a wider frequency range of the clock signal, the gain of the voltage-controlled oscillator can only be changed, but this will increase the noise of the phase-locked loop and reduce the stability and accuracy of the phase-locked loop.

[0004] A wider control voltage adjustment range of a voltage-controlled oscillator, lower charge pump current mismatch, and glitches have always been research hotspots; if the operating range of the control voltage at the output of the charge pump can be widened so that the charge pump still has the ability to have low current mismatch when the control voltage VC of the voltage-controlled oscillator is too high or too low, then the control voltage VC generated by the low-pass filter will have a wider voltage adjustment range, thereby increasing the frequency range of the clock signal output by the voltage-controlled oscillator, widening the output frequency range of the phase-locked loop, and also reducing the gain of the voltage-controlled oscillator through phase-locked loop adjustment to reduce the impact of noise. Current research on charge pumps is limited to reducing the mismatch current within the normal operating range of the control voltage VC and to widening the control voltage VC range at the output of the charge pump to a certain extent; however, changes in the control voltage VC will affect the current output by the charge pump, and even within the normal operating range of the control voltage VC, the charging current and the discharging current will also change with changes in the control voltage VC; the mismatch current generated by the inequality of the charging current and the discharging current generally has a dynamic mismatch range of about 1%-4%, and when the control voltage VC deviates from the intermediate voltage, glitches will be generated at the output of the low-pass filter connected to the charge pump.

[0005] At present, the method of reducing the current mismatch of the charge pump is mainly to ensure that the drain-source voltage Vds of the MOS tube of the charging current source and the discharging current source inside the charge pump remains unchanged through circuit design, so that the current of the charging current source and the discharging current source is constant; however, as the control voltage VC changes, the drain-source voltage Vds of the MOS tube of the charging current source and the discharging current source inside the charge pump will change, and even enter the linear region when the control voltage VC is too high or too low, resulting in a sharp increase in the mismatch current generated by the charge pump. The existing method of widening the working range of the charge pump, such as using a MOS tube with a low threshold voltage, can only increase the working range of the charge pump to a certain extent, but it will still be affected by the threshold voltage of the MOS tube. When the control voltage VC is too high or too low, it will still cause serious current mismatch in the charge pump, thus limiting the further expansion of the working range of the charge pump (the range of the control voltage VC). Summary of the invention

[0006] In order to solve the above-mentioned limitations on the working range of the charge pump in the phase-locked loop, as well as the current mismatch and other problems, the present invention discloses a rail-to-rail ultra-low mismatch charge pump circuit powered by a floating power supply. The floating power supply circuit generates a positive floating power supply and a negative floating power supply that maintain a constant difference with the charge pump output terminal voltage VC and change with the change of VC, provides floating power supply access and floating ground access for the charge pump, widens the charge pump working range to 0-3.3V, and keeps the current mismatch close to zero within this range, while avoiding the burr problem caused by charge sharing caused by the VC voltage deviating from the intermediate voltage, and simplifies the charge pump structure.

[0007] The present invention proposes the following technical scheme: a rail-to-rail ultra-low mismatch charge pump circuit powered by a floating power supply, the rail-to-rail ultra-low mismatch charge pump circuit includes a charge pump, in a phase-locked loop to which the rail-to-rail ultra-low mismatch charge pump circuit is applicable, a frequency detector and a phase detector output four clock control signals (UP, UPB, DN, DNB) for controlling a charge pump switch, the charge pump outputs a charge and discharge current to a low-pass filter, the low-pass filter generates a control voltage VC for adjusting an oscillation frequency of a voltage-controlled oscillator according to the charge and discharge current, the rail-to-rail ultra-low mismatch charge pump circuit also includes a floating power supply circuit and a level conversion circuit; a floating control terminal of the floating power supply circuit is used to A floating voltage control signal VIN_VC which is equal to the control voltage VC is input in real time, and a positive floating power supply voltage VDDH_VC and a negative floating power supply voltage VSSL_VC which follow the change of the control voltage VC are generated based on the operation result of the floating voltage control signal VIN_VC and the pre-configured voltage signal; the floating power supply output terminal of the floating power supply circuit is connected to the power supply terminal of the charge pump, so as to provide the positive floating power supply voltage VDDH_VC for the charge pump; the floating ground output terminal of the floating power supply circuit is connected to the power ground terminal of the charge pump, so as to provide the negative floating power supply voltage VSSL_VC for the charge pump; wherein, the positive floating power supply voltage VDD H_VC and the negative floating power supply voltage VSSL_VC both maintain a constant difference with the control voltage VC, and the constant difference is a pre-configured voltage difference when the charging current and the discharging current of the charge pump are equal; by adjusting the charge pump parameters, the control voltage VC is always at the average value of the positive floating power supply voltage VDDH_VC and the negative floating power supply voltage VSSL_VC; the four conversion input terminals set by the level conversion circuit are respectively used to input the four-way clock control signals (UP, UPB, DN, DNB) in the traditional power supply state, and convert and output the four-way clock control signals (UP1, UPB1, D N1, DNB1), wherein, in the floating power supply state, the power supply is the positive floating power supply voltage VDDH_VC, and the power ground is the negative floating power supply voltage VSSL_VC; the four conversion output terminals of the level conversion circuit are correspondingly connected to the four clock control input terminals of the charge pump, and are used to receive four clock control signals (UP1, UPB1, DN1, DNB1) in the floating power supply state, so that the charge pump performs the same switch control function as before the conversion, so as to achieve the adaptation of the four clock control signals (UP1, UPB1, DN1, DNB1) transmitted by the rail-to-rail ultra-low mismatch charge pump circuit and the frequency and phase detector circuit.

[0008] Compared with the prior art, the rail-to-rail ultra-low mismatch charge pump circuit generates a positive floating power supply and a negative floating power supply through a floating power supply circuit, which maintain a constant difference with the charge pump output terminal voltage VC and change with the change of VC. When the voltage VC changes, the positive floating power supply voltage VDDH_VC and the negative floating power supply voltage VSSL_VC both change with VC and maintain a constant difference, thereby widening the charge pump operating range to 0-3.3V, and maintaining the current mismatch close to zero within this range. At the same time, the charge sharing caused by the voltage VC deviating from the intermediate voltage and the burr problem caused thereby are avoided, thereby simplifying the charge pump structure; therefore, the charge pump operating range is widened, and the charge pump always operates in a state close to zero current mismatch.

[0009] Furthermore, the floating power supply circuit includes a positive floating power supply circuit and a negative floating power supply circuit; the power supply terminal of the positive floating power supply circuit and the power supply terminal of the negative floating power supply circuit are both connected to the power supply terminal of the floating power supply circuit, for inputting the power supply of the phase-locked loop; the power ground terminal of the positive floating power supply circuit and the power ground terminal of the negative floating power supply circuit are both connected to the power ground terminal of the floating power supply circuit, for inputting the ground power of the phase-locked loop; the floating control terminal of the positive reference power supply generating circuit and the floating control terminal of the negative reference power supply generating circuit are both connected to the floating control terminal of the floating power supply circuit, for inputting the floating voltage control signal VIN_VC. This technical solution provides floating power access and floating ground access for the charge pump in circuit design.

[0010] Further, the positive floating power supply circuit includes a positive power supply generating circuit, a positive reference power supply generating circuit and a positive floating power supply generating circuit; the positive power supply generating circuit, the positive reference power supply generating circuit and the positive floating power supply generating circuit are all provided with a power supply terminal and a power ground terminal, wherein the power ground terminals provided in the aforementioned circuits are all connected to the power ground terminal of the positive floating power supply circuit; the power ground terminal of the operational amplifier inside the positive reference power supply generating circuit and the power ground terminal of the operational amplifier inside the positive floating power supply generating circuit are both connected to the power ground terminal HG of the positive power supply generating circuit; the power supply terminal of the operational amplifier inside the positive reference power supply generating circuit and the power supply terminal of the operational amplifier inside the positive floating power supply generating circuit are both connected to the signal output terminal of the positive power supply generating circuit, and the signal output terminal of the positive reference power supply generating circuit is connected to the positive input terminal of the operational amplifier inside the positive floating power supply generating circuit; The power supply generating circuit includes an adding circuit composed of an operational amplifier and a resistor, so that the floating voltage control signal VIN_VC and the pre-configured voltage to be added VIN_VADD are input into the positive input terminal of the operational amplifier inside the positive reference power supply generating circuit through the resistor, and the signal output terminal of the positive reference power supply generating circuit outputs the positive reference power supply voltage VDDH_REF to the positive input terminal of the positive floating power supply generating circuit; the signal output terminal of the positive floating power supply generating circuit outputs the positive floating power supply voltage VDDH_VC with anti-interference characteristics, and the positive reference power supply voltage VDDH_REF is equal to the voltage sum of the floating voltage control signal VIN_VC and the pre-configured voltage to be added VIN_VADD, so that the voltage difference between the positive floating power supply voltage VDDH_VC and the control voltage VC is maintained at the pre-configured voltage to be added VIN_VADD.

[0011] Further, the positive power supply generating circuit includes a first inverter INV1, a second inverter INV2, a first differential charge pump CP_Diff1, a second differential charge pump CP_Diff2, a first capacitor C1 and a second capacitor C2; the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, the output end of the first differential charge pump CP_Diff1 is connected to the input end of the second differential charge pump CP_Diff2, the input end of the first inverter INV1 is used to input a clock signal outside the positive floating power supply circuit, the positive clock input end of the first differential charge pump CP_Diff1 and the positive clock input end of the second differential charge pump CP_Diff2 are both connected to the output end of the first inverter INV1, and the negative clock input end of the first differential charge pump CP_Diff1 and the negative clock input end of the second differential charge pump CP_Diff2 are both connected to the second inverter INV2. The output end of the first differential charge pump CP_Diff2 is connected; the power supply end of the first inverter INV1, the power supply end of the second inverter INV2, and the input end of the first differential charge pump CP_Diff1 are connected to the power supply end HV of the positive power generation circuit; the power ground end of the first inverter INV1 and the power ground end of the second inverter INV2 are both connected to the power ground end HG of the positive power generation circuit; the input end of the second differential charge pump CP_Diff2 is connected to the upper plate of the first capacitor C1, and the lower plate of the first capacitor C1 is connected to the power ground end HG of the positive power generation circuit; the output end of the second differential charge pump CP_Diff2 is connected to the upper plate of the second capacitor C2, and the lower plate of the second capacitor C2 is connected to the power ground end HG of the positive power generation circuit; the connection node between the output end of the second differential charge pump CP_Diff2 and the upper plate of the second capacitor C2 is the signal output end of the positive power generation circuit. In this technical solution, the positive power supply generating circuit is designed with a two-stage differential charge pump to achieve two boosts of the conventional power supply, thereby providing a sufficiently large output voltage floating range for the positive reference power supply generating circuit and the positive floating power supply generating circuit.

[0012] Furthermore, the positive reference power supply generating circuit includes a first operational amplifier AMP1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor (R6), a third capacitor C3 and a fourth capacitor C4; one end of the first resistor R1 is used to input the floating voltage control signal VIN_VC, and the other end of the first resistor R1 is connected to the positive input end of the first operational amplifier AMP1; one end of the second resistor R2 is used to input the voltage to be applied VIN_VADD, and the other end of the second resistor R2 is connected to the positive input end of the first operational amplifier AMP1; one end of the third resistor R3 is connected to the positive input end of the first operational amplifier AMP1, and the other end of the third resistor R3 is connected to the power ground end HG of the positive reference power supply generating circuit; one end of the fourth resistor R4 is connected to the negative input end of the first operational amplifier AMP1, and the other end of the fourth resistor R4 is connected to the power ground end HG of the positive reference power supply generating circuit; one end of the fifth resistor R5 is connected to the first operational amplifier The first operational amplifier AMP1 is connected to the negative input terminal of the first operational amplifier AMP1, the other end of the fifth resistor R5 is connected to the output terminal of the first operational amplifier AMP1; one end of the third capacitor C3 is connected to the output terminal of the first operational amplifier AMP1, the other end of the third capacitor C3 is connected to the power ground terminal HG of the positive reference power generation circuit, one end of the sixth resistor R6 is connected to the output terminal of the first operational amplifier AMP1, the other end of the sixth resistor R6 is connected to the upper plate of the fourth capacitor C4, the connection node between the other end of the sixth resistor R6 and the upper plate of the fourth capacitor C4 is the signal output terminal of the positive reference power generation circuit, and the lower plate of the fourth capacitor C4 is connected to the power ground terminal HG of the positive reference power generation circuit; the power supply terminal of the first operational amplifier AMP1 is connected to the signal output terminal of the positive power generation circuit, the power ground terminal of the first operational amplifier AMP1 is connected to the power ground terminal HG of the positive floating power generation circuit, and the reference source input terminal IBN set by the first operational amplifier AMP1 is used to input the first reference current IBN1. This technical solution uses resistors R1 to R5 and a first operational amplifier AMP1 to form an adding circuit, so that the positive reference power supply voltage VDDH_REF is equal to the voltage sum of the floating voltage control signal VIN_VC and the pre-configured added voltage VIN_VADD, and changes in real time with the control voltage VC, so that the voltage difference between the positive floating power supply voltage VDDH_VC and the control voltage VC is maintained at a constant value.

[0013] Further, the positive floating power supply generating circuit includes a second operational amplifier AMP2 and a fifth capacitor C5; the positive input terminal of the second operational amplifier AMP2 is connected to the signal output terminal of the positive reference power supply generating circuit, the negative input terminal of the second operational amplifier AMP2 is connected to the output terminal of the second operational amplifier AMP2, the output terminal of the second operational amplifier AMP2 is connected to the upper plate of the fifth capacitor C5, the lower plate of the fifth capacitor C5 is connected to the power ground terminal HG of the positive floating power supply generating circuit, and the connection node between the output terminal of the second operational amplifier AMP2 and the upper plate of the fifth capacitor C5 is the signal output terminal of the positive floating power supply generating circuit; the power supply terminal HV of the second operational amplifier AMP2 is connected to the signal output terminal of the positive power supply generating circuit, the power ground terminal HG of the second operational amplifier AMP2 is connected to the power ground terminal HG of the positive floating power supply generating circuit, and the reference source input terminal IBN set by the second operational amplifier AMP2 is used to input the second reference current IBN2. The load capacity of the addition output signal of the positive reference power generation circuit is enhanced, so that the signal output end of the positive floating power generation circuit outputs the positive floating power voltage VDDH_VC with anti-interference characteristics.

[0014] Further, the negative floating power supply circuit includes a negative power supply generating circuit, a negative reference power supply generating circuit and a negative floating power supply generating circuit, and the negative power supply generating circuit, the negative reference power supply generating circuit and the negative floating power supply generating circuit are all provided with a power supply terminal and a power ground terminal, wherein the power supply terminals provided in the aforementioned circuits are all connected to the power supply terminal of the negative floating power supply circuit; the power supply terminal of the operational amplifier inside the negative reference power supply generating circuit and the power supply terminal of the operational amplifier inside the negative floating power supply generating circuit are both connected to the power supply terminal HV of the negative power supply generating circuit; the power ground terminal of the operational amplifier inside the negative floating power supply generating circuit and the power ground terminal of the operational amplifier inside the negative reference power supply generating circuit are both connected to the signal output terminal of the negative power supply generating circuit, and the signal output terminal of the negative reference power supply generating circuit is connected to the positive input terminal of the operational amplifier inside the negative floating power supply generating circuit; the negative reference power supply generating circuit The circuit includes a subtraction circuit composed of an operational amplifier and a resistor, so that the floating voltage control signal VIN_VC is input into the positive input terminal of the operational amplifier inside the negative reference power generation circuit through the resistor, the pre-configured voltage to be subtracted VIN_VDIV is input into the negative input terminal of the operational amplifier inside the negative reference power generation circuit through the resistor, and the signal output terminal of the negative reference power generation circuit outputs the negative reference power voltage VSSL_REF to the positive input terminal of the negative floating power generation circuit; the signal output terminal of the negative floating power generation circuit outputs the negative floating power voltage VSSL_VC with anti-interference characteristics, wherein the negative reference power voltage VSSL_REF is equal to the voltage difference between the floating voltage control signal VIN_VC and the pre-configured voltage to be subtracted VIN_VDIV, so that the voltage difference between the negative floating power voltage VSSL_VC and the control voltage VC is maintained at a constant value.

[0015] Further, the negative power supply generating circuit includes a third inverter INV3, a fourth inverter INV4, a third differential charge pump CP_Diff3, a fourth differential charge pump CP_Diff4, a sixth capacitor C6 and a seventh capacitor C7; the output end of the third inverter INV3 is connected to the input end of the fourth inverter INV4, the input end of the third differential charge pump CP_Diff3 is connected to the output end of the fourth differential charge pump CP_Diff4, the input end of the third inverter INV3 is used to input a clock signal outside the negative floating power supply circuit, the positive clock input end of the third differential charge pump CP_Diff3 and the positive clock input end of the fourth differential charge pump CP_Diff4 are both connected to the output end of the third inverter INV3, and the negative clock input end of the third differential charge pump CP_Diff3 and the negative clock input end of the fourth differential charge pump CP_Diff4 are both connected to the fourth inverter INV4. The output end of the negative power generation circuit is connected; the power supply end of the third inverter INV3 and the power supply end of the fourth inverter INV4 are connected to the power supply end HV of the negative power generation circuit; the power ground end of the third inverter INV3, the power ground end of the fourth inverter INV4 and the output end of the third differential charge pump CP_Diff3 are all connected to the power ground end HG of the negative power generation circuit; the output end of the fourth differential charge pump CP_Diff4 is connected to the upper plate of the sixth capacitor C6, and the lower plate of the sixth capacitor C6 is connected to the power ground end HG of the negative power generation circuit; the input end of the fourth differential charge pump CP_Diff4 is connected to the upper plate of the seventh capacitor C7, and the lower plate of the seventh capacitor C7 is connected to the power ground end HG of the negative power generation circuit; the connection node between the input end of the fourth differential charge pump CP_Diff4 and the upper plate of the seventh capacitor C7 is the signal output end of the negative power generation circuit. This technical solution completes the charge transfer process through two stages of oppositely connected differential charge pumps, achieves two voltage reductions of the conventional power supply input to the charge pump, and cooperates with the aforementioned positive power generation circuit to significantly broaden the power supply floating range of the charge pump.

[0016] Further, the negative reference power supply generating circuit includes a third operational amplifier AMP3, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, an eighth capacitor C8 and a ninth capacitor C9; one end of the eighth resistor R8 is used to input the floating voltage control signal VIN_VC, the positive input end of the third operational amplifier AMP3, the positive input end of the third operational amplifier AMP3 and one end of the ninth resistor R9 are all connected to the other end of the eighth resistor R8, and the other end of the ninth resistor R9 is connected to the power ground HG of the negative reference power supply generating circuit; one end of the seventh resistor R7 is used to input the voltage to be reduced VIN_VDIV, and the other end of the seventh resistor R7 is connected to the negative input end of the third operational amplifier AMP3; one end of the tenth resistor R10 is connected to the negative input end of the third operational amplifier AMP3, and the other end of the tenth resistor R10 is connected to the positive input end of the third operational amplifier AMP3 The output end is connected; one end of the eighth capacitor C8 is connected to the output end of the third operational amplifier AMP3, and the other end of the eighth capacitor C8 is connected to the power ground terminal HG of the negative reference power generating circuit; one end of the eleventh resistor R11 is connected to the output end of the third operational amplifier AMP3, and the other end of the eleventh resistor R11 is connected to the upper plate of the ninth capacitor C9, and the connection node between the other end of the eleventh resistor R11 and the upper plate of the ninth capacitor C9 is the signal output end of the negative reference power generating circuit, and the lower plate of the ninth capacitor C9 is connected to the power ground terminal HG of the negative reference power generating circuit; the power supply terminal of the third operational amplifier AMP3 is connected to the power supply terminal HV of the negative floating power generating circuit, and the power ground terminal of the third operational amplifier AMP3 is connected to the signal output end of the negative power generating circuit, and the reference source input terminal IBP set by the third operational amplifier AMP3 is used to input the first reference current IBP1. This technical solution uses resistors R7 to R10 and a third operational amplifier AMP3 to form a subtraction circuit. The negative reference power supply voltage VSSL_REF is equal to the voltage difference between the floating voltage control signal VIN_VC and the pre-configured voltage to be reduced VIN_VDIV. It changes in real time with the change of the control voltage VC, and keeps the voltage difference between the negative floating power supply voltage VSSL_VC and the control voltage VC at the pre-configured voltage to be reduced VIN_VDIV.

[0017] Further, the negative floating power supply generating circuit includes a fourth operational amplifier AMP4 and a tenth capacitor C10; the positive input terminal of the fourth operational amplifier AMP4 is connected to the signal output terminal of the negative reference power supply generating circuit, the negative input terminal of the fourth operational amplifier AMP4 is connected to the output terminal of the fourth operational amplifier AMP4, the output terminal of the fourth operational amplifier AMP4 is connected to the upper plate of the tenth capacitor C10, the connection node between the output terminal of the fourth operational amplifier AMP4 and the upper plate of the tenth capacitor C10 is the signal output terminal of the negative floating power supply generating circuit, and the lower plate of the tenth capacitor C10 is connected to the power ground terminal HG of the negative floating power supply generating circuit; the power supply terminal HV of the fourth operational amplifier AMP4 is connected to the power supply terminal HV of the negative floating power supply generating circuit, the power ground terminal HG of the fourth operational amplifier AMP4 is connected to the signal output terminal of the negative floating power supply generating circuit, and the reference source input terminal IBP set by the fourth operational amplifier AMP4 is used to input the second reference current IBP2. The load capacity of the subtraction output signal of the negative reference power generation circuit is enhanced, so that the signal output end of the negative floating power generation circuit outputs the negative floating power voltage VSSL_VC with anti-interference characteristics.

[0018] Furthermore, inside the level conversion circuit, an inverter chain is provided corresponding to each of the clock pulse signals, and four cascaded inverters are provided in each inverter chain; the input end of the first-stage inverter is used to input the clock pulse signal; the power supply end of the first-stage inverter is used to input the power supply of the phase-locked loop, a resistor is connected between the power supply end of the first-stage inverter and the power supply end of the second-stage inverter, a resistor is connected between the power supply end of the second-stage inverter and the power supply end of the third-stage inverter, the power supply end of the third-stage inverter is directly connected to the power supply end of the fourth-stage inverter, and the power supply end of the fourth-stage inverter is used to input the positive floating power supply voltage VDDH_VC, wherein the voltage of the power supply end of the second-stage inverter is the voltage of the power supply end of the first-stage inverter and the power supply end of the third-stage inverter. The power ground terminal of the first-stage inverter is used to input the power ground of the phase-locked loop, a resistor is connected between the power ground terminal of the first-stage inverter and the power ground terminal of the second-stage inverter, a resistor is connected between the power ground terminal of the second-stage inverter and the power ground terminal of the third-stage inverter, the power ground terminal of the third-stage inverter is directly connected to the power ground terminal of the fourth-stage inverter, and the power ground terminal of the fourth-stage inverter is used to input the negative floating power supply voltage VSSL_VC, wherein the voltage of the power ground terminal of the second-stage inverter is the average voltage of the voltage of the power ground terminal of the first-stage inverter and the voltage of the power ground terminal of the third-stage inverter; the output terminal of the fourth-stage inverter is correspondingly connected to the functional port of the charge pump for controlling the charging switch, wherein the current clock pulse signal is used to turn on or off the switch MOS tube connected to the functional port. The technical solution is used to convert four clock control signals (UP, UPB, DN, DNB) into effective switch control signals in the charging and discharging state corresponding to the positive floating power supply voltage VDDH_VC at the power supply end of the charge pump and the negative floating power supply voltage VSSL_VC at the power ground end of the charge pump. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a simplified structural connection diagram between the frequency detector, phase detector, charge pump and low-pass filter.

[0020] Figure 2 It is the charge pump charging and discharging current curve in the phase-locked loop (the current mismatch is zero at the intersection A).

[0021] Figure 3 The invention discloses an overall structural diagram of a rail-to-rail ultra-low mismatch charge pump circuit, a frequency detector, a phase detector and a low-pass filter powered by a floating power supply.

[0022] Figure 4 It is a circuit structure diagram of a positive floating power supply circuit.

[0023] Figure 5It is a circuit structure diagram of a negative floating power supply circuit.

[0024] Figure 6 Schematic diagram of the structure of an inverter chain inside the level conversion circuit.

[0025] Figure 7 It is a simulation diagram of the output signals of the positive floating power supply circuit and the negative floating power supply circuit.

[0026] Figure 8 It is a simulation diagram of the mismatch between the charging current and the discharging current of a charge pump with a traditional structure.

[0027] Fig. 9 It is a simulation diagram of the mismatch between the charging current and the discharging current of the charge pump under the control of the floating power supply circuit provided in the embodiment of the present invention.

[0028] Fig.10 4 is a current error curve diagram of the charging current and the discharging current of the charge pump according to the embodiment of the present invention. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0030] The phase-locked loop system mainly includes a phase frequency detector PFD, a charge pump CP, a low-pass filter LPF, a voltage-controlled oscillator and an N-divider. The schematic diagram of the partial circuit of a general phase frequency detector PFD, a charge pump CP and a low-pass filter LPF is as follows: Figure 1As shown, the phase frequency detector PFD is composed of two upper and lower D flip-flops and a NAND gate that plays a reset role. The clock input terminals of the upper and lower D flip-flops are respectively used to input the feedback clock signal Fbk and the reference clock signal Fref output by the N frequency divider. The phase frequency detector PFD compares the frequency and phase of the input reference clock signal Fref and the feedback clock signal Fbk, and outputs a signal UP and a signal DN representing the difference between the two. The charge pump CP is mainly composed of a charging current source, a discharging current source, a switch PMOS tube and a switch NMOS tube; the gate of the switch PMOS tube is used to receive the control signal UP output by the output terminal Q of the D flip-flop of the phase frequency detector PFD, and the gate of the switch NMOS tube is used to receive the control signal DN output by the output terminal Q of the D flip-flop of the phase frequency detector PFD. The control signal UP turns on the switch PMOS tube, and the charging current source outputs the charging current Icharge. The control signal DN turns on the switch NMOS tube, and the discharge current source outputs the discharge current Idischarge. The low-pass filter LPF is a passive low-pass filter, generally second-order and third-order are more commonly used, mainly composed of a resistor-capacitor network, and the drain of the switch MOS tube is connected to the connection node of the resistor and the capacitor. Among them, the charge pump CP converts the control signal output by the phase frequency detector PFD into the charge and discharge current of the low-pass filter LPF, and the low-pass filter LPF converts the charge and discharge current into the control voltage VC of the voltage-controlled oscillator.

[0031] In the locking process of the phase-locked loop, the frequency detector performs frequency and phase detection on the reference clock signal Fref and the feedback clock signal Fbk, and outputs the control signal UP and the control signal DN to control the switch MOS tube of the charge pump to turn on and off, and realizes the control of the control voltage VC of the voltage-controlled oscillator through the low-pass filter. When the phase-locked loop is locked, the frequency detector will continue to compare the frequency fref of the reference clock signal and the frequency fbk of the feedback clock signal, and output two narrow pulse control signals UP and DN with the same pulse width to control the charge and discharge switches of the charge pump, so that the charge switch MOS tube and the discharge switch MOS tube are turned on briefly at the same time to avoid falling into the dead zone. Since the opening widths of the two control signals UP and DN to control the switch MOS tube are completely consistent when the phase lock is stable, the charge pump controls the charge flowing into the low-pass filter to be equal to the charge flowing out, and the control voltage VC is kept unchanged, thereby locking the oscillation frequency output by the voltage-controlled oscillator at the target frequency. However, since the control voltage VC imposes non-ideal factors on the charge and discharge current source of the charge pump, the charge current and discharge current of the charge pump to the low-pass filter are not equal when the control voltage VC changes. like Figure 2As shown, the charging current Icharge and the discharging current Idischarge are equal only at the intersection A. When the control voltage VC is lower than the voltage at point A, the charging current Icharge is greater than the discharging current Idischarge; when the control voltage VC is higher than the voltage at point A, the charging current Icharge is less than the discharging current Idischarge. Figure 2 From the curve change trend, we can see that as the control voltage VC moves away from point A, the current mismatch gradually increases. When the control voltage VC is too high or too low, the MOS tube that constitutes the charge pump current source enters the linear region, and the mismatch between the charge current and the discharge current of the charge pump increases sharply. Therefore, when there is no serious mismatch in the internal current source of the charge pump, the corresponding control voltage VC interval is the normal working range of the charge pump. Theoretically, the limit that the charge pump can reach is a charge pump with zero current mismatch in the full adjustment range. The aforementioned full adjustment range is that the control voltage VC is between the conventional power supply and the ground terminal (between 0 and 3.3V). In fact, zero current mismatch is difficult to achieve, and it can only be close to zero current mismatch. Therefore, the charge pump with this characteristic is called a rail-to-rail ultra-low mismatch charge pump.

[0032] Figure 2 The figure shows the charging current curve Icharge and the discharging current curve Idischarge of the traditional charge pump. It can be seen that the charging and discharging currents are equal at point A, that is, the current mismatch is zero at point A. The position of point A will also change due to the different structures and device parameters of the charge pump. By adjusting the parameters of the charge pump, point A can be adjusted to move to the vicinity of the middle coordinate position of the horizontal axis. When the control voltage VC is lower than the voltage at point A, the charging current Icharge is greater than the discharging current Idischarge; when the control voltage VC is higher than the voltage at point A, the charging current Icharge is less than the discharging current Idischarge; as long as the control voltage VC is not equal to the voltage corresponding to point A, Figure 1 The drain-source voltage of the charging current source and the drain-source voltage of the discharging current source of the charge pump will change, resulting in current mismatch. On the other hand, when the phase-locked loop is stably locked, since the control voltage VC is associated with the oscillation frequency of the voltage-controlled oscillator, when the control voltage VC is not at the middle voltage (average value voltage) between the power supply of the charge pump and the power ground, the voltage difference between the power supply of the charge pump and the control voltage VC is not equal to the voltage difference between the control voltage VC and the power ground of the charge pump, and there are parasitic capacitors in the charging path and discharge circuit inside the charge pump. Therefore, when the charge and discharge switches of the charge pump are turned on at the same time, the required charges of the parasitic capacitors on the charging path and the discharging path are also different. The difference in the amount of charge stored in the parasitic capacitors on the two paths needs to be supplemented by the charge on the output capacitor of the low-pass filter, thus generating a charge sharing effect, which causes the burr problem of the low-pass filter.

[0033] To this end, the embodiment of the present invention provides a rail-to-rail ultra-low mismatch charge pump circuit powered by a floating power supply. The overall circuit is as follows: Figure 3As shown, in a phase-locked loop to which the rail-to-rail ultra-low mismatch charge pump circuit is applicable, the four clock control signals UP, UPB, DN, and DNB output by the frequency detector and the phase detector for controlling the charge and discharge switches of the charge pump control the charge pump to output the charge and discharge current to the low-pass filter, and the low-pass filter converts the charge and discharge current signal into a control voltage VC for adjusting the oscillation frequency of the voltage-controlled oscillator; the rail-to-rail ultra-low mismatch charge pump circuit includes a floating power supply circuit, a charge pump, and a level conversion circuit, the floating control terminal of the floating power supply circuit is used to input a floating voltage control signal VIN_VC that is kept equal to the control voltage VC in real time, and generates a positive signal that follows the change of the control voltage VC based on the operation result of the floating voltage control signal VIN_VC and a pre-configured voltage signal. A floating power supply voltage VDDH_VC and a negative floating power supply voltage VSSL_VC; a floating power supply output terminal of the floating power supply circuit is connected to the power supply terminal of the charge pump, so as to provide the charge pump with a positive floating power supply voltage VDDH_VC; a floating ground output terminal of the floating power supply circuit is connected to the power ground terminal of the charge pump, so as to provide the charge pump with a negative floating power supply voltage VSSL_VC; wherein both the positive floating power supply voltage VDDH_VC and the negative floating power supply voltage VSSL_VC maintain a constant difference with the control voltage VC, and the constant difference is a pre-configured voltage difference when the charging current and the discharging current of the charge pump are equal; by adjusting the charge pump parameters, the control voltage VC is always at the positive floating power supply voltage VDDH_VC and the negative floating power supply voltage The embodiment adopts a level conversion circuit LS to convert the four clock control signals UP, UPB, DN, and DNB under the traditional power supply and ground voltage output by the phase frequency detector PFD into effective switch control signals in the charging state and the discharging state corresponding to the positive floating power supply voltage VDDH_VC of the power supply end of the charge pump and the negative floating power supply voltage VSSL_VC of the power ground end of the charge pump respectively. The enable signal EN is connected to the enable control end of the charge pump after passing through the level conversion circuit LS to start enabling the charge and discharge operation of the charge pump; the four conversion input ends provided by the level conversion circuit are respectively used to input the four clock control signals (UP, UPB, DN, and DNB) under the traditional power supply state. B), and convert and output four clock control signals (UP1, UPB1, DN1, DNB1) in a floating power supply state, wherein, in the floating power supply state, the power supply is a positive floating power supply voltage VDDH_VC, and the power ground is a negative floating power supply voltage VSSL_VC; the four conversion output terminals of the level conversion circuit are correspondingly connected to the four clock control input terminals of the charge pump, and are used to receive the four clock control signals (UP1, UPB1, DN1, DNB1) in a floating power supply state, so that the charge pump performs the same switch control function as before the conversion, so as to achieve the adaptation of the rail-to-rail ultra-low mismatch charge pump circuit and the four clock control signals (UP1, UPB1, DN1, DNB1) transmitted by the frequency detector and phase detector.

[0034] When this embodiment is put into practical application, compared with the prior art, it is only necessary to add a floating power supply circuit and a level conversion circuit, and change the power supply mode of the existing charge pump, and the circuit part related to avoiding the burr problem caused by charge sharing in the traditional charge pump can be deleted as needed; in addition, when designing the layout, it should be noted that the charge pump and other circuit modules are isolated. The floating power supply circuit controls the voltage difference between the positive floating power supply voltage and the negative floating power supply voltage to be constant, and makes the control voltage VC always be at the middle value between the positive floating power supply voltage VDDH_VC and the negative floating power supply voltage VSSL_VC, thereby meeting the high matching requirements of the entire phase-locked loop for the charge and discharge current output by the charge pump within the corresponding power supply voltage working range, and also avoids the charge sharing problem causing the control voltage VC output by the low-pass filter to the voltage-controlled oscillator to produce burrs.

[0035] Specifically, in the present embodiment, the floating power supply circuit includes a positive floating power supply circuit and a negative floating power supply circuit. The power supply terminals HV of the positive floating power supply circuit and the negative floating power supply circuit are both used to input the power supply HV of the phase-locked loop, and the power ground terminals HG of the positive floating power supply circuit and the negative floating power supply circuit are both used to input the ground power HG of the phase-locked loop. The positive reference power supply generating circuit inside the positive floating power supply circuit and the negative reference power supply generating circuit inside the negative floating power supply circuit both input the floating voltage control signal VIN_VC which is kept equal to the control voltage VC in real time. The floating voltage control signal VIN_VC is generated after the control voltage VC is isolated and transformed. The positive floating power supply generating circuit inside the positive floating power supply circuit is used to generate a positive floating power supply voltage VDDH_VC which changes with the control voltage VC, and output it to the power supply terminal of the charge pump, replacing the power supply VDD of the traditional charge pump to broaden the floating range of the power supply of the charge pump. The difference between the positive floating power supply voltage VDDH_VC and the control voltage VC is controlled by the pre-configuration signal VIN_VADD input to the positive floating power supply circuit. The pre-configuration signal VIN_VADD is controlled by Figure 2 The voltage value corresponding to the intersection point A of the charge current and discharge current curves of the charge pump is determined. Figure 2 The control voltage VC corresponding to point A is 1.65V, so in this embodiment, VIN_VADD=1.65V is set to obtain VDDH_VC=VC+1.65V; the negative floating power generation circuit inside the negative floating power circuit is used to generate a negative floating power voltage VSSL_VC that follows the change of the control voltage VC, and output it to the power ground terminal of the charge pump, replacing the ground terminal GND of the traditional charge pump to widen the floating range of the ground voltage of the charge pump, wherein the difference between the control voltage VC and the negative floating power voltage VSSL_VC is controlled by the pre-configuration signal VIN_VDIV input to the negative floating power circuit, and the pre-configuration signal VIN_VDIV is controlled by Figure 2 The voltage value corresponding to the intersection point A of the charge current and discharge current curves of the charge pump is determined. Figure 2 The control voltage VC corresponding to point A is 1.65V, so in this embodiment, VIN_VDIV=1.65V is set, and VSSL_VC=VC-1.65V is obtained. Therefore, the difference between the positive floating power supply voltage VDDH_VC and the negative floating power supply voltage VSSL_VC is: VDDH_VC-VSSL_VC=VC+1.65V-VC+1.65V=3.3V, that is, as the control voltage VC changes, the difference between the positive and negative floating power supplies of the input charge pump processed by the floating power supply circuit is constant at 3.3V, wherein the difference between the positive floating power supply voltage VDDH_VC and the control voltage VC is stabilized at 1.65V, that is, Figure 2 The voltage value of the pre-configured signal VIN_VADD corresponding to point A; the difference between the negative floating power supply voltage VSSL_VC and the control voltage VC is stabilized at 1.65V, that is, Figure 2 The voltage value of the pre-configured signal VIN_VDIV corresponding to point A of the charge pump is guaranteed to work stably at Figure 2 The charging current and discharge current curves are at the intersection of point A. It is worth noting that for the charge sharing problem of the charge pump: the rail-to-rail ultra-low mismatch charge pump circuit provided in this embodiment ensures that the control voltage VC is always at the middle value of the power supply voltage and the ground voltage of the charge pump, that is, the average value of the positive floating power supply voltage VDDH_VC and the negative floating power supply voltage VSSL_VC, which is equal to the formula average value of the positive floating power supply voltage VDDH_VC and the negative floating power supply voltage VSSL_VC, so that the charging charge required by the parasitic capacitors on the charging path and the discharge path inside the charge pump is equivalent, and the respective charge requirements will not change, which fundamentally solves the burr problem caused by charge sharing. Compared with the traditional charge pump by adding a unit gain voltage follower and related circuit structures, this embodiment does not add additional circuits, and only needs to ensure the average voltage value from point A to the aforementioned point.

[0036] Combination Figure 4It can be seen that the positive floating power supply circuit includes a positive power supply generating circuit, a positive reference power supply generating circuit and a positive floating power supply generating circuit. The positive power supply generating circuit, the positive reference power supply generating circuit and the positive floating power supply generating circuit are all provided with a power supply terminal HV and a power ground terminal HG, wherein the power ground terminal HG provided in the aforementioned circuits are all connected to the power ground terminal HG of the positive floating power supply circuit; the power supply terminal HV of the positive power supply generating circuit is the power supply terminal HV of the positive floating power supply circuit, and the power supply terminals HV of the positive reference power supply generating circuit and the positive floating power supply generating circuit are connected to the signal output terminal VDDH_H of the positive power supply generating circuit. The power ground terminal HG of the operational amplifier inside the positive reference power generation circuit and the power ground terminal HG of the operational amplifier inside the positive floating power generation circuit are both connected to the power ground terminal HG of the positive power generation circuit; the power supply terminal HV of the operational amplifier inside the positive reference power generation circuit and the power supply terminal HV of the operational amplifier inside the positive floating power generation circuit are both connected to the signal output terminal VDDH_H of the positive power generation circuit, and are used to receive the high power supply voltage VDDH_H output by the level-boosting conversion of the normal power supply voltage HV by the positive power generation circuit; the signal output terminal VDDH_REF of the positive reference power generation circuit is connected to the positive input terminal IN+ of the operational amplifier inside the positive floating power generation circuit, and the positive reference power generation circuit includes an operational amplifier and a resistor. The adding circuit is configured such that the floating voltage control signal VIN_VC and the pre-configured voltage to be added VIN_VADD are input to the positive input terminal IN+ of the operational amplifier inside the positive reference power supply generating circuit via a resistor, so that the positive reference power supply voltage VDDH_REF outputted from the signal output terminal of the positive reference power supply generating circuit is equal to the voltage sum of the floating voltage control signal VIN_VC and the pre-configured voltage to be added VIN_VADD, and the signal output terminal of the positive floating power supply generating circuit outputs the positive floating power supply voltage VDDH_VC having anti-interference characteristics, so that the voltage difference between the positive floating power supply voltage VDDH_VC and the control voltage VC is maintained at the voltage value of the pre-configured voltage to be added VIN_VADD. This embodiment mainly discloses a positive power supply generating circuit, a positive reference power supply generating circuit and a positive floating power supply generating circuit, wherein the positive floating power supply circuit includes an internal connection relationship, and the positive floating power supply circuit uses an adder composed of a two-stage boost differential charge pump and an operational amplifier to widen the input working power supply range of the charge pump, so that the charge pump can work in a wider range of power supply domains after being connected to the positive floating power supply circuit, and these power supply domains cannot support the normal operation of the charge pump before it is connected to the positive floating power supply circuit. Compared with the prior art, this embodiment dynamically widens the positive floating power supply voltage range of the charge pump.

[0037] It is worth noting that the rail-to-rail output characteristic is that the output voltage range allowed by the positive power supply generating circuit and the negative power supply generating circuit is larger than the voltage variation range of the power supply and the power supply ground of the rail-to-rail ultra-low mismatch charge pump circuit, so that the variable range of the control voltage VC at the output end is the same as the power supply and the power supply ground of other circuit modules of the phase-locked loop (phase frequency detector PFD, voltage controlled oscillator VCO and N divider), that is, the operating range of the control voltage VC at the output end of the rail-to-rail ultra-low mismatch charge pump circuit is the same as the power supply voltage of the phase-locked loop circuit (rail to rail).

[0038] like Figure 4 As shown, the positive power generation circuit includes a first inverter INV1, a second inverter INV2, a first differential charge pump CP_Diff1, a second differential charge pump CP_Diff2, a first capacitor C1 and a second capacitor C2; the output terminal Vout of the first inverter INV1 is connected to the input terminal Vin of the second inverter INV2, forming a two-stage cascade inverter; the output terminal Vout of the first differential charge pump CP_Diff1 is connected to the input terminal Vin of the second differential charge pump CP_Diff2, forming a two-stage cascade differential charge pump; the power supply terminal of the first inverter INV1, the power supply terminal of the second inverter INV2, and the input terminal Vin of the first differential charge pump CP_Diff1 are connected to the power supply terminal HV of the positive power generation circuit; the power ground terminal of the first inverter INV1 and the power ground terminal of the second inverter INV2 are both connected to the power ground terminal HG of the positive power generation circuit.

[0039] The input end of the first inverter INV1 is used to input the clock signal outside the positive floating power supply circuit. The positive clock input end clk+ of the first differential charge pump CP_Diff1 and the positive clock input end clk+ of the second differential charge pump CP_Diff2 are both connected to the output end of the first inverter INV1. The negative clock input end clk- of the first differential charge pump CP_Diff1 and the negative clock input end clk- of the second differential charge pump CP_Diff2 are both connected to the output end of the second inverter INV2. The clock signal CLK outside the positive floating power supply circuit passes through the first inverter INV1 to generate an opposite clock signal to the positive clock input end clk+. The clock signal CLK continuously passes through the first inverter INV1 and the second inverter INV2 to generate an opposite clock signal to the negative clock input end clk-, forming a differential clock input. Another function of the first inverter INV1 and the second inverter INV2 is to enhance the driving capability of the clock signal, that is, to provide a sufficiently large current for the differential charge pump.

[0040] The input terminal Vin of the second differential charge pump CP_Diff2 is connected to the upper plate of the first capacitor C1, and the lower plate of the first capacitor C1 is connected to the power ground terminal HG of the positive power generating circuit; the output terminal Vout of the second differential charge pump CP_Diff2 is connected to the upper plate of the second capacitor C2, and the lower plate of the second capacitor C2 is connected to the power ground terminal HG of the positive power generating circuit; the connection node between the output terminal Vout of the second differential charge pump CP_Diff2 and the upper plate of the second capacitor C2 is the signal output terminal VDDH_H of the positive power generating circuit.

[0041] In this embodiment, the function of the differential charge pump is to transfer the charge of the input terminal Vin to its internal capacitor first through the high and low changes of the differential clock, and then transfer it again to the output capacitor connected to the output terminal Vout to achieve the function of voltage boosting, so the first differential charge pump CP_Diff1 (first-stage differential charge pump) boosts the voltage and stores it on the first capacitor C1 (output capacitor), and the second differential charge pump CP_Diff2 (second-stage differential charge pump) boosts the voltage again. Since the input voltage of the second differential charge pump CP_Diff2 has been boosted by the first differential charge pump CP_Diff1, the second differential charge pump CP_Diff2 boosts the output voltage of the first differential charge pump CP_Diff1 for a second time, thereby reaching a higher voltage value, which is stored on the second capacitor C2 (output capacitor) and serves as the output signal VDDH_H of the positive power supply generating circuit.

[0042] like Figure 4 As shown, the positive reference power generation circuit includes a first operational amplifier AMP1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor (R6), a third capacitor C3 and a fourth capacitor C4.

[0043] One end of the first resistor R1 is used to input the floating voltage control signal VIN_VC, and the other end of the first resistor R1 is connected to the positive input terminal IN+ of the first operational amplifier AMP1; one end of the second resistor R2 is used to input the voltage to be applied VIN_VADD, and the other end of the second resistor R2 is connected to the positive input terminal IN+ of the first operational amplifier AMP1; one end of the third resistor R3 is connected to the positive input terminal IN+ of the first operational amplifier AMP1, and the other end of the third resistor R3 is connected to the power ground terminal HG of the positive reference power generation circuit; one end of the fourth resistor R4 is connected to The negative input terminal IN- of the first operational amplifier AMP1 is connected, and the other end of the fourth resistor R4 is connected to the power ground terminal HG of the positive reference power generation circuit; one end of the fifth resistor R5 is connected to the negative input terminal IN- of the first operational amplifier AMP1, and the other end of the fifth resistor R5 is connected to the output terminal OUT+ of the first operational amplifier AMP1; wherein the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the first operational amplifier AMP1 constitute an in-phase addition circuit, and in this embodiment, R1=R2=R3=R4=2*R5 is set. According to the output voltage calculation formula of the in-phase addition circuit, the output voltage of the first operational amplifier AMP1 is equal to the sum of VIN_VADD and VIN_VC.

[0044] One end of the third capacitor C3 is connected to the output terminal OUT+ of the first operational amplifier AMP1, the other end of the third capacitor C3 is connected to the power ground terminal HG of the positive reference power generating circuit, one end of the sixth resistor R6 is connected to the output terminal OUT+ of the first operational amplifier AMP1, the other end of the sixth resistor R6 is connected to the upper plate of the fourth capacitor C4, the connection node between the other end of the sixth resistor R6 and the upper plate of the fourth capacitor C4 is the signal output terminal VDDH_REF of the positive reference power generating circuit, and the lower plate of the fourth capacitor C4 is connected to the power ground terminal HG of the positive reference power generating circuit; wherein, the third capacitor C3, the fourth capacitor C4 and the sixth resistor R6 form a low-pass filter for filtering out the signal ripple at the output terminal OUT+ of the first operational amplifier AMP1, C3 is approximately equal to 0.1*C4, and the value of the sixth resistor R6 is adjusted according to the actual capacitance values ​​of the third capacitor C3 and the fourth capacitor C4.

[0045] The power supply terminal HV of the first operational amplifier AMP1 is connected to the signal output terminal VDDH_H of the positive power supply generating circuit, and the positive power supply generating circuit raises the power supply voltage HV to a higher positive power supply voltage VDDH_H as the power supply of the first operational amplifier AMP1; the power ground terminal HG of the first operational amplifier AMP1 is connected to the power ground terminal HG of the positive reference power supply generating circuit, and the reference source input terminal IBN set in the first operational amplifier AMP1 is used to input an external first reference current IBN1.

[0046] In this embodiment, the positive reference power supply generating circuit uses resistors R1 to R5 and a first operational amplifier AMP1 to form an adding circuit, so that the positive reference power supply voltage VDDH_REF is equal to the voltage sum of the floating voltage control signal VIN_VC and the pre-configured voltage to be applied VIN_VADD, and changes in real time with the change of the control voltage VC, keeping the voltage difference between the positive reference power supply voltage VDDH_REF and the control voltage VC at the voltage of the pre-configured voltage to be applied VIN_VADD.

[0047] like Figure 4 As shown, the positive floating power supply generating circuit includes a second operational amplifier AMP2 and a fifth capacitor C5; the output terminal OUT+ of the second operational amplifier AMP2 is connected to the upper plate of the fifth capacitor C5, the lower plate of the fifth capacitor C5 is connected to the power ground terminal HG of the positive floating power supply generating circuit, and the connection node between the output terminal OUT+ of the second operational amplifier AMP2 and the upper plate of the fifth capacitor C5 is the signal output terminal VDDH_VC of the positive floating power supply generating circuit, wherein the fifth capacitor C5 serves as the output capacitor of the positive floating power supply generating circuit and plays a role in filtering the ripple of the output signal VDDH_VC; the power supply terminal HV of the second operational amplifier AMP2 is connected to the signal output terminal VDDH_H of the positive power supply generating circuit, the power ground terminal HG of the second operational amplifier AMP2 is connected to the power ground terminal HG of the positive floating power supply generating circuit, and the reference source input terminal IBN set by the second operational amplifier AMP2 is used to input the second reference current IBN2.

[0048] The positive input terminal IN+ of the second operational amplifier AMP2 is connected to the signal output terminal VDDH_REF of the positive reference power supply generating circuit, and the negative input terminal IN- of the second operational amplifier AMP2 is connected to the output terminal OUT+ of the second operational amplifier AMP2. The second operational amplifier AMP2 is connected in the form of a voltage follower circuit, so that the voltage at the output terminal OUT+ of the second operational amplifier AMP2 is the same as the voltage at the positive input terminal IN+ of the second operational amplifier AMP2, thereby improving the load capacity of the signal output terminal VDDH_VC signal of the positive floating power supply generating circuit, and the aforementioned connected voltage follower plays the role of impedance transformation, so that the signal output terminal of the positive floating power supply generating circuit outputs the positive floating power supply voltage VDDH_VC with anti-interference characteristics. Ensure the stable operation of the charge pump.

[0049] like Figure 5As shown, the negative floating power supply circuit includes a negative power supply generating circuit, a negative reference power supply generating circuit and a negative floating power supply generating circuit, and the negative power supply generating circuit, the negative reference power supply generating circuit and the negative floating power supply generating circuit are all provided with a power supply terminal HV and a power ground terminal HG, wherein the power supply terminals HV provided in the aforementioned circuits are all connected to the power supply terminal HV of the positive floating power supply circuit; the power supply terminal HV of the negative power supply generating circuit is the power supply terminal HV of the negative floating power supply circuit, and the power ground terminal HG of the negative power supply generating circuit is the power ground terminal HG of the negative floating power supply circuit. The power supply terminal HV of the operational amplifier inside the negative reference power supply generating circuit and the power supply terminal HV of the operational amplifier inside the negative reference power supply generating circuit are both connected to the power supply terminal HV of the negative power supply generating circuit; the power ground terminal HG of the operational amplifier inside the negative floating power supply generating circuit and the power ground terminal HG of the operational amplifier inside the negative reference power supply generating circuit are both connected to the signal output terminal VSSL_L of the negative power supply generating circuit, and are used to receive the low power supply voltage VSSL_L output by the conventional power ground HG after the step-down conversion of the negative power supply generating circuit; the signal output terminal VSSL_REF of the negative reference power supply generating circuit is connected to the positive input terminal IN+ of the operational amplifier inside the negative floating power supply generating circuit, and the floating voltage control signal VIN_VC is input to the positive input terminal of the operational amplifier inside the negative reference power supply generating circuit through a resistor. IN+, the negative reference power supply generating circuit includes a subtraction circuit composed of an operational amplifier and a resistor, and the pre-configured voltage to be subtracted VIN_VDIV is input into the negative input terminal IN- of the operational amplifier inside the negative reference power supply generating circuit through the resistor, so that the signal output terminal of the negative reference power supply generating circuit outputs the negative reference power supply voltage VSSL_REF, and the signal output terminal OUT+ of the negative floating power supply generating circuit outputs the negative floating power supply voltage VSSL_VC with anti-interference characteristics; wherein, the negative floating power supply voltage VSSL_VC is equal to the voltage difference between the floating voltage control signal VIN_VC and the pre-configured voltage to be subtracted VIN_VDIV, and the voltage difference between the negative floating power supply voltage VSSL_VC and the control voltage VC is maintained at the pre-configured voltage value of the voltage to be subtracted VIN_VDIV. This embodiment mainly discloses the circuit connection relationship between a negative power supply generating circuit, a negative reference power supply generating circuit and a negative floating power supply generating circuit. The negative floating power supply circuit uses a subtractor composed of a two-stage step-down differential charge pump and an operational amplifier to widen the floating range of the input working power supply of the charge pump, so that the charge pump can operate in a wider range of power supply domains after being connected to the negative floating power supply circuit. These power supply domains cannot support the normal operation of the charge pump before it is connected to the positive floating power supply circuit.

[0050] like Figure 5As shown, the negative power generation circuit includes a third inverter INV3, a fourth inverter INV4, a third differential charge pump CP_Diff3, a fourth differential charge pump CP_Diff4, a sixth capacitor C6 and a seventh capacitor C7; the output terminal Vout of the third inverter INV3 is connected to the input terminal Vin of the fourth inverter INV4, forming a two-stage cascade inverter; the input terminal Vin of the third differential charge pump CP_Diff3 is connected to the output terminal Vout of the fourth differential charge pump CP_Diff4, forming a two-stage cascade differential charge pump; the power supply terminal of the third inverter INV3 and the power supply terminal of the fourth inverter INV4 are connected to the power supply terminal HV of the negative power generation circuit; the power ground terminal of the third inverter INV3, the power ground terminal of the fourth inverter INV4 and the input terminal Vout of the third differential charge pump CP_Diff3 are all connected to the power ground terminal HG of the negative power generation circuit.

[0051] The input end of the third inverter INV3 is used to input the clock signal CLK outside the negative floating power supply circuit. The positive clock input end CLK+ of the third differential charge pump CP_Diff3 and the positive clock input end CLK+ of the fourth differential charge pump CP_Diff4 are both connected to the output end of the third inverter INV3. The negative clock input end clk- of the third differential charge pump CP_Diff3 and the negative clock input end clk- of the fourth differential charge pump CP_Diff4 are both connected to the output end of the fourth inverter INV4. The clock signal CLK outside the negative floating power supply circuit generates an opposite clock signal to the positive clock input end clk+ through the third inverter INV3. The clock signal CLK continuously passes through the third inverter INV3 and the fourth inverter INV4 to generate an opposite clock signal to the negative clock input end clk-, forming a differential clock input. Another function of the third inverter INV3 and the fourth inverter INV4 is to enhance the driving capability of the clock signal, thereby providing a sufficiently large current for the differential charge pump.

[0052] The output end of the fourth differential charge pump CP_Diff4 is connected to the upper plate of the sixth capacitor C6, and the lower plate of the sixth capacitor C6 is connected to the power ground terminal HG of the negative power generation circuit; the input end of the fourth differential charge pump CP_Diff4 is connected to the upper plate of the seventh capacitor C7, and the lower plate of the seventh capacitor C7 is connected to the power ground terminal HG of the negative power generation circuit; the connection node between the input end of the fourth differential charge pump CP_Diff4 and the upper plate of the seventh capacitor C7 is the signal output terminal VSSL_L of the negative power generation circuit. According to the functional characteristics of the differential charge pump, the fourth differential charge pump CP_Diff4 transfers the charge on the seventh capacitor C7 connected to its input terminal Vin to the sixth capacitor C6 connected to its output terminal Vout, and the voltage (VSSL_L) on the seventh capacitor C7 is lower than the voltage on the sixth capacitor C6, and the third differential charge pump CP_Diff3 transfers the charge on the sixth capacitor C6 connected to its input terminal Vin to the power ground terminal HG of the negative power supply generating circuit connected to its output terminal Vout, and the voltage on the sixth capacitor C6 is lower than the HG voltage, thereby completing the charge transfer process of the two-stage oppositely connected differential charge pump. In this embodiment, the upper plate of the sixth capacitor C6 connected to the output terminal Vout of the fourth differential charge pump CP_Diff4 has been reduced by a certain value due to the action of the third differential charge pump CP_Diff3, so the upper plate of the seventh capacitor C7 is reduced to a lower voltage value through the action of the fourth differential charge pump CP_Diff4, so the generation of the low power supply voltage VSSL_L is achieved through the two-stage differential charge pump. Cooperating with the positive power generation circuit mentioned above, the power supply floating range of the charge pump is significantly widened.

[0053] like Figure 5 As shown, the negative reference power generation circuit includes a third operational amplifier AMP3, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, an eighth capacitor C8 and a ninth capacitor C9.

[0054] One end of the eighth resistor R8 is used to input the floating voltage control signal VIN_VC, the positive input terminal IN+ of the third operational amplifier AMP3 and one end of the ninth resistor R9 are both connected to the other end of the eighth resistor R8, and the other end of the ninth resistor R9 is connected to the power ground terminal HG of the negative reference power generation circuit; one end of the seventh resistor R7 is used to input the voltage to be subtracted VIN_VDIV, and the other end of the seventh resistor R7 is connected to the negative input terminal IN- of the third operational amplifier AMP3; one end of the tenth resistor R10 is connected to the negative input terminal IN- of the third operational amplifier AMP3, and the other end of the tenth resistor R10 is connected to the output terminal OUT+ of the third operational amplifier AMP3; wherein the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10 and the third operational amplifier AMP3 constitute an in-phase subtraction circuit, and in this embodiment, R7=R8=R9=R10 is set. According to the output voltage calculation formula of the in-phase subtraction circuit, the output voltage of the third operational amplifier AMP3 is equal to the difference between VIN_VC and VIN_VDIV.

[0055] One end of the eighth capacitor C8 is connected to the output terminal OUT+ of the third operational amplifier AMP3, and the other end of the eighth capacitor C8 is connected to the power ground terminal HG of the negative reference power generating circuit; one end of the eleventh resistor R11 is connected to the output terminal OUT+ of the third operational amplifier AMP3, and the other end of the eleventh resistor R11 is connected to the upper plate of the ninth capacitor C9, and the connection node between the other end of the eleventh resistor R11 and the upper plate of the ninth capacitor C9 is the signal output terminal VSSL_REF of the negative reference power generating circuit, and the lower plate of the ninth capacitor C9 is connected to the power ground terminal HG of the negative reference power generating circuit; wherein, the eighth capacitor C8, the ninth capacitor C9 and the eleventh resistor R11 form a low-pass filter for filtering out the signal ripple at the output terminal OUT+ of the third operational amplifier AMP3, C8 is approximately equal to 0.1*C9, and the resistance value of the eleventh resistor R11 is adjusted according to the actual capacitance values ​​of the eighth capacitor C8 and the ninth capacitor C9.

[0056] The power supply terminal HV of the third operational amplifier AMP3 is connected to the power supply terminal HV of the negative reference power supply generating circuit, and the power supply terminal HV of the negative reference power supply generating circuit provides a power supply voltage for the third operational amplifier AMP3; the power ground terminal HG of the third operational amplifier AMP3 is connected to the signal output terminal VSSL_L of the negative power supply generating circuit, serving as the power ground input terminal of the third operational amplifier AMP3; the reference source input terminal IBP set in the third operational amplifier AMP3 is used to input the first reference current IBP1.

[0057] In this embodiment, the negative reference power supply generating circuit uses resistors R7 to R10 and a third operational amplifier AMP3 to form a subtraction circuit, so that the negative reference power supply voltage VSSL_REF is equal to the voltage difference between the floating voltage control signal VIN_VC and the pre-configured voltage to be subtracted VIN_VDIV, and changes in real time with the change of the control voltage VC, keeping the voltage difference between the negative reference power supply voltage VSSL_REF and the control voltage VC at a constant value.

[0058] like Figure 5 As shown, the negative floating power supply generating circuit includes a fourth operational amplifier AMP4 and a tenth capacitor C10; the output terminal OUT+ of the fourth operational amplifier AMP4 is connected to the upper plate of the tenth capacitor C10, the connection node between the output terminal OUT+ of the fourth operational amplifier AMP4 and the upper plate of the tenth capacitor C10 is the signal output terminal VSSL_VC of the negative floating power supply generating circuit, the lower plate of the tenth capacitor C10 is connected to the power ground terminal HG of the negative floating power supply generating circuit, wherein the tenth capacitor C10 is the output capacitor of the negative floating power supply generating circuit, and plays a role in filtering the ripple of the output signal VSSL_VC; the power ground terminal HG of the fourth operational amplifier AMP4 is connected to the signal output terminal VSSL_L of the negative floating power supply generating circuit, the power supply terminal HV of the fourth operational amplifier AMP4 is connected to the power supply terminal HV of the negative floating power supply generating circuit, the power supply terminal HV of the negative floating power supply generating circuit provides working power for the fourth operational amplifier AMP4, and the reference source input terminal IBP set by the fourth operational amplifier AMP4 is used to input the second reference current IBP2.

[0059] The positive input terminal IN+ of the fourth operational amplifier AMP4 is connected to the signal output terminal VSSL_REF of the negative reference power supply generating circuit, and the negative input terminal IN- of the fourth operational amplifier AMP4 is connected to the output terminal OUT+ of the fourth operational amplifier AMP4. The fourth operational amplifier AMP4 is connected in the form of a voltage follower circuit, so that the voltage at the output terminal OUT+ of the fourth operational amplifier AMP4 is the same as the voltage at the positive input terminal IN+ of the fourth operational amplifier AMP4, and the aforementioned voltage follower connection plays a role of impedance transformation, thereby improving the load capacity of the output VSSL_VC signal of the negative floating power supply generating circuit, so that the signal output terminal of the negative floating power supply generating circuit outputs the negative floating power supply voltage VSSL_VC with anti-interference characteristics, and the voltage difference between the negative floating power supply voltage VSSL_VC and the control voltage VC is maintained at the pre-configured voltage value of the reduction voltage VIN_VDIV.

[0060] In the level conversion circuit, an inverter chain is provided for each clock pulse signal, and four cascaded inverters are provided in each inverter chain. The input end of the first stage inverter is used to input the clock control signal and the enable control signal EN of the charge pump. Figure 6 As shown, for each inverter chain, the power supply terminal of the first-stage inverter INV31 is used to input the power supply HV of the phase-locked loop, a resistor R31 is connected between the power supply terminal of the first-stage inverter INV31 and the power supply terminal of the second-stage inverter INV32, a resistor R32 is connected between the power supply terminal of the second-stage inverter INV32 and the power supply terminal of the third-stage inverter INV33, the power supply terminal of the third-stage inverter INV33 is directly connected to the power supply terminal of the fourth-stage inverter INV34, and the power supply terminal of the fourth-stage inverter INV34 is used to input the positive floating power supply voltage VDDH_VC; the power ground terminal of the first-stage inverter INV31 is used to input the power ground of the phase-locked loop, and a resistor R33 is connected between the power ground terminal of the first-stage inverter INV31 and the power ground terminal of the second-stage inverter INV32 A resistor R34 is connected between the power ground terminal of the second-stage inverter INV32 and the power ground terminal of the third-stage inverter INV33, the power ground terminal of the third-stage inverter INV33 is directly connected to the power ground terminal of the fourth-stage inverter INV34, and the power ground terminal of the fourth-stage inverter INV34 is used to input the negative floating power supply voltage VSSL_VC; the output end of the fourth-stage inverter INV34 is correspondingly connected to the functional port of the charge pump for controlling the charge and discharge switch, such as the relevant ports UP, UPB, DN, DNB, and EN of the charge pump for controlling the charge and discharge switch, wherein the current clock pulse signal is used to turn on or off the switch MOS tube connected to the functional port, the voltage value output by the inverter matches the positive power supply and negative power supply voltage connected to it, and the first-stage inverter is used to input a control signal with fixed power supply and ground voltages.

[0061] When the resistance value of the resistor R31 is preferably equal to the resistance value of the resistor R32, the intermediate power supply voltage in this preferred example is the power supply terminal voltage of the second-stage inverter INV32, that is, the average voltage of the power supply terminal voltage of the first-stage inverter INV31 and the power supply terminal voltage of the third-stage inverter INV33; the intermediate ground voltage in this preferred example is the power ground terminal voltage of the second-stage inverter INV32, that is, the average voltage of the power ground terminal voltage of the first-stage inverter INV31 and the power ground terminal voltage of the third-stage inverter INV33. Then the output signal of the second-stage inverter INV32 is a control signal that matches the intermediate power supply voltage and the intermediate ground voltage after the resistor connected to the power supply and the ground is transitioned, and the output signal of the third-stage inverter INV33 is a control signal that matches the floating power supply voltage VDDH_VC and the floating ground voltage VSSL_VC. In this way, the control signal under the traditional fixed power supply voltage and ground voltage is converted into the corresponding control signal under the power supply conditions of the floating power supply voltage and ground voltage, but the function to be realized by the control signal remains unchanged. In other embodiments, the resistance value of resistor R31 may not be equal to the resistance value of resistor R32, but the ratio of the two resistance values ​​should meet the actual control requirements of the charge pump. At the same time, the resistance value cannot be set too small to avoid excessive current.

[0062] Therefore, the level conversion circuit provided in this embodiment is used to convert the four clock pulse signals (UP, UPB, DN, DNB) into effective switch control signals in the charge and discharge states corresponding to the positive floating power supply voltage VDDH_VC at the power supply end of the charge pump and the negative floating power supply voltage VSSL_VC at the power ground end of the charge pump, that is, the output level of the inverter of the last stage is pulled up to the target level corresponding to the floating voltage VDDH_VC and VSSL_VC.

[0063] In this embodiment, the positive floating power supply circuit provides the positive floating power supply voltage VDDH_VC for the charge pump, and the negative floating power supply circuit provides the negative floating power supply voltage VSSL_VC for the charge pump, while ensuring that the voltage difference between VDDH_VC and VSSL_VC is constant and equal to 3.3V, and in the process of changing the control voltage VC, VDDH_VC and VSSL_VC change with the change of the VC voltage; the simulation waveforms of the positive floating power supply voltage VDDH_VC and the positive ideal floating power supply voltage VDDH_IDEAL, and the simulation waveforms of the negative floating power supply voltage VSSL_VC and the negative ideal floating power supply voltage VSSL_IDEAL are as shown in FIG. Figure 7 As shown, it can be seen that the actual simulation waveform has a small error with the ideal waveform, and the voltage difference between VDDH_IDEAL and VSSL_IDEAL is constant and equal to 3.3V.

[0064] Based on the above-mentioned embodiment, the positive floating power supply circuit, the negative floating power supply circuit and the corresponding level conversion circuit LS complete the matching of the switch control signal (UP, UPB, DN, DNB) output by the phase frequency detector PFD and the enable control signal (EN) when they are input into the charge pump through the level conversion circuit LS, and convert the fixed power supply and ground signals into the positive floating power supply voltage VDDH_VC and the negative floating power supply voltage VSSL_VC as the control signals of the charge and discharge switch of the charge pump, so that the control signal and the enable signal received by the charge pump can perform their functions normally. The floating power supply circuit changes the power supply mode of the charge pump and can be applied to various phase-locked loops.

[0065] Figure 8 It is a simulation diagram of the charge pump current curve under the traditional structure. The charging current Icharge and the discharging current Idischarge are equal only at the voltage corresponding to point A. In other intervals where the control voltage VC deviates from the voltage corresponding to point A, the charging current Icharge and the discharging current Idischarge are not equal. Fig. 9 It is a current curve simulation diagram of the rail-to-rail ultra-low mismatch charge pump circuit described in this embodiment. The charging current Ichargem23 and the discharging current Idischargem21 remain equal in any interval of the control voltage VC. Through simulation tests, it can be known that the charge pump of the traditional structure has a current error of 0.05% between the charging current Icharge and the discharging current Idischarge within the working range of the control voltage VC of about 0.6V-2.65V, which is about 2nA; the charge pump under this embodiment has a current error of 0.0002% between the charging current Ichargem23 and the discharging current Idischargem21 within the range of the control voltage VC of 0V-3.3V. Compared with the existing structure, this embodiment reduces the charge and discharge current error by 2500 times, and the working range of the control voltage VC output by the charge pump is increased by 50% to the rail-to-rail output range. The charge and discharge current curves of the charge pump under this embodiment are further amplified to obtain the following: Fig.10 As shown in the simulation waveform, within the control voltage VC range of 0-3.3V, the current error between the charge pump's charging current Ichargem and the discharge current Idischargem remains unchanged at 8pA. This error is due to the influence of simulation accuracy and process, and it is difficult to accurately obtain the optimal point A information and control the accuracy close to 0.

[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, ordinary technicians in the field should understand that the specific implementation methods of the present invention can still be modified or some technical features can be replaced by equivalents without departing from the spirit of the technical solution of the present invention, which should be included in the scope of the technical solution for protection of the present invention.

Claims

1. A rail-to-rail ultra-low mismatch charge pump circuit powered by a floating power supply, the rail-to-rail ultra-low mismatch charge pump circuit comprising a charge pump, in a phase-locked loop to which the rail-to-rail ultra-low mismatch charge pump circuit is applicable, a frequency detector and a phase detector output four clock control signals (UP, UPB, DN, DNB) for controlling a charge pump switch, the charge pump outputs a charge and discharge current to a low-pass filter, and the low-pass filter generates a control voltage (VC) for adjusting an oscillation frequency of a voltage-controlled oscillator according to the charge and discharge current, characterized in that: The rail-to-rail ultra-low mismatch charge pump circuit also includes a floating power supply circuit and a level conversion circuit; The floating control terminal of the floating power supply circuit is used to input a floating voltage control signal (VIN_VC) that is kept equal to the control voltage (VC) in real time, and to generate a positive floating power supply voltage (VDDH_VC) and a negative floating power supply voltage (VSSL_VC) that follow the change of the control voltage (VC) based on the operation result of the floating voltage control signal (VIN_VC) and the pre-configured voltage signal; the floating power supply output terminal of the floating power supply circuit is connected to the power supply terminal of the charge pump, and is used to provide the positive floating power supply voltage (VDDH_VC) for the charge pump; the floating ground output terminal of the floating power supply circuit is connected to the power ground terminal of the charge pump, and is used to provide the negative floating power supply voltage (VSSL_VC) for the charge pump; wherein, the positive floating power supply voltage (VDDH_VC) and the negative floating power supply voltage (VSSL_VC) both keep a constant difference with the control voltage (VC), and the constant difference is a pre-configured voltage difference when the charging current and the discharging current of the charge pump are equal; The charge pump is isolated from other circuit modules; The four conversion input terminals of the level conversion circuit are respectively used to input four clock control signals (UP, UPB, DN, DNB) in the traditional power supply state, and convert and output four clock control signals (UP1, UPB1, DN1, DNB1) in the floating power supply state, wherein in the floating power supply state, the power supply is a positive floating power supply voltage (VDDH_VC), and the power ground is a negative floating power supply voltage (VSSL_VC); the four conversion output terminals of the level conversion circuit are correspondingly connected to the four clock control input terminals of the charge pump, and are used to receive the four clock control signals (UP1, UPB1, DN1, DNB1) in the floating power supply state, so that the charge pump performs the same switch control function as before the conversion, so as to achieve the adaptation of the rail-to-rail ultra-low mismatch charge pump circuit and the four clock control signals (UP1, UPB1, DN1, DNB1) transmitted by the frequency detector and phase detector.

2. The rail-to-rail ultra-low mismatch charge pump circuit according to claim 1, characterized in that: The floating power supply circuit includes a positive floating power supply circuit and a negative floating power supply circuit; the power supply terminal of the positive floating power supply circuit and the power supply terminal of the negative floating power supply circuit are both connected to the power supply terminal of the floating power supply circuit, for inputting the power supply of the phase-locked loop; the power ground terminal of the positive floating power supply circuit and the power ground terminal of the negative floating power supply circuit are both connected to the power ground terminal of the floating power supply circuit, for inputting the power ground of the phase-locked loop; the floating control terminal of the positive reference power supply generating circuit and the floating control terminal of the negative reference power supply generating circuit are both connected to the floating control terminal of the floating power supply circuit, for inputting the floating voltage control signal (VIN_VC).

3. The rail-to-rail ultra-low mismatch charge pump circuit according to claim 2, characterized in that: The positive floating power supply circuit comprises a positive power supply generating circuit, a positive reference power supply generating circuit and a positive floating power supply generating circuit; the positive power supply generating circuit, the positive reference power supply generating circuit and the positive floating power supply generating circuit are all provided with a power supply terminal and a power ground terminal, wherein the power ground terminals provided in the aforementioned circuits are all connected to the power ground terminal of the positive floating power supply circuit; The power ground terminal of the operational amplifier inside the positive reference power generation circuit and the power ground terminal of the operational amplifier inside the positive floating power generation circuit are both connected to the power ground terminal (HG) of the positive power generation circuit; the power supply terminal of the operational amplifier inside the positive reference power generation circuit and the power supply terminal of the operational amplifier inside the positive floating power generation circuit are both connected to the signal output terminal of the positive power generation circuit, and the signal output terminal of the positive reference power generation circuit is connected to the positive input terminal of the operational amplifier inside the positive floating power generation circuit; The positive reference power supply generating circuit includes an adding circuit composed of an operational amplifier and a resistor, so that the floating voltage control signal (VIN_VC) and the pre-configured voltage to be added (VIN_VADD) are input into the positive input terminal of the operational amplifier inside the positive reference power supply generating circuit through the resistor, and the signal output terminal of the positive reference power supply generating circuit outputs the positive reference power supply voltage (VDDH_REF) to the positive input terminal of the positive floating power supply generating circuit; the signal output terminal of the positive floating power supply generating circuit outputs the positive floating power supply voltage (VDDH_VC) with anti-interference characteristics, wherein the positive reference power supply voltage (VDDH_REF) is equal to the voltage sum of the floating voltage control signal (VIN_VC) and the pre-configured voltage to be added (VIN_VADD), and the voltage difference between the positive floating power supply voltage (VDDH_VC) and the control voltage (VC) is maintained at the voltage value of the pre-configured voltage to be added (VIN_VADD).

4. The rail-to-rail ultra-low mismatch charge pump circuit according to claim 3, characterized in that: The positive power generation circuit includes a first inverter (INV1), a second inverter (INV2), a first differential charge pump (CP_Diff1), a second differential charge pump (CP_Diff2), a first capacitor (C1) and a second capacitor (C2); The output end of the first inverter (INV1) is connected to the input end of the second inverter (INV2), the output end of the first differential charge pump (CP_Diff1) is connected to the input end of the second differential charge pump (CP_Diff2), the input end of the first inverter (INV1) is used to input a clock signal outside the positive floating power supply circuit, the positive clock input end of the first differential charge pump (CP_Diff1) and the positive clock input end of the second differential charge pump (CP_Diff2) are both connected to the output end of the first inverter (INV1), the negative clock input end of the first differential charge pump (CP_Diff1) and the negative clock input end of the second differential charge pump (CP_Diff2) are both connected to the output end of the second inverter (INV2); the power supply end of the first inverter (INV1), the power supply end of the second inverter (INV2), and the first differential The input end of the charge pump (CP_Diff1) is connected to the power supply end (HV) of the positive power generation circuit; the power ground end of the first inverter (INV1) and the power ground end of the second inverter (INV2) are both connected to the power ground end (HG) of the positive power generation circuit; the input end of the second differential charge pump (CP_Diff2) is connected to the upper plate of the first capacitor (C1), and the lower plate of the first capacitor (C1) is connected to the power ground end (HG) of the positive power generation circuit; the output end of the second differential charge pump (CP_Diff2) is connected to the upper plate of the second capacitor (C2), and the lower plate of the second capacitor (C2) is connected to the power ground end (HG) of the positive power generation circuit; the connection node between the output end of the second differential charge pump (CP_Diff2) and the upper plate of the second capacitor (C2) is the signal output end of the positive power generation circuit.

5. The rail-to-rail ultra-low mismatch charge pump circuit according to claim 4, characterized in that: The positive reference power generation circuit comprises a first operational amplifier (AMP1), a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5), a sixth resistor (R6), a third capacitor (C3) and a fourth capacitor (C4); One end of the first resistor (R1) is used to input the floating voltage control signal (VIN_VC), and the other end of the first resistor (R1) is connected to the positive input end of the first operational amplifier (AMP1); one end of the second resistor (R2) is used to input the voltage to be applied (VIN_VADD), and the other end of the second resistor (R2) is connected to the positive input end of the first operational amplifier (AMP1); one end of the third resistor (R3) is connected to the positive input end of the first operational amplifier (AMP1), and the other end of the third resistor (R3) is connected to the power ground end (HG) of the positive reference power generation circuit; One end of the fourth resistor (R4) is connected to the negative input end of the first operational amplifier (AMP1), and the other end of the fourth resistor (R4) is connected to the power ground end (HG) of the positive reference power generation circuit; one end of the fifth resistor (R5) is connected to the negative input end of the first operational amplifier (AMP1), and the other end of the fifth resistor (R5) is connected to the output end of the first operational amplifier (AMP1); One end of the third capacitor (C3) is connected to the output end of the first operational amplifier (AMP1), the other end of the third capacitor (C3) is connected to the power ground end (HG) of the positive reference power generation circuit, one end of the sixth resistor (R6) is connected to the output end of the first operational amplifier (AMP1), the other end of the sixth resistor (R6) is connected to the upper plate of the fourth capacitor (C4), the connection node between the other end of the sixth resistor (R6) and the upper plate of the fourth capacitor (C4) is the signal output end of the positive reference power generation circuit, and the lower plate of the fourth capacitor (C4) is connected to the power ground end (HG) of the positive reference power generation circuit; A power supply terminal of the first operational amplifier (AMP1) is connected to a signal output terminal of the positive power supply generating circuit, a power ground terminal of the first operational amplifier (AMP1) is connected to a power ground terminal (HG) of the positive floating power supply generating circuit, and a reference source input terminal (IBN) set in the first operational amplifier (AMP1) is used to input a first reference current.

6. The rail-to-rail ultra-low mismatch charge pump circuit according to claim 5, characterized in that: The positive floating power supply generating circuit comprises a second operational amplifier (AMP2) and a fifth capacitor (C5); The positive input terminal of the second operational amplifier (AMP2) is connected to the signal output terminal of the positive reference power supply generating circuit, the negative input terminal of the second operational amplifier (AMP2) is connected to the output terminal of the second operational amplifier (AMP2), the output terminal of the second operational amplifier (AMP2) is connected to the upper plate of the fifth capacitor (C5), the lower plate of the fifth capacitor (C5) is connected to the power ground terminal (HG) of the positive floating power supply generating circuit, and the connection node between the output terminal of the second operational amplifier (AMP2) and the upper plate of the fifth capacitor (C5) is the signal output terminal of the positive floating power supply generating circuit; The power supply terminal (HV) of the second operational amplifier (AMP2) is connected to the signal output terminal of the positive power supply generating circuit, the power ground terminal (HG) of the second operational amplifier (AMP2) is connected to the power ground terminal (HG) of the positive floating power supply generating circuit, and the reference source input terminal (IBN) set in the second operational amplifier (AMP2) is used to input a second reference current.

7. The rail-to-rail ultra-low mismatch charge pump circuit according to claim 2, characterized in that: The negative floating power supply circuit comprises a negative power supply generating circuit, a negative reference power supply generating circuit and a negative floating power supply generating circuit, wherein the negative power supply generating circuit, the negative reference power supply generating circuit and the negative floating power supply generating circuit are all provided with a power supply terminal and a power ground terminal, wherein the power supply terminals provided in the aforementioned circuits are all connected to the power supply terminal of the negative floating power supply circuit; The power supply terminal of the operational amplifier in the negative reference power supply generating circuit and the power supply terminal of the operational amplifier in the negative floating power supply generating circuit are both connected to the power supply terminal (HV) of the negative power supply generating circuit; the power ground terminal of the operational amplifier in the negative floating power supply generating circuit and the power ground terminal of the operational amplifier in the negative reference power supply generating circuit are both connected to the signal output terminal of the negative power supply generating circuit, and the signal output terminal of the negative reference power supply generating circuit is connected to the positive input terminal of the operational amplifier in the negative floating power supply generating circuit; The negative reference power supply generating circuit includes a subtraction circuit composed of an operational amplifier and a resistor, so that the floating voltage control signal (VIN_VC) is input into the positive input terminal of the operational amplifier inside the negative reference power supply generating circuit through the resistor, the pre-configured voltage to be reduced (VIN_VDIV) is input into the negative input terminal of the operational amplifier inside the negative reference power supply generating circuit through the resistor, and the signal output terminal of the negative reference power supply generating circuit outputs the negative reference power supply voltage (VSSL_REF) to the positive input terminal of the negative floating power supply generating circuit; the signal output terminal of the negative floating power supply generating circuit outputs the negative floating power supply voltage (VSSL_VC) with anti-interference characteristics, wherein the negative reference power supply voltage (VSSL_REF) is equal to the voltage difference between the floating voltage control signal (VIN_VC) and the pre-configured voltage to be reduced (VIN_VDIV), and the voltage difference between the negative floating power supply voltage (VSSL_VC) and the control voltage (VC) is maintained at the pre-configured voltage to be reduced (VIN_VDIV).

8. The rail-to-rail ultra-low mismatch charge pump circuit according to claim 7, characterized in that: The negative power supply generating circuit comprises a third inverter (INV3), a fourth inverter (INV4), a third differential charge pump (CP_Diff3), a fourth differential charge pump (CP_Diff4), a sixth capacitor (C6) and a seventh capacitor (C7); the output end of the third inverter (INV3) is connected to the input end of the fourth inverter (INV4), the input end of the third differential charge pump (CP_Diff3) is connected to the output end of the fourth differential charge pump (CP_Diff4), the input end of the third inverter (INV3) is used to input a clock signal outside the negative floating power supply circuit, the positive clock input end of the third differential charge pump (CP_Diff3) and the positive clock input end of the fourth differential charge pump (CP_Diff4) are both connected to the output end of the third inverter (INV3), the negative clock input end of the third differential charge pump (CP_Diff3) and the negative clock input end of the fourth differential charge pump (CP_Diff4) are both connected to the output end of the fourth inverter (INV4), and the negative clock input end of the third differential charge pump (CP_Diff3) and the negative clock input end of the fourth differential charge pump (CP_Diff4) are both connected to the output end of the fourth inverter (INV4). The output end of the third inverter (INV3) and the output end of the fourth inverter (INV4) are connected to the power supply end (HV) of the negative power generation circuit; the power ground end of the third inverter (INV3), the power ground end of the fourth inverter (INV4) and the output end of the third differential charge pump (CP_Diff3) are all connected to the power ground end (HG) of the negative power generation circuit; the output end of the fourth differential charge pump (CP_Diff4) is connected to the sixth capacitor The upper plate of the sixth capacitor (C6) and the lower plate of the sixth capacitor (C6) are connected to the power ground (HG) of the negative power generation circuit; the input end of the fourth differential charge pump (CP_Diff4) is connected to the upper plate of the seventh capacitor (C7), and the lower plate of the seventh capacitor (C7) is connected to the power ground (HG) of the negative power generation circuit; the connection node between the input end of the fourth differential charge pump (CP_Diff4) and the upper plate of the seventh capacitor (C7) is the signal output end of the negative power generation circuit.

9. The rail-to-rail ultra-low mismatch charge pump circuit according to claim 8, characterized in that: The negative reference power generation circuit includes a third operational amplifier (AMP3), a seventh resistor (R7), an eighth resistor (R8), a ninth resistor (R9), a tenth resistor (R10), an eleventh resistor (R11), an eighth capacitor (C8) and a ninth capacitor (C9); One end of the eighth resistor (R8) is used to input the floating voltage control signal (VIN_VC), the positive input end of the third operational amplifier (AMP3) and one end of the ninth resistor (R9) are both connected to the other end of the eighth resistor (R8), and the other end of the ninth resistor (R9) is connected to the power ground terminal (HG) of the negative reference power generation circuit; One end of the seventh resistor (R7) is used to input the voltage to be reduced (VIN_VDIV), and the other end of the seventh resistor (R7) is connected to the negative input end of the third operational amplifier (AMP3); one end of the tenth resistor (R10) is connected to the negative input end of the third operational amplifier (AMP3), and the other end of the tenth resistor (R10) is connected to the output end of the third operational amplifier (AMP3); one end of the eighth capacitor (C8) is connected to the output end of the third operational amplifier (AMP3), and the other end of the eighth capacitor (C8) is connected to the power ground end (HG) of the negative reference power generation circuit; One end of the eleventh resistor (R11) is connected to the output end of the third operational amplifier (AMP3), the other end of the eleventh resistor (R11) is connected to the upper plate of the ninth capacitor (C9), the connection node between the other end of the eleventh resistor (R11) and the upper plate of the ninth capacitor (C9) is the signal output end of the negative reference power generation circuit, and the lower plate of the ninth capacitor (C9) is connected to the power ground terminal (HG) of the negative reference power generation circuit; The power supply terminal of the third operational amplifier (AMP3) is connected to the power supply terminal (HV) of the negative floating power supply generating circuit, the power ground terminal of the third operational amplifier (AMP3) is connected to the signal output terminal of the negative power supply generating circuit, and the reference source input terminal (IBP) set in the third operational amplifier (AMP3) is used to input a first reference current.

10. The rail-to-rail ultra-low mismatch charge pump circuit according to claim 9, characterized in that: The negative floating power supply generating circuit comprises a fourth operational amplifier (AMP4) and a tenth capacitor (C10); The positive input terminal of the fourth operational amplifier (AMP4) is connected to the signal output terminal of the negative reference power supply generating circuit, the negative input terminal of the fourth operational amplifier (AMP4) is connected to the output terminal of the fourth operational amplifier (AMP4), the output terminal of the fourth operational amplifier (AMP4) is connected to the upper plate of the tenth capacitor (C10), the connection node between the output terminal of the fourth operational amplifier (AMP4) and the upper plate of the tenth capacitor (C10) is the signal output terminal of the negative floating power supply generating circuit, and the lower plate of the tenth capacitor (C10) is connected to the power ground terminal (HG) of the negative floating power supply generating circuit; The power supply terminal (HV) of the fourth operational amplifier (AMP4) is connected to the power supply terminal (HV) of the negative floating power supply generating circuit, the power ground terminal (HG) of the fourth operational amplifier (AMP4) is connected to the signal output terminal of the negative power supply generating circuit, and the reference source input terminal (IBP) set in the fourth operational amplifier (AMP4) is used to input a second reference current.

11. The rail-to-rail ultra-low mismatch charge pump circuit according to any one of claims 1 to 10, characterized in that: Inside the level conversion circuit, an inverter chain is provided corresponding to each clock control signal, and four cascaded inverters are provided in each inverter chain; the input end of the first-stage inverter is used to input the clock control signal; The power supply terminal of the first-stage inverter is used to input the power supply of the phase-locked loop, a resistor is connected between the power supply terminal of the first-stage inverter and the power supply terminal of the second-stage inverter, a resistor is connected between the power supply terminal of the second-stage inverter and the power supply terminal of the third-stage inverter, the power supply terminal of the third-stage inverter is directly connected to the power supply terminal of the fourth-stage inverter, and the power supply terminal of the fourth-stage inverter is used to input the positive floating power supply voltage (VDDH_VC); The power ground terminal of the first-stage inverter is used to input the power ground of the phase-locked loop, a resistor is connected between the power ground terminal of the first-stage inverter and the power ground terminal of the second-stage inverter, a resistor is connected between the power ground terminal of the second-stage inverter and the power ground terminal of the third-stage inverter, the power ground terminal of the third-stage inverter is directly connected to the power ground terminal of the fourth-stage inverter, and the power ground terminal of the fourth-stage inverter is used to input the negative floating power supply voltage (VSSL_VC); The output end of the fourth-stage inverter is correspondingly connected to a functional port of the charge pump for controlling a charging switch, wherein the current clock control signal is used to turn on or off the switch MOS tube connected to the functional port.

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