Level shifter circuit and transmitter

Abstract

The invention discloses a level shifter circuit and a transmitter. The level shifter circuit comprises a low-voltage domain module and a high-voltage domain module, wherein the low-voltage domain module is connected with the high-voltage domain module; the low-voltage domain module is used for dividing an input clock signal into a positive-phase initial low level and a positive-phase initial high level and transmitting the positive-phase initial low level and the positive-phase initial high level to the high-voltage domain module, and the high-voltage domain module is used for converting the initial low level into a target low level and converting the initial high level into a target high level at the same time. The level shifter circuit not only can realize simultaneous conversion of high and low levels of a clock signal, but also can greatly improve the clock overturning speed.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of NFC near field communication, and in particular to a level converter circuit and a transmitter. Background Art

[0002] At present, in order to meet the clock requirements of driving the transmitter power tube, the level converter circuit of the 13.56MHZ frequency clock generally adopts the following level converter circuits:

[0003] Figure 1 It is a schematic diagram of the structure of a traditional level converter circuit, such as Figure 1 As shown, it is also the most common. The P tube adopts a cross-coupled circuit structure, and the N tube adopts a pull-down structure driven by a positive and negative two-phase clock signal. PM1 and PM2 are cross-coupled P tubes. The source of PM1 tube is connected to the source of PM2 tube and connected to the high-voltage domain VDDPA power supply. The gate of PM2 tube is connected to the drain of PM1 tube, and the gate of PM1 tube is connected to the drain of PM2 tube. On the other hand, NM1 and NM2 constitute a pull-down tube. The drain of NM1 is connected to the drain of PM1, the drain of NM2 is connected to the drain of PM2, the source of NM1 is connected to the source of NM2, and is connected to the ground. PM1, PM2, NM1, and NM2 all use CMOS tubes in the high-voltage domain. The positive and negative phases of the low-voltage domain clock are connected to the gates of NM1 tube and NM2 tube respectively. This structure converts the clock signal in the low-voltage domain into a high-voltage domain signal. The PMOS tube and NMOS tube of this structure are in competition with each other, so the high-voltage side of the PMOS tube needs to be smaller, which results in a relatively slow output rising edge time and high dynamic power consumption. In systems with high requirements for low-noise clock signals, the level converter of this structure seriously restricts communication performance.

[0004] Figure 2 It is a schematic diagram of the structure of a level converter circuit with a high-voltage zero-threshold NMOS protection tube, such as Figure 2As shown, based on the first circuit, the edge flip speed of the output signal is improved, and the level conversion range is also improved, which is suitable for application scenarios with low input power domain and higher output power domain. In this circuit structure, NM6 and NM7 are high voltage domain (VDDPA = 5V) zero threshold tubes, NM4 and NM5 are conventional low voltage domain (VDDA = 1.1V) N tubes, and the low voltage domain N tubes NM4 and NM5 are characterized by low threshold voltage, which is conducive to fast clock edge flip. At the same time, high voltage N tubes NM6 and NM7 can protect the drain voltage of NM4 and NM5 tubes to ensure that it does not exceed the low voltage domain power supply voltage of 1.1V. Similarly, PM1 and PM2 are cross-coupled structures, the gate of PM1 is connected to the drain of PM2, and the gate of PM2 is connected to the drain of PM1. The drain of PM1 is connected to the drain of NM6 of the high voltage zero threshold tube, the drain of PM2 is connected to the drain of NM7 of the high voltage zero threshold tube, the source of NM6 is connected to the drain of NM4 tube, the source of NM7 tube is connected to the drain of NM5 tube. NM6 is connected to the gate of NM4 tube, and NM7 is connected to the gate of NM5 tube.

[0005] Figure 3 It is a schematic diagram of the structure of a level converter circuit with a PMOS switch tube in series. Figure 3 As shown, in order to further improve the edge flip speed of the output clock signal, PM4 and PM5 switch tubes are connected in series in the cross-coupling structure composed of PM1 and PM2, in order to improve the flip speed of the output clock edge. When the clock input is low, NM4 is turned off, PM4 is turned on, the gate of PM2 is quickly pulled up, PM2 is turned off, at the same time, NM5 is turned on, PM5 is turned off, and the output end is quickly pulled up; when the clock input is high, NM4 is turned on, PM4 is turned off, the gate of PM2 is quickly pulled down, NM5 is turned off, PM5 is turned on, and the output end is quickly pulled up.

[0006] Figure 4 It is a schematic diagram of the structure of a level converter circuit with a series resistor, such as Figure 4 As shown, two resistors R1 and R2 are used to replace PM4 and PM5 in the third level converter circuit, which can also increase the switching speed of the clock edge.

[0007] Figure 5 It is a schematic diagram of a level converter circuit using a unilateral auxiliary flip structure. Figure 5 As shown, an auxiliary NM4 tube is used to accelerate the flipping of the clock signal. When the clock signal is at a high level, the NM4 tube is turned off; when the clock signal is at a low level, the voltage VGS between the gate and the source of the NM4 tube is greater than the threshold voltage VTH, and the NM4 tube is turned on, which plays a role in accelerating the flipping.

[0008] Figure 6It is a schematic diagram of a level converter circuit using a two-stage level-assisted flip structure. Figure 6 As shown, the level converter adopts a two-stage level change method. In the first stage, the level of the input clock signal is converted from the low voltage domain to the middle domain, and in the second stage, it is converted from the middle domain to the high voltage domain. The circuit structure of the two stages is basically similar. The middle domain voltage VBIAS in the first stage is constructed by the voltage VGS between the gate and source of the NM6 tube, VBIAS = VDDPA-VGS_NM6. The clock signal is converted from the low voltage domain (VHV) to the middle domain (VBIAS); in the second stage, the clock signal is converted from the middle domain to the high voltage domain (VDDPA). Due to the two-stage conversion, the flipping speed of each stage is greatly improved, and the flipping speed of the level converter is greatly improved overall.

[0009] Figure 7 It is a schematic diagram of the structure of a level converter circuit that controls the source voltage of an NMOS tube. Figure 7 As shown, the clock input signal is connected to the source of the N-tube, that is, the gate voltage of the N-tube is fixed, and the N-tube is controlled to be turned on and off by changing the source voltage of the N-tube, thereby controlling the level of the output terminal. When the input signal is low, the source of NM5 is high, at this time, the voltage VGS between the gate and source of NM5 is less than the threshold turn-on voltage, and NM5 is turned off; the source of NM6 is low, the voltage VGS between the gate and source of NM6 is greater than the threshold turn-on voltage, and NM6 is turned on; PM1 is turned on, PM2 is turned off, and the clock output terminal is pulled down to 0 level; when the input signal is high, the source of NM5 is low, at this time, the voltage VGS between the gate and source of NM5 is greater than the threshold turn-on voltage, and NM5 is turned on; the source of NM6 is high, the voltage VGS between the gate and source of NM6 is less than the threshold turn-on voltage, and NM6 is turned off; PM1 is turned off, PM2 is turned on, and the clock output terminal is pulled high to a high level. This circuit avoids controlling the NMOS tube by gate voltage, but due to the large gate capacitance of the NMOS tube, the response speed is slow. The flipping speed of the level converter is improved by controlling the source voltage of the NMOS tube to change the conduction current.

[0010] In summary, the problem with the existing level converter circuit is that it is not possible to change the high and low levels of the clock signal at the same time, and the switching speed of the clock signal is not fast enough. Summary of the invention

[0011] The present invention provides a level converter circuit and a transmitter, which solve the problems that the existing level converter circuit cannot change the high and low levels of a clock signal at the same time and the switching speed of the clock signal is not fast enough, and can not only realize the simultaneous conversion of the high and low levels of the clock signal, but also greatly improve the clock switching speed.

[0012] According to one aspect of the present invention, there is provided a level converter circuit, the level converter circuit comprising: a low voltage domain module and a high voltage domain module, the low voltage domain module being connected to the high voltage domain module;

[0013] The low-voltage domain module is used to divide the input clock signal into an initial low level and an initial high level of positive and negative phases and transmit them to the high-voltage domain module. The high-voltage domain module is used to convert the initial low level into a target low level and convert the initial high level into a target high level.

[0014] Optionally, the high-voltage domain module includes: a coupling module, a pre-charge unit, a pump capacitor and an inverter;

[0015] The control end of the pre-charge unit is connected to the high-voltage domain enable signal, the first end of the pre-charge unit is connected to the high-voltage domain low level, the second end of the pre-charge unit is connected to the pump capacitor and the low-voltage domain module in sequence, the pre-charge unit is used to pre-charge the pump capacitor, and the pump capacitor is used to assist the flipping of the initial low level and the initial high level;

[0016] The first end of the coupling module is connected to the high voltage domain at a high level, the second end of the coupling module is connected to the low voltage domain at a low level, and the third end of the coupling module is grounded;

[0017] The first end of the inverter is connected to the high level of the high voltage domain, the second end of the inverter is connected to the low level of the high voltage domain, the third end of the inverter is connected to the fourth end of the coupling module, the fourth end of the inverter is connected to the fifth end of the coupling module, and the inverter is used to accelerate the flipping of the initial low level and the initial high level.

[0018] Optionally, the coupling module includes: a first coupling branch and a second coupling branch;

[0019] The first end of the first coupling branch and the first end of the second coupling branch are connected to the high voltage domain at a high level, the second end of the first coupling branch and the second end of the second coupling branch are connected to the high voltage domain at a low level, and the third end of the first coupling branch and the third end of the second coupling branch are connected to ground;

[0020] The first coupling branch includes a first node, the second coupling branch includes a second node, the first end of the inverter is connected to the high level of the high voltage domain, the second end of the inverter is connected to the low level of the high voltage domain, the third end of the inverter is connected to the first node, and the fourth end of the inverter is connected to the second node.

[0021] Optionally, the high-voltage domain module further includes: a first-stage inverter and a second-stage inverter;

[0022] The first end of the first-stage inverter and the first end of the second-stage inverter are connected and serve as the output end of the high-voltage domain module, the second end of the first-stage inverter is connected to the low level of the high-voltage domain, the second end of the second-stage inverter is connected to the low level of the high-voltage domain, the third end of the first-stage inverter is connected to the second node, the fourth end of the first-stage inverter is connected to the third end of the second-stage inverter, the fourth end of the second-stage inverter serves as the output end of the high-voltage domain module, and the first-stage inverter and the second-stage inverter are used to enhance the driving capability of the level converter circuit.

[0023] Optionally, the pre-charge unit includes a third MOS tube, the control end of the third MOS tube is connected to the high-voltage domain enable signal, the first end of the third MOS tube is connected to the high-voltage domain low level, the second end of the third MOS tube is connected to the pump capacitor and the low-voltage domain module in sequence, and the third MOS tube is used to pre-charge the pump capacitor.

[0024] Optionally, the first coupling branch includes: a first MOS transistor, a seventh MOS transistor and an eleventh MOS transistor, and the second coupling branch includes: a second MOS transistor, an eighth MOS transistor and a twelfth MOS transistor;

[0025] The first end of the first MOS tube is connected to the first end of the second MOS tube and then connected to the high-voltage domain at a high level; the control end of the first MOS tube is connected to the second end of the second MOS tube and the fourth end of the inverter; the control end of the second MOS tube is connected to the second end of the first MOS tube and the third end of the inverter; the first end of the inverter is connected to the high-voltage domain at a high level; and the second end of the inverter is connected to the low-voltage domain at a low level;

[0026] The control end of the seventh MOS tube is connected to the control end of the eighth MOS tube and then connected to the high-voltage domain at a low level; the first end of the seventh MOS tube is connected to the third end of the inverter; the first end of the eighth MOS tube is connected to the fourth end of the inverter; the second end of the seventh MOS tube is connected to the first end of the eleventh MOS tube; the second end of the eighth MOS tube is connected to the first end of the twelfth MOS tube; the second end of the eleventh MOS tube is connected to the second end of the twelfth MOS tube and then grounded; the control end of the eleventh MOS tube and the control end of the twelfth MOS tube are connected to the low-voltage domain module.

[0027] Optionally, the inverter includes: a fourth MOS tube and a fourteenth MOS tube;

[0028] The first end of the fourth MOS tube is connected to the high-voltage domain at a high level, the second end of the fourth MOS tube is connected to the second end of the fourteenth MOS tube and serves as the fourth end of the inverter, the control end of the fourth MOS tube is connected to the control end of the fourteenth MOS tube and serves as the third end of the inverter, and the second end of the fourteenth MOS tube is connected to the high-voltage domain at a low level.

[0029] Optionally, the first-stage inverter includes: a fifth MOS tube and a fifteenth MOS tube;

[0030] The first end of the fifth MOS tube is connected to the high level of the high voltage domain, the control end of the fifth MOS tube is connected to the control end of the fifteenth MOS tube and then connected to the inverter, the second end of the fifth MOS tube is connected to the first end of the fifteenth MOS tube and then connected to the second-stage inverter, and the second end of the fifteenth MOS tube is connected to the low level of the high voltage domain.

[0031] Optionally, the second-stage inverter includes: a sixth MOS tube and a sixteenth MOS tube;

[0032] The first end of the sixth MOS tube is connected to the high level of the high voltage domain, the control end of the sixth MOS tube is connected to the control end of the sixteenth MOS tube and then connected to the first-stage inverter, the second end of the sixth MOS tube is connected to the first end of the sixteenth MOS tube and serves as the output end of the high voltage domain module, and the second end of the sixteenth MOS tube is connected to the low level of the high voltage domain.

[0033] Optionally, the high-voltage domain module further includes: a NAND gate, a first inverter and a thirteenth MOS tube;

[0034] The first end of the NAND gate is connected to the control signal, the second end of the NAND gate is connected to the clock signal, the output end of the NAND gate is connected to the first inverter, the first inverter is connected to the control end of the thirteenth MOS tube, the first end of the thirteenth MOS tube is connected to the pump capacitor, and the second end of the thirteenth MOS tube is grounded.

[0035] Optionally, the low-voltage domain module includes: a ninth MOS tube and an eighteenth MOS tube;

[0036] The first end of the ninth MOS tube is connected to the normally-on power domain, the control end of the ninth MOS tube is connected to the control end of the eighteenth MOS tube and then connected to the clock signal, the second end of the ninth MOS tube is connected to the first end of the eighteenth MOS tube and then connected to the high-voltage domain module, and the second end of the eighteenth MOS tube is grounded.

[0037] According to another aspect of the present invention, a transmitter is provided, the transmitter comprising the level converter circuit, the buffer and the power tube as described in any one of the above aspects;

[0038] The level converter circuit is connected to the buffer, the buffer is connected to the power tube, the level converter circuit is used to drive and control the power tube, and the buffer is used to enhance the driving capability of the level converter circuit.

[0039] The technical solution of the embodiment of the present invention proposes a level converter circuit that can change the high and low levels of the clock signal at the same time. The low-voltage domain module divides the input clock signal into an initial low level and an initial high level of positive and negative phases and transmits it to the high-voltage domain module. The high-voltage domain module converts the initial low level to a target low level and converts the initial high level to a target high level at the same time. This can not only realize the simultaneous conversion of the high and low levels of the clock signal, but also greatly improve the clock flip speed. In summary, the present invention solves the problem that the existing level converter circuit cannot change the high and low levels of the clock signal at the same time, and the flip speed of the clock signal is not fast enough.

[0040] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 It is a schematic diagram of the structure of a conventional level converter circuit;

[0043] Figure 2 It is a schematic diagram of the structure of a level converter circuit with a high-voltage zero-threshold NMOS protection tube;

[0044] Figure 3 It is a schematic diagram of the structure of a level converter circuit with a PMOS switch tube in series;

[0045] Figure 4 It is a schematic diagram of the structure of a level converter circuit with a series resistor;

[0046] Figure 5 It is a schematic diagram of the structure of a level converter circuit using a single-side auxiliary flip structure;

[0047] Figure 6 It is a schematic diagram of the structure of a level converter circuit using a two-stage level-assisted flipping structure;

[0048] Figure 7 It is a schematic diagram of the structure of a level converter circuit that uses a method of controlling the source voltage of an NMOS tube;

[0049] Figure 8 is a schematic structural diagram of a level converter circuit provided according to an embodiment of the present invention;

[0050] Fig. 9 is a schematic structural diagram of another level converter circuit provided according to an embodiment of the present invention;

[0051] Fig.10 is a schematic diagram of an input clock signal and an output clock signal waveform provided according to an embodiment of the present invention;

[0052] Fig.11 is a schematic diagram of a circuit structure of a gate fixed bias voltage generating module provided according to an embodiment of the present invention;

[0053] Fig.12 It is a schematic diagram of a transmitter power tube array using LDMOS provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0054] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0055] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0056] Figure 8is a schematic diagram of a level converter circuit provided according to an embodiment of the present invention, with reference to Figure 8 , an embodiment of the present invention provides a level converter circuit, the level converter circuit includes: a low voltage domain module 10 and a high voltage domain module 20, the low voltage domain module 10 is connected to the high voltage domain module 20;

[0057] The low voltage domain module 10 is used to divide the input clock signal into positive and negative initial low level and initial high level and transmit them to the high voltage domain module 20. The high voltage domain module 20 is used to convert the initial low level into a target low level and convert the initial high level into a target high level.

[0058] Specifically, the NFC communication chip mainly includes: a transmitter, a receiver, a clock generation integrated processing unit and a digital signal processing unit. Among them, the main function of the transmitter is to transmit a 13.56MHZ carrier signal containing amplitude modulation information through an antenna coil. Usually, the modulated data transmitted by the transmitter comes from a low-voltage power domain. The device that drives the antenna of the transmitter is a high-voltage domain device. It is necessary to transfer the 13.56MHZ clock signal containing modulation information from the low-voltage domain to the high-voltage domain and drive the power tube. The key to realizing this function is the level converter circuit. The role of the receiver is to receive the modulated data of the other device through the receiving antenna and demodulate and recover it through the receiver circuit. The role of the clock generation integrated processing unit is to provide each module in the NFC system with the required frequency value, duty cycle value, and high-precision value required clock signal. The transmitter, receiver and system clock all need this unit to provide a reliable clock source to work properly.

[0059] The level converted by the existing level converter circuit is single, that is, the low level of the signal is kept unchanged, and the high level of the signal is transferred from a relatively low level potential to another relatively high level potential. The level converter circuit of the present invention can simultaneously transfer the high and low levels of the clock signal, and ensure that the clock signal has a fast flip edge speed. The purpose of using the level converter circuit is to allow the gate clock signal voltage of the driving power tube to meet the required working range. If the gate clock signal voltage of the driving power tube is too high or too low, the signal cannot be transmitted, and even the power tube device may be damaged.

[0060] The level converter circuit mainly converts the high and low levels of the input clock signal to another set of high and low level values ​​at the same time. The clock level before the conversion is the initial low level and the initial high level; the clock level after the conversion is the target low level and the target high level. The high-voltage domain module 20 in the level converter circuit converts the clock signal of the 0~1.8V low-voltage domain to the high-voltage domain signal of (VDDPA-1.8V=3.2V~VDDPA=5V). The 0 level of the low-voltage domain is raised to VDDPA-1.8V=3.2V of the high-voltage domain, and the 1.8V level of the low-voltage domain is raised to VDDPA=5V. The high and low levels of the clock signal are converted at the same time, and the high and low levels of the signal are more flexible, which expands the application range of the clock signal. The clock flip edge speed is fast and the anti-noise ability is strong.

[0061] By simultaneously converting the high and low levels of the clock signal, the gate voltage of the power tube can be adjusted more flexibly, and then the transmission power of the power tube can be adjusted more flexibly. The adjustment range of the level converter circuit is increased, and the transmitter power tube can use a more efficient LDMOS tube as the power tube array, thereby reducing the chip area as a whole. At the same time, the level converter circuit has a faster clock flip speed, which can meet the noise resistance of 13.56MHZ communication and greatly reduce the phase noise of the clock link.

[0062] The technical solution of the embodiment of the present invention proposes a level converter circuit that can change the high and low levels of the clock signal at the same time. The low-voltage domain module divides the input clock signal into an initial low level and an initial high level of positive and negative phases and transmits it to the high-voltage domain module. The high-voltage domain module converts the initial low level to a target low level and converts the initial high level to a target high level at the same time. This can not only realize the simultaneous conversion of the high and low levels of the clock signal, but also greatly improve the clock flip speed. In summary, the present invention solves the problem that the existing level converter circuit cannot change the high and low levels of the clock signal at the same time, and the flip speed of the clock signal is not fast enough.

[0063] Fig. 9 is a schematic structural diagram of another level converter circuit provided according to an embodiment of the present invention, Fig.10 is a schematic diagram of an input clock signal and an output clock signal waveform provided according to an embodiment of the present invention, with reference to Fig. 9 and Fig.10 , Optionally, the high-voltage domain module 20 includes: a coupling module 212, a pre-charge unit 23, a pump capacitor C0 and an inverter 24;

[0064] The control end of the pre-charge unit 23 is connected to the high-voltage domain enable signal OE_H, the first end of the pre-charge unit 23 is connected to the high-voltage domain low level VSS_BIAS, the second end of the pre-charge unit 23 is connected to the pump capacitor C0 and the low-voltage domain module 10 in sequence, the pre-charge unit 23 is used to pre-charge the pump capacitor C0, and the pump capacitor C0 is used to assist the flipping of the initial low level and the initial high level;

[0065] A first end of the coupling module 212 is connected to a high voltage domain high level VDDPA, a second end of the coupling module 212 is connected to a low voltage domain VSS_BIAS, and a third end of the coupling module 212 is grounded;

[0066] The first end of the inverter 24 is connected to the high voltage domain high level VDDPA, the second end of the inverter 24 is connected to the high voltage domain low level VSS_BIAS, the third end of the inverter 24 is connected to the fourth end of the coupling module 212, and the fourth end of the inverter 24 is connected to the fifth end of the coupling module 212. The inverter 24 is used to accelerate the flipping of the initial low level and the initial high level.

[0067] Continue to refer Fig. 9 and Fig.10 , Optionally, the coupling module 212 includes: a first coupling branch 21 and a second coupling branch 22;

[0068] The first end of the first coupling branch 21 and the first end of the second coupling branch 22 are connected to the high voltage domain high level VDDPA, the second end of the first coupling branch 21 and the second end of the second coupling branch 22 are connected to the high voltage domain low level VSS_BIAS, and the third end of the first coupling branch 21 and the third end of the second coupling branch 22 are connected to ground;

[0069] The first coupling branch 21 includes a first node C, the second coupling branch 22 includes a second node D, the first end of the inverter 24 is connected to the high voltage domain high level VDDPA, the second end of the inverter 24 is connected to the high voltage domain low level VSS_BIAS, the third end of the inverter 24 is connected to the first node C, and the fourth end of the inverter 24 is connected to the second node D.

[0070] Specifically, the rising and falling edges of the clock signal CLK-IN are assisted by the pump capacitor C0 for level inversion. When the input clock signal CLK-IN is at an initial high level, one end of the positive plate of the pump capacitor C0 is precharged to a target low level, and one end of the negative plate of the pump capacitor C0 is kept at an initial low level. At the falling edge of the clock, since the charges at both ends of the pump capacitor C0 cannot change suddenly, one end of the positive plate of the pump capacitor C0 continues to be raised to a target high level, and one end of the negative plate of the pump capacitor C0 is raised to an initial high level. At the rising edge of the clock, one end of the positive plate of the pump capacitor C0 is pulled down to a target low level, and one end of the negative plate of the pump capacitor C0 is pulled down to an initial low level. The negative plate of the pump capacitor C0 is connected to the clock signal CLK-IN through an inverter formed by the ninth MOS transistor PM9 and the eighteenth MOS transistor NM8.

[0071] The timing constraints of the pre-charge control signal of the pre-charge unit 23 on the pump capacitor C0 are specifically as follows: when the clock signal CLK-IN is turned off and pulled up to the initial high level, the pump capacitor is charged to the target low level; when the clock signal CLK-IN starts to flip, the forced charging of the pump capacitor C0 ends.

[0072] Continue to refer Fig. 9 , Optionally, the high-voltage domain module 20 further includes: a first-stage inverter 25 and a second-stage inverter 26;

[0073] The first end of the first-stage inverter 25 and the first end of the second-stage inverter 26 are connected and serve as the output end of the high-voltage domain module 20. The second end of the first-stage inverter 25 is connected to the high-voltage domain low level VSS_BIAS. The second end of the second-stage inverter 26 is connected to the high-voltage domain low level VSS_BIAS. The third end of the first-stage inverter 25 is connected to the second node D. The fourth end of the first-stage inverter 25 is connected to the third end of the second-stage inverter 26. The fourth end of the second-stage inverter 26 serves as the output end of the high-voltage domain module 20. The first-stage inverter 25 and the second-stage inverter 26 are used to enhance the driving capability of the level converter circuit.

[0074] Specifically, the first-stage inverter 25 and the second-stage inverter 26 are used to enhance the driving capability of the level converter circuit. Finally, the output end of the level converter circuit needs to be connected to a load to ensure signal quality.

[0075] Continue to refer Fig. 9 Optionally, the pre-charge unit 23 includes a third MOS transistor PM3, the control end of the third MOS transistor PM3 is connected to the high-voltage domain enable signal OE_H, the first end of the third MOS transistor PM3 is connected to the high-voltage domain low level VSS_BIAS, the second end of the third MOS transistor PM3 is connected to the pump capacitor C0 and the low-voltage domain module 10 in sequence, and the third MOS transistor PM3 is used to pre-charge the pump capacitor C0.

[0076] Continue to refer Fig. 9 Optionally, the first coupling branch 21 includes: a first MOS transistor PM1, a seventh MOS transistor PM7 and an eleventh MOS transistor NM1, and the second coupling branch 22 includes: a second MOS transistor PM2, an eighth MOS transistor PM8 and a twelfth MOS transistor NM2;

[0077] The first end of the first MOS transistor PM1 is connected to the first end of the second MOS transistor PM2 and then connected to the high voltage domain high level VDDPA, the control end of the first MOS transistor PM1 is connected to the second end of the second MOS transistor PM2 and the fourth end of the inverter 24, the control end of the second MOS transistor PM2 is connected to the second end of the first MOS transistor PM1 and the third end of the inverter 24, the first end of the inverter 24 is connected to the high voltage domain high level VDDPA, and the second end of the inverter 24 is connected to the low voltage domain low level VSS_BIAS;

[0078] The control end of the seventh MOS transistor PM7 is connected to the control end of the eighth MOS transistor PM8 and then connected to the high-voltage domain low level VSS_BIAS, the first end of the seventh MOS transistor PM7 is connected to the third end of the inverter 24, the first end of the eighth MOS transistor PM8 is connected to the fourth end of the inverter 24, the second end of the seventh MOS transistor PM7 is connected to the first end of the eleventh MOS transistor NM1, the second end of the eighth MOS transistor PM8 is connected to the first end of the twelfth MOS transistor NM2, the second end of the eleventh MOS transistor NM1 is connected to the second end of the twelfth MOS transistor NM2 and then grounded, and the control end of the eleventh MOS transistor NM1 and the control end of the twelfth MOS transistor NM2 are connected to the low-voltage domain module 10.

[0079] Continue to refer Fig. 9 and Fig.10 , Optionally, the inverter 24 includes: a fourth MOS transistor PM4 and a fourteenth MOS transistor NM4;

[0080] A first end of the fourth MOS transistor PM4 is connected to the high voltage domain high level VDDPA, a second end of the fourth MOS transistor PM4 is connected to the second end of the fourteenth MOS transistor NM4 and serves as a fourth end of the inverter 24, a control end of the fourth MOS transistor PM4 is connected to the control end of the fourteenth MOS transistor NM4 and serves as a third end of the inverter 24, and a second end of the fourteenth MOS transistor NM4 is connected to the high voltage domain low level VSS_BIAS.

[0081] Specifically, the switching speed of the clock signal CLK-IN is very fast, and a special inverter 24 is embedded in the level converter circuit. The power supply of the inverter 24 is the target high level, and the ground level of the inverter 24 is the target low level. The function of the inverter 24 is to accelerate the switching of the output clock signal CLK-OUT level, and also ensure that the output level is not lower than the target low level.

[0082] Continue to refer Fig. 9 Optionally, the first-stage inverter 25 includes: a fifth MOS transistor PM5 and a fifteenth MOS transistor NM5;

[0083] A first end of the fifth MOS transistor PM5 is connected to the high voltage domain high level VDDPA, a control end of the fifth MOS transistor PM5 is connected to the control end of the fifteenth MOS transistor NM5 and then connected to the inverter 24, a second end of the fifth MOS transistor PM5 is connected to the first end of the fifteenth MOS transistor NM5 and then connected to the second-stage inverter 26, and a second end of the fifteenth MOS transistor NM5 is connected to the high voltage domain low level VSS_BIAS.

[0084] Continue to refer Fig. 9 Optionally, the second-stage inverter 26 includes: a sixth MOS transistor PM6 and a sixteenth MOS transistor NM6;

[0085] A first end of the sixth MOS transistor PM6 is connected to the high voltage domain high level VDDPA, a control end of the sixth MOS transistor PM6 is connected to the control end of the sixteenth MOS transistor NM6 and then connected to the first-stage inverter 25, a second end of the sixth MOS transistor PM6 is connected to the first end of the sixteenth MOS transistor NM6 and then serves as an output end of the high voltage domain module 20, and a second end of the sixteenth MOS transistor NM6 is connected to the high voltage domain low level VSS_BIAS.

[0086] Specifically, the output level of the level converter circuit is clamped for protection, and a PMOS tube—the sixth MOS tube PM6 is used for clamping. The gate of the P-type clamp tube is fixedly connected to the target low level, and the source of the P-type clamp tube is the output of the level converter circuit, thereby ensuring that the output low level of the level converter circuit is not lower than the target low level.

[0087] Continue to refer Fig. 9 and Fig.10 , Optionally, the low voltage domain module 10 includes: a ninth MOS transistor PM9 and an eighteenth MOS transistor NM8;

[0088] A first end of the ninth MOS transistor PM9 is connected to the normally-on power domain VHV, a control end of the ninth MOS transistor PM9 is connected to the control end of the eighteenth MOS transistor NM8 and then connected to the clock signal CLK-IN, a second end of the ninth MOS transistor PM9 is connected to the first end of the eighteenth MOS transistor NM8 and then connected to the high-voltage domain module 20, and a second end of the eighteenth MOS transistor NM8 is grounded.

[0089] Specifically, the ninth MOS transistor PM9 and the eighteenth MOS transistor NM8 form an inverter in the VHV domain. The high voltage domain high level VDDPA=5V, and the low voltage domain VSS_BIAS=3.2V. Therefore, the fourth MOS transistor PM4, the fifth MOS transistor PM5, the sixth MOS transistor PM6, the fifteenth MOS transistor NM5, the sixteenth MOS transistor NM6, and the NM7 all use CMOS transistors with a withstand voltage of 1.8V to meet the withstand voltage requirement. Since the voltage at both ends of the source and drain of the first MOS transistor PM1 and the second MOS transistor PM2 does not exceed 1.8V, they also use 1.8V withstand voltage tubes. The gate voltages of the seventh MOS transistor PM7 and the eighth MOS transistor PM8 are fixedly biased to 3.2V, and the source voltage of the seventh MOS transistor PM7 and the source voltage of the eighth MOS transistor PM8 will not exceed the high voltage domain high level VDDPA. The seventh MOS transistor PM7 and the eighth MOS transistor PM8 can both adopt LDPMOS tubes, and the source and drain voltage of the LDMOS tube can withstand a voltage difference of 5V, which can safely ensure the safe use of the seventh MOS transistor PM7 and the eighth MOS transistor PM8. The gate voltages of the eleventh MOS transistor NM1 and the twelfth MOS transistor NM2 are both the voltage of the normally open power domain (VHV=1.8V), and the sources of the eleventh MOS transistor NM1 and the twelfth MOS transistor NM2 are simultaneously grounded at a level of 0V. Therefore, the eleventh MOS transistor NM1 and the twelfth MOS transistor NM2 adopt LDNMOS tubes. Similarly, the LDMOS source and drain voltage is 5V, which can also safely ensure the safe use of the eleventh MOS transistor NM1 and the twelfth MOS transistor NM2.

[0090] The seventh MOS transistor PM7 and the eighth MOS transistor PM8 function to protect the first MOS transistor PM1 and the second MOS transistor PM2 to ensure that the drain voltage of the first MOS transistor PM1 and the second MOS transistor PM2 will not be lower than the high-voltage domain low level VSS_BIAS.

[0091] The function of the third MOS transistor PM3 is to precharge the pump capacitor C0 to ensure that the initial state of the level converter circuit is correct. When the level converter circuit is in the initial state: the clock is not turned on, the high-voltage domain enable signal OE_H is 0, the third MOS transistor PM3 is in the on state, the positive plate of the pump capacitor C0 is clamped to the high-voltage domain low level VSS_BIAS, and the negative plate of the pump capacitor C0 is clamped to the 0 level. The output of the level converter circuit is forced to output 0. When the level converter circuit is in the working state, the clock is turned on. The level of the high-voltage domain enable signal OE_H is the high-voltage domain high level VDDPA, and the third MOS transistor PM3 is in the off state. At the same time, due to the turning on of the clock, the negative plate of the pump capacitor C0 is raised to the high level of the VHV domain, the charge of the pump capacitor C0 cannot change suddenly, the positive plate of the pump capacitor C0 is raised to the high-voltage domain high level VDDPA, and the output of the level converter circuit is the high-voltage domain low level VSS_BIAS. When the second half cycle of the clock arrives, the negative plate of the pump capacitor C0 is pulled down to the 0 level. The positive plate of the pump capacitor C0 is simultaneously pulled down to the high-voltage domain low level VSS_BIAS, and the output of the level converter circuit is the high-voltage domain high level VDDPA.

[0092] VHV is the name of a normally open power domain, and the voltage of this power domain is 1.8V. During normal operation, the pump capacitor C0 works in conjunction with the first MOS transistor PM1, the second MOS transistor PM2, the eleventh MOS transistor NM1, and the twelfth MOS transistor NM2. When the clock signal CLK_IN is at a high level in the VHV domain, the eleventh MOS transistor NM1 is turned on, the twelfth MOS transistor NM2 is turned off, the second MOS transistor PM2 is turned on, and the first MOS transistor PM1 is turned off. The positive plate of the pump capacitor C0 is the high-voltage domain low level VSS_BIAS, and the negative plate of the pump capacitor C0 is 0 level. When the clock signal CLK_IN is at a 0 level, the twelfth MOS transistor NM2 is turned on, the eleventh MOS transistor NM1 is turned off, the first MOS transistor PM1 is turned on, and the second MOS transistor PM2 is turned off. The pump capacitor C0 raises the voltage of the positive and negative plates at the same time. The positive plate of the pump capacitor C0 is the high-voltage domain high level VDDPA, and the negative plate of the pump capacitor C0 is VHV.

[0093] The low voltage logic part is the VHV part. The clock signal CLK_IN is a 13.56 MHZ clock signal. The high level of the clock signal is VHV (1.8 V). The low level of the clock signal is 0 level. PM9 and NM8 form an inverter in the VHV domain, which divides the input clock signal into positive and negative phases. The positive phase clock is connected to point A, and the negative phase clock is connected to point B. Point A is connected to the gate of the eleventh MOS tube NM1, and point B is connected to the gate of the twelfth MOS tube NM2. Since the gate voltage of the eleventh MOS tube NM1 and the twelfth MOS tube NM2 does not exceed VHV = 1.8 V, the eleventh MOS tube NM1 and the twelfth MOS tube NM2 use LDNMOS. The drain of the eleventh MOS tube NM1 is connected to the drain of the seventh MOS tube PM7, and the drain of the twelfth MOS tube NM2 is connected to the drain of the eighth MOS tube PM8. The gates of the seventh MOS transistor PM7 and the eighth MOS transistor PM8 adopt a fixed biased high-voltage domain low level VSS_BIAS=1.8V. Since the source voltages of the seventh MOS transistor PM7 and the eighth MOS transistor PM8 do not exceed the high-voltage domain high level VDDPA, the seventh MOS transistor PM7 and the eighth MOS transistor PM8 adopt LDPMOS transistors, and the source end of the seventh MOS transistor PM7 is connected to the gate of the second MOS transistor PM2. The source of the eighth MOS transistor PM8 is connected to the gate of the first MOS transistor PM1. The sources of the first MOS transistor PM1 and the second MOS transistor PM2 are connected to the high-voltage domain high level VDDPA, and the first MOS transistor PM1 and the second MOS transistor PM2 form a cross-coupling structure. An inverter 24 for accelerating clock edge flipping is connected between point C and point D. The inverter 24 is composed of the fourth MOS transistor PM4 and the fourteenth MOS transistor NM4. The power supply of the inverter 24 is the high-voltage domain high level VDDPA, and the ground level is the high-voltage domain low level VSS_BIAS. The output driver stage is formed by two inverters connected to each other. The fifth MOS tube PM5 and the fifteenth MOS tube NM5 constitute the first stage inverter 25, and the sixth MOS tube PM6 and the sixteenth MOS tube NM6 constitute the second stage inverter 26. The power supply of these two stages of inverters is the high level VDDPA=5V in the high voltage domain, and the ground level is the low level VSS_BIAS=3.2V in the high voltage domain. A pump capacitor C0 is connected between point B and point C. The pump capacitor C0 uses a 5pF capacitor. In summary, the level converter circuit realizes the transfer of the signal (0V~VHV=1.8V) of the low voltage power domain to the signal (VSS_BIAS(3.2V)~VDDPA(5V)) of the high voltage power domain.

[0094] Continue to refer Fig. 9 and Fig.10 Optionally, the high-voltage domain module 20 further includes: a NAND gate, a first inverter and a thirteenth MOS transistor NM3;

[0095] A first end of the NAND gate is connected to the control signal CTRL0, a second end of the NAND gate is connected to the clock signal CLK-IN, an output end of the NAND gate is connected to the first inverter, the first inverter is connected to the control end of the thirteenth MOS transistor NM3, a first end of the thirteenth MOS transistor NM3 is connected to the pump capacitor C0, and a second end of the thirteenth MOS transistor NM3 is grounded.

[0096] Specifically, the level converter circuit adds an output state voltage locking circuit composed of a NAND gate, a first inverter, and a thirteenth MOS tube NM3. When the high-voltage domain enable signal OE_H is high and the input clock is in a pulled-up state, the clock state can be locked to a high level in the high-voltage domain by controlling the control signal CTRL0 to be high. The thirteenth MOS tube NM3 functions as a pull-down switch. When the high-voltage domain enable signal OE_H is high, the input clock signal CLK-IN is high, and the gate voltage of the thirteenth MOS tube NM3 is high, which pulls down the drain voltage of the thirteenth MOS tube NM3, thereby ensuring that the output clock signal CLK_OUT is output and locked to a high level state of the high-voltage domain (VDDPA=5V).

[0097] Fig.11 is a schematic diagram of a circuit structure of a gate fixed bias voltage generating module provided according to an embodiment of the present invention, with reference to Fig.11 The high-voltage domain low level VSS_BIAS is the gate fixed bias voltage of the seventh MOS transistor PM7 and the eighth MOS transistor PM8 and the output target ground level of the level converter circuit. The high-voltage domain low level VSS_BIAS is generated by the output of an external low-dropout regulator (LDO). Fig.11 As shown in the figure: The LDO reference voltage VREF is obtained by subtracting the product of the bias current IBAS and the bias resistor R1 from the high voltage domain high level VDDPA. The value of IBIAS*R1 is equal to 1.8V, so the high voltage domain low level VSS_BIAS=VDDPA-1.8V. The LDO uses NMOS tube as the power tube, and the load current is the sink current from the high voltage domain high level VDDPA to the high voltage domain low level VSS_BIAS.

[0098] An embodiment of the present invention also provides a transmitter, which includes the level converter circuit, buffer and power tube provided by any embodiment of the present invention; the level converter circuit is connected to the buffer, the buffer is connected to the power tube, the level converter circuit is used to drive and control the power tube, and the buffer is used to enhance the driving capability of the level converter circuit.

[0099] Since the transmitter includes the level converter circuit provided by any embodiment of the present invention, the beneficial effects of the transmitter and the level converter circuit are the same, which will not be described in detail herein.

[0100] Specifically, from the perspective of circuit structure, the source of the clock signal that drives the power tube is in the low-voltage domain, which is converted to the power domain that enables the power tube to work normally through the level converter circuit. A buffer that enhances the driving capability is included between the level converter and the power tube, that is, the level converter is not directly connected to the power tube.

[0101] Fig.12 FIG. 1 is a schematic diagram of a transmitter power tube array using LDMOS according to an embodiment of the present invention. The power tube array is composed of LDNMOS and LDPMOS. Fig.12 As shown in the figure, LDMOS is used as a power tube device, which has the advantages of high source and drain voltage resistance. Compared with ordinary high-voltage tubes, it has the characteristics of high current efficiency and small area, which greatly saves the cost of the chip. The driving capability is improved, and the chip area is reduced while ensuring the performance remains unchanged.

[0102] The P power tube array is P1, P2, P3, P4...Pn, and the N power tube array is N1, N2, N3, N4...Nn. When the power is maximum, the gates of the P1~Pn tubes are connected in parallel at the same time, and the gates of the N1~Nn tubes are connected in parallel at the same time. The gate control voltage of the P power tube is VGP, and the gate control voltage of the N power tube is VGN. The control voltage range of VGP is VSS_BIAS=3.2V~VDDPA=5V, and the control voltage range of VGN is VSS_PA=0V~VHV=1.8V. The driving clock generated by the level converter circuit of this embodiment is used for the control of VGP.

[0103] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A level converter circuit, characterized in that: include: A low-voltage domain module and a high-voltage domain module, wherein the low-voltage domain module is connected to the high-voltage domain module; The low-voltage domain module is used to divide the input clock signal into an initial low level and an initial high level of positive and negative phases and transmit them to the high-voltage domain module. The high-voltage domain module is used to convert the initial low level into a target low level and convert the initial high level into a target high level.

2. The circuit according to claim 1, characterized in that The high-voltage domain module includes: a coupling module, a pre-charge unit, a pump capacitor and an inverter; The control end of the pre-charge unit is connected to the high-voltage domain enable signal, the first end of the pre-charge unit is connected to the high-voltage domain low level, the second end of the pre-charge unit is connected to the pump capacitor and the low-voltage domain module in sequence, the pre-charge unit is used to pre-charge the pump capacitor, and the pump capacitor is used to assist the flipping of the initial low level and the initial high level; The first end of the coupling module is connected to the high voltage domain at a high level, the second end of the coupling module is connected to the low voltage domain at a low level, and the third end of the coupling module is grounded; The first end of the inverter is connected to the high level of the high voltage domain, the second end of the inverter is connected to the low level of the high voltage domain, the third end of the inverter is connected to the fourth end of the coupling module, the fourth end of the inverter is connected to the fifth end of the coupling module, and the inverter is used to accelerate the flipping of the initial low level and the initial high level.

3. The circuit according to claim 2, characterized in that The coupling module comprises: a first coupling branch and a second coupling branch; The first end of the first coupling branch and the first end of the second coupling branch are connected to the high voltage domain at a high level, the second end of the first coupling branch and the second end of the second coupling branch are connected to the high voltage domain at a low level, and the third end of the first coupling branch and the third end of the second coupling branch are connected to ground; The first coupling branch includes a first node, the second coupling branch includes a second node, the first end of the inverter is connected to the high level of the high voltage domain, the second end of the inverter is connected to the low level of the high voltage domain, the third end of the inverter is connected to the first node, and the fourth end of the inverter is connected to the second node.

4. The circuit according to claim 3, characterized in that Also includes: a first-stage inverter and a second-stage inverter; The first end of the first-stage inverter and the first end of the second-stage inverter are connected and serve as the output end of the high-voltage domain module, the second end of the first-stage inverter is connected to the low level of the high-voltage domain, the second end of the second-stage inverter is connected to the low level of the high-voltage domain, the third end of the first-stage inverter is connected to the second node, the fourth end of the first-stage inverter is connected to the third end of the second-stage inverter, the fourth end of the second-stage inverter serves as the output end of the high-voltage domain module, and the first-stage inverter and the second-stage inverter are used to enhance the driving capability of the level converter circuit.

5. The circuit according to claim 2, characterized in that The pre-charge unit includes a third MOS tube, a control end of the third MOS tube is connected to the high-voltage domain enable signal, a first end of the third MOS tube is connected to the high-voltage domain at a low level, a second end of the third MOS tube is connected to the pump capacitor and the low-voltage domain module in sequence, and the third MOS tube is used to pre-charge the pump capacitor.

6. The circuit according to claim 3, characterized in that The first coupling branch includes: a first MOS transistor, a seventh MOS transistor and an eleventh MOS transistor, and the second coupling branch includes: a second MOS transistor, an eighth MOS transistor and a twelfth MOS transistor; The first end of the first MOS tube is connected to the first end of the second MOS tube and then connected to the high-voltage domain at a high level; the control end of the first MOS tube is connected to the second end of the second MOS tube and the fourth end of the inverter; the control end of the second MOS tube is connected to the second end of the first MOS tube and the third end of the inverter; the first end of the inverter is connected to the high-voltage domain at a high level; and the second end of the inverter is connected to the low-voltage domain at a low level; The control end of the seventh MOS tube is connected to the control end of the eighth MOS tube and then connected to the high-voltage domain at a low level; the first end of the seventh MOS tube is connected to the third end of the inverter; the first end of the eighth MOS tube is connected to the fourth end of the inverter; the second end of the seventh MOS tube is connected to the first end of the eleventh MOS tube; the second end of the eighth MOS tube is connected to the first end of the twelfth MOS tube; the second end of the eleventh MOS tube is connected to the second end of the twelfth MOS tube and then grounded; the control end of the eleventh MOS tube and the control end of the twelfth MOS tube are connected to the low-voltage domain module.

7. The circuit according to claim 6, characterized in that The inverter comprises: a fourth MOS tube and a fourteenth MOS tube; The first end of the fourth MOS tube is connected to the high-voltage domain at a high level, the second end of the fourth MOS tube is connected to the second end of the fourteenth MOS tube and serves as the fourth end of the inverter, the control end of the fourth MOS tube is connected to the control end of the fourteenth MOS tube and serves as the third end of the inverter, and the second end of the fourteenth MOS tube is connected to the high-voltage domain at a low level.

8. The circuit according to claim 4, characterized in that The first-stage inverter includes: a fifth MOS tube and a fifteenth MOS tube; The first end of the fifth MOS tube is connected to the high level of the high voltage domain, the control end of the fifth MOS tube is connected to the control end of the fifteenth MOS tube and then connected to the inverter, the second end of the fifth MOS tube is connected to the first end of the fifteenth MOS tube and then connected to the second-stage inverter, and the second end of the fifteenth MOS tube is connected to the low level of the high voltage domain.

9. The circuit according to claim 4, characterized in that The second-stage inverter includes: a sixth MOS tube and a sixteenth MOS tube; The first end of the sixth MOS tube is connected to the high level of the high voltage domain, the control end of the sixth MOS tube is connected to the control end of the sixteenth MOS tube and then connected to the first-stage inverter, the second end of the sixth MOS tube is connected to the first end of the sixteenth MOS tube and serves as the output end of the high voltage domain module, and the second end of the sixteenth MOS tube is connected to the low level of the high voltage domain.

10. The circuit according to claim 2, characterized in that The high-voltage domain module further includes: a NAND gate, a first inverter and a thirteenth MOS tube; The first end of the NAND gate is connected to the control signal, the second end of the NAND gate is connected to the clock signal, the output end of the NAND gate is connected to the first inverter, the first inverter is connected to the control end of the thirteenth MOS tube, the first end of the thirteenth MOS tube is connected to the pump capacitor, and the second end of the thirteenth MOS tube is grounded.

11. The circuit according to claim 1, characterized in that The low voltage domain module comprises: a ninth MOS tube and an eighteenth MOS tube; The first end of the ninth MOS tube is connected to the normally-on power domain, the control end of the ninth MOS tube is connected to the control end of the eighteenth MOS tube and then connected to the clock signal, the second end of the ninth MOS tube is connected to the first end of the eighteenth MOS tube and then connected to the high-voltage domain module, and the second end of the eighteenth MOS tube is grounded.

12. A transmitter, characterized in that: A level converter circuit, a buffer and a power tube comprising any one of claims 1 to 11; The level converter circuit is connected to the buffer, the buffer is connected to the power tube, the level converter circuit is used to drive and control the power tube, and the buffer is used to enhance the driving capability of the level converter circuit.

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