Wafer processing method

Abstract

Provided is a wafer processing method that can suppress the increase in required man-hours while providing a defect removal capability. The wafer processing method is a wafer thinning method, wherein the wafer processing method comprises the following steps: a protective member pasting step (ST2) of pasting the protective member on the front side of the wafer; a grinding step (ST3) of thinning the wafer by grinding the back side of the wafer using a grinding tool in which abrasive grains are fixed via a bonding material while holding the protective member side of the wafer with a holding surface of a chuck table; and a polishing step (ST4) of polishing the back side of the wafer until a grinding strain layer formed by grinding slightly remains after the grinding step (ST3).

Description

Technical Field

[0001] The present invention relates to a wafer processing method, in particular to a wafer thinning process. Background Art

[0002] As electronic devices become thinner and smaller, semiconductor devices are often required to be thin and small. For example, memory devices stack a large number of thin device chips to achieve high performance without increasing the size. In order to stack a large number of device chips, it is necessary to improve the bending strength of each device chip. In order to improve the bending strength of thin device chips, a processing technology has been developed to remove the strain layer caused by grinding from the ground wafer by grinding.

[0003] However, the processing technology of removing the strain layer caused by grinding by polishing will cause the following new problems: as the strain layer is removed, the defect removal ability of the device chip disappears, and the device has poor characteristics due to heavy metal contamination. Therefore, various processing technologies are considered to process the surface from which the strain layer is removed by polishing to a degree that has defect removal performance (for example, refer to Patent Documents 1 and 2).

[0004] Patent Document 1: Japanese Patent No. 4871617

[0005] Patent Document 2: Japanese Patent No. 6192778

[0006] However, the processing techniques disclosed in Patent Documents 1 and 2 temporarily cause a problem that the time required for processing to impart a gettering capability to the surface from which the strain layer has been removed by grinding increases. Summary of the invention

[0007] The present invention has been made in view of the above problems, and an object of the present invention is to provide a wafer processing method capable of providing a gettering capability while suppressing an increase in required man-hours.

[0008] In order to solve the above-mentioned problems and achieve the purpose, the wafer processing method of the present invention thins the wafer, and is characterized in that the wafer processing method has the following steps: a protective component pasting step, in which the protective component is pasted on the front side of the wafer; a grinding step, in which the protective component side of the wafer is held by the holding surface of a chuck table, and the back side of the wafer is ground and thinned by a grinding tool obtained by fixing abrasive grains by means of a bonding material; and a grinding step, in which, after the grinding step, slurry is supplied to the back side of the wafer and a rotating grinding pad is pressed against the back side of the wafer, and the back side of the wafer is ground until a grinding strain layer formed by grinding slightly remains, thereby generating a defect removal layer.

[0009] In the chip processing method, the chip processing method may also include the following grinding condition selection step: in order to determine the grinding conditions of the grinding step, the chip is ground after the grinding step is implemented, the surface roughness of the back side of the chip after grinding is measured according to the pressing force or grinding time of the grinding pad, and the grinding conditions corresponding to the surface roughness to be finished by the grinding step are selected.

[0010] In the wafer processing method, in the polishing step, the back side of the wafer may be polished so that the surface roughness of the grinding strain layer exceeds 1 nm and is 10 nm or less.

[0011] In the chip processing method, the chip may be a packaged chip obtained by covering a device chip mounted on a plate-shaped supporting substrate with a molded resin, and in the grinding step, the molded resin side is ground until the device chip is exposed, and in the grinding step, the surface of the molded resin side of the packaged chip is ground until the grinding strain layer slightly remains on the front side of the device chip exposed by grinding.

[0012] The wafer processing method of the present invention has the effect of providing a gettering capability while suppressing an increase in required man-hours. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a perspective view showing an example of a wafer to be processed by the wafer processing method according to the first embodiment.

[0014] Figure 2 This is a flowchart showing the flow of the wafer processing method according to the first embodiment.

[0015] Figure 3 It is shown Figure 2 A perspective view of a protective component pasting step in a wafer processing method shown.

[0016] Figure 4 It is shown Figure 2 A perspective view of a wafer after a protective member sticking step in the wafer processing method shown.

[0017] Figure 5 It is shown in partial section. Figure 2 A side view of the grinding step of the wafer processing method is shown.

[0018] Figure 6 yes Figure 2 A cross-sectional view of a main portion of a wafer after a grinding step of the wafer processing method is shown.

[0019] Figure 7 It is shown Figure 2 A side view of the grinding step of the wafer processing method is shown.

[0020] Figure 8 yes Figure 2 A side view of a main portion of a wafer after a grinding step of the wafer processing method is shown.

[0021] Fig. 9 yes Figure 2 The figure is a cross-sectional view of a main part of a wafer before the polishing condition selection step in the wafer processing method shown.

[0022] Fig.10 This is a perspective view showing a wafer to be processed by the wafer processing method according to the second embodiment.

[0023] Fig.11 It is along Fig.10 Cross-sectional view along line XI-XI.

[0024] Fig.12 This is a perspective view showing a wafer after processing according to the wafer processing method of the second embodiment.

[0025] Fig.13 It is along Fig.12 Cross-sectional view along line XIII-XIII in FIG.

[0026] Fig.14 Yes Fig.13 The XIV region is shown enlarged in the figure.

[0027] Description of symbols

[0028] 1: chip; 1-2: chip (packaged chip); 3, 11-1: front side; 6: back side; 7: grinding strain layer; 7-1: defect removal layer; 11: supporting substrate; 12: molding resin; 12-1: surface of molding resin (back side of chip); 21: chuck table; 22: holding surface; 23: grinding tool; 33: grinding pad; 200: adhesive tape (protective component); ST2: protective component pasting step; ST3: grinding step; ST4: grinding step; ST5: grinding condition selection step. DETAILED DESCRIPTION

[0029] With reference to the accompanying drawings, the mode (embodiment) for implementing the present invention is described in detail. The present invention is not limited by the contents described in the following embodiments. In addition, the constituent elements described below include contents that can be easily thought of by those skilled in the art, and substantially the same contents. In addition, the structures described below can be appropriately combined. In addition, various omissions, substitutions or changes in the structure can be made within the scope of the gist of the present invention.

[0030] [Implementation Method 1]

[0031] A wafer processing method according to Embodiment 1 of the present invention will be described with reference to the drawings. Figure 1 This is a perspective view showing an example of a wafer to be processed by the wafer processing method according to the first embodiment. Figure 2 This is a flowchart showing the flow of the wafer processing method according to the first embodiment.

[0032] The wafer processing method of the first embodiment is to Figure 1 The processing method for thinning the wafer 1 shown in the figure. In the first embodiment, the wafer 1 is a disk-shaped semiconductor wafer or an optical device wafer, and a substrate 2 is made of silicon, sapphire or gallium arsenide. Figure 1 and Figure 2 As shown, the wafer 1 has devices 5 formed in a plurality of regions divided by grid-shaped dividing lines 4 on the front surface 3 of the substrate 2. The device 5 is, for example, an IC (Integrated Circuit) or an LSI (Large Scale Integration).

[0033] The wafer processing method of the first embodiment is a method of thinning the wafer 1 to a predetermined finished thickness 100. Figure 2 As shown, the wafer processing method of the first embodiment includes a holding member pasting step ST2, a grinding step ST3, a lapping step ST4, and a lapping condition selection step ST5. In the wafer processing method of the first embodiment, an operator or the like determines whether the lapping conditions in the lapping step ST4 have been determined (step ST1), and when it is determined that the lapping conditions have been determined (step ST1: yes), the process proceeds to the protection member pasting step ST2. In addition, in the first embodiment, the lapping conditions in the lapping step ST4 are determined when a new type of wafer 1 is manufactured.

[0034] (Protective parts pasting steps)

[0035] Figure 3 It is shown Figure 2 A perspective view of a protective component pasting step in a wafer processing method shown. Figure 4 It is shown Figure 2 A perspective view of a wafer after a protective member sticking step in the wafer processing method shown.

[0036] The protective member pasting step ST2 is a step of pasting an adhesive tape 200 as a protective member on the front surface 3 side of the substrate 2 of the wafer 1. Figure 3 As shown, in the protective member pasting step ST2, after the adhesive layer of the adhesive tape 200 having the same diameter as the wafer 1 is placed opposite to the front surface 3 side of the substrate 2 of the wafer 1, as shown in FIG. Figure 4 As shown, the adhesive layer of the adhesive tape 200 is attached to the front surface 3 of the substrate 2 of the wafer 1. In the first embodiment, the adhesive tape 200 having the same diameter as the wafer 1 is used as the protective member, but in the present invention, the protective member is not limited to the adhesive tape 200, and for example, a hard disk-shaped substrate having the same diameter as the wafer 1 may be used. When the adhesive tape 200 is attached to the front surface 3 side of the substrate 2 of the wafer 1, the wafer processing method enters the grinding step ST3.

[0037] (Grinding steps)

[0038] Figure 5 It is shown in partial section. Figure 2 A side view of the grinding step of the wafer processing method is shown. Figure 6 yes Figure 2 1 is a cross-sectional view of a main part of a wafer after a grinding step of the wafer processing method shown in FIG. The grinding step ST3 is a step of thinning the wafer 1 by grinding the back side 6 of the wafer 1 located on the opposite side of the front side 3 by a grinding tool 23 obtained by fixing abrasive grains with a binder while holding the adhesive tape 200 side of the wafer 1 by a holding surface 22 of a chuck table 21 of a grinding device 20.

[0039] In the grinding step ST3, the grinding device 20 sucks and holds the front surface 3 of the wafer 1 on the holding surface 22 of the chuck table 21 via the adhesive tape 200. Figure 5 As shown, the grinding device 20 rotates the grinding wheel 25 and the chuck table 21 around the axis through the main shaft 24 while supplying grinding water 26 to the back side 6 of the wafer 1, and makes the grinding tool 23 of the grinding wheel 25 approach the chuck table 21 at a specified feed speed, so that the back side 6 of the substrate 2 of the wafer 1 is ground by the grinding tool 23.

[0040] When Figure 6 When the wafer 1 is thinned to a predetermined thickness 101 slightly thicker than the finished thickness 100 as shown, the wafer processing method enters the grinding step ST4. Figure 6 As shown, the wafer 1 after the grinding step ST3 has a grinding strain layer 7 formed on the entire back side 6 due to the grinding process in the grinding step ST3. The grinding strain layer 7 is a layer formed with crystal defects and strain on the surface layer of the back side 6 of the substrate 2 of the wafer 1, and is a layer that exerts a so-called defect removal ability, which can capture impurities mainly composed of metals such as copper (Cu) attached to the wafer 1 and suppress metal contamination of the device 5 due to impurities. In addition, the predetermined thickness 101 is preferably a thickness obtained by adding a thickness dimension (hereinafter referred to as a removal amount) 102 of the grinding strain layer 7 removed when the wafer 1 is ground according to the determined grinding conditions in the grinding step ST4 to the finished thickness 100.

[0041] (Grinding Step)

[0042] Figure 7 It is shown Figure 2 A side view of the grinding step of the wafer processing method is shown. Figure 8 yes Figure 2 1 is a side view of a main part of a wafer after the grinding step of the wafer processing method shown in FIG. The grinding step ST4 is a step in which, after the grinding step ST3, the back side 6 of the wafer 1 is ground by pressing the grinding pad 33 of the rotating grinding device 30 against the back side 6 while supplying slurry to the back side 6 of the wafer 1 until a grinding strain layer 7 formed by grinding slightly remains, thereby generating a gettering layer 7-1.

[0043] In the grinding step ST4, the grinding device 30 sucks and holds the front surface 3 side of the wafer 1 on the holding surface 32 of the chuck table 31 via the adhesive tape 200. In the grinding step ST4, as shown in FIG. Figure 7 As shown, while the grinding wheel 35 is rotated by the main shaft 34 and the chuck table 31 is rotated around the axis, slurry as a grinding liquid is supplied from the slurry supply source 36 via the opening and closing valve 37 and the supply path 38 provided in the grinding wheel 35 to between the grinding pad 33 of the grinding wheel 35 and the back side 6 of the wafer 1, and the grinding pad 33 is brought close to the chuck table 31 at a prescribed feed speed, so that the back side 6 of the wafer 1 is ground by the grinding pad 33.

[0044] In embodiment 1, in the polishing step ST4, the polishing device 30 polishes the back side 6 of the chip 1 while providing a slurry containing abrasive grains as a polishing liquid. However, in the present invention, the back side 6 of the chip 1 can be polished using a polishing pad 33 with fixed abrasive grains while providing pure water as a polishing liquid, and chemical mechanical polishing (CMP: Chemical Mechanical Polishing) can be performed using a polishing pad 33 while providing an alkaline polishing liquid as a polishing liquid.

[0045] In addition, in the grinding step ST4, the back side 6 of the wafer 1 is ground according to a predetermined grinding condition. In the first embodiment, the grinding condition is the pressing force and grinding time of pressing the grinding pad 33 to the back side 6 of the wafer 1, and is a condition for grinding in such a manner that the surface of the grinding strain layer 7 is removed by grinding in the grinding step ST4, and the grinding strain layer 7 is slightly left to be flattened so that the surface roughness Ra of the surface of the grinding strain layer 7, i.e., the back side 6 of the wafer 1, exceeds 1 nm and is less than 10 nm. That is, "grinding the back side 6 of the wafer 1 until a state in which the grinding strain layer 7 slightly remains" mentioned in the present invention means grinding the back side 6 of the wafer 1 in such a manner that the surface roughness Ra of the grinding strain layer 7 remaining after grinding, i.e., the surface roughness Ra of the back side 6 of the wafer 1, exceeds 1 nm and is less than 10 nm. In addition, the surface roughness Ra is the so-called arithmetic mean roughness. In this way, in the grinding step ST4, the grinding device 30 thins the grinding strain layer 7, and as Figure 8 As shown, the surface of the grinding strain layer 7, that is, the back side 6 of the substrate 2 of the wafer 1, is ground to form the grinding strain layer 7 into a gettering layer 7-1 having gettering capability, and the wafer 1 is thinned to a finished thickness of 100.

[0046] In the chip processing method of embodiment 1, the pressing pressure of the grinding pad 33 in the processing conditions of the grinding step ST4 is set to 15 kPa, and the grinding time is set to 15 seconds, so that the surface roughness Ra of the surface of the defect removal layer 7-1, that is, the back side 6 of the substrate 2 of the chip 1 is formed to be greater than 7nm and less than 8nm. However, the present invention can also set the pressing pressure of the grinding pad 33 in the processing conditions of the grinding step ST4 to 15 kPa, and the grinding time is set to 30 seconds, so that the surface roughness Ra of the surface of the defect removal layer 7-1, that is, the back side 6 of the substrate 2 of the chip 1 is formed to be greater than 4nm and less than 6nm. The pressing pressure of the grinding pad 33 in the processing conditions of the grinding step ST4 can also be set to 15 kPa, and the grinding time is set to 60 seconds, so that the surface roughness Ra of the surface of the defect removal layer 7-1, that is, the back side 6 of the substrate 2 of the chip 1 is formed to be greater than 2nm and less than 3nm.

[0047] In the wafer processing method of the first embodiment, the diameter of the polishing pad 33 used in the polishing step ST4 is, for example, 450 mm, and the thickness of the polishing pad 33 is, for example, 4 mm. In the wafer processing method of the first embodiment, in the polishing step ST4, the rotation speed of the spindle 34 is, for example, 500 rpm, the rotation speed of the chuck table 31 is 505 rpm, and the supply amount of the slurry is 0.2 L / min. When the back side 6 of the wafer 1 is polished according to the processing conditions in the polishing step ST4, the wafer processing method ends.

[0048] In addition, in the wafer processing method, when it is determined that the grinding conditions have not been determined (step ST1: No), the process proceeds to grinding condition selection step ST5.

[0049] (Grinding condition selection step)

[0050] Fig. 9 yes Figure 2 1 is a cross-sectional view of a main part of a wafer before the step of selecting a grinding condition in the method for processing a wafer shown in FIG. The step of selecting a grinding condition ST5 is a step of grinding the wafer 1 after the grinding step ST3 is performed in order to determine the grinding condition of the grinding step ST4, measuring the surface roughness Ra of the back side 6 of the ground wafer 1 according to the pressing force of the grinding pad 33 or the grinding time, and selecting the grinding condition corresponding to the surface roughness Ra to be finished by the grinding step ST4.

[0051] In the grinding condition selection step ST5, first, a plurality of wafers 1 that have been subjected to the grinding step ST3 are prepared, and different grinding conditions are set for each wafer 1. The back side 6 of the wafer 1 is ground using the grinding device 30 in the same manner as in the grinding step ST4, so that the grinding strain layer 7 is thinned, and the surface of the grinding strain layer 7, i.e., the back side 6 of the wafer 1, is flattened to form a gettering layer 7-1. In the grinding condition selection step ST5, Fig. 9 In the wafer after the grinding step ST3 shown in the figure, the removal amount 102 of the grinding strain layer 7 and the residual amount (the amount obtained by subtracting the removal amount 102 from the thickness 103 of the grinding strain layer 7) 104 are different according to the processing conditions, that is, the pressing force of the grinding pad 33 or the grinding time, and the surface roughness Ra of the surface of the getter layer 7-1 after grinding, that is, the back side 6 of the wafer 1 is different. In addition, the residual amount 104 is the thickness of the getter layer 7-1 after the grinding step ST4.

[0052] In the first embodiment, the larger the removal amount 102 in the polishing condition selection step ST5, the smaller the surface roughness Ra of the surface of the gettering layer 7-1, i.e., the back side 6 of the wafer 1. In addition, in the first embodiment, when the surface roughness Ra of the surface of the gettering layer 7-1 increases, the gettering ability (ability to capture impurities) of the device 5 after the wafer 1 is divided is improved, but the bending strength is reduced.

[0053] In the polishing condition selection step ST5, the surface roughness Ra of the back side 6 of the wafer 1 after polishing is measured according to the pressing force or polishing time of the polishing pad 33, and the surface roughness Ra of the back side 6 of the plurality of polishing conditions is the surface roughness to be finished by the polishing step ST4, that is, the processing condition within the range of more than 1 nm and less than 10 nm is selected as the processing condition of the polishing step ST4. In addition, in the polishing condition selection step ST5, when there are a plurality of processing conditions in which the surface roughness Ra of the back side 6 of the wafer 1 after polishing is more than 1 nm and less than 10 nm, the processing condition is selected in consideration of the defect removal capability and bending strength required for the device 5 after the wafer 1 is divided. When the processing condition of the polishing step ST4 is selected, the wafer processing method enters the protective component pasting step ST2.

[0054] In the wafer processing method of the first embodiment, in the grinding step ST4 after the grinding step ST3 of grinding the back side 6 of the wafer 1, the grinding removal amount 102 is set so that the grinding strain layer 7 is not completely removed but slightly remains, and then the back side 6 of the wafer 1 is ground in the grinding step ST4. Therefore, in the wafer processing method, the processing of the wafer 1 is completed in a state where the bending strength is improved and the gettering layer 7-1 having gettering ability is formed, so that effective wafer thinning and grinding can be performed. As a result, the wafer processing method has the following effects: it is not necessary to perform a step for imparting gettering ability after the grinding step ST4, and it is possible to suppress an increase in the required man-hours, and it is possible to impart gettering ability to the wafer 1 and the devices 5 obtained by singulating from the wafer 1 one by one.

[0055] In addition, in the wafer processing method of the first embodiment, in the grinding condition selection step ST5, the processing conditions are changed and the wafers 1 after the grinding step ST3 are ground in the same manner as in the grinding step ST4, thereby selecting appropriate grinding conditions. As a result, in the wafer processing method, it is not necessary to perform a step for imparting a gettering ability after the grinding step ST4, and it is possible to impart a gettering ability to the devices 5 obtained by singulating from the wafer 1 one by one and improve the bending strength.

[0056] In addition, in the chip processing method of embodiment 1, in the grinding step ST4, the back side 6 of the chip 1 is ground in such a manner that the surface of the grinding strain layer 7, i.e., the back side 6 of the chip 1, has a surface roughness Ra of more than 1 nm and less than 10 nm. Therefore, there is no need to perform a process for imparting defect removal capability after the grinding step ST4. At the same time, it is possible to impart defect removal capability and improve bending strength to the devices 5 singulated one by one from the chip 1.

[0057] [Implementation Method 2]

[0058] A wafer processing method according to Embodiment 1 of the present invention will be described with reference to the drawings. Fig.10 This is a perspective view showing a wafer to be processed by the wafer processing method according to the second embodiment. Fig.11 It is along Fig.10 Cross-sectional view along line XI-XI. Fig.12 This is a perspective view showing a wafer after processing according to the wafer processing method of the second embodiment. Fig.13 It is along Fig.12 Cross-sectional view along line XIII-XIII in FIG. Fig.14 Yes Fig.13 The XIV region in FIG. is enlarged and shown in FIG. Fig.10 , Fig.11 , Fig.12 , Fig.13 as well as Fig.14 In the present invention, the same parts as those in Implementation 1 are marked with the same reference numerals and the description thereof is omitted.

[0059] The wafer processing method of the second embodiment is the same as the first embodiment except that the wafer 1-2 to be processed is different. Fig.10 and Fig.11 As shown, a wafer 1 - 2 to be processed by the wafer processing method of the second embodiment includes: a plurality of device chips 10 ; a disk-shaped support substrate 11 ; and a mold resin 12 .

[0060] The device chip 10 is manufactured, for example, by dividing the wafer 1 shown in the first embodiment along the predetermined dividing line 4. The device chip 10 is mounted on the support substrate 11 at equal intervals by overlapping the front surface 3 on which the device 5 is formed on the support substrate 11. In the second embodiment, the support substrate 11 has a wiring layer (not shown) connected to the electrodes of the device chip 10, but the present invention is not limited to this. The molding resin 12 is composed of a synthetic resin and covers the plurality of device chips 10 on the support substrate 11. In this way, the wafer 1-2 to be processed by the wafer processing method of the second embodiment is a so-called packaged wafer in which the device chip 10 mounted on the support substrate 11 is covered with the molding resin 12.

[0061] The wafer processing method of the second embodiment includes the protective member pasting step ST2, the grinding step ST3, the polishing step ST4 and the polishing condition selection step ST5 in the same manner as the first embodiment. Fig.12As shown in FIG. 1 , an adhesive tape 200 as a protective member is attached to the front surface 11-1 of the support substrate 11 of the wafer 1-2. In the wafer processing method of Embodiment 2, in the grinding step ST3, the adhesive tape 200 side of the wafer 1-2 is held by the chuck table 21 of the grinding device 20, and the surface 12-1 of the molded resin 12 as the back side of the wafer 1-2 is ground by the grinding tool 23, thereby grinding the molded resin 12 until the wafer 1-2 is as shown in FIG. Fig.12 and Fig.13 As shown, the grinding strain layer 7 is formed on the back surface 6 of the device chip 10 located on the opposite side to the front surface 3 until the device chip 10 is exposed on the surface 12 - 1 side of the mold resin 12 .

[0062] In the wafer processing method of the second embodiment, in the grinding step ST4, while providing slurry to the surface 12-1 of the molded resin 12 of the wafer 1-2 and the back side 6 of the device chip 10 exposed by grinding, the back side 6 and the surface 12-1 of the molded resin 12 side of the wafer 1-2 are ground in the same manner as in the first embodiment until a state is achieved in which a grinding strain layer 7 slightly remains, as shown in FIG. Fig.14 As shown, a gettering layer 7 - 1 having the same surface roughness Ra as that of the first embodiment is formed on the back surface 6 of the device chip 10 .

[0063] In the wafer processing method of the second embodiment, in the grinding step ST4 after the grinding step ST3 for grinding the back side 6 of each device chip 10 of the wafer 1-2, the removal amount 102 by grinding is set so that the grinding strain layer 7 is not completely removed but slightly left, and then the back side 6 of the wafer 1-2 is ground in the grinding step ST4. As a result, in the wafer processing method of the second embodiment, in the same manner as in the first embodiment, it is not necessary to perform a step for imparting a gettering capability after the grinding step ST4, and an increase in the required man-hours can be suppressed, while imparting a gettering capability to the wafer 1-2 and the device chips 10 including the devices 5 obtained by singulating from the wafer 1-2 one by one.

[0064] In addition, in the chip processing method of embodiment 2, in the grinding step ST4, the grinding is performed in a manner that the grinding strain layer 7 is not completely removed but slightly remains, so that the remaining grinding strain layer 7 becomes the defect removal layer 7-1. Therefore, it is particularly possible to suppress the required working time for processing the packaged chip, i.e., the chip 1-2, which is obtained by covering the device chip 10 arranged on the supporting substrate 11 with the molding resin 12, and at the same time, the defect removal layer 7-1 can be formed on the device chip 10.

[0065] Next, the inventors of the present invention confirmed the effect of the wafer processing method of the present invention. The results are shown in Table 1.

[0066]

Table 1

[0067] Pressing force Grinding time Surface roughness Ra Defect removal capability Bending strength Comparative Example 1 25kPa 2min Below 1nm × ○ Product 1 of the present invention 15kPa 60sec 2nm~3nm ○ ○ Product 2 of the present invention 15kPa 30sec 4nm~6nm ○ ○ Product 3 of the present invention 15kPa 15sec 7nm~8nm ○ ○ Comparative Example 2 15kPa 5sec More than 10nm ○ ×

[0068] In Table 1, the inventors of the present invention grind a plurality of wafers 1 after the grinding step ST3 in the same manner as the grinding step ST4 with different grinding conditions, and produce Comparative Example 1, Comparative Example 2, Inventive Product 1, Inventive Product 2, and Inventive Product 3. The inventors of the present invention respectively confirmed the surface roughness Ra of the surface of the residual grinding strain layer 7, i.e., the removal layer 7-1, the removal ability, and the bending strength after division in Comparative Example 1, Comparative Example 2, Inventive Product 1, Inventive Product 2, and Inventive Product 3 in Table 1. In addition, in Comparative Example 1, Comparative Example 2, Inventive Product 1, Inventive Product 2, and Inventive Product 3, the surface roughness Ra of the surface of the grinding strain layer 7 of the wafer 1 after the grinding step ST3 is about 10 nm.

[0069] The grinding conditions of Comparative Example 1 are as follows: the pressing force of the grinding pad 33 is set to 25 kPa, and the grinding time is set to 2 min. The grinding conditions of Comparative Example 2 are as follows: the pressing force of the grinding pad 33 is set to 15 kPa, and the grinding time is set to 5 sec. The grinding conditions of the present invention product 1 are as follows: the pressing force of the grinding pad 33 is set to 15 kPa, and the grinding time is set to 60 sec. The grinding conditions of the present invention product 2 are as follows: the pressing force of the grinding pad 33 is set to 15 kPa, and the grinding time is set to 30 sec. The grinding conditions of the present invention product 3 are as follows: the pressing force of the grinding pad 33 is set to 15 kPa, and the grinding time is set to 15 sec.

[0070] The surface roughness Ra of the surface of the gettering layer 7-1 of Comparative Example 1 is less than 1 nm, and the surface roughness Ra of the surface of the gettering layer 7-1 of Comparative Example 2 exceeds 10 nm. In addition, the surface roughness Ra of the front surface of the gettering layer 7-1 of the present invention product 1 is greater than 2 nm and less than 3 nm, the surface roughness Ra of the front surface of the gettering layer 7-1 of the present invention product 2 is greater than 4 nm and less than 6 nm, and the surface roughness Ra of the front surface of the gettering layer 7-1 of the present invention product 3 is greater than 7 nm and less than 8 nm.

[0071] In Table 1, device chips having the required gettering capability after being singulated one by one are indicated by "○", and device chips not having the required gettering capability are indicated by "×". In Table 1, device chips having the required bending strength after being singulated one by one are indicated by "○", and device chips not having the required bending strength are indicated by "×".

[0072] According to Table 1, the defect removal capability of Comparative Example 1 is "×", whereas the defect removal capabilities of Inventive Product 1, Inventive Product 2, and Inventive Product 3 are "○". Therefore, it can be seen from Table 1 that the required defect removal capability can be imparted by grinding the wafers 1 and 1-2 after the grinding step ST3 in the grinding step ST4 so that the surface roughness Ra of the defect removal layer 7-1 of the remaining grinding strain layer 7 exceeds 1 nm and is 10 nm or less.

[0073] In addition, according to Table 1, the bending strength of Comparative Example 2 is "×", while the bending strength of Inventive Product 1, Inventive Product 2, and Inventive Product 3 is "○". Therefore, according to Table 1, it can be seen that in the grinding step ST4, by grinding the wafers 1 and 1-2 after the grinding step ST3 so that the surface roughness Ra of the gettering layer 7-1 of the remaining grinding strain layer 7 exceeds 1 nm and is 10 nm or less, the required bending strength can be imparted. Therefore, according to Table 1, by grinding the wafers 1 and 1-2 after the grinding step ST3 so that the surface roughness Ra of the gettering layer 7-1 exceeds 1 nm and is 10 nm or less in the grinding step ST4, the required gettering ability and bending strength can be imparted, and it is not necessary to perform a step for imparting the gettering ability after the grinding step ST4, and it is possible to simultaneously achieve the impartment of the gettering ability and the improvement of the bending strength.

[0074] The present invention is not limited to the above-described embodiment, and can be implemented with various modifications within the scope of the present invention.

Claims

1. A method for processing a wafer, wherein the wafer is thinned, wherein: The wafer processing method has the following steps: a step of attaching a protective component to the front side of the wafer; A grinding step, wherein the protective component side of the wafer is held by a holding surface of a chuck table, and the back side of the wafer is ground and thinned by a grinding tool in which abrasive grains are fixed by a bonding material; as well as a grinding step, after the grinding step, supplying slurry to the back side of the wafer while pressing a rotating grinding pad to the back side of the wafer, grinding the back side of the wafer until a grinding strain layer formed by grinding slightly remains, thereby generating a gettering layer, This wafer is a packaged wafer in which a device chip mounted on a plate-shaped supporting substrate is covered with a mold resin. In the grinding step, the molded resin side is ground until the device chip is exposed. In the grinding step, the surface of the package wafer on the mold resin side is ground until the grinding strain layer slightly remains on the front surface of the device chip exposed by grinding.

2. The wafer processing method according to claim 1, wherein: The chip processing method also has the following grinding condition selection step: in order to determine the grinding conditions of the grinding step, the chip is ground after the grinding step is implemented, the surface roughness of the back side of the chip after grinding is measured according to the pressing force or grinding time of the grinding pad, and the grinding conditions corresponding to the surface roughness to be finished by the grinding step are selected.

3. The wafer processing method according to claim 1 or 2, wherein: In the polishing step, the back side of the wafer is polished so that the surface roughness of the grinding strain layer exceeds 1 nm and is 10 nm or less.

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