NMOS ESD protection device with gate boost

Abstract

An ESD protection device includes: a PNP transistor connected to an input pad; a diode connected to the PNP transistor and to an output pad; and an NMOS transistor connected to the PNP transistor and the output pad, wherein the diode, the PNP transistor, and the NMOS transistor are configured to route electrostatic discharge (ESD) current pulses of different levels from the input pad to the output pad.

Description

Technical Field

[0001] Various exemplary embodiments disclosed herein relate to electrostatic discharge (ESD) protection, and more particularly to a gate-boosted NMOS ESD protection device triggered by a PNP in series with a diode. Background Art

[0002] Traditionally, grounded gate NMOS (GGNMOS) devices are used as local protection for fail-safe applications and open-drain applications. However, the trigger voltage (VT1) of both the GGNMOS and the device to be protected (victim) is usually almost the same. In fact, the gate of the victim is floating during ESD stress, and when the gate node is raised relative to the grounded gate condition, the fault voltage of the victim is lower. Therefore, GGNMOS is not able to protect the victim. Using other process options, devices that have been drain engineered (with p-type heavily doped or ESD implanted layers) and triggered by Zener diodes have been demonstrated. With other circuit systems, gate coupling solutions, gate drive solutions, or PNP trigger solutions for reducing VT1 have been demonstrated. In fact, these methods are only useful for power supply protection because fast signals may cause false triggering. Summary of the invention

[0003] A brief overview of various embodiments is presented below. Some simplifications and omissions may be made in the following overview, which is intended to highlight and introduce certain aspects of the various embodiments, rather than to limit the scope of the invention. A detailed description of embodiments sufficient to allow one of ordinary skill in the art to create and use the inventive concept will be presented in later chapters.

[0004] An embodiment includes an electrostatic discharge (ESD) protection device comprising: a PNP transistor connected to an input pad; a diode connected to the PNP transistor and to an output pad; and an NMOS transistor connected to the PNP transistor and to the output pad, wherein the diode, the PNP transistor, and the NMOS transistor are configured to route electrostatic discharge (ESD) current pulses of different levels from the input pad to the output pad.

[0005] The ESD protection device may be triggered by a PNP transistor connected in series with the diode. The trigger mechanism of the ESD protection device may be a floating base region of the PNP transistor connected in series with the diode. Due to the floating base region of the PNP transistor, the NMOS transistor may be in an initially disconnected state.

[0006] The diode and the PNP transistor may combine to form a low current path for ESD current.

[0007] The PNP transistor and the NMOS transistor may combine to form a medium current path for the ESD current.

[0008] The NMOS transistor and the PNP transistor may be combined to form an embedded SCR configured to route a high current path for the ESD current.

[0009] The gate of the NMOS transistor may be connected to the collector of the PNP transistor and to the anode of the diode.

[0010] An emitter of the PNP transistor may be connected to the input pad.

[0011] The ESD current may be conducted through the channel of the NMOS transistor and the parasitic parallel NPN transistor through the gate-boosted NMOS, and boosted at a higher current level via the action of the embedded SCR.

[0012] The ESD protection device may include: a first isolation region disposed between the diode and the PNP transistor; and a second isolation region disposed between the PNP transistor and the NMOS transistor.

[0013] The first highly doped isolation region may be wider than the second highly doped isolation region.

[0014] The PNP transistor may have emitter and collector contact regions having the same conductivity type as the first isolation region and the second isolation region.

[0015] Embodiments may also include a method of operating an electrostatic discharge (ESD) device, comprising: receiving a low-energy current portion of an ESD pulse at a PNP transistor; conducting the low-energy current portion of the ESD pulse to an output pad through a diode; receiving a medium-current pulse of the ESD pulse at the PNP transistor; conducting the medium-energy current of the ESD pulse to the output pad through an NMOS transistor; receiving a high-energy current portion of the ESD pulse at the PNP transistor; and conducting the high-energy current portion of the ESD pulse to the output pad through a silicon-controlled rectifier (SCR) formed by the PNP transistor and the NMOS transistor.

[0016] The method may include triggering the ESD protection device using the PNP transistor in series with the diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Additional objects and features of the present invention will become more readily apparent from the following detailed description and the appended claims when taken in conjunction with the accompanying drawings. Although several embodiments are shown and described, like reference numerals designate like parts in the various drawings, in which:

[0018] Figure 1 shows a circuit diagram of an ESD protection device according to an embodiment described herein;

[0019] Figure 2 Shown according to Figure 1 Layout design of ESD protection devices;

[0020] Figure 3 Shown along the basis Figure 2 A cross-sectional view of a layout structure of an ESD protection device taken along line XX′;

[0021] Figure 4A A first operating mechanism of an ESD protection device during a positive ESD stress from a PAD to a VSS pin according to embodiments described herein is shown;

[0022] Figure 4B A second operating mechanism of the ESD protection device during a positive ESD stress from the PAD to the VSS pin according to embodiments described herein is shown;

[0023] Figure 4C A third operating mechanism of an ESD protection device during a positive ESD stress from a PAD to a VSS pin according to embodiments described herein is shown;

[0024] Figure 5 shows DC current-voltage characteristics with respect to temperature for an ESD protection device according to embodiments described herein;

[0025] Figure 6 shows a DC holding voltage (VH) and a trigger voltage (VT1) as a function of temperature for an ESD protection device according to embodiments described herein;

[0026] Figure 7 shows a test structure of an ESD device connected in parallel with a device to be protected (victim) according to embodiments described herein;

[0027] Figure 8 A schematic diagram showing the VF-TLP characteristics of an ESD protection device and an independent 5-V gate monitoring test structure according to embodiments described herein; and

[0028] Fig. 9 The TLP long pulse characteristics of GGNMOS, FBPNP+diode and ESD protection device are shown. DETAILED DESCRIPTION

[0029] It should be understood that the drawings are only schematic and are not necessarily drawn to scale. It should also be understood that the same reference numerals are used throughout the drawings to indicate the same or similar parts.

[0030] The specification and the accompanying drawings illustrate the principle of each example embodiment. Therefore, it should be understood that those skilled in the art will be able to design various arrangements that embody the principle of the present invention and are included in the scope of the present invention, although the arrangement is not clearly described or shown herein. In addition, all examples cited herein are clearly intended to be used for teaching purposes in principle to help readers understand the concept of the principle of the present invention and the inventor's contribution to promote this area, and should be understood as not being limited to the examples and conditions of this specific citation. In addition, unless otherwise indicated (for example, "otherwise" or "or in an alternative scheme"), the term "or" as used herein refers to non-exclusive or (that is, and / or). Moreover, each embodiment described herein is not necessarily mutually exclusive, because some embodiments can be combined with one or more other embodiments to form a new embodiment. Descriptors such as "first", "second", "third" do not mean to limit the order of the elements discussed, but are used to distinguish an element from the next element, and are usually interchangeable. Values ​​such as maximum or minimum values ​​can be predetermined and set to different values ​​based on application.

[0031] The embodiments described herein include voltage-triggered ESD devices based on PNP, diode, and GGNMOS components. By connecting the gate of an NMOS to the anode of a diode, a gate-boosted NMOS is formed and triggered by a floating base PNP transistor in series with a diode.

[0032] Figure 1 A circuit diagram of an ESD protection device 100 according to embodiments described herein is shown. Figure 2 Shown according to Figure 1 Layout design of the ESD protection device 100 . Figure 3 Shown along the basis Figure 2 FIG. 1 is a cross-sectional view of a layout structure of the ESD protection device 100 taken along line XX′.

[0033] like Figure 1-3 As shown, the ESD protection device 100 includes a diode 101, a PNP transistor 102, and an NMOS transistor 103. In normal operation, the ESD protection device 100 is in an off state. The ESD protection device 100 can be configured to handle ESD pulses originating from the human body, which is called the human body model (HBM), or to handle manufacturing discharges, which is called the charged device model (CDM).

[0034] An ESD current pulse may be received at pad 105. The ESD protection device 100 described herein is configured to handle and direct ESD current pulses of different current levels. The diode 101 in combination with the PNP transistor 102 may be configured to handle a low current path for an ESD current pulse. The PNP transistor 102 in combination with the diode 101 and the NMOS transistor 103 may be configured to handle a medium current path for an ESD current pulse. The PNP transistor 102 in combination with the NMOS transistor 103 may form an embedded silicon controlled rectifier (SCR) device configured to handle a high current path for an ESD current pulse.

[0035] Regarding the structure of the device, Figure 1 As shown, diode 101 has an anode terminal 120 connected to the collector region 118 of PNP transistor 102 and the gate of NMOS transistor 103. Cathode terminal 130 is connected to reference node VSS 107. Figure 2 The diode 101 is shown disposed along one edge of the semiconductor substrate 200. The semiconductor substrate 200 may be of a first conductivity type, P-type. The diode 101 may be disposed in a first well 310 (shown in FIG. 1 ) of a second conductivity type, N-type. Figure 3 The diode 101 may include a highly doped anode terminal 120 of a first conductivity type P type and a highly doped cathode terminal 130 of a second conductivity type N type. The highly doped anode terminal 120 and the highly doped cathode terminal 130 may be separated by a shallow trench isolation (STI) region 230. Figure 3 The diode 101 is shown disposed along the one edge of the semiconductor substrate 200. The anode terminal 120 may be connected to the collector region 118 of the PNP transistor 102 and to the gate electrode 110 of the NMOS transistor 103 through a first conductive line 330.

[0036] During an ESD event, the low current component of the ESD pulse can enter the highly doped emitter region 122 of the first conductivity type through the pad 105, and enter the collector region 118, which is also highly doped and belongs to the first conductivity type, through the second well 320 of the second conductivity type acting as the base. The collector region 118 sends the low current component to the anode terminal 120 of the diode 101 through the first conductive line 330, and the low current is routed to the reference node VSS 107 through the cathode terminal 130 to complete the low current path.

[0037] Figure 4A1 shows a first operating mechanism of the ESD protection device 100 during a positive ESD stress from the PAD 105 to the VSS pin 107. Before the PNP transistor 102 connected in series with the diode 101 is triggered, the NMOS transistor 103 can remain in the off state and behave like a large resistor. Therefore, the base well 320 and the base contact region 116 (shown in FIG. 1 ) of the PNP transistor 102 are Figure 3 Thus, for the low current path, the trigger mechanism of the ESD protection device 100 can be determined by a floating base PNP transistor 102 (FBPNP) in series with the diode 101, as shown in Figure 3 The low current path 311 is shown with a small dash in the Figure 4A Indicated in .

[0038] For PNP transistor 102, see Figure 1 , the emitter region 122 of the PNP transistor 102 is connected to the pad 105. The base contact region 116 of the PNP transistor 102 is connected to the drain region 114 of the NMOS transistor 103. The collector region 118 of the PNP transistor 102 is connected to the anode terminal 120 of the diode 101 and to the gate electrode 110 of the NMOS transistor 103.

[0039] like Figure 2 As shown, a plurality of PNP transistors 202 may be disposed in a middle portion of a semiconductor substrate 200. The plurality of PNP transistors 202 may include a parallel configuration of emitter regions 122 and collector contact regions 118 separated by different segments of an N-well 220. The configuration of the emitter region 122 and the collector contact region 118 may be bounded on four sides by STI regions 240. The STI region 240 may be further bounded by a high doping concentration base contact region 116. The configuration of the emitter contact region 122, the collector contact region 118, and the STI 240 region may reside within a base well 320 of a second conductivity type N-type. The high doping concentration base contact regions 116 and 124 may be bounded by STI regions 240 and 250.

[0040] like Figure 3 As shown, the string of the emitter region 122 and the collector region 118 is disposed in a second well 320 of the second conductivity type, and the second well 320 is disposed on top of the semiconductor substrate 200 of the first conductivity type. The PNP transistor 102 and the diode 101 can be separated by a first highly doped isolation region 326 of the first conductivity type P type and a first well 328 of the first conductivity type P type. On the other hand, the PNP transistor 102 and the NMOS transistor 103 can be separated by a second highly doped isolation region 336 of the first conductivity type P type and a second well 338 of the second conductivity type P type. The first highly doped isolation region 326 can have a wider width than the second highly doped isolation region 336.

[0041] PNP transistor 102 funnels the medium current of the received ESD current pulse to Figure 3 107. In combination with the low current path routed by diode 101 and PNP 102, the medium intensity energy of the current pulse penetrates deep into the N well 320 below the STI region and is attracted to the adjacent highly doped P base contact region 124. A second conductive line 340 connects the base contact region 124 and the drain 114 of the NMOS transistor 103. The ESD current in the NMOS transistor 103 flows from the drain 114 to the source 112 and then flows to the reference node VSS through the third conductive line 350. The reference node 107 VSS can provide a bias potential for the isolated P regions 326 / 328 and 336 / 338.

[0042] Figure 4B FIG. 1 shows a second operating mechanism of the ESD protection device 100 during a positive ESD stress from the PAD 105 to the VSS pin 107. For the medium current path, after the FBPNP transistor 102 conducts the ESD current, the gate voltage of the NMOS transistor 103 is above VSS 107 by at least the voltage drop across the diode 101. Therefore, the ESD current is conducted by the channel of the NMOS 103 and the parasitic NPN of the NMOS 103 through the gate boost, as shown in FIG. Figure 3 The dashed arrow 322 and the Figure 4B The parasitic NPN transistor may extend from the drain 114 to the source 112 into the P-well region 338 .

[0043] Regarding the NMOS transistor 103, Figure 2 A plurality of drain-connected NMOS devices 203a are shown on one side of the PNP transistor region 202 and a second plurality of NMOS devices 203b are shown on a second side of the PNP transistor region 202. Figure 2 The cross section of X′ shows the cross section of a single NMOS transistor 103 .

[0044] NMOS transistor 103 sinks the high current of the received ESD current pulse to Figure 3The high current path 333 shown by the long dashed line 333 in the ESD protection device 100. The routing of the high current path 333 in the ESD protection device 100 includes the operation of the embedded PNPN silicon controlled rectifier (SCR) device. The high energy component of the ESD current pulse enters the P-doped emitter contact region 122 and is further driven into the low component and medium component N-well 320. The high energy component flows substantially to the bottom of the medium doped N-well 320. The high current path 333 flows into the medium doped P-well 338 and flows out of the highly doped N source region 112. The discharge current can be routed from the source through the wire 350 to the reference potential VSS 107.

[0045] Figure 4C 1 shows a third operating mechanism of the ESD protection device 100 during a positive ESD stress from the PAD 105 to the VSS pin 107. For the high current path, once the current is high enough to trigger the parasitic transistors PNP (regions 122, 320, 338) and NPN (regions 320, 338, 112), the embedded SCR discussed above starts to function and shunts the remaining ESD current, as shown in FIG. Figure 3 The long dashed arrow 333 and Figure 4C as indicated in the “high current path” 333 portion.

[0046] The above embodiments can be used for positive stress from PAD 105 to VSS 107. For negative ESD current pulses, a dedicated external diode 104 can be used to enhance the ESD performance of negative stress from PAD 105 to reference node VSS 107.

[0047] Depending on the conductivity preference of the designer, the diode 101, the lateral PNP transistor 102 and the NMOS transistor 103 can be silicided or non-silicided. The total width of the PNP transistor 102, the NMOS transistor 103 and the diode 101 can be 1000 μm, 200 μm and 46 μm respectively. The finger width of both the PNP transistor 102 and the NMOS transistor 103 can be 50 μm.

[0048] like Figure 3 As shown, in order to avoid SCR action between PNP transistor 102 and diode 101, wide high-doped P region 326 may have a length of about 10 μm. In order to enhance the high current path ESD current capability by triggering the embedded SCR between PNP transistor 102 and GGNMOS 103 in the high current range, distance d1 may be about 7.5 μm, including intentionally narrow high-doped P region 336.

[0049] An alternative to using PNP 102 would be to use a PMOS device. Figure 3As shown, the highly doped P emitter 122 region and the highly doped P collector 118 region can be used as P doped source region and P doped drain region. A gate 360 ​​can be used to create a conduction channel. Instead of connecting to the emitter 122 of the PAD 105, the gate 360 ​​will be connected to the PAD 105 to receive the ESD pulse.

[0050] Figure 5 The DC current-voltage characteristics with respect to temperature are shown for the ESD protection device 100. The breakdown voltage is above 5V at all temperatures, and the leakage current is less than 1 μA at sub-5-V, which is a typical product requirement.

[0051] Figure 6 1 shows the DC holding voltage (VH) and trigger voltage (VT1) for the ESD protection device 100 as a function of temperature. Figure 5 As shown, VH can be captured at the lowest voltage point in the magnified view. For good noise or transient event immunity, VT1 can be higher than 5V. The ESD protection device 100 shows a VT1 of 7.2V at 150°C, which represents a 40% margin. The requirement for VH is that after the device has triggered, VH should be higher than 5V to obtain reasonably good latch-up immunity. Therefore, it should be clear that the ESD protection device 100 can be safely used in most mobile applications at 85°C.

[0052] Figure 7 A test structure 700 of an ESD device in parallel with a device to be protected (victim) according to an embodiment described herein is shown. The embodiment discusses transmission line pulse (TLP) current-voltage characteristics. To estimate ESD robustness, a safe operating region and voltage and current conditions can be characterized under which the device can be expected to operate without self-damage to the NMOS victim transistor. In order to increase the victim's breakover voltage by reducing the base resistance of the parasitic lateral bipolar transistor, an additional Psub protection ring can be inserted around each two fingers of the victim. The use of a floating base PNP 102 can be used to reduce VT1. The use of a gate-lifted NMOS 103 reduces VT1 and provides substantially uniform turn-on for multi-finger implementations. In this technique, the VT1 of the FBPNP 102 plus the diode 101 is about 7.6V, which is much lower than the 9.3V of the non-floating base PNP plus the diode. When the voltage at the gate 110 is 1-2V, the VT1 of the parasitic NPN bipolar transistor of the NMOS 103 is about 6.5-7.0V.

[0053] Figure 7The TLP characteristics of the ESD protection device 100 and those of the FBPNP 102 plus the diode 101 and the 200 μm wide non-silicided GGNMOS 103 are shown. The total width of the silicided NMOS "victim" can be 240 μm. The last point of each curve is the point just before the hard failure. The ESD protection device shows three ESD current conduction ranges. In the low current range (up to 0.4A), the mechanism is determined by the FBPNP 102 plus the diode 101, as indicated in the "low current" TLP characteristics via the similar slope of the FBPNP 102 plus the diode 101. In the medium current range (0.5-1.7A), the ESD current is conducted by the parallel combination of the NMOS 103, FBPNP 102 and the diode 101 through the gate lifting and is greater than the current of the single GGNMOS, as indicated in the "medium current" TLP characteristics. As discussed previously, the trigger voltage of the GGNMOS can be reduced if the gate node experiences a potential drop equivalent to a diode (at least), which is consistent with a VT1 of 8.6V (FBPNP 102 plus diode 101 = ~9.2V at 1.1A when diode doping = ~0.6V). In addition, extrapolating the curve from the medium current range to 6V on the voltage axis can indicate that the mechanism is determined by the NMOS 103 through gate boosting. In the high current range (1.8-4.0A), the additional ESD conduction current can be attributed to the embedded SCR action, because there is no separate ESD component in this scheme that can sustain such a high current IT2. In addition, extrapolating from the high current range to 4.5V on the voltage axis shows the SCR action with a deep breakover voltage.

[0054] Example ESD parameters for the devices described herein are summarized in Table I.

[0055] Table I - ESD parameters of ESD devices at 25°C

[0056]

[0057] a DC I leak Evaluation was performed at V = 5V.

[0058] b Width: 240 μm.

[0059] c Width: PNP=1000μm, Dp=23μm.

[0060] d Width: PNP=1000μm, Dp=46μm, ggNMOS=200μm.

[0061] If the ESD device fails to turn on in time, the gate oxide may be damaged by the ESD event in a very short rise time. Figure 8 Schematic diagram showing the VF-TLP characteristics of the ESD protection device 100 and an independent 5-V gate monitoring test structure. The last point of the curve is the point just before the hard failure. It can be seen that the ESD protection device 100 can be triggered early enough to protect the gate oxide layer.

[0062] As surge robustness requirements become more and more important, it is of interest to examine the ESD protection device 100 behavior at long pulse widths. Fig. 9 The TLP long pulse characteristics of GGNMOS, FBPNP+diode and ESD protection device 100 are shown. The last point of each curve is the point just before the hard failure. As can be seen, the ESD protection device 100 exhibits performance that is superior to that of conventional GGNMOS and FBPNP+DP ESD devices. The SCR action lasts until at least tpulse=500 nanoseconds. Table II shows the ESD mechanism of the ESD protection device 100 under 10-nanosecond rise time TLP conditions at different pulse widths.

[0063] Table II - ESD performance and I characteristics of the ESD protection device 100 at different pulse widths under 10-ns rise time TLP conditions at 25°C. T2 .

[0064]

[0065] Figure 5 The inset of FIG. 1 shows the DC current-voltage characteristics of the ESD protection device 100 with respect to temperature after the foldback. It can be seen that the conduction of the ESD current at 25° C. is dominated by the parasitic NPN transistor. Therefore, Figure 6 As shown, a high VH can be expected, which is consistent with the high VH under 25°C TLP conditions. Figure 7 1A). The ESD protection device 100 may have been damaged before the current level at which SCR action would kick in (see also Figure 8 ).

[0066] Figure 6 The DC measurement results are summarized (maximum current is 90mA). These DC power levels are about 10 times lower than the TLP power levels with longer pulse widths. Figure 5As shown in Figure 1, while the trigger current of the SCR decreases with increasing temperature, the SCR action begins to dominate the ESD conduction at higher temperatures. Therefore, VH is much lower at 150°C than at 25°C. When considering the self-heating effect, Figure 6 The deeper VH (3.2V) at 150°C and (at 25°C TLP conditions, Figure 7 This is consistent with the SCR conduction mechanism at high current levels (as seen in ).

[0067] For better latch-up safety, by increasing the base distance (d1) with a wider Psub tap, the ESD current can be rerouted through the gate-coupled NMOS. Alternatively, by simply increasing the channel length of the NMOS transistor, a higher VH can be expected. Figure 6 , surge robustness can be optimized by increasing the size of the NMOS transistor.

[0068] This combination of devices can be used to form ESD devices for specific applications such as open drain, fail safe, power supply and surge protection. This established approach saves silicon area, reduces time to market and can be easily ported to different technologies.

[0069] Embodiments described herein include a gate-boosted NMOS ESD protection device triggered by a PNP in series with a diode, which is demonstrated for 5-V mobile applications at up to 85°C in a 0.18μm CMOS process. The trigger mechanism can be determined by a floating base PNP in series with a diode, while the ESD current is conducted through the channel of the gate-boosted NMOS and a parasitic parallel NPN transistor, and boosted at higher current levels via the embedded SCR action. This voltage triggering technique can protect signal pins due to false triggering issues under capacitor triggering solutions. In addition, the ESD protection device 100 exhibits long pulse TLP characteristics that are superior to those of conventional GGNMOS and FBPNP+DP ESD devices, so robust surge performance can be expected.

[0070] In 0.18μm bulk CMOS technology, a gate-boosted NMOS ESD protection device is triggered by a PNP in series with a diode for 5V mobile applications up to 85°C. This voltage-triggered scheme is suitable for fail-safe, open-drain, power supply and surge protection. In addition, robust ESD performance is enhanced by embedded SCR action at high current ranges. This implementation does not require additional masks or additional RC control circuitry.

[0071] Although various exemplary embodiments have been described in detail with particular reference to certain exemplary aspects of the exemplary embodiments, it should be understood that the present invention is capable of other embodiments and that the details of the present invention are capable of modification in various obvious aspects. As will be readily apparent to those skilled in the art, changes and modifications may be made while remaining within the spirit and scope of the present invention. Therefore, the foregoing disclosure, description, and drawings are intended for illustrative purposes only and do not limit the present invention in any way, the present invention being limited only by the claims.

Claims

1. An electrostatic discharge (ESD) protection device, It is characterized in that include: A PNP transistor connected to an input pad; a diode having an anode terminal directly connected to the collector of the PNP transistor and a cathode terminal directly connected to an output pad; as well as An NMOS transistor connected to the PNP transistor and the output pad, wherein the diode, the PNP transistor are directly connected to a floating base region of the PNP transistor and the output pad, wherein the diode, the PNP transistor and the NMOS transistor are configured to route electrostatic discharge (ESD) current pulses of different levels from the input pad to the output pad, wherein the diode and the PNP transistor are combined to form a low current path for the ESD current, the PNP transistor and the NMOS transistor are combined to form a medium current path for the ESD current, and the NMOS transistor and the PNP transistor are combined to form an embedded SCR configured to route a high current path for the ESD current.

2. The ESD protection device according to claim 1, It is characterized in that The ESD protection device is triggered by a PNP in series with the diode.

3. The ESD protection device according to claim 1, It is characterized in that The gate of the NMOS transistor is connected to the collector of the PNP transistor and to the anode of the diode.

4. The ESD protection device according to claim 1, It is characterized in that The emitter of the PNP transistor is connected to the input pad.

5. The ESD protection device according to claim 1, It is characterized in that The ESD current is conducted through the channel of the NMOS transistor and the parasitic parallel NPN transistor through the gate-boosted NMOS, and is boosted at high current levels through the action of the embedded SCR.

6. The ESD protection device according to claim 1, It is characterized in that include: a first isolation region disposed between the diode and the PNP transistor; and a second isolation region disposed between the PNP transistor and the NMOS transistor.

7. A method of operating an electrostatic discharge (ESD) protection device, It is characterized in that include: Receiving a low energy current portion of the ESD pulse at the PNP transistor; conducting the low energy current portion of the ESD pulse to an output pad through a diode having an anode terminal directly connected to a collector of the PNP transistor and a cathode terminal directly connected to the output pad; receiving a medium energy current portion of the ESD pulse at the PNP transistor; conducting the medium energy current portion of the ESD pulse to the output pad through an NMOS transistor directly connected to a floating base region of a PNP transistor; receiving a high energy current portion of an ESD pulse at the PNP transistor; as well as conducting the high energy current portion of the ESD pulse to the output pad through a silicon controlled rectifier (SCR) formed by the PNP transistor and the NMOS transistor, wherein the diode and the PNP transistor are combined to form a low current path for the ESD current, the PNP transistor and the NMOS transistor are combined to form a medium current path for the ESD current, and the NMOS transistor and the PNP transistor are combined to form an embedded SCR configured to route a high current path for the ESD current.

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