Frequency drift detector, communication unit and method thereof

Abstract

The present disclosure relates to frequency drift detectors, communication units and methods thereof. A frequency drift detector (490) comprises a frequency-voltage converter FVC (450) arranged to receive a reference frequency signal (407) and configured to generate an FVC output voltage (455). The frequency drift detector (490) further comprises: a voltage regulator (310) arranged to output at least one regulated voltage; and a voltage comparator (460) coupled to the output of the FVC (450) and the output of the voltage regulator (310). The voltage comparator (460) is arranged to compare the FVC output voltage (455) with the at least one regulated voltage (458) and generate an error signal (470) in response to determining that the FVC output voltage (455) exceeds a frequency drift level indicated by the at least one regulated voltage (458).

Description

Technical Field

[0001] The technical field of the invention relates to frequency drift detectors and calibration methods thereof, for example for frequency synthesizers and communication units like automotive radar units. Background Art

[0002] Modern automotive frequency modulated continuous wave (FMCW) radar systems typically use a transceiver consisting of a transmitter, a receiver, and a frequency synthesizer source. In many of today's wireless communication applications, frequency synthesizers are used to facilitate RF communications and are often implemented by way of a phase locked loop (PLL), which often uses a crystal oscillator (XCO) as a reference signal for controlling a voltage controlled oscillator (VCO). The frequency synthesizer generates (often referred to as 'synthesizing') an output RF (sometimes referred to as a 'local oscillator') signal for transmitting and / or receiving RF signals. Frequency synthesizers are also used to generate the FMCW waveforms required for radar transmitters.

[0003] Figure 1 A conventional PLL design 100 for a radar unit is shown. A crystal oscillator 105 uses a crystal resonator 180, a load capacitor 175, which constitute a resonator in combination. The crystal oscillator 105 generates a resonant input frequency 107 provided to a frequency synthesizer 102 including a phase frequency detector (PFD) and a charge pump (CP) 110, which compares a feedback signal 145 with the generated resonant input frequency 107 and outputs an oscillator control signal 115 based on the comparison of the feedback signal 145 with the generated resonant input frequency 107. A low-pass loop filter 120 filters the oscillator control signal 115 and outputs a filtered oscillator control signal 125, which is provided to a voltage controlled oscillator (VCO) 130. The VCO 130 outputs a radio frequency signal 135 based on the filtered oscillator control signal 125. The feedback path of the PLL 100 consists of a frequency divider 140 that divides the output RF signal 135 to generate a divided feedback signal 145 , which is provided to the PFD and CP 110 .

[0004] Typically, in such a frequency synthesizer 102, there is also a voltage regulator 155 for providing a constant DC voltage to the PLL circuits and components, as well as safety sensors 150 such as an overvoltage detector and an undervoltage detector connected to the voltage regulator 155, and a PLL unlock monitor (not shown), for example, connected to the PLL.

[0005] However, due to temperature changes, voltage changes, component aging, etc., the reference frequency 107 may show variations. This variation is usually predetermined during design and verified during testing to ensure that the PLL design can operate in all possible variations or actual use. However, due to such excessive frequency drift (i.e., higher than this possible predetermined variation) of the crystal oscillator 105 output frequency 107, for example due to excessive variations of the crystal resonator 180 or the load capacitor (e.g., such as solder fracture or abnormal aging), there may be a risk of radar device failure. The result of the frequency drift higher than this known variation will be a transmitted signal that falls outside the regulated RF bandwidth. Specifically, such as in automotive radar device applications, such frequency drift may occur without any detection by any PLL safety sensor such as an unlock detector. In this specific case, the crystal oscillator 105 will still function, but its frequency will move by a few percentage points, and then this drift frequency is provided to the PLL. In order to withstand possible process, temperature and power supply variations (PVT), the PLL needs to have a higher frequency range than the radar device operating range. This effectively means that the PLL may remain locked outside the desired operating frequency range due to frequency drift of the crystal oscillator 105. Conventional safety detectors like PLL unlock monitors will not be triggered, ie no error signal like a flag will be enabled.

[0006] There are conventional methods for detecting frequency drift in synthesizers. However, these conventional methods use relative metrics with a second known frequency. For example, US 6064270A describes a system and method for compensating for reference frequency drift in a communication system, which uses a reference frequency for a comparison step. Other known frequency synthesizers transform the clock signal into a digital spectrum by using an ADC (whereby the ADC clock is used as a second known frequency in this case) and a Fourier transform. However, using a radar transceiver in the art (i.e., such as one installed in a car), it is impossible to detect any frequency drift by comparing the frequency of the crystal oscillator 105 output frequency 107 with the second known frequency, because all transceiver frequencies are referenced to a crystal oscillator 107 that is susceptible to excessive frequency drift. Summary of the invention

[0007] According to a first aspect of the present invention, there is provided a frequency drift detector, comprising:

[0008] a frequency-to-voltage converter FVC arranged to receive a reference frequency signal and configured to generate a FVC output voltage;

[0009] a voltage regulator arranged to output at least one regulated voltage; and

[0010] a voltage comparator coupled to the output of the FVC and to the output of the voltage regulator and arranged to compare the FVC output voltage with the at least one regulated voltage and to generate an error signal in response to determining that the FVC output voltage exceeds a level of frequency drift indicated by the at least one regulated voltage.

[0011] In one or more embodiments, the FVC includes a phase-locked loop PLL, which is arranged to receive the reference frequency signal; wherein the PLL includes: a phase detector, which detects the phase of the reference frequency signal and outputs a control signal; a loop filter, which is configured to filter the control signal; a voltage-controlled oscillator VCO, which is configured to generate an output radio frequency signal in response to the filtered control signal; and a feedback loop, which connects the output of the VCO to the phase detector; and a low-pass filter, which is arranged to filter the filtered control signal and generate the FVC output voltage.

[0012] In one or more embodiments, the PLL is operably coupled to a temperature compensation circuit such that the temperature compensation circuit is coupled to the VCO, and the temperature compensation circuit is arranged to apply a temperature compensation signal to the VCO such that in response thereto, the VCO tuning voltage remains constant with temperature.

[0013] In one or more embodiments, the PLL is operably coupled to a temperature compensation circuit such that the temperature compensation circuit is coupled to a programmable divider in a feedback path of the PLL, and the temperature compensation circuit is arranged to apply a temperature compensation signal to the programmable divider such that in response thereto, the VCO tuning voltage remains constant with temperature.

[0014] In one or more embodiments, the phase detector circuit is an XOR logic gate or a phase frequency detector plus charge pump circuit.

[0015] In one or more embodiments, the frequency drift detector is coupled to a safety sensor configured to receive the error signal and raise a flag in response to the FVC output voltage exceeding a frequency drift level indicated by the at least one regulated voltage comparison.

[0016] In one or more embodiments, the frequency drift detector is calibrated during a test mode of operation, whereby an external calibration reference source provides the reference frequency signal.

[0017] In one or more embodiments, the regulation voltage supplied to the voltage comparator is trimmed corresponding to a frequency drift limit during a test mode of operation to compensate for any process variations of the voltage comparator.

[0018] In one or more embodiments, the FVC is trimmed during a test mode of operation to compensate for any temperature variations using input from an external source configured to simulate resonator variations.

[0019] In one or more embodiments, a voltage controlled oscillator (VCO) of the FVC is temperature compensated so that a tuning voltage of the VCO remains constant over temperature.

[0020] In one or more embodiments, the VCO comprises a resonant circuit comprising at least two components from the group consisting of: one or more resistors, one or more capacitors, one or more inductors, and the temperature compensation is performed by adjusting at least one of the components of the resonant circuit such that the tuning voltage of the VCO is the same for each sample.

[0021] According to a second aspect of the present invention, there is provided a communication unit comprising a frequency drift detector according to any disclosed herein.

[0022] According to a third aspect of the present invention, there is provided a method for calibrating a frequency drift detector, the method being characterized by:

[0023] receiving at least one regulated voltage from a voltage regulator;

[0024] receiving a reference frequency signal at a frequency-to-voltage converter FVC input and generating a FVC output voltage in response thereto;

[0025] comparing the FVC output voltage to the at least one regulated voltage; and

[0026] At least one of: the FVC output voltage, the at least one regulated voltage output from the voltage regulator is trimmed so that the FVC output voltage and / or the at least one regulated voltage falls within a comparator window range.

[0027] In one or more embodiments, the method further includes generating an error signal in response to determining that the FVC output voltage exceeds the at least one regulation voltage, the error signal identifying excessive frequency drift.

[0028] In one or more embodiments, comparing the FVC output voltage to the at least one regulated voltage further includes measuring the FVC output voltage and measuring the at least one regulated voltage during final testing or production testing.

[0029] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Additional details, aspects and embodiments of the present invention will be described by way of example only with reference to the accompanying drawings. In the accompanying drawings, similar reference numerals are used to identify similar or functionally similar elements. The elements in the accompanying drawings are shown for simplicity and clarity but are not necessarily drawn to scale.

[0031] Figure 1 A conventional phase-locked loop block diagram is shown.

[0032] Figure 2 A simplified block diagram of a communication unit such as a radar device adapted according to examples of the present invention is shown.

[0033] Figure 3 A more detailed block diagram of a communication unit according to an example of the present invention is shown, such as a radar device, a transceiver and a controller of the communication unit.

[0034] Figure 4 The example according to the present invention is shown as follows: Figure 3 A simplified block diagram of a first example of a frequency drift detector for a security sensor associated with a frequency synthesizer used in a communication unit.

[0035] Figure 5 The example according to the present invention is shown Figure 4 An example of an architectural implementation of a frequency-to-voltage converter (450) is shown.

[0036] Figure 6 The example according to the present invention is shown Figure 4 A simplified block diagram of a second example of an architectural implementation of a frequency-to-voltage converter (450) is shown.

[0037] Figure 7 A simplified flow chart showing an example of a calibration method for a frequency drift detector according to an example of the present invention (e.g., at T0 when a circuit (such as a frequency synthesizer) is in final test or production test and before the circuit is integrated into a communication unit such as a radar module).

[0038] Figure 8 An example of a safety sensor detector function in a radar device according to an example of the present invention is shown. DETAILED DESCRIPTION

[0039] According to some example embodiments of the present invention, a frequency drift detector and method of calibrating frequency drift detection are provided, for example where the frequency drift variation may be above an expected frequency drift range. In some examples, the frequency drift detector circuit (and one or more associated methods) uses a frequency-to-voltage converter to provide an indication of the frequency drift as a voltage and compares this converted voltage to a known calibration voltage. In this way, the inventors have recognized that parameters associated with the frequency drift variation may be evaluated by comparison operations, rather than unavailable (reference) frequency signals, thereby avoiding the above-mentioned current problems found in communication units such as modern radar units.

[0040] In some examples, it is contemplated that the frequency drift detection of the crystal oscillator output is converted to a DC voltage that can be compared to a regulated voltage that has been accounted for and monitored by the safety sensor. If the measured DC voltage is outside a given voltage range, such as corresponding to a known excessive frequency drift (e.g., based on crystal oscillator temperature and aging specified values), an error signal will be triggered.

[0041] In some examples, an external source may be used to calibrate the output voltage range of the frequency-to-voltage converter (FVC) corresponding to a predetermined crystal oscillator output frequency during the final test of the transceiver (e.g., by trimming, including adjusting the component values ​​of the FVC). In this way, in order to identify a fault indication of the resonator / oscillator, detecting the frequency drift ensures that the crystal oscillator output frequency starts at a suitable frequency within the desired frequency range after starting the transceiver or radar unit. In some examples, the voltage reference of the comparator corresponding to the frequency drift limit may also be trimmed. In the context of the present invention, the term trimming includes adjusting the voltage reference of the comparator corresponding to the frequency drift limit by changing the resistor value, while measuring the voltage reference until the voltage target is reached. In order to compensate for any process variations, the trimming operation may be performed in the final test.

[0042] In some examples, it is contemplated that frequency drift detection may be enabled as part of a safety sensor implemented in a radar transceiver for automotive applications. A safety sensor is part of a safety mechanism implemented in a system to detect and minimize any changes outside of a defined range that would result in a violation of a system safety goal. In this way, a frequency drift of a reference (e.g., crystal) oscillator used in a car's radar transceiver may be detected, and thus possible out-of-band emissions of the radar transceiver may be avoided.

[0043] Although examples of the invention are described with reference to a frequency drift detector of a reference clock to a PLL, it is envisaged that other examples may be applied to any fixed and unmodulated clock frequency (ie the frequency remains constant except for 'normal' variations due to PVT and aging).

[0044] Although examples of the present invention are described with reference to a frequency drift detector using FVC in a PLL circuit, it is contemplated that FVC may be used in other examples.

[0045] refer to Figure 2 , a block diagram of a wireless communication unit adapted according to some examples of the present invention is shown. For illustrative purposes only, a wireless communication unit is described according to a radar device 200 operating at a millimeter wave (MMW) frequency. The radar device 200 includes one or more antennas 202 for receiving a radar signal 221 and one or more antennas 203 for transmitting a radar signal 222, and for simplicity, only one antenna is shown for each radar signal. The number of antennas 202, 203 used may depend on the number of radar receivers and transmitter channels implemented in a given radar device. As is known in the art, one or more receiver chains include a receiver front-end circuit system 206, thereby effectively providing reception, frequency conversion, filtering and intermediate amplification or baseband amplification and final analog-to-digital conversion. In some examples, depending on the specific architecture selected, multiple such circuits or components may reside in a signal processing module 208. The receiver front-end circuit system 206 is coupled to the signal processing module 208 (usually implemented by a digital signal processor (DSP)). Those skilled in the art will appreciate that in some cases, the level of integration of the receiver circuit or component may depend on the implementation.

[0046] Controller 214 maintains overall operational control of radar device 200 and, in some examples, may include time-based digital functions (not shown) for controlling the timing of operations (e.g., transmission or reception of time-dependent signals, FMCW modulation generation, etc.) within radar device 200. Controller 214 is also coupled to receiver front-end circuitry 206 and signal processing module 208. In some examples, controller 214 is also coupled to a memory device 216 that selectively stores operating schemes, such as decoding / encoding functions, etc.

[0047] Regarding the transmit chain, it basically includes a power amplifier (PA) 224 and may include phase shifters coupled to one or more antennas 203, an antenna array or multiple antennas of the transmitter. In the radar device 200, the radar transceiver topology is different from the traditional wireless communication architecture (e.g., Bluetooth TM , WiFi TMetc.), since the modulation occurs within a phase locked loop (PLL) (typically via a fractional-N frequency divider) and is applied directly to the PA 224. Thus, in some examples, the receiver front end circuitry 206 and transmitter PA 224 are coupled to a frequency generation circuit 230 arranged to provide a local oscillator signal. The generated local oscillator signal thus directly modulates the generated transmitted radar signal and is also used to down-convert the received modulated radar signal to a final intermediate or baseband frequency or digital signal for processing in a receive operation.

[0048] According to an example of the present invention, Figure 5 and Figure 6 As further described in the example shown, the frequency generation circuit 230 includes a frequency drift detector consisting of a frequency-voltage converter and a voltage comparator. According to an example of the present invention, the frequency-voltage converter includes an XOR logic gate or a phase frequency detector plus a charge pump circuit arranged to receive a reference frequency and convert the reference frequency into a representative voltage. According to an example of the present invention, the frequency-voltage converter further includes a loop filter and a voltage-controlled oscillator (VCO) and a feedback loop. PLL-based applications for FVC are particularly useful because the frequency range (e.g., the reference frequency normal operating range) can be easily adjusted by adjusting the frequency range of the VCO, and PVT changes can also be easily compensated as described herein. The frequency generation circuit 230 includes a reference oscillator (e.g., a crystal oscillator) configured to generate a signal describing, for example, a desired frequency modulated continuous wave.

[0049] In some examples, a phase / frequency comparator (configured as a phase frequency detector and charge pump) is arranged to compare the output from a reference oscillator with a signal fed back from the VCO via a feedback loop and output a voltage signal representative of the reference oscillator output signal, thereby significantly indicating any associated frequency drift.

[0050] In some examples, such as reference Figure 4 As described, to determine the frequency drift variation of a reference oscillator, the frequency-to-voltage converter output voltage (representing the reference frequency) is compared to a known calibration voltage, such as a regulated supply voltage.

[0051] Those skilled in the art will appreciate that in some cases the level of integration of circuits or components may depend on the implementation.

[0052] Reference now Figure 3, a more detailed block diagram of a communication unit 300 is shown according to an example of the present invention, such as a radar device, a transceiver 320, and a controller 214 within the communication unit 300. In this example, the automotive radar device is composed of a multi-chip solution that combines a transceiver 320, a processing unit (e.g., a microcontroller unit (MCU)) 214, and antennas 202, 203.

[0053] The transceiver 320 includes multiple circuits and / or components, including: a power management unit 310, a frequency generation circuit 230, a transmitter circuit 324, a receiver circuit 206, multiple sensors 312 (for example, different sensors configured to perform various system tests), a digital controller 314, at least one interface 318, and in this example, an external crystal resonator 330 connected to a crystal oscillator inside 230.

[0054] The controller 214 comprises a processing unit 302, a memory unit 304 and a further digital controller 306. The controller 214 further comprises at least one interface 308 connected to the at least one interface 318 of the transceiver 320, the at least one interface 308 being a serial-parallel interface (SPI) in the example shown.

[0055] In order to be able to achieve an acceptable level of safety in the entire radar device, each part of the radar device must comply with the safety requirement level. Safety compliance at the transceiver can be achieved by implementing a number of individual sensor functions, which are often referred to as safety mechanisms. These safety / sensor mechanisms are responsible for detecting system failures within the radar device.

[0056] Thus, in some examples, the frequency generation circuit 230 includes a frequency-to-voltage converter arranged to receive a reference frequency and convert the reference frequency to a representative voltage. The frequency generation circuit 230 is coupled to (or includes) a reference oscillator (such as a crystal oscillator) configured to generate a reference frequency signal describing, for example, a desired frequency continuous wave. The reference frequency signal is converted to a voltage by the frequency-to-voltage converter, wherein the converted voltage also indicates any frequency drift of the reference frequency signal, and the converted voltage is compared to a known voltage, such as a regulated voltage from the power management unit 310. The output of the comparison indicates when the frequency drift exceeds a desired limit, as the frequency drift detector can essentially form part of the safety sensor 312.

[0057] In this way, the inventors have realised that parameters associated with frequency drift variations can be evaluated by a comparison (e.g. voltage comparison) operation, thereby avoiding the problem that changes in a crystal oscillator output cannot be compared with another (unchanged) reference frequency when known radar units utilise a reference frequency as a basis for all subsequent clock and frequency signals, the crystal oscillator output being in fact the reference frequency of the transceiver.

[0058] Figure 4 An example of the present invention is shown. Figure 3 4 is a simplified block diagram 400 of a first example of a frequency drift detector 490 of a safety sensor of a synthesizer 230 used in a radar device of FIG. One or more safety sensors 312 such as an overvoltage detector and an undervoltage detector and one or more voltage regulators 310 are provided. The frequency synthesizer 230 includes a crystal oscillator 405 that generates a resonant input frequency 407, which is provided to a phase frequency detector (PFD) and a charge pump (CP) 410, which compares a feedback signal 445 with the generated resonant input frequency 407 and outputs an oscillator control signal 415 based on the comparison of the feedback signal 445 with the generated resonant input frequency 407. A low pass loop filter 420 filters the oscillator control signal 415 and outputs a filtered oscillator control signal 425, which is provided to a VCO 430. The VCO 430 outputs a radio frequency signal 435 based on the filtered oscillator control signal 425. The feedback path of the PLL consists of a frequency divider 440 that divides the output RF signal 435 to generate a divided feedback signal 445 , which is provided to the PFD and CP 410 .

[0059] In this example, the generated resonant input frequency 407 is also input to a frequency drift detection circuit 490 that includes a frequency-to-voltage converter 450 that is configured to output a voltage 455 that is representative of the generated resonant input frequency 407. Notably, this output voltage 455 will also include an indication of any frequency drift exhibited by the crystal oscillator 405. The voltage 455 output from the frequency-to-voltage converter 450 is input to a voltage comparator 460 where it is compared to a regulated voltage 458 from the voltage regulator 310. If the voltage 455 output from the frequency-to-voltage converter 450 exceeds a threshold value set by the regulated voltage from the voltage regulator 310, which is also used as a regulated voltage for other components and circuits in the PLL, the voltage comparator 460 outputs an error signal, such as in the form of a generated flag 470, indicating that excessive frequency drift has occurred. This situation may occur due to abnormal aging or failure of components of the crystal oscillator 405 or resonator 432, etc. In some examples, the frequency drift detector 490 can be coupled to the safety sensor 312, or in some instances, the frequency drift detector can be part of the safety sensor 312 and used as a safety sensor to identify excessive frequency drift in response to the FVC output voltage 455 exceeding a frequency drift level represented by at least one regulated voltage 458.

[0060] It is contemplated that the frequency-to-voltage converter 450 may be implemented using any suitable technique to identify frequency drift in, for example, a PLL-based frequency synthesizer. In some examples, where the PLL uses a relatively small area when integrated into an integrated circuit and requires low power consumption, the frequency-to-voltage converter 450 of the frequency drift detector circuit 490 may be implemented using, for example, Figure 5 and Figure 6 The simple PLL method shown.

[0061] In some examples of the present invention, during the calibration phase of the frequency drift detector 490, the use of an external source 434 facilitates the measurement of the FVC output voltage within a given frequency range. This voltage range will vary according to the sample. The external source 434 simulates the changes (temperature, aging, process changes) of the resonator 432 within a known (or predetermined) frequency range. Calibration allows the designer to trim the FVC of each component so that the output voltage range is adjusted to be compatible with the voltage comparator 460, and the voltage comparator 460 itself can also be adjusted. In some examples of the present invention, it is envisioned that, for example, the FVC voltage range may not be adjusted due to process changes, and only the comparator range is adjusted to fit the FVC range.

[0062] In some examples, the absolute output voltage range of the frequency-to-voltage conversion is configured to be compatible with the voltage accuracy of the voltage comparator 460 .

[0063] In some examples, the frequency-to-voltage conversion is monotonic, where the linearity of the conversion from frequency to voltage depends on the VCO voltage-to-frequency conversion curve. In some examples, the frequency-to-voltage conversion may not necessarily be linear, because the purpose of the frequency-to-voltage conversion in the frequency drift detector 490 is to detect whether a threshold is exceeded.

[0064] In some examples, it is contemplated that the detection of frequency drift changes in the crystal oscillator output may be converted to a DC voltage that may be compared to a regulation voltage 458, which in some examples has been accounted for by the safety sensor. If the measured DC voltage output from the frequency-to-voltage converter circuit is outside a given voltage range, such as corresponding to a known drift (e.g., based on crystal oscillator temperature, process, and aging specified values), an error signal may be triggered by the voltage comparator 460.

[0065] In some examples, it is contemplated that frequency drift variation detection may be enabled as part of a safety sensor implemented in a radar transceiver for automotive applications. In this example, an output voltage range of a frequency-to-voltage converter (FVC) 450 corresponding to a predetermined (or known) crystal oscillator output frequency 407 may be calibrated using an external source 434 during final testing of the transceiver (e.g., by trimming) to simulate 'normal' variations (over temperature, process, aging) of the resonator. In some examples, the voltage reference of the comparator corresponding to the frequency drift limit may also be trimmed at final test to compensate for any expected PVT variations. In some examples, embodiments of the present invention propose to at least compensate for regulator / comparator process variations per sample, and in some examples adjust the comparator window based on the FVC output voltage per section.

[0066] Figure 5 A first exemplary implementation of a PLL-based frequency-to-voltage converter (FVC) according to an example of the present invention is shown. Figure 44. The frequency-to-voltage converter 450 shown in FIG. 4. According to an example of the present invention, the PLL-based FVC 450 includes a VCO 530. A reference frequency such as a resonant input frequency 507 is input from, for example, a crystal oscillator. The reference frequency is provided to a phase frequency detector (PFD) and a charge pump (CP) 510, which compares a feedback signal 545 with the generated resonant input frequency 507 and outputs a control signal 515 based on the comparison of the feedback signal 545 with the generated resonant input frequency 507. A low-pass loop filter 520 filters the control signal 515 and outputs a filtered control signal 525, which is provided to the VCO 530. The VCO 530 outputs a radio frequency signal to a feedback path of the PLL based on the filtered oscillator control signal 525. The feedback path 545 of the PLL is provided to the PFD and the CP 510.

[0067] In this example, the filtered control signal 525 of the PLL-based FVC 450 is input to a low-pass filter 550, which is configured to output a DC voltage 555 indicating the generated resonant input frequency 507. In this context, the loop filter 520 is optimized for PLL loop stability, while a further low-pass filter 550 is included to filter noise and filter the clock (reference) frequency. In practice, the clock frequency from the reference may not be sufficiently attenuated by the loop filter, e.g. in the case of a (first order) XOR 510-based PLL, where the loop filter band is only fixed in terms of loop stability compared to, e.g., a (second order) PFD and CP 510-based PLL.

[0068] It is worth noting that such voltage 555 will also include an indication of any frequency drift exhibited by, for example, a crystal oscillator. The voltage 555 output from the low pass filter 550 is input to a voltage comparator where the voltage 555 is compared to a voltage regulation voltage from the voltage regulator 310, which is also used as a regulation voltage for other components and circuits in the PLL. If the voltage 555 output from the low pass filter 550 exceeds a threshold value set by the regulation voltage from the voltage regulator 310, the voltage comparator generates a flag, such as a digital flag, indicating that excessive drift has occurred. This situation may occur due to abnormal behavior of the crystal oscillator and / or crystal resonator (e.g., component solder breakage or abnormal aging).

[0069] Although this example shows a divide-by-1 type PLL, it is contemplated that in other examples a PLL with a higher division ratio may be used, such as Figure 6As shown. Although this example shows the use of a PFD+CP 510PLL-based FVC 450, it is contemplated that a phase detector such as an XOR logic gate may be used in other examples. In some examples, the VCO 530 may be temperature compensated so that the tuning voltage 525 of the VCO 530 remains constant over temperature. In some examples, the VCO 530 may be trimmed by adjusting the resonant circuit of the VCO 530 (e.g., by adjusting one or more resistors, one or more capacitors, or one or more inductors) so that the tuning voltage 525 of the VCO 530 is the same for each sample (in some alternative examples, this may be considered to be the same for each circuit or each IC or each chip) independent of any process variations.

[0070] In some examples, the loop filter 520 may also be adjusted to have the correct loop operation to ensure the stability of the entire PLL. The tuning voltage of the VCO is used as the output voltage because the tuning voltage of the VCO is exactly a function of the crystal oscillator frequency. This tuning voltage may need to be filtered in an XOR logic gate or PFD+CP 510 to remove any remaining loop frequency signal.

[0071] The PLL-based FVC 450 architecture is particularly useful because the frequency range (eg, reference frequency normal operating range) can be easily adjusted by adjusting the VCO frequency range, and PVT variations can also be easily compensated as described herein. Figure 5 The architecture in is also beneficial in that it supports reduced die size and current consumption.

[0072] Figure 6 The example according to the present invention is shown as follows Figure 4A second example of a frequency-to-voltage converter implementation such as the frequency-to-voltage converter 450 shown. According to an example of the invention, the frequency-to-voltage converter includes a VCO 630. Again, a reference frequency such as a resonant input frequency 607 is input from, for example, a crystal oscillator. The reference frequency is provided to a detector 610, for example in the form of an XOR logic gate or a phase frequency detector (PFD) and a charge pump (CP), which compares a feedback signal 645 with the generated resonant input frequency 607 and outputs a control signal 615 based on the comparison of the feedback signal 645 with the generated resonant input frequency 607. A low pass loop filter 620 filters the control signal 615 and outputs a filtered control signal 625, which is provided to the VCO 630. The VCO 630 outputs a radio frequency signal to the feedback path of the PLL based on the filtered oscillator control signal 625. The feedback path of the PLL includes a frequency divider in the form of a programmable frequency divider 640 that divides the output RF signal to generate a divided feedback signal 645 that is provided to the detector 610 .

[0073] In this example, the filtered control signal 625 is input to a low pass filter 650, which is configured to output a DC voltage 655 representing the generated resonant input frequency 607. It is worth noting that this voltage 655 will also include an indication of any frequency drift exhibited by, for example, a crystal oscillator. The voltage 655 output from the low pass filter 650 is input to a voltage comparator (not shown), where the voltage 655 is compared with a voltage regulation voltage from a voltage regulator (not shown), which is also used as a regulation voltage for other components and circuits in the PLL. If the voltage 655 output from the low pass filter 650 exceeds a threshold value set by the regulation voltage from the voltage regulator (not shown), the voltage comparator generates a flag, such as a digital flag, indicating that excessive drift has occurred. This situation may occur due to abnormal behavior of the crystal oscillator / crystal resonator (e.g., component solder fracture or abnormal aging).

[0074] Although this example shows the use of a PFD+CP 610PLL-based FVC 450, it is contemplated that a phase detector such as an XOR logic gate may be used in other examples. In some examples, the VCO 630 may be temperature compensated such that the tuning voltage 625 of the VCO 630 remains constant over temperature. In some examples, the VCO 630 may be trimmed by adjusting the resonant circuit of the VCO 630 (e.g., by adjusting one or more resistors, one or more capacitors, or one or more inductors) such that the tuning voltage 625 of the VCO 630 is the same for each sample independent of any process variations.

[0075] Alternatively or additionally, temperature compensation 685 may be applied to the divided feedback signal 645 via the programmable divider 640 so that the filtered control signal (eg, VCO tuning voltage) 625 is modified according to any dominant PVT effects.

[0076] Figure 7 A simplified flowchart 700 illustrates an example of a calibration method for a frequency drift detector (e.g., at T0 when a frequency generation circuit is calibrated in final or production testing and before the circuit is integrated into a communication unit such as a radar module). The simplified flowchart 700 describes determining Figures 3 to 6 An example of frequency drift that can be employed in the circuits of any of the figures is shown in FIG.

[0077] At 705, an external source (e.g., Figure 4 The resonator for the reference oscillator is replaced by an external source 434 in the reference oscillator. The operating frequency of this source can be swept within a corresponding reference frequency normal operating condition range representing known changes due to temperature changes, voltage changes, component aging, etc. At 706, the flowchart 700 includes generating an FVC output voltage representing a known reference frequency change due to temperature changes, voltage changes, component aging, etc. At 707, the flowchart 700 includes comparing the FVC output voltage with at least one regulation voltage to determine whether the FVC output voltage exceeds at least one regulation voltage threshold. At 708, the flowchart 700 includes generating an error signal identifying excessive frequency drift in response to determining that the FVC output voltage exceeds the at least one regulation voltage threshold. In this case, it is indicated that one or both of the FVC output voltage and / or the comparator window must be tuned (e.g., adjusted) to meet the target voltage (when the reference frequency is externally driven within its known normal operating condition range). In some example embodiments of the present invention, the FVC output voltage and the comparator threshold can be measured at the final test or production test and compared with the known target value.

[0078] At 710, a frequency-voltage trimming operation may be performed at the final test frequency (e.g., such as by adjusting the resonant circuit by adjusting one or more resistors, one or more capacitors, or one or more inductors) to compensate for any process variations, thereby tuning the frequency-voltage output voltage range within a known range of normal operating conditions. In an example of the present invention, the trimming operation at 710 may be performed on at least one of the following: the FVC output voltage, e.g., Figure 4 The FVC output voltage 455 and / or the at least one regulated voltage, for example, from Figure 4The at least one regulated voltage 458 output by the voltage regulator 310 is configured such that the FVC output voltage and / or the at least one regulated voltage falls within a comparator window (normal) operating range.

[0079] At 715, a frequency-voltage temperature compensation calibration operation may be performed independently to compensate for the FVC VCO (eg, Figure 5 FVC VCO 530 or Figure 6 The FVC VCO 630 in the FVC VCO 630 is adjusted to minimize the effects of temperature changes such that the FVC output voltage remains constant with temperature. At 720, a voltage comparator trimming operation may be performed at the final test voltage (e.g., by programming or adjusting the value of one or more resistors to adjust the reference voltage) to tune the voltage comparison window when comparing the output voltage from the frequency-to-voltage converter to the reference voltage output by the voltage regulator. When the FVC output voltage is adjusted to its known 'normal' range, the comparator window may be adjusted so that the comparator does not raise a flag (i.e., Figure 8 As will be appreciated, after the comparison operation at 707, one or more of the operations at 708, 710, and 715 may be optional and used in various examples of the present invention.

[0080] Figure 8 The example according to the present invention is shown in Figure 2 800 in a communication unit such as a radar device of a radar device. The first diagram 805 of the detector function shows a normal operating condition and the second diagram 895 of the detector function shows an error condition, i.e. a condition resulting in the generation of a flag indicating excessive drift of the reference oscillator of the radar device.

[0081] The first illustration 805 of the detector function shows the relationship between the frequency-to-voltage conversion output voltage 810 and the reference frequency 815, and the ideal frequency variation range of the resonator (or crystal oscillator) 855 (e.g., a normal operating condition range that identifies known variations due to temperature changes, voltage changes, component aging, etc.) corresponds to the acceptable voltage range 857 output from the frequency-to-voltage converter 830. It is worth noting that under this normal operating condition, the frequency variation range of the resonator (or crystal oscillator) 855 falls within the threshold limits 859, such as somewhere between F1 820 and F2 825, that is, observed output from the frequency-to-voltage converter 830. Therefore, the range falls within the exact voltage limits 875 of the voltage comparator 860, and no error signal, such as a flag or error condition, is generated.

[0082] The second illustration 895 of the detector function shows the relationship between the frequency-to-voltage conversion output voltage 810 and the reference frequency 815 under an error condition. In this error condition, the reference frequency has drifted to a frequency range 847 that exceeds the acceptable performance of the resonator (or crystal oscillator) 857, beyond F2 825 to frequency 828. This frequency range corresponds to a voltage output range 858 from the frequency-to-voltage converter 830 that falls outside the accuracy voltage limit 875 of the voltage comparator 860 and results in a flag or error condition generated by the voltage comparator 860.

[0083] In the foregoing description, the invention has been described with reference to specific examples of embodiments of the invention. However, it will be apparent that various modifications and changes may be made in the invention without departing from the scope of the invention as set forth in the appended claims, and the claims are not limited to the specific examples described above.

[0084] Furthermore, since the embodiments shown in the present invention can in most cases be implemented using electronic components and circuits known to those skilled in the art, details are explained to a greater extent than is deemed necessary above in order to understand and appreciate the basic concepts of the present invention and not to obscure or deviate from the teachings of the present invention.

[0085] As discussed herein, connection can be any type of connection suitable for transmitting signals from or to corresponding nodes, units or devices, for example, via an intermediate device. Therefore, unless otherwise implied or indicated, connection can be, for example, a direct connection or an indirect connection. Connection can be shown or described with reference to a single connection, multiple connections, unidirectional connections or bidirectional connections. However, different embodiments can change the implementation scheme of the connection. For example, a separate unidirectional connection can be used instead of a bidirectional connection, and vice versa. Moreover, multiple connections can be replaced by a single connection that transmits multiple signals serially or in a time-multiplexed manner. Similarly, a single connection that carries multiple signals can be separated into each different connection that carries a subset of these signals. Therefore, there are many options for transmitting signals.

[0086] Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative, and that alternative embodiments may merge logic blocks or circuit elements or perform alternative decompositions of functionality on individual logic blocks or circuit elements. Therefore, it should be understood that the architectures depicted herein are merely exemplary, and that in fact, many other architectures that achieve the same functionality may be implemented.

[0087] Any arrangement of components for achieving the same function is effectively 'associated' so that the desired function is achieved. Thus, any two components combined herein to achieve a particular function may be considered to be 'associated' with each other so that the desired function is achieved, regardless of architecture or intermediate components. Likewise, any two components so associated may also be considered to be 'operably connected' or 'operably coupled' to each other so as to achieve the desired function.

[0088] In addition, those skilled in the art will recognize that the boundaries between the above operations are illustrative only. Multiple operations may be performed at least partially overlapping in time. In addition, alternative exemplary embodiments may include multiple instances of specific operations, and the order of operations may be changed in various other embodiments.

[0089] For another example, in one embodiment, the examples shown may be implemented as a circuit system located on a single integrated circuit or within the same device. Alternatively, the examples may be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner.

[0090] For another example, the examples or their various parts may be implemented as a physical circuit system or a soft representation or code representation of a logical representation that can be converted into a physical circuit system, such as in any appropriate type of hardware description language. Moreover, the examples of the present invention are not limited to physical devices or physical units implemented in non-programmable hardware, but may also be applied to wireless programmable devices or units that can perform desired device functions by operating according to suitable program codes. However, other modifications, variations and alternatives are also possible. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

[0091] In the claims, any reference numerals placed in brackets should not be interpreted as limiting the claims. The word 'comprising' does not exclude the existence of other elements or steps other than those listed in the claims. In addition, as used herein, the term 'a / an' is limited to one / kind or more than one / kind. Moreover, the use of introductory phrases such as 'at least one / kind' and 'one / kind or more / kind' in the claims should not be understood as implying that another claim element introduced by the indefinite article 'a / kind' limits any specific claim containing such introduced claim element to the content of the invention containing only one such element, even when the same claim contains the introductory phrases 'one / kind or more / kind' or 'at least one / kind' and indefinite articles such as 'one / kind'. The same is true for the use of definite articles. Unless otherwise stated, terms such as 'first' and 'second' are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the time or other priority of such elements. The fact that certain measures are cited in mutually different claims does not indicate that these measures cannot be combined for use.

Claims

1. A frequency drift detector, characterized in that: include: a frequency-to-voltage converter FVC arranged to receive a reference frequency signal from a crystal oscillator and configured to generate a FVC output voltage; a voltage regulator arranged to output at least one regulated voltage; as well as a voltage comparator coupled to the output of the FVC and the output of the voltage regulator and arranged to compare the FVC output voltage to the at least one regulation voltage and to generate an error signal in response to determining that the FVC output voltage exceeds a level of frequency drift indicated by the at least one regulation voltage such that the error signal corresponds to excessive frequency drift of the crystal oscillator; The FVC comprises a phase locked loop PLL, the PLL being arranged to receive the reference frequency signal; wherein the PLL comprises: a phase detector, the phase detector detecting the phase of the reference frequency signal and outputting a control signal; a loop filter, the loop filter being arranged to filter the control signal; a voltage controlled oscillator VCO, the VCO being arranged to generate an output radio frequency signal in response to the filtered control signal; and a feedback loop connecting the output of the VCO to the phase detector; and a low pass filter, the low pass filter being arranged to filter the filtered control signal and generate the FVC output voltage; the PLL being operatively coupled to a temperature compensation circuit such that the temperature compensation circuit is coupled to the VCO, and the temperature compensation circuit being arranged to apply a temperature compensation signal to the VCO such that in response thereto, the VCO tuning voltage remains constant with temperature; The PLL is operably coupled to a temperature compensation circuit such that the temperature compensation circuit is coupled to a programmable frequency divider in a feedback path of the PLL, and the temperature compensation circuit is arranged to apply a temperature compensation signal to the programmable frequency divider such that in response thereto, the VCO tuning voltage remains constant with temperature.

2. The frequency drift detector according to claim 1, characterized in that: The phase detector is an XOR logic gate or a phase frequency detector plus a charge pump circuit.

3. The frequency drift detector according to claim 1 or 2, characterized in that: The frequency drift detector is coupled to a safety sensor configured to receive the error signal and raise a flag in response to the FVC output voltage exceeding a frequency drift level indicated by the at least one regulated voltage comparison.

4. The frequency drift detector according to claim 1 or 2, characterized in that: The frequency drift detector is calibrated during a test mode of operation, whereby an external calibration reference source provides the reference frequency signal.

5. The frequency drift detector according to claim 1 or 2, characterized in that: The regulation voltage supplied to the voltage comparator is trimmed corresponding to a frequency drift limit during a test mode of operation to compensate for any process variations of the voltage comparator.

6. A communication unit, characterized in that: Comprising a frequency drift detector according to any preceding claim and a crystal oscillator.

7. A method for calibrating a frequency drift detector according to any one of claims 1 to 5, characterized in that: The method is characterized by: receiving at least one regulated voltage from a voltage regulator; receiving a reference frequency signal from a crystal oscillator at a frequency-to-voltage converter FVC input and generating a FVC output voltage in response thereto, wherein the reference frequency signal emulates a normal operating range of the crystal oscillator; comparing the FVC output voltage to the at least one regulated voltage; as well as Trimming at least one of: the FVC output voltage, the at least one regulated voltage output from the voltage regulator so that the FVC output voltage and / or the at least one regulated voltage falls within a comparator window normal operating range and the comparison does not generate an error signal.

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