Non-volatile memory device

Abstract

A nonvolatile memory device with improved reliability is provided. The nonvolatile memory device includes: a mold structure including a first insulating pattern, a first gate electrode, and a second insulating pattern sequentially stacked on a substrate; a semiconductor pattern penetrating the mold structure, connected to the substrate, and extending in a first direction; a first charge storage film extending in the first direction and located between the first insulating pattern and the second insulating pattern and between the first gate electrode and the semiconductor pattern; and a blocking insulating film located between the first gate electrode and the first charge storage film, wherein a first length extending in the first direction of the first charge storage film is longer than a second length extending in the first direction of the blocking insulating film.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2018-0125725, filed on October 22, 2018, and all benefits arising therefrom, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present inventive concept relates to a nonvolatile memory device and a method of manufacturing the same. More particularly, the present inventive concept relates to a nonvolatile memory device including a cut charge storage film and a method of manufacturing the same. Background Art

[0004] A semiconductor memory device is a memory device implemented using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). Semiconductor memory devices can be roughly classified into volatile memory devices and nonvolatile memory devices.

[0005] A volatile memory device is a memory device that causes stored data to disappear when the power is cut off. Volatile memory devices may include SRAM (static RAM), DRAM (dynamic RAM), SDRAM (synchronous DRAM), etc. A nonvolatile memory device is a memory device that retains stored data even if the power is cut off. A nonvolatile memory device may be a flash memory device, a ROM (read-only memory), a PROM (programmable ROM), an EPROM (electrically programmable ROM), an EEPROM (electrically erasable programmable ROM), a resistive memory device (e.g., PRAM (phase change RAM), FRAM (ferroelectric RAM), and RRAM (resistive RAM)), etc.

[0006] The integration level of non-volatile memory devices is increasing day by day in order to meet the improved performance and / or low price required by consumers. In the case of two-dimensional devices or planar memory devices, the integration level is determined by the area occupied by the unit memory cell. Therefore, recently, three-dimensional memory devices in which the unit memory cells are arranged vertically have been developed. Summary of the invention

[0007] Aspects of the inventive concept provide a nonvolatile memory device that improves reliability by cutting a charge storage film to protrude from a blocking insulating film.

[0008] Aspects of the inventive concept also provide a method for manufacturing a nonvolatile memory device capable of manufacturing a nonvolatile memory device having improved reliability by cutting a charge storage film to protrude from a blocking insulating film.

[0009] However, aspects of the inventive concept are not limited to the aspects set forth herein. The above and other aspects of the inventive concept will become more apparent to those skilled in the art to which the inventive concept pertains by referring to the detailed description of the inventive concept given below.

[0010] According to various aspects of the present invention, a nonvolatile memory device is provided, comprising: a mold structure comprising a first insulating pattern, a first gate electrode, and a second insulating pattern sequentially stacked on a substrate; a semiconductor pattern penetrating the mold structure, connected to the substrate, and extending in a first direction; a first charge storage film extending in the first direction and located between the first insulating pattern and the second insulating pattern and between the first gate electrode and the semiconductor pattern; and a blocking insulating film located between the first gate electrode and the first charge storage film, wherein a first length of the first charge storage film extending in the first direction is longer than a second length of the blocking insulating film extending in the first direction.

[0011] According to various aspects of the present inventive concept, a nonvolatile memory device is provided, comprising: a mold structure comprising a first gate electrode, an insulating pattern, and a second gate electrode sequentially stacked on a substrate; a semiconductor pattern penetrating the mold structure and connected to the substrate; a first charge storage film located between the first gate electrode and the semiconductor pattern; a second charge storage film separated from the first charge storage film and located between the second gate electrode and the semiconductor pattern; a first blocking insulating film located between the first gate electrode and the insulating pattern; and a second blocking insulating film located between the second gate electrode and the insulating pattern, wherein a first distance separating the first charge storage film and the second charge storage film from each other is shorter than a second distance separating the first blocking insulating film and the second blocking insulating film from each other.

[0012] According to various aspects of the present invention, a nonvolatile memory device is provided, comprising: a mold structure including a first insulating pattern, a first gate electrode, and a second insulating pattern sequentially stacked on a substrate; a semiconductor pattern penetrating the mold structure, connected to the substrate, and extending in a first direction; and a first charge storage film extending in the first direction and located between the first insulating pattern and the second insulating pattern and between the first gate electrode and the semiconductor pattern, wherein a first length of the first charge storage film extending in the first direction increases as it approaches the semiconductor pattern.

[0013] According to aspects of the present inventive concept, a nonvolatile memory device is provided, comprising: a mold structure including insulating patterns and gate electrodes alternately stacked on a substrate; a semiconductor pattern penetrating the mold structure and connected to the substrate; a first charge storage film located between the gate electrode and the semiconductor pattern; and a blocking insulating film extending along a bottom surface, a side wall, and an upper surface of the gate electrode, wherein the first charge storage film includes a protrusion protruding from the blocking insulating film toward the insulating pattern.

[0014] According to various aspects of the present invention, a method for manufacturing a nonvolatile memory device is provided, the method comprising: forming a preliminary mold structure including first to third sacrificial films on a substrate, the first sacrificial films and the third sacrificial films being alternately stacked, and a second sacrificial film being inserted between the first sacrificial films and the third sacrificial films; forming a first hole penetrating the preliminary mold structure to expose the substrate; sequentially forming a preliminary charge storage film and a semiconductor pattern in the first hole; removing the third sacrificial film to expose a portion of the preliminary charge storage film; and performing an etch-back process on the preliminary charge storage film to form a plurality of charge storage films separated from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other aspects and features of the inventive concept will become more apparent by describing in detail example embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0016] Figure 1 is a schematic circuit diagram for explaining a nonvolatile memory device according to some embodiments of the technical concept of the inventive concept.

[0017] Figure 2 1 is a schematic layout diagram of a nonvolatile memory device for explaining some embodiments according to technical concepts of the inventive concept.

[0018] Figure 3 is along Figure 2 A cross-sectional view taken along line AA.

[0019] Figure 4 and Figure 5 Show Figure 3 Various magnified views of region R1.

[0020] Figure 6 is a cross-sectional view illustrating a nonvolatile memory device according to some embodiments of the technical concept of the inventive concept.

[0021] Figures 7 to 10 Show Figure 6 Various magnified views of region R2.

[0022] Fig.11is a cross-sectional view illustrating a nonvolatile memory device according to some embodiments of the technical concept of the inventive concept.

[0023] Fig.12 is a cross-sectional view illustrating a nonvolatile memory device according to some embodiments of the technical concept of the inventive concept.

[0024] Fig.13 is a cross-sectional view illustrating a nonvolatile memory device according to some embodiments of the technical concept of the inventive concept.

[0025] Fig.14 1 is a schematic layout diagram of a nonvolatile memory device for explaining some embodiments according to technical concepts of the inventive concept.

[0026] FIG. 15A to FIG. 29 1 is a diagram of intermediate stages for explaining a method for manufacturing a nonvolatile memory device according to some embodiments of the technical concept of the inventive concept.

[0027] Figure 30 to Figure 36 are intermediate step diagrams for explaining methods for manufacturing nonvolatile memory devices according to some embodiments of the technical concepts of the inventive concepts.

[0028] Fig.37 are intermediate step diagrams for explaining methods for manufacturing nonvolatile memory devices according to some embodiments of the technical concepts of the inventive concepts.

[0029] Figures 38 to 43 1 is a diagram of intermediate stages for explaining a method for manufacturing a nonvolatile memory device according to some embodiments of the technical concept of the inventive concept. DETAILED DESCRIPTION

[0030] In the following, reference will be made to Figures 1 to 14 A nonvolatile memory device according to some embodiments of the technical concept of the inventive concept will be described.

[0031] Figure 1 is a schematic circuit diagram for explaining a nonvolatile memory device according to some embodiments of the technical concept of the inventive concept. Figure 2 1 is a schematic layout diagram of a nonvolatile memory device for explaining some embodiments according to technical concepts of the inventive concept. Figure 3 is along Figure 2 A cross-sectional view taken along line AA. Figure 4 and Figure 5 Show Figure 3 Various magnified views of region R1.

[0032] First refer to Figure 1, a nonvolatile memory device according to some embodiments may include a common source line CSL, a plurality of bit lines BL, and / or a plurality of cell strings CSTR.

[0033] The plurality of bit lines BL may be arranged two-dimensionally. For example, each bit line BL may be separated from each other and extend in the first direction X, respectively. A plurality of cell strings CSTR may be connected in parallel to each bit line BL. The cell strings CSTR may be commonly connected to a common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the plurality of bit lines BL and the common source line CSL.

[0034] In some embodiments, a plurality of common source lines CSL may be arranged two-dimensionally. For example, the common source lines CSL may be spaced apart from each other and extend respectively in the second direction Y. The same voltage may be applied to the common source lines CSL, or different voltages may be applied to the common source lines CSL to be individually controlled.

[0035] Each cell string CSTR may include a ground selection transistor GST connected to a common source line CSL, a string selection transistor SST connected to a bit line BL, and a plurality of memory cell transistors MCT disposed between the ground selection transistor GST and the string selection transistor SST. Each memory cell transistor MCT may include a data storage element. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistor MCT may be connected in series to each other.

[0036] The common source line CSL may be commonly connected to the source of the ground selection transistor GST. In addition, the ground selection line GSL, a plurality of word lines WL0 to WLn, and a string selection line SSL may be arranged between the common source line CSL and the bit line BL. The ground selection line GSL may be used as a gate electrode of the ground selection transistor GST, a plurality of word lines WL0 to WLn may be used as a gate electrode of the memory cell transistor MCT, and the string selection line SSL may be used as a gate electrode of the string selection transistor SST.

[0037] Next, refer to Figures 2 to 4 , a nonvolatile memory device according to some embodiments includes a substrate 100, a mold structure MS, a channel structure CS, a tunnel insulating film 142, charge storage films 144 and 144U, a blocking insulating film 146, a channel pad 150, a separation structure 160, an interlayer insulating film 210 and / or a bit line BL.

[0038] The substrate 100 may include a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the substrate 100 may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or the like.

[0039] The mold structure MS may include a plurality of gate electrodes (GSL, WL0 to WLn, and SSL) and / or a plurality of insulating patterns 110. Each gate electrode (GSL, WL0 to WLn, and SSL) and each insulating pattern 110 may extend long in a direction parallel to the upper surface of the substrate 100.

[0040] The respective gate electrodes (GSL, WL0 to WLn, and SSL) may be alternately stacked with the respective insulating patterns 110. For example, the plurality of gate electrodes (GSL, WL0 to WLn, and SSL) may be sequentially stacked on the substrate 100 while being spaced apart from each other along the third direction Z. The plurality of insulating patterns 110 may be interposed between the plurality of gate electrodes (GSL, WL0 to WLn, and SSL) and between the gate electrodes (GSL, WL0 to WLn, and SSL) and the substrate 100. For example, Figure 4 As shown in FIG. 1 , the mold structure MS may include a first insulating pattern 1101 , a first gate electrode WL1 , a second insulating pattern 1102 , and a second gate electrode WL2 sequentially stacked on a substrate 100 .

[0041] Although the plurality of gate electrodes (GSL, WL0 to WLn, and SSL) are illustrated as having the same thickness, the technical idea of ​​the inventive concept is not limited thereto, and the plurality of gate electrodes (GSL, WL0 to WLn, and SSL) may have different thicknesses from each other.

[0042] In some embodiments, the lowermost gate electrode GSL among the plurality of gate electrodes (GSL, WL0 to WLn, and SSL) may be provided as Figure 1 In some embodiments, the uppermost gate electrode SSL among the plurality of gate electrodes (GSL, WL0 to WLn, and SSL) may be provided as a ground selection line GSL. Figure 1 The gate electrodes WL0 to WLn between the ground selection line GSL and the string selection line SSL may be provided as Figure 1 The word lines WL0 to WLn.

[0043] The plurality of gate electrodes (GSL, WL0 to WLn, and SSL) may include a conductive material. The plurality of gate electrodes (GSL, WL0 to WLn, and SSL) may include, for example but not limited to, a metal such as tungsten (W), cobalt (Co), and nickel (Ni), or a semiconductor material such as silicon.

[0044] The plurality of insulating patterns 110 may include an insulating material. The plurality of insulating patterns 110 may include, for example, silicon oxide, but is not limited thereto.

[0045] The channel structure CS may penetrate the mold structure MS to extend in the third direction Z. For example, the channel structure CS is formed in a pillar shape on the substrate 100 and may penetrate the plurality of gate electrodes (GSL, WL0 to WLn, and SSL) and the plurality of insulating patterns 110. Therefore, the plurality of gate electrodes (GSL, WL0 to WLn, and SSL) may cross the channel structure CS.

[0046] A plurality of channel structures CS may be provided. Figure 2 As shown in , the plurality of channel structures CS may be arranged along the second direction Y. In addition, for example, the plurality of channel structures CS may be respectively disposed at both sides of the separation structure 160 .

[0047] The channel structure CS may include a semiconductor pattern 130. The semiconductor pattern 130 penetrates the mold structure MS and may be connected to the substrate 100. For example, the semiconductor pattern 130 may extend in the third direction Z. The semiconductor pattern 130 may be formed in, for example, a cup shape. For example, the channel structure CS may include a filling insulating pattern 120 having a column shape and a semiconductor pattern 130 extending conformally along the bottom surface and sidewall of the filling insulating pattern 120. The filling insulating pattern 120 may include, for example, silicon oxide. However, the technical concept of the inventive concept is not limited thereto, and the semiconductor pattern 130 may have various shapes such as a cylindrical shape, a square column shape, a solid column shape, etc.

[0048] The semiconductor pattern 130 may include (but is not limited to) a semiconductor material, such as single crystal silicon.

[0049] The tunnel insulating film 142 may be formed on the sidewall of the channel structure CS. For example, the tunnel insulating film 142 may be formed to surround the sidewall of the semiconductor pattern 130. In addition, the tunnel insulating film 142 may extend in the third direction Z.

[0050] The tunnel insulating film 142 may include, for example, silicon oxide or silicon oxynitride. Alternatively, for example, the tunnel insulating film 142 may be formed of a double layer of a silicon oxide film and a silicon nitride film. For ease of explanation, hereinafter, the tunnel insulating film 142 will be described as including silicon oxide.

[0051] The charge storage films 144 and 144U may be formed on the sidewalls of the tunnel insulating film 142. Thus, the tunnel insulating film 142 may be interposed between the semiconductor pattern 130 and the charge storage films 144 and 144U. In addition, the charge storage films 144 and 144U may extend in the third direction Z.

[0052] Each of the charge storage films 144 and 144U may be interposed between the semiconductor pattern 130 and each of the gate electrodes (GSL, WL0 to WLn, and SSL). Figure 4As shown in , the first charge storage film 1441 may be interposed between the semiconductor pattern 130 and the first gate electrode WL1 , and the second charge storage film 1442 may be interposed between the semiconductor pattern 130 and the second gate electrode WL2 .

[0053] In addition, the respective charge storage films 144 and 144U may be spaced apart from each other in the third direction Z. For example, the first charge storage film 1441 may be inserted between the first insulating pattern 1101 and the second insulating pattern 1102. Therefore, the first charge storage film 1441 and the second charge storage film 1442 may be spaced apart from each other by the second insulating pattern 1102.

[0054] Charges from the semiconductor pattern 130 passing through the tunnel insulating film 142 may be stored in the charge storage films 144 and 144U. The charges stored in the charge storage films 144 and 144U may be changed by, for example, Fowler-Nordheim tunneling caused by a voltage difference between the semiconductor pattern 130 and the gate electrodes (GSL, WL0 to WLn, and SSL).

[0055] The charge storage films 144 and 144U may include, for example, at least one of silicon nitride, silicon oxynitride, Si-rich nitride, and nanocrystal (Si). For ease of explanation, hereinafter, the charge storage films 144 and 144U will be described as including silicon nitride.

[0056] The blocking insulating film 146 may be formed on the sidewalls of the charge storage films 144 and 144U. As a result, the charge storage films 144 and 144U may be interposed between the tunnel insulating film 142 and the blocking insulating film 146.

[0057] Each blocking insulating film 146 may be interposed between each of the charge storage films 144 and 144U and each of the gate electrodes (GSL, WL0 to WLn, and SSL). Figure 4 As shown in , the first blocking insulating film 1461 may be inserted between the first charge storage film 1441 and the first gate electrode WL1 , and the second blocking insulating film 1462 may be inserted between the second charge storage film 1442 and the second gate electrode WL2 .

[0058] In addition, each blocking insulating film 146 may be formed to surround each gate electrode (GSL, WL0 to WLn, and SSL). For example, the first blocking insulating film 1461 may extend along the bottom surface, sidewalls, and upper surface of the first gate electrode WL1. Therefore, the lower portion of the first blocking insulating film 1461 may be inserted between the first gate electrode WL1 and the first insulating pattern 1101, the side portion of the first blocking insulating film 1461 may be inserted between the first gate electrode WL1 and the first charge storage film 1441, and the upper portion of the first blocking insulating film 1461 may be inserted between the first gate electrode WL1 and the second insulating pattern 1102.

[0059] The blocking insulating film 146 may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide. The high-k material may include, for example, at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof. For ease of explanation, hereinafter, the blocking insulating film 146 will be described as including silicon oxide.

[0060] In some embodiments, Figure 4 As shown in , each of the charge storage films 144 and 144U may include a protrusion 144P protruding from the blocking insulating film 146 toward the insulating pattern 110. The outer surface of the protrusion 144P is shown as being angled, but this is only for convenience of explanation, and the technical concept of the inventive concept is not limited thereto. For example, the outer surface of the protrusion 144P may have a circular shape.

[0061] As a result, each charge storage film 144 and 144U may extend longer than each blocking insulating film 146 in the third direction Z. For example, a first length L11 of the first charge storage film 1441 extending in the third direction Z may be longer than a second length L12 of the first blocking insulating film 1461 extending in the third direction Z.

[0062] In addition, the distances at which the charge storage films 144 and 144U are spaced apart from each other may be shorter than the distances at which the blocking insulating films 146 are spaced apart from each other. For example, the first distance D11 at which the first charge storage film 1441 and the second charge storage film 1442 are spaced apart from each other may be shorter than the second distance D12 at which the first blocking insulating film 1461 and the second blocking insulating film 1462 are spaced apart from each other.

[0063] In some embodiments, a portion of the charge storage films 144 and 144U is shown as being in contact with the upper surface of the substrate 100, but this is only for ease of description, and the technical concept of the inventive concept is not limited thereto. For example, there may be no portion of the charge storage films 144 and 144U in contact with the upper surface of the substrate 100.

[0064] In some embodiments, the upper charge storage film 144U disposed at the uppermost portion among the charge storage films 144 and 144U may include a portion extending along the upper surface of the uppermost gate electrode SSL. For example, the upper charge storage film 144U may extend along the upper surface and sidewalls of the string selection line SSL.

[0065] The channel pad 150 may be formed on the channel structure CS. The channel pad 150 may be connected to the semiconductor pattern 130. Figure 3, the upper surface of the semiconductor pattern 130 is shown as being disposed on the same plane as the upper surface of the channel pad 150, but the technical concept of the inventive concept is not limited thereto. For example, unlike the case shown, the upper surface of the semiconductor pattern 130 may be disposed on the same plane as the upper surface of the filling insulation pattern 120. For example, in some embodiments, the channel pad 150 may be formed on the upper surface of the filling insulation pattern 120 and the upper surface of the semiconductor pattern 130.

[0066] The channel pad 150 may include a conductive material. The channel pad 150 may include, for example, polysilicon doped with impurities, but is not limited thereto.

[0067] The separation structure 160 penetrates the mold structure MS and may be connected to the impurity region 105 in the substrate 100. For example, a separation hole HY extending in the second direction Y between adjacent channel structures CS may be formed in the mold structure MS. The separation structure 160 may be formed to fill the separation hole HY. The impurity region 105 may be formed in a region of the substrate 100 exposed by the separation hole HY. For example, the impurity region 105 may extend in the second direction Y. The separation structure 160 and / or the impurity region 105 may be provided as Figure 1 A common source line CSL.

[0068] In some embodiments, the separation structure 160 may include a common source plug pattern 164 and / or an insulating spacer 162. The common source plug pattern 164 penetrates the mold structure MS and may be connected to the impurity region 105 in the substrate 100. The common source plug pattern 164 may include, for example, a conductive material, but is not limited thereto. The insulating spacer 162 may extend along the sidewall of the common source plug pattern 164.

[0069] In some embodiments, a sidewall of the separation structure 160 adjacent to the uppermost gate electrode (SSL; eg, string selection line) may include a step.

[0070] The interlayer insulating film 210 may be formed on the mold structure MS. The interlayer insulating film 210 may be formed of, for example, but not limited to, BSG (borosilicate glass), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), USG (undoped silicate glass), TEOS (tetraethylorthosilicate glass), or HDP-CVD (high density plasma-CVD).

[0071] The bit line BL may extend in the first direction X on the interlayer insulating film 210 . The bit line BL may be connected to the channel pad 150 . For example, the bit line BL may be connected to a bit line plug 220 penetrating the interlayer insulating film 210 and connected to the channel pad 150 .

[0072] Reference Figure 5In the nonvolatile memory device according to some embodiments, the protrusion 144P of the charge storage film 144 and 144U may include a first concave surface 144S1. The first concave surface 144S1 may be formed at a distal end of the charge storage film 144 and 144U in the third direction Z.

[0073] In some embodiments, the center of curvature of the first concave surface 144S1 may be formed between the tunnel insulating film 142 and the blocking insulating film 146. For example, the first length L11 of the first charge storage film 1441 extending in the third direction Z may decrease and then increase as it approaches the semiconductor pattern 130.

[0074] In the case where the charge storage film of a nonvolatile memory device extends continuously between memory cell transistors, there is a problem that charges are lost in the direction along which the charge storage film extends (for example, the third direction Z). This becomes a problem of causing coupling between adjacent memory cell transistors and reducing the reliability of the nonvolatile memory device.

[0075] However, the nonvolatile memory device according to some embodiments may include the charge storage films 144 and 144U separated from each other to correspond to each memory cell transistor MCT. As a result, it is possible to provide a memory device in which the charge loss in the extension direction (e.g., the third direction Z) of the charge storage film is improved, the coupling between adjacent memory cell transistors is improved, and the reliability is improved.

[0076] In addition, the nonvolatile memory device according to some embodiments may include the charge storage films 144 and 144U protruding from the blocking insulating film 146. The charge storage films 144 and 144U can store a large amount of charge and can have an improved terminal profile compared to the charge storage film recessed from the blocking insulating film 146. Therefore, a nonvolatile memory device with further improved reliability can be provided.

[0077] Figure 6 is a cross-sectional view illustrating a nonvolatile memory device according to some embodiments of the technical concept of the inventive concept. Figures 7 to 10 Show Figure 6 For the sake of convenience, the following description will be briefly explained or omitted. Figures 1 to 5 The repeated portion of the provided description.

[0078] Reference Figure 6 and Figure 7 In the nonvolatile memory device according to some embodiments, the length of the charge storage films 144 and 144U extending in the third direction Z may increase as approaching the semiconductor pattern 130 .

[0079] For example, a first length L21 of the first charge storage film 1441 extending in the third direction Z may be equal to a second length L22 of the first blocking insulating film 1461 extending in the third direction Z at a position adjacent to the first gate electrode WL1, and then increase as approaching the semiconductor pattern 130, but the technical concepts conceived in the present invention are not limited thereto.

[0080] In addition, a first distance D21 separating the first charge storage film 1441 and the second charge storage film 1442 from each other may be equal to a second distance D22 separating the first blocking insulating film 1461 and the second blocking insulating film 1462 from each other at a position adjacent to the second insulating pattern 1102, and then decreases as approaching the semiconductor pattern 130, but the technical concepts conceived by the present invention are not limited to this.

[0081] In some embodiments, the protrusion 144P of the charge storage films 144 and 144U may include a first concave surface 144S 1. In this case, the center of curvature of the first concave surface 144S 1 may be formed at a position farther from the charge storage films 144 and 144U based on the semiconductor pattern 130 .

[0082] Reference Figure 8 In the nonvolatile memory device according to some embodiments, a portion of the protrusion 144P of the charge storage films 144 and 144U may extend along a portion of the bottom surface of the blocking insulating film 146 or a portion of the upper surface of the blocking insulating film 146 .

[0083] For example, a portion of the protrusion 144P may extend between the first blocking insulating film 1461 and the first insulating pattern 1101 and between the first blocking insulating film 1461 and the second insulating pattern 1102. Therefore, a first thickness TH1 of the first charge storage film 1441 between the first blocking insulating film 1461 and the tunnel insulating film 142 may be less than a second thickness TH2 of the protrusion 144P in the first direction X. Here, the thickness means the thickness in the first direction X.

[0084] The protrusion 144P is shown to extend along a portion of the bottom surface of the blocking insulating film 146 and a portion of the upper surface of the blocking insulating film 146, but the technical concept of the inventive concept is not limited thereto. For example, the protrusion 144P extends only along a portion of the bottom surface of the blocking insulating film 146 and may not extend along the upper surface of the blocking insulating film 146. Alternatively, for example, the protrusion 144P may extend only along a portion of the upper surface of the blocking insulating film 146 and may not extend along the bottom surface of the blocking insulating film 146.

[0085] Reference Fig. 9 In the nonvolatile memory device according to some embodiments, the tunnel insulating film 142 may include a second concave surface 142S.

[0086] The second concave surface 142S of the tunnel insulating film 142 may be formed between the charge storage films 144 and 144U. For example, the second concave surface 142S may be formed on the outer surface of the tunnel insulating film 142 between the first charge storage film 1441 and the second charge storage film 1442.

[0087] In some embodiments, the thickness of the tunnel insulating film 142 in the first direction X may decrease as it moves away from the charge storage films 144 and 144U.

[0088] Reference Fig.10 In the nonvolatile memory device according to some embodiments, the charge storage films 144 and 144U may include a third concave surface 144S2 .

[0089] The third concave surface 144S2 of the charge storage films 144 and 144U may be adjacent to the blocking insulating film 146. For example, the third concave surface 144S2 of the first charge storage film 1441 may be formed on an outer surface of the first charge storage film 1441 adjacent to the first blocking insulating film 1461.

[0090] In some embodiments, the blocking insulating film 146 and the gate electrodes (GSL, WL0 to WLn, and SSL) may extend along the contour of the third concave surface 144S2. For example, the first blocking insulating film 1461 and the first gate electrode WL1 may extend along the contour of the third concave surface 144S2 of the first charge storage film 1441. Therefore, in some embodiments, the sidewall of the first gate electrode WL1 adjacent to the first charge storage film 1441 may include a convex surface WLS.

[0091] Fig.11 1 is a cross-sectional view showing a nonvolatile memory device according to some embodiments of the technical concept of the present invention. Figures 1 to 10 The repeated portion of the provided description.

[0092] Reference Fig.11 , in the nonvolatile memory device according to some embodiments, the insulating pattern 110 may include an air gap AG.

[0093] An air gap AG may be formed in each insulating pattern 110. Thus, the air gap AG may be inserted between the gate electrodes (GSL, WL0 to WLn, and SSL). The air gap AG may be, for example, a void.

[0094] All the insulating patterns 110 are shown to include the air gaps AG, but the technical concept of the inventive concept is not limited thereto. For example, some portions of the insulating patterns 110 may include the air gaps AG, and other portions of the insulating patterns 110 may not include the air gaps AG.

[0095] Fig.121 is a cross-sectional view showing a nonvolatile memory device according to some embodiments of the technical concept of the present invention. Figures 1 to 10 The repeated portion of the provided description.

[0096] Reference Fig.12 , in the nonvolatile memory device according to some embodiments, each blocking insulating film 146 may not extend along the bottom surface and the upper surface of each gate electrode (GSL, WL0 to WLn, and SSL).

[0097] For example, each blocking insulating film 146 may extend only along the sidewall of each gate electrode (GSL, WL0 to WLn, and SSL). As a result, each blocking insulating film 146 may be formed between each gate electrode (GSL, WL0 to WLn, and SSL) and the charge storage films 144 and 144U. In addition, the blocking insulating film 146 may not be interposed between each gate electrode (GSL, WL0 to WLn, and SSL) and the insulating pattern 110.

[0098] In some embodiments, the respective gate electrodes (GSL, WL0 to WLn, and SSL) and the respective insulating patterns 110 may directly contact each other.

[0099] The length of each blocking insulating film 146 extending in the third direction Z is shown to be equal to the length of each gate electrode (GSL, WL0 to WLn and SSL) extending in the third direction Z. However, this is only for convenience of explanation, and the technical concept of the inventive concept is not limited thereto. For example, the length of each blocking insulating film 146 extending in the third direction Z may be greater than the length of each gate electrode (GSL, WL0 to WLn and SSL) extending in the third direction Z.

[0100] Fig.13 1 is a cross-sectional view showing a nonvolatile memory device according to some embodiments of the technical concept of the present invention. Figures 1 to 12 The repeated portion of the provided description.

[0101] Reference Fig.13 , in the nonvolatile memory device according to some embodiments, the upper charge storage film 144U may not extend along the upper surface of the uppermost gate electrode SSL.

[0102] For example, the upper charge storage film 144U may extend only along the sidewalls of the string selection line SSL and may not extend along the upper surface of the string selection line SSL.

[0103] Fig.141 is a schematic layout diagram of a nonvolatile memory device for explaining some embodiments of the technical concept of the present invention. For the sake of convenience of explanation, the following description will be briefly explained or omitted. Figures 1 to 13 The repeated portion of the provided description.

[0104] Reference Fig.14 In the nonvolatile memory device according to some embodiments, a plurality of channel structures CS may be arranged in a zigzag form.

[0105] For example, a portion of the plurality of channel structures CS may form a first row arranged in a line along the second direction Y. Furthermore, other channel structures CS adjacent to the channel structures CS forming the first row may form a second row spaced apart from the first row in the first direction X and arranged in a line along the second direction Y. That is, in some embodiments, the plurality of channel structures CS may be formed such that they do not completely overlap in the second direction Y.

[0106] In the following, reference will be made to Figures 1 to 43 Methods for manufacturing nonvolatile memory devices according to some embodiments of the technical concepts of the inventive concepts are described.

[0107] FIG. 15A to FIG. 29 The following is an intermediate stage diagram for explaining a method for manufacturing a nonvolatile memory device according to some embodiments of the technical concept of the present invention. For the sake of convenience of explanation, the following will be briefly explained or omitted. Figures 1 to 14 The repeated portion of the provided description.

[0108] Refer to 15A to Fig. 15C , a preliminary mold structure MSp including a first sacrificial film 310 , a second sacrificial film 320 , and a third sacrificial film 330 is formed on the substrate 100 .

[0109] In some embodiments, the second sacrificial films 320 and the third sacrificial films 330 may be alternately stacked, and the first sacrificial film 310 may be formed to be interposed between the second sacrificial film 320 and the third sacrificial film 330. Fig.15A As shown in FIG. 1 , the first sacrificial film 310 , the second sacrificial film 320 , and the third sacrificial film 330 may be sequentially stacked on the substrate 100 in the order of the third sacrificial film 330 , the first sacrificial film 310 , the second sacrificial film 320 , and the first sacrificial film 310 to form the preliminary mold structure MSp.

[0110] In some embodiments, Fig. 15B As shown in FIG. 1 , the first sacrificial film 310 , the second sacrificial film 320 , and the third sacrificial film 330 may be repeatedly stacked on the substrate 100 in the order of the first sacrificial film 310 , the third sacrificial film 330 , the first sacrificial film 310 , and the second sacrificial film 320 to form the preliminary mold structure MSp.

[0111] In some embodiments, Fig. 15C As shown in FIG. 1 , the first sacrificial film 310 , the second sacrificial film 320 , and the third sacrificial film 330 may be repeatedly stacked on the substrate 100 in the order of the first sacrificial film 310 , the second sacrificial film 320 , the first sacrificial film 310 , and the third sacrificial film 330 to form the preliminary mold structure MSp.

[0112] Although the first sacrificial films 310 are shown to have the same thickness, this is only for ease of explanation, and the technical concept of the present invention is not limited thereto. For example, the lowermost first sacrificial film 310 may have a thickness different from the thickness of the other first sacrificial films 310. Similarly, each second sacrificial film 320 and each third sacrificial film 330 may have thicknesses different from each other. The first sacrificial film 310 may include, for example, at least one of silicon nitride, silicon oxynitride, Si-rich nitride, and nanocrystal (Si). For ease of explanation, the first sacrificial film 310 will be described below as including silicon nitride.

[0113] The second sacrificial film 320 may define a region where the above-mentioned gate electrodes (GSL, WL0 to WLn, and SSL) are formed. The second sacrificial film 320 may include, for example, polysilicon, but is not limited thereto.

[0114] The third sacrificial film 330 and the first sacrificial film 310 may define a region where the above-mentioned insulating pattern 110 is formed. The third sacrificial film 330 may include, for example, silicon oxide, but is not limited thereto.

[0115] Reference Fig.16 , a first hole H1 is formed in the preliminary mold structure MSp.

[0116] For example, a portion of the preliminary mold structure MSp may be etched to form a first hole H1 penetrating through the first sacrificial film 310, the second sacrificial film 320, and the third sacrificial film 330. The first hole H1 may be formed to penetrate the preliminary mold structure MSp and expose a portion of the substrate 100. In some embodiments, the formation of the first hole H1 may include etching a portion of an upper portion of the substrate 100.

[0117] In some embodiments, the first hole H1 may have a tapered shape. For example, the width of the first hole H1 may become narrower as it approaches the substrate 100. The shape of the first hole H1 may be caused by the characteristics of the etching process used to form the first hole H1, but is not limited thereto.

[0118] Reference Fig.17 , a preliminary charge storage film 144 x , a tunnel insulating film 142 , and a semiconductor pattern 130 are sequentially formed in the first hole H1 .

[0119] The semiconductor pattern 130 may be formed to be connected to the substrate 100. For example, the semiconductor pattern 130 may be formed to penetrate the bottom surface of the preliminary charge storage film 144x and the bottom surface of the tunnel insulating film 142 to be connected to the substrate 100.

[0120] The preliminary charge storage film 144x, the tunnel insulating film 142, and the semiconductor pattern 130 may extend along the outline of the first hole H1. The preliminary charge storage film 144x, the tunnel insulating film 142, and the semiconductor pattern 130 are shown as filling only a portion of the first hole H1, but the technical concept of the inventive concept is not limited thereto. For example, in some embodiments, the semiconductor pattern 130 may be formed to fill all remaining areas of the first hole H1.

[0121] The preliminary charge storage film 144x may include, for example, at least one of silicon nitride, silicon oxynitride, Si-rich nitride, and nanocrystal (Si). In some embodiments, the preliminary charge storage film 144x may have a material composition substantially the same as that of the first sacrificial film 310. For example, the preliminary charge storage film 144x may include silicon nitride.

[0122] Reference Fig.18 , a filling insulating pattern 120 is formed on the semiconductor pattern 130 .

[0123] The filling insulating pattern 120 may be formed to fill all remaining areas of the first hole H1. The filling insulating pattern 120 may include, for example, silicon oxide, but is not limited thereto.

[0124] Reference Fig.19 , a channel pad 150 connected to the semiconductor pattern 130 is formed.

[0125] For example, the upper portion of the filling insulating pattern 120 may be removed, and the channel pad 150 may be formed on the remaining filling insulating pattern 120. Although the width of the channel pad 150 is shown to be the same as the width of the filling insulating pattern 120, the technical concept of the inventive concept is not limited thereto. For example, the channel pad 150 may be formed after removing the upper portion of the semiconductor pattern 130, the tunnel insulating film 142, and / or the preliminary charge storage film 144x.

[0126] The channel pad 150 may include, for example, polysilicon doped with impurities, but is not limited thereto.

[0127] Reference Fig. 20 , a second hole H2 is formed in the uppermost third sacrificial film 330 .

[0128] The second hole H2 may be formed between the semiconductor patterns 130 adjacent to each other in the second direction ( Figure 3 In some embodiments, the second hole H2 may be formed to expose the uppermost second sacrificial film 320.

[0129] Subsequently, a protective film 340 is formed to cover the preliminary mold structure MSp. The protective film 340 may extend along the contour of the second hole H2. As a result, the protective film 340 may cover the uppermost first sacrificial film 310, the uppermost second sacrificial film 320, and the uppermost third sacrificial film 330.

[0130] The protection film 340 may include, for example, polysilicon, but is not limited thereto. In some embodiments, the protection film 340 may have a material composition substantially the same as that of the second sacrificial film 320 .

[0131] Reference Fig.21 , a third hole H3 is formed in the preliminary mold structure MSp.

[0132] The third hole H3 may be formed between the semiconductor patterns 130 adjacent to each other in the second direction ( Figure 3 In addition, the third hole H3 may be formed to overlap with the second hole H2. A portion of the protective film 340 in the second hole H2 may be removed through the third hole H3. The second hole H2 and the third hole H3 may form a separation hole HY.

[0133] The first sacrificial film 310, the second sacrificial film 320, and the third sacrificial film 330 may be exposed through the separation hole HY. However, in some embodiments, the protective film 340 on the sidewall of the second hole H2 may not be removed. For example, the width of the third hole H3 may be formed to be smaller than the width of the second hole H2. As a result, the protective film 340 may still cover the uppermost first sacrificial film 310 and the uppermost third sacrificial film 330. In addition, the separation hole HY including a step may be formed on the sidewall adjacent to the uppermost second sacrificial film 320.

[0134] Reference Fig. 22 , the third sacrificial film 330 exposed through the separation hole HY is removed.

[0135] For example, a first etch-back process may be performed on the third sacrificial film 330 to form a first recess RC1 in a region of the third sacrificial film 330 exposed by the separation hole HY. The first recess RC1 may expose a portion of the preliminary charge storage film 144x. In some embodiments, the uppermost third sacrificial film 330 is protected by the protective film 340 and may not be removed by the first etch-back process.

[0136] Reference Figure 23 to Figure 25 , a second etch-back process is performed on the preliminary charge storage film 144x exposed through the first recess RC1. For reference, Fig.24 and Fig.25 yes Fig.23 Various magnified views of region R3.

[0137] As a result, the charge storage films 144 spaced apart from each other in the third direction Z may be formed. During the second etch-back process, at least a portion of the preliminary charge storage film 144 x overlapping the first sacrificial film 310 may be protected. As a result, each of the charge storage films 144 may include a protrusion 144P protruding from the second sacrificial film 320 .

[0138] Fig.23 and Fig.24 It is illustrated that all portions of the preliminary charge storage film 144 x overlapping the first sacrificial film 310 are not removed, but this is for convenience of explanation, and the technical idea of ​​the inventive concept is not limited thereto.

[0139] The first sacrificial film 310 may be removed in the second etch-back process or in a subsequent process. In some embodiments, the uppermost first sacrificial film 310 is protected by the protective film 340 and may not be removed by the second etch-back process. The lowermost first sacrificial film 310 is shown as not being removed, but this is only for ease of explanation, and at least a portion of the lowermost first sacrificial film 310 may be removed in the second etch-back process or in a subsequent process.

[0140] In some embodiments, a portion of the preliminary charge storage film 144x adjacent to the substrate 100 may not be removed. As a result, a portion of the charge storage film 144 may remain on the upper surface of the substrate 100. However, this is only for convenience of explanation, and the technical concept of the inventive concept is not limited thereto. For example, depending on the characteristics of the process for forming the charge storage film 144, a portion of the charge storage film 144 may not remain on the upper surface of the substrate 100.

[0141] Reference Fig.25 In the nonvolatile memory device according to some embodiments, the protrusion 144P of the charge storage film 144 may include a first concave surface 144S1. The first concave surface 144S1 may be due to, for example, characteristics of the second etch-back process.

[0142] Reference Fig.26 , a plurality of insulating patterns 110 are formed in the first recess RC1.

[0143] As a result, the insulating patterns 110 alternately stacked with the second sacrificial films 320 may be formed. The plurality of insulating patterns 110 may include, for example, silicon oxide, but is not limited thereto.

[0144] Reference Fig. 27 , the second sacrificial film 320 exposed through the separation hole HY is removed.

[0145] For example, a third etch-back process may be performed on the second sacrificial film 320 to form the second recess RC2 in the region of the second sacrificial film 320 exposed by the separation hole HY.

[0146] Reference Fig.28, a blocking insulating film 146 and gate electrodes (GSL, WL0 to WLn, and SSL) are sequentially formed in the second recess RC2.

[0147] For example, the blocking insulating film 146 may be formed along the outline of the second recess RC2. Subsequently, the gate electrodes (GSL, WL0 to WLn, and SSL) for filling the second recess RC2 may be formed on the blocking insulating film 146.

[0148] As a result, each blocking insulating film 146 may be formed to surround the respective gate electrodes (GSL, WL0 to WLn, and SSL). In addition, a plurality of gate electrodes (GSL, WL0 to WLn, and SSL) alternately stacked with a plurality of insulating patterns 110 may be formed.

[0149] Reference Fig.29 , an impurity region 105 is formed in a region of the substrate 100 exposed by the separation hole HY.

[0150] The formation of the impurity region 105 may be performed by, for example, an ion implantation process, but is not limited thereto.

[0151] Next, an insulating spacer 162 and a common source plug pattern 164 are formed in the separation hole HY. For example, the insulating spacer 162 may be formed along the outline of the separation hole HY. Subsequently, a common source plug pattern 164 penetrating the bottom surface of the insulating spacer 162 and connected to the impurity region 105 may be formed.

[0152] Subsequently, a bit line BL connected to the channel pad 150 may be formed. Thus, Figure 3 A non-volatile memory device.

[0153] Figure 30 to Figure 36 1 is an intermediate step diagram for explaining a method for manufacturing a nonvolatile memory device according to some embodiments of the technical concept of the present invention. For the sake of convenience of explanation, the description will be briefly described or omitted. Figures 1 to 29 A duplicate portion of the description provided. For reference, Fig.30 It is used to explain Fig. 22 Diagram of the next steps.

[0154] Reference Figure 30 to Figure 32 , a second etch-back process is performed on the preliminary charge storage film 144x exposed through the first recess RC1. For reference, Fig.31 and Fig.32 Show Fig.30 Various magnified views of region R4.

[0155] Reference Fig.31In the nonvolatile memory device according to some embodiments, the length of the charge storage film 144 extending in the third direction Z may increase as it approaches the semiconductor pattern 130 .

[0156] For example, the protrusion 144P of the charge storage film 144 may include a first concave surface 144S1. The first concave surface 144S1 may be due to, for example, characteristics of the second etch-back process.

[0157] Reference Fig.32 In the nonvolatile memory device according to some embodiments, the tunnel insulating film 142 may include a second concave surface 142S. The second concave surface 142S may be due to, for example, characteristics of the second etch-back process.

[0158] Reference Fig.33 , a plurality of insulating patterns 110 are formed in the first recess RC1. Due to the formation and use of the plurality of insulating patterns 110 Fig.26 The descriptions are substantially the same, so a detailed description thereof will not be provided below.

[0159] Reference Figure 34 to Figure 36 , remove the second sacrificial film 320 exposed through the separation hole HY. For reference, Fig.35 and Fig.36 Show Fig.34 Various magnified views of region R5.

[0160] Reference Fig.34 and Fig.35 , a third etch-back process is performed on the second sacrificial film 320 , and a second recess RC2 may be formed in a region of the second sacrificial film 320 exposed by the separation hole HY.

[0161] Reference Fig.36 In the nonvolatile memory device according to some embodiments, the charge storage film 144 may include a third concave surface 144S2. The third concave surface 144S2 may be due to, for example, characteristics of the third etch-back process.

[0162] Fig.37 is an intermediate step diagram for explaining a method for manufacturing a nonvolatile memory device according to some embodiments of the technical concept of the present invention. For reference, Fig.37 It is used to explain Fig.30 Diagram of the next steps.

[0163] Reference Fig.37 , a plurality of insulating patterns 110 including air gaps AG are formed in the first recess RC1.

[0164] For example, the plurality of insulation patterns 110 including the air gaps AG in the first recess RC1 may be formed using a material having a poor step coverage characteristic.

[0165] Figures 38 to 43 FIG. 1 is an intermediate stage diagram for explaining a method for manufacturing a nonvolatile memory device according to some embodiments of the technical concept of the present invention. For the sake of convenience of explanation, the description will be briefly described or omitted. Figures 1 to 29 A duplicate portion of the description provided. For reference, Fig.38 It is used to explain Fig.15A Diagram of the next steps.

[0166] Reference Fig.38 , a first hole H1 is formed in the preliminary mold structure MSp.

[0167] For example, a portion of the preliminary mold structure MSp may be etched to form a first hole H1 penetrating the first sacrificial film 310, the second sacrificial film 320, and the third sacrificial film 330. The first hole H1 may be formed to penetrate the preliminary mold structure MSp and expose a portion of the substrate 100. In some embodiments, the formation of the first hole H1 may include etching a portion of an upper portion of the substrate 100.

[0168] Reference Fig.39 , a preliminary blocking insulating film 146 x , a preliminary charge storage film 144 x , a tunnel insulating film 142 , and a semiconductor pattern 130 are sequentially formed in the first hole H1 .

[0169] The preliminary blocking insulating film 146 x , the preliminary charge storage film 144 x , the tunnel insulating film 142 , and the semiconductor pattern 130 may extend along the outline of the first hole H1 .

[0170] The preliminary blocking insulating film 146x may include a high-k material having a dielectric constant higher than, for example, silicon oxide or silicon oxide. The high-k material may include, for example, at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof. For ease of explanation, the blocking insulating film 146 will be described below as including silicon oxide.

[0171] Reference Fig.40 , the third sacrificial film 330 exposed through the separation hole HY is removed.

[0172] For example, the above steps can be used Figures 18 to 21 As a result, a separation hole HY including the second hole H2 and the third hole H3 may be formed in the preliminary mold structure MSp.

[0173] Next, a first etch-back process is performed on the first sacrificial film 330 , and a first recess RC1 may be formed in a region of the third sacrificial film 330 exposed by the separation hole HY.

[0174] In some embodiments, the first recess RC1 may expose a portion of the preliminary charge storage film 144x. For example, a portion of the preliminary blocking insulating film 146x may be removed together by the first etch-back process. As a result, a blocking insulating film 146 extending along the sidewalls of each gate electrode (GSL, WL0 to WLn, and SSL) may be formed. However, the technical concept of the inventive concept is not limited thereto, and according to the characteristics of the first etch-back process, the preliminary blocking insulating film 146x may not be removed by the first etch-back process.

[0175] Reference Fig.41 , a second etch-back process is performed on the preliminary charge storage film 144x exposed through the first recess RC1.

[0176] As a result, the charge storage films 144 spaced apart from each other in the third direction Z may be formed. In the process of performing the second etch-back process, at least a portion of the preliminary charge storage film 144 x overlapping the first sacrificial film 310 may be protected.

[0177] A portion of the blocking insulating film 146 overlapping the first sacrificial film 310 is shown as being removed, but this is only for convenience of explanation, and the technical concept of the inventive concept is not limited thereto. For example, a portion of the blocking insulating film 146 overlapping the first sacrificial film 310 may remain without being removed. Fig.42 , the second sacrificial film 320 exposed through the separation hole HY is removed.

[0178] For example, the above steps can be used Fig.26 As a result, a plurality of insulating patterns 110 may be formed in the first recess RC1.

[0179] Next, a third etch-back process is performed on the second sacrificial film 320 , and a second recess RC2 may be formed in a region of the second sacrificial film 320 exposed by the separation hole HY.

[0180] Reference Fig.43 , gate electrodes (GSL, WL0 to WLn, and SSL) are formed in the second recess RC2.

[0181] For example, the gate electrodes (GSL, WL0 to WLn, and SSL) for filling the second recess RC2 may be formed on the blocking insulating film 146 .

[0182] As a result, each blocking insulating film 146 may be formed between each gate electrode (GSL, WL0 to WLn, and SSL) and the charge storage films 144 and 144U. In addition, the blocking insulating film 146 may not be interposed between each gate electrode (GSL, WL0 to WLn, and SSL) and the insulating pattern 110.

[0183] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the exemplary embodiments without departing substantially from the principles of the inventive concept. Therefore, the exemplary embodiments of the disclosed inventive concept are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A non-volatile memory device, comprising: a mold structure including a first insulating pattern, a first gate electrode, and a second insulating pattern sequentially stacked on a substrate; a semiconductor pattern penetrating the mold structure, connected to the substrate, and extending in a first direction; a first charge storage film extending in the first direction and located between the first insulating pattern and the second insulating pattern and between the first gate electrode and the semiconductor pattern; as well as a blocking insulating film located between the first gate electrode and the first charge storage film, wherein a first length of the first charge storage film extending in the first direction is longer than a second length of the blocking insulating film extending in the first direction, and Among them, the first charge storage film includes a protrusion, which extends in the first direction to one of the first insulating pattern and the second insulating pattern, so that the protrusion of the first charge storage film is in contact with the one of the first insulating pattern and the second insulating pattern, and the rest of the first charge storage film is in contact with the blocking insulating film.

2. The nonvolatile memory device according to claim 1, wherein: The blocking insulating film extends along a bottom surface, side walls, and an upper surface of the first gate electrode.

3. The nonvolatile memory device according to claim 1, wherein: The mold structure further includes a second gate electrode located on the second insulating pattern, and The nonvolatile memory device further includes a second charge storage film spaced apart from the first charge storage film and located between the second gate electrode and the semiconductor pattern.

4. The nonvolatile memory device according to claim 1, wherein: The first insulating pattern and the second insulating pattern include air gaps therein.

5. The nonvolatile memory device according to claim 1, wherein: The first length increases as approaching the semiconductor pattern.

6. The nonvolatile memory device according to claim 1, wherein: A side wall of the first charge storage film adjacent to the blocking insulating film includes a concave surface.

7. The nonvolatile memory device according to claim 1, wherein: The mold structure further includes a ground selection line between the substrate and the first insulation pattern.

8. The nonvolatile memory device according to claim 1, wherein: The molding structure further includes a string selection line located on the second insulating pattern, and The nonvolatile memory device further includes an upper charge storage film extending along an upper surface and a sidewall of the string selection line.

9. The nonvolatile memory device according to claim 1, further comprising: an impurity region located in the substrate; as well as a separation structure penetrating the mold structure and connected to the impurity region, Wherein, the mold structure further includes a string selection line located on the second insulating pattern, and A sidewall of the separation structure adjacent to the string selection line includes a step.

10. A non-volatile memory device comprising: a molded structure including a first gate electrode, an insulating pattern, and a second gate electrode sequentially stacked on a substrate; a semiconductor pattern penetrating the mold structure and connected to the substrate; a first charge storage film located between the first gate electrode and the semiconductor pattern; a second charge storage film separated from the first charge storage film and located between the second gate electrode and the semiconductor pattern; a first blocking insulating film located between the first gate electrode and the insulating pattern; as well as a second blocking insulating film located between the second gate electrode and the insulating pattern, wherein a first distance separating the first charge storage film and the second charge storage film from each other is shorter than a second distance separating the first blocking insulating film and the second blocking insulating film from each other, and Among them, the first charge storage film includes a first protrusion extending into the insulating pattern in a first direction, the first protrusion of the first charge storage film is in contact with the insulating pattern, and the rest of the first charge storage film is in contact with the first blocking insulating film, and the second charge storage film includes a second protrusion extending into the insulating pattern in the first direction, the second protrusion of the second charge storage film is in contact with the insulating pattern, and the rest of the second charge storage film is in contact with the second blocking insulating film.

11. The nonvolatile memory device according to claim 10, wherein: The first blocking insulating film extends along a bottom surface, side walls, and an upper surface of the first gate electrode, and The second blocking insulating film extends along a bottom surface, side walls, and an upper surface of the second gate electrode.

12. The nonvolatile memory device according to claim 10, wherein: The semiconductor pattern extends in a first direction and penetrates the mold structure, and A first length of the first charge storage film extending in the first direction is longer than a second length of the first blocking insulating film extending in the first direction.

13. The non-volatile memory device according to claim 12, further comprising: a tunnel insulating film penetrating the mold structure and located between the semiconductor pattern and the insulating pattern, Wherein, a side wall of the tunnel insulating film between the first charge storage film and the second charge storage film includes a concave surface.

14. The nonvolatile memory device according to claim 10, wherein: The insulating pattern includes an air gap therein.

15. The nonvolatile memory device according to claim 10, wherein: The first distance decreases as approaching the semiconductor pattern.

16. A non-volatile memory device comprising: a mold structure including a first insulating pattern, a first gate electrode, and a second insulating pattern sequentially stacked on a substrate; a semiconductor pattern penetrating the mold structure, connected to the substrate, and extending in a first direction; a first charge storage film extending in the first direction and located between the first insulating pattern and the second insulating pattern and between the first gate electrode and the semiconductor pattern; as well as a blocking insulating film located between the first gate electrode and the first charge storage film, wherein a first length of the first charge storage film extending in the first direction increases as it approaches the semiconductor pattern, The first charge storage film includes: a first protrusion extending in the first direction into the first insulating pattern, and a second protrusion extending in the first direction into the second insulating pattern, so that the first protrusion of the first charge storage film contacts the first insulating pattern, the second protrusion of the first charge storage film contacts the second insulating pattern, and the rest of the first charge storage film contacts the blocking insulating film. The first protrusion is disposed above an upper surface of the first gate electrode, and The second protrusion is disposed below a bottom surface of the first gate electrode.

17. The nonvolatile memory device according to claim 16, wherein: The mold structure further includes a second gate electrode located on the second insulating pattern, and The nonvolatile memory device further includes a second charge storage film spaced apart from the first charge storage film and located between the second gate electrode and the semiconductor pattern.

18. The nonvolatile memory device according to claim 16, wherein: A distal end of the first charge storage film adjacent to the first insulating pattern includes a concave surface.

19. The nonvolatile memory device according to claim 16, in, The blocking insulating film extends along a bottom surface, side walls, and an upper surface of the first gate electrode.

20. The nonvolatile memory device according to claim 16, in, A second length of the barrier insulating film extending in the first direction is shorter than the first length.

Images