Semiconductor packaging

Abstract

A semiconductor package is provided. The semiconductor package includes: a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip disposed on the lower structure and including a lower insulating layer and a lower pad. The lower insulating layer contacts and is coupled to the upper insulating layer, and the lower pad contacts and is coupled to the upper pad, and a side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and includes a concave portion.

Description

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0127736 filed on October 24, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the present disclosure relate to a semiconductor package. Background Art

[0004] As demands for higher capacity, thinning, and miniaturization of electronic products increase, various types of semiconductor packages have been developed. Summary of the invention

[0005] One or more exemplary embodiments provide a semiconductor package having a reduced thickness.

[0006] One or more exemplary embodiments provide a semiconductor package in which a semiconductor chip can be mounted without defects.

[0007] According to aspects of an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip disposed on the lower structure and including a lower insulating layer and a lower pad. The lower insulating layer contacts and is coupled to the upper insulating layer, and the lower pad contacts and is coupled to the upper pad, and a side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and includes a concave portion.

[0008] According to aspects of an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a lower structure; and a semiconductor chip, which is disposed on the lower structure and has an upper side and a lower side opposite to the upper side. The lower structure includes an upper pad and an upper insulating layer, the semiconductor chip includes a lower pad and a lower insulating layer disposed at the lower side of the semiconductor chip, the lower pad contacts and is coupled to the upper pad, the lower insulating layer contacts and is coupled to the upper insulating layer, and the lower side of the semiconductor chip is narrower than the upper side of the semiconductor chip.

[0009] According to aspects of an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a lower structure; and a plurality of semiconductor chips disposed on the lower structure. The plurality of semiconductor chips include a first semiconductor chip and a second semiconductor chip that are in direct contact with each other, the first semiconductor chip having a first upper side and a first lower side opposite to the first upper side, the second semiconductor chip having a second upper side and a second lower side opposite to the second upper side, the first semiconductor chip including an upper insulating layer and an upper pad disposed at the first upper side of the first semiconductor chip, the second semiconductor chip including a lower insulating layer and a lower pad disposed at the second lower side of the second semiconductor chip, the lower insulating layer and the upper insulating layer being in contact with each other and coupled to each other, the lower pad and the upper pad being in contact with each other and coupled to each other, and the second lower side of the second semiconductor chip being narrower than the second upper side of the second semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present invention will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a cross-sectional view illustrating an example of a semiconductor package according to an exemplary embodiment.

[0012] Figures 2 to 5 It is shown Figure 1 Partially enlarged views of various examples of portion "A" in FIG.

[0013] Figure 6 is a cross-sectional view showing a modified example of the semiconductor package according to the exemplary embodiment.

[0014] Figure 7 is a cross-sectional view showing a modified example of the semiconductor package according to the exemplary embodiment.

[0015] Figure 8 is a cross-sectional view showing a modified example of the semiconductor package according to the exemplary embodiment.

[0016] Fig. 9 yes Figure 8 A partial enlarged view of part "B" in FIG.

[0017] Fig.10 is a cross-sectional view showing a modified example of the semiconductor package according to the exemplary embodiment.

[0018] Fig.11 is a flowchart illustrating an example of a method of forming a semiconductor package according to an exemplary embodiment.

[0019] Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D is a cross-sectional view illustrating an example of a method of forming a semiconductor package according to an exemplary embodiment.

[0020] Description of Figure Numbers

[0021] 1a, 1b, 1c, 1d, 1e: Semiconductor packaging

[0022] 10, 10': Base

[0023] 15: Base insulation layer

[0024] 20: Base pad

[0025] 50: Connection structure

[0026] 100: Lower structure / lower chip

[0027] 100', 100c: Lower structure

[0028] 100a, 100b: semiconductor chip / lower structure

[0029] 101s, 201s, 501s: Side

[0030] 101s1, 201s1: Part 1

[0031] 101s2, 501s2: Part 2

[0032] 107, 150, 170a: Lower connection pad

[0033] 110: Lower body

[0034] 210f: Lower side

[0035] 110b, 110f: upper side / lower side

[0036] 115: Lower internal circuit

[0037] 120, 520: penetrating electrode structure

[0038] 125, 525: Insulating spacers

[0039] 130, 530: Penetrating electrode

[0040] 135a, 135b: Lower internal circuit area

[0041] 140a, 140b: Lower internal interconnect

[0042] 145a, 145b: Lower inner insulation layer

[0043] 160b, 160c: Redistribution area

[0044] 165a: Lower protective insulation layer

[0045] 167: First redistribution insulation layer

[0046] 175: Redistribution pattern

[0047] 180: Second redistribution insulation layer

[0048] 190: Upper insulation layer

[0049] 195: Upper pad

[0050] 197: Lower insulation layer

[0051] 199: Lower pad

[0052] 200: Semiconductor chip / chip on

[0053] 201b: Second side / upper side

[0054] 201f: First side / lower side

[0055] 201s2: The second part / concave side part

[0056] 201s2': Modified Part II

[0057] 201s2a, 501s2a: vertical section

[0058] 201s2b, 501s2b: curved part

[0059] 201s2ba: First bend

[0060] 201s2bb: Second bend

[0061] 210, 510: semiconductor body

[0062] 215, 515: Internal circuits of semiconductors

[0063] 235, 535: Semiconductor internal circuit area

[0064] 240, 540: Semiconductor internal interconnection

[0065] 245, 545: Insulation layer inside semiconductor

[0066] 250: Lower semiconductor insulating layer / lower insulating layer

[0067] 255: Lower semiconductor pad / lower pad

[0068] 310, 310', 610, 610': Molding layer

[0069] 320, 620: heat dissipation structure

[0070] 325, 625: Insulation and thermal conductive layer

[0071] 330, 630: heat sink

[0072] 500: Semiconductor chips

[0073] 500a: lower semiconductor chip / lowermost semiconductor chip

[0074] 500b, 500c: lower semiconductor chip

[0075] 500d: semiconductor chip

[0076] 501s1: Side / Part 1

[0077] 550: Lower semiconductor insulating layer

[0078] 555: Lower semiconductor pad

[0079] 570: Semiconductor protection insulation layer

[0080] 590: Upper semiconductor insulating layer

[0081] 595: Upper semiconductor pad

[0082] 1000: Carrier substrate

[0083] 1010: Adhesive layer

[0084] 1100: Protective layer

[0085] 1200: Grooves

[0086] 1300: Sawing process

[0087] A, B: Part

[0088] CA: Chip Area

[0089] S10, S20, S30, S40, S50, S60: Steps

[0090] Wa: semiconductor wafer

[0091] Wb: substrate wafer DETAILED DESCRIPTION

[0092] It will be understood that when an element or layer is referred to as being “on,” “over,” “on,” “connected to,” or “coupled to” another element or layer, the element or layer may be directly on, over, on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly over,” “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers.

[0093] Figure 1 is a cross-sectional view illustrating an example of a semiconductor package according to an exemplary embodiment.

[0094] Reference Figure 1 , the semiconductor package 1a may include a lower structure 100 and a semiconductor chip 200 located on the lower structure 100. The semiconductor chip 200 may be a memory semiconductor chip or a logic semiconductor chip. For example, the memory semiconductor chip may be a volatile memory chip, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or may be a non-volatile memory chip, such as a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM) or a resistive random access memory (RRAM). The logic semiconductor chip may be a microprocessor, an analog device or a digital signal processor.

[0095] In an example, the lower structure 100 may be a lower semiconductor chip different from the semiconductor chip 200, but exemplary embodiments thereof are not limited thereto. For example, the lower structure 100 may also be an interposer.

[0096] The lower structure 100 may include an upper insulating layer 190 and an upper pad 195. The semiconductor chip 200 may include a lower semiconductor insulating layer 250 and a lower semiconductor pad 255, the lower semiconductor insulating layer 250 contacts and is coupled to the upper insulating layer 190, and the lower semiconductor pad 255 contacts and is coupled to the upper pad 195. The semiconductor chip 200 may include a side 201s, the side 201s including a first portion 201s1 and a second portion 201s2 having an undercut shape that is recessed compared to the first portion 201s1.

[0097] The upper pad 195 and the lower semiconductor pad 255 may be formed of a conductive material such as copper, etc., and may be combined with each other and contact each other.

[0098] The upper insulating layer 190 and the lower semiconductor insulating layer 250 may be formed of an insulating material such as silicon oxide, and may be combined with and contact each other. The material of the upper insulating layer 190 and the lower semiconductor insulating layer 250 may be formed of SiCN or the like, but is not limited to silicon oxide.

[0099] The semiconductor package 1 a may further include a mold layer 310 disposed on the lower structure 100 and covering the semiconductor chip 200 .

[0100] The semiconductor package 1a may further include a substrate 10 located below the lower structure 100 and a connection structure 50 physically connecting the substrate 10 and the lower structure 100. The substrate 10 may be a printed circuit board, an interposer, or a semiconductor chip. The connection structure 50 may be a solder ball or a bump.

[0101] Next, we will refer to Figures 2 to 5 Various examples of the structure 100 and the semiconductor chip 200 are described below. Figures 2 to 5 It is shown Figure 1 Partially enlarged views of various examples of portion "A" in FIG.

[0102] In the example, refer to Figure 1 and Figure 2 The semiconductor chip 200 includes a first side 201f contacting the lower structure 100 and a second side 201b opposite to the first side 201f. The first side 201f may be referred to as a "lower side", and the second side 201b may be referred to as an "upper side".

[0103] The semiconductor chip 200 may include a semiconductor body 210, a semiconductor internal circuit region 235, a lower semiconductor insulating layer 250, and a lower semiconductor pad 255. The semiconductor internal circuit region 235 may be disposed below the semiconductor body 210, and the lower semiconductor insulating layer 250 and the lower semiconductor pad 255 may be disposed below the semiconductor internal circuit region 235.

[0104] The semiconductor body 210 may be a semiconductor substrate, and the semiconductor internal circuit region 235 may be disposed on a lower side 210 f of the semiconductor body 210 .

[0105] The semiconductor internal circuit region 235 may include a semiconductor internal circuit 215 and a semiconductor internal interconnection 240 electrically connecting the semiconductor internal circuit 215 and a lower semiconductor pad 255. The semiconductor internal circuit 215 and the semiconductor internal interconnection 240 may be disposed within a semiconductor internal insulating layer 245.

[0106] The semiconductor chip 200 may have a lower side 201f and an upper side 201b opposite to each other. The lower side 201f of the semiconductor chip 200 may contact and be coupled to the lower structure 100. In the semiconductor chip 200, the width of the lower side 201f may be smaller than the width of the upper side 201b. The width of the semiconductor internal circuit region 235 may be smaller than the width of the upper side 201b of the semiconductor chip 200.

[0107] The side 201s of the semiconductor chip 200 includes a first portion 201s1 and a second portion 201s2. The first portion 201s1 may extend from an edge of the upper side 201b in a direction substantially perpendicular to the upper side 201b, and the second portion 201s2 may extend from an edge of the lower side 201f to the first portion 201s1. The second portion 201s2 may include a vertical portion 201s2a extending from an edge of the lower side 201f in a direction substantially perpendicular to the lower side 201f, and a bent portion 201s2b extending from the vertical portion 201s2a to the first portion 201s1.

[0108] Figure 1 The lower structure 100 shown may correspond to Figure 2 The lower structure 100a is shown. The lower structure 100a may include a lower body 110, a lower protective insulating layer 165a and a lower connecting pad 170a located below the lower body 110, a lower internal circuit region 135a located on the lower body 110, and an upper insulating layer 190 and an upper pad 195 located on the lower internal circuit region 135a. The lower body 110 may be a semiconductor substrate, such as a silicon substrate, etc. The lower internal circuit region 135a may be disposed on the upper side 110f of the lower body 110, and the lower protective insulating layer 165a and the lower connecting pad 170a may be disposed on the lower side 110b of the lower body 110.

[0109] The lower structure 100a may include a through-electrode structure 120 that penetrates the lower body 110 to electrically connect the lower connection pad 170a and the upper pad 195. The through-electrode structure 120 may include a through-electrode 130 formed of a conductive material such as copper and an insulating spacer 125 surrounding the side of the through-electrode 130. The lower internal interconnection 140a may electrically connect the upper pad 195 and the through-electrode 120. The upper pad 195 may be electrically connected to the lower connection pad 170a through the lower internal interconnection 140a and the through-electrode 120.

[0110] The lower internal circuit region 135a may include a lower internal circuit 115 and a lower internal interconnection 140a electrically connecting the lower internal circuit 115 and the upper pad 195. The lower internal circuit 115 and the lower internal interconnection 140a may be disposed in a lower internal insulating layer 145a.

[0111] Therefore, the lower structure 100 may be a semiconductor chip 100 a including a lower inner circuit region 135 a facing the semiconductor chip 200 .

[0112] In the modified example, reference is made to Figure 1 and Figure 3 , refer to the above Figure 1 The lower structure 100 described may correspond to Figure 3 The lower structure 100b may include a lower body 110, a redistribution region 160b disposed on an upper side 110b of the lower body 110, a lower internal circuit region 135b disposed on a lower side 110f of the lower body 110, and an upper insulating layer 190 and an upper pad 195 disposed on the redistribution region 160b.

[0113] The lower internal circuit region 135b may include a lower internal circuit 115, a lower internal interconnection 140b electrically connected to the lower internal circuit 115, and a lower connection pad 150 electrically connected to the lower internal interconnection 140b. The lower internal circuit 115 and the lower internal interconnection 140b may be disposed in the lower internal insulating layer 145b. The lower connection pad 150 may be connected to the above-mentioned connection structure 50.

[0114] The redistribution region 160 b may include a redistribution pattern 175 , a first redistribution insulation layer 167 between the redistribution pattern 175 and the lower body 110 , and a second redistribution insulation layer 180 between the first redistribution insulation layer 167 and the upper insulation layer 190 .

[0115] The lower structure 100b may include a through electrode structure 120 that penetrates the lower body 110 and electrically connects the lower internal interconnection 140b and the redistribution pattern 175 to each other. Therefore, the upper pad 195 and the lower connection pad 150 of the lower structure 100b may be electrically connected to each other through the through electrode structure 120.

[0116] Therefore, the lower structure 100 may be a semiconductor chip 100b including a lower internal circuit region 135b formed on a lower side 110f of a lower body 110 whose upper side 110b faces the semiconductor chip 200 and the lower internal circuit region 135b faces the substrate 10.

[0117] In the modified example, reference is made to Figure 1 and Figure 4 , refer to the above Figure 1 The lower structure 100 described may correspond to Figure 4 The lower structure 100c may include a lower body 110, a redistribution region 160c disposed on an upper side 110b of the lower body 110, a lower protective insulating layer 165a and lower connecting pads 107 formed on a lower side 110f of the lower body 110, and an upper insulating layer 190 and upper pads 195 disposed on the redistribution region 160c.

[0118] The redistribution area 160c can be compared with the reference Figure 3 The redistribution region 160b similarly includes a redistribution pattern 175, a first redistribution insulating layer 167 and a second redistribution insulating layer 180. The lower structure 100c may include a through-electrode structure 120 that penetrates the lower body 110 and electrically connects the redistribution pattern 175 and the lower connection pad 107.

[0119] Therefore, the lower structure 100 c may be an interposer including the redistribution region 160 c facing the semiconductor chip 200 .

[0120] In the modified example, reference is made to Figure 1 and Figure 5 The side 201s of the semiconductor chip 200 may include a modified second portion 201s2' and the above reference Figure 1 and Figure 2 The first part 201s1 is described. In this case, since the above reference Figure 1 and Figure 2 The remaining components except the second portion 201s2' of the side 201s are described, and thus will not be described again.

[0121] The second portion 201s2' of the semiconductor chip 200 may include a vertical portion 201s2a extending from an edge of the lower side 201f of the semiconductor chip 200 in a direction substantially perpendicular to the lower side 201f, a first bent portion 201s2ba extending from the vertical portion 201s2a, and a second bent portion 201s2bb extending from the first bent portion 201s2ba to the first portion 201s1 and different from the first bent portion 201s2ba.

[0122] Will refer to Figure 6 A semiconductor package according to an exemplary embodiment is described. Figure 6 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment.

[0123] like Figure 6 As shown, the semiconductor package 1b can be Figure 1 A similar structure includes a substrate 10, a lower structure 100 located on the substrate 10, and a semiconductor chip 200 located on the lower structure 100. The semiconductor package 1b may include a mold layer 310' covering the side 201s of the semiconductor chip 200.

[0124] The semiconductor package 1b may include a heat dissipation structure 320 covering the semiconductor chip 200 and the molding layer 310'. The heat dissipation structure 320 may include an insulating heat conductive layer 325 and a heat dissipation plate 330. The heat dissipation plate 330 may be formed of a metal material capable of radiating heat generated in the semiconductor chip 200 to the outside. The insulating heat conductive layer 325 may couple the heat dissipation plate 330 to the semiconductor chip.

[0125] Figure 7 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment.

[0126] Reference Figure 7 The semiconductor package 1 c may include a substrate 10 ′, a lower structure 100 ′ located on the substrate 10 ′, and a semiconductor chip 200 located on the lower structure 100 ′.

[0127] The substrate 10 ′ may include a substrate insulating layer 15 and a substrate pad 20 .

[0128] The lower structure 100 ′ may include a lower insulating layer 197 contacting and coupled to the base insulating layer 15 , and a lower pad 199 contacting and coupled to the base pad 20 .

[0129] The semiconductor chip 200 may be similar to the semiconductor chip described above. For example, the semiconductor chip 200 may include the lower semiconductor insulating layer 250 and the lower semiconductor pad 255 as described above, and may include the side 201s having the first portion 201s1 and the second portion 201s2 as described above. The lower structure 100' may include an upper insulating layer 190 and an upper pad 195, the upper insulating layer 190 contacts the lower semiconductor insulating layer 250 of the semiconductor chip 200 and is coupled to the lower semiconductor insulating layer 250 of the semiconductor chip 200, and the upper pad 195 contacts the lower semiconductor pad 255 of the semiconductor chip 200 and is coupled to the lower semiconductor pad 255 of the semiconductor chip 200. The side 101s of the lower structure 100' may include the first portion 101s1 and the second portion 101s2. Compared with the first portion 101s1, the second portion 101s2 may be further recessed. The second portion 101s2 of the lower structure 100' extends from a surface of the lower structure 100' and contacts and is coupled to the substrate 10'. The first portion 101s1 of the lower structure 100' may extend from an edge of the lower structure 100'.

[0130] Figure 8 is a cross-sectional view showing a modified example of a semiconductor package according to an exemplary embodiment, and Fig. 9 yes Figure 8 A partial enlarged view of portion 'B'.

[0131] Reference Figure 8 and Fig. 9 The semiconductor package 1d may include a substrate 10, a lower structure 100 coupled to the substrate 10 through a connection structure 50 above the substrate 10, a plurality of semiconductor chips 500 located above the lower structure 100, and a molding layer 610 disposed on the lower structure 100 and covering the plurality of semiconductor chips 500.

[0132] In an example, the substrate 10 may be a printed circuit board or a semiconductor chip.

[0133] In an example, the lower structure 100 may be similar to Figure 1 The following structure is described in .

[0134] In an example, the plurality of semiconductor chips 500 may include one or more lower semiconductor chips 500 a , 500 b , and 500 c and an upper semiconductor chip 500 d located on the one or more lower semiconductor chips 500 a , 500 b , and 500 c .

[0135] In an example, in the case of the plurality of lower semiconductor chips 500 a , 500 b , and 500 c , the plurality of lower semiconductor chips 500 a , 500 b , and 500 c may have a similar shape or a similar structure.

[0136] Each of the plurality of semiconductor chips 500 includes a side 501s, the side 501s including a first portion 501s1 and a second portion 501s2 extending from the first portion 501s1 and further recessed than the first portion 501s1. The second portion 501s2 may include a vertical portion 501s2a and a curved portion 501s2b. The first portion 501s1 and the second portion 501s2 of the side 501s may have the same structure as described above. Figure 1 and Figure 2 The shapes or structures of the first portion 201s1 and the second portion 201s2 of the side 201s described above are similar to those of the first portion 501s1 and the second portion 501s2 of the side 501s. Therefore, the first portion 501s1 and the second portion 501s2 of the side 501s will not be described in detail.

[0137] Each of the plurality of semiconductor chips 500 may include a semiconductor body 510, a semiconductor internal circuit region 535 located below the semiconductor body 510, and a lower semiconductor insulating layer 550 and a lower semiconductor pad 555 located below the semiconductor internal circuit region 535. The semiconductor body 510 may be a semiconductor substrate, such as a silicon substrate, etc. The semiconductor internal circuit region 535 may include a semiconductor internal insulating layer 545, a semiconductor internal circuit 515, and a semiconductor internal interconnection 540 that electrically connects the semiconductor internal circuit 515 and the lower semiconductor pad 555 to each other. The semiconductor internal circuit 515 and the semiconductor internal interconnection 540 may be disposed in the semiconductor internal insulating layer 545.

[0138] Each of the lower semiconductor chips 500a, 500b, and 500c of the plurality of semiconductor chips 500 may further include an upper semiconductor insulating layer 590 and an upper semiconductor pad 595 on the semiconductor body 510. Each of the lower semiconductor chips 500a, 500b, and 500c of the plurality of semiconductor chips 500 may further include a semiconductor protection insulating layer 570 between the semiconductor body 510 and the upper semiconductor insulating layer 590.

[0139] Each of the lower semiconductor chips 500a, 500b, and 500c may include a semiconductor through-electrode structure 520 that penetrates the semiconductor body 510 and electrically connects the lower semiconductor pad 555 and the upper semiconductor pad 595 to each other. The semiconductor through-electrode structure 520 may include a through-electrode 530 formed of a conductive material such as copper and an insulating spacer 525 surrounding a side of the through-electrode 530.

[0140] In the semiconductor chip 500, the upper semiconductor insulating layer 590 of the semiconductor chip located at a relatively low position and the lower semiconductor insulating layer 550 of the semiconductor chip located at a relatively high position may contact and couple with each other. In addition, in the semiconductor chip 500, the upper semiconductor pad 595 of the semiconductor chip located at a relatively low position and the lower semiconductor pad 555 of the semiconductor chip located at a relatively high position may contact and couple with each other. Therefore, since the upper semiconductor insulating layer 590 and the lower semiconductor insulating layer 550 contact and couple with each other and the upper semiconductor pad 595 and the lower semiconductor pad 555 contact and couple with each other, the semiconductor chips 500 can be stacked in sequence.

[0141] The lowermost semiconductor chip 500a among the lower semiconductor chips 500a, 500b, and 500c may be coupled while contacting the lower structure 100. For example, the lower semiconductor insulating layer 550 of the lowermost semiconductor chip 500a may contact the upper insulating layer 190 of the lower structure 100 to be coupled thereto, and the lower semiconductor pad 555 of the lowermost semiconductor chip 500a may contact the upper pad 195 of the lower structure 100 to be coupled thereto.

[0142] Fig.10 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment.

[0143] like Fig.10 As shown, the semiconductor package 1 e may include a substrate 10 , a lower structure 100 located on the substrate 10 , and a plurality of semiconductor chips 500 located on the lower structure 100 .

[0144] The semiconductor package 1e may further include a mold layer 610' covering the side 501s of the plurality of semiconductor chips 500 and a heat dissipation structure 620 covering the upper portion of the upper semiconductor chip 500d of the plurality of semiconductor chips 500 and the mold layer 610'. The heat dissipation structure 620 may include a heat dissipation plate 630 and an insulating heat conductive layer 625. The insulating heat conductive layer 625 may combine the heat dissipation plate 630 with the upper semiconductor chip 500d.

[0145] Fig.11 is a process flow chart showing an example of a method of forming a semiconductor package according to an exemplary embodiment, and Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D is a cross-sectional view illustrating an example of a method of forming a semiconductor package according to an exemplary embodiment.

[0146] Reference Fig.11 and Fig. 12AIn S10, a semiconductor wafer Wa having a chip area CA may be formed. The chip area CA of the semiconductor wafer Wa may include a lower insulating layer 250 and a lower pad 255. A protective layer 1100 covering the lower insulating layer 250 and the lower pad 255 may be formed on the semiconductor wafer Wa.

[0147] The semiconductor wafer Wa may be bonded to the carrier substrate 1000 through the adhesive layer 1010 on the carrier substrate 1000 .

[0148] Reference Fig.11 and Fig. 12B In S20, a trench 1200 may be formed in the semiconductor wafer Wa between the chip areas CA. The trench 1200 may penetrate the lower insulating layer 250 and extend into the semiconductor wafer Wa. The trench 1200 may be formed using a laser or using a blade having a relatively large width.

[0149] Reference Fig.11 , Fig. 12C and Fig.12D , the semiconductor wafer Wa may be cut along the central portion of the trench 1200 to form the semiconductor chip 200 in S30 . Cutting the semiconductor wafer Wa may include performing a sawing process 1300 .

[0150] The protective layer 1100 remaining on the semiconductor chip 200 may be removed. The semiconductor chip 200 may be separated from the adhesive layer 1010 of the carrier substrate 1000. Then, the separated semiconductor chip 200 may be bonded to a base wafer Wb in S40.

[0151] The base wafer Wb may include an upper insulating layer 190 and upper pads 195. The lower insulating layer 250 of the semiconductor chip 200 may contact and be coupled to the upper insulating layer 190, and the lower pads 255 of the semiconductor chip 200 may contact and be coupled to the upper pads 195.

[0152] The bonding of the semiconductor chip 200 to the substrate wafer Wb may be performed by positioning the semiconductor chip 200 on the substrate wafer Wb and bonding the upper pad 195 of the substrate wafer Wb and the lower pad 255 of the semiconductor chip 200 to each other. Bonding the semiconductor chip 200 to the substrate wafer Wb may include applying pressure to the semiconductor chip 200 in a temperature atmosphere higher than room temperature. For example, the temperature atmosphere may be a hot atmosphere of about 200° C. to about 300° C. The temperature of the hot atmosphere is not limited to about 200° C. to about 300° C., and may be variously changed according to various exemplary embodiments.

[0153] Reference Fig.11, the base wafer Wb may be cut along the space between the semiconductor chips 200 in S50. The method may further include forming a mold layer 310 covering the semiconductor chips 200 before cutting the base wafer Wb. Therefore, the mold layer 310 may also be cut while cutting the base wafer Wb. The cut portion of the base wafer Wb may be mounted on the lower structure 100 in S60. Therefore, the above reference may be formed. Figure 1 The semiconductor package 1a.

[0154] According to an exemplary embodiment, the lower structure 100 may be provided as a lower chip located at a relatively low position, and the semiconductor chip 200 may be provided as an upper chip located at a relatively high position. Therefore, a semiconductor package including the lower chip 100 and the upper chip 200 may be provided. The lower chip 100 and the upper chip 200 may be coupled to each other through the pads 195 and 255 and the insulating layers 190 and 250. The pad 195 and the pad 255 may be in direct contact with each other. The insulating layer 190 and the insulating layer 250 may be in direct contact with each other.

[0155] The semiconductor package according to the exemplary embodiment includes the above-described lower chip 100 and upper chip 200 , and thus may have a reduced thickness.

[0156] According to an exemplary embodiment, the upper chip 200 located at a relatively high position may include a concave side portion 201s2. For example, a semiconductor wafer Wa is formed, a groove 1200 is formed in one side of the semiconductor wafer Wa, and a sawing process 1300 for cutting a central portion of the groove 1200 is performed, thereby forming a semiconductor chip, in detail, the upper chip 200. A portion of the upper chip 200 may remain to form the concave side portion 201s2 of the upper chip 200 where the groove 1200 is formed. The concave side portion 201s2 of the upper chip 200 may significantly reduce or prevent contamination of the upper chip 200 due to particles generated during the sawing process 1300. Therefore, defects occurring in a process in which the upper chip 200 having a concave side directly contacts and couples to a lower structure (e.g., the lower chip 100) located at a relatively low position may be significantly reduced or prevented.

[0157] As described above, according to an exemplary embodiment, a semiconductor package including pads that are in direct contact with each other and coupled to each other and insulating layers that are in direct contact with each other and coupled to each other can be provided. Therefore, the pad and the insulating layer can combine a chip, or a semiconductor chip and an interposer can be combined. The chip or the chip and the interposer can be coupled to each other using the pad and the insulating layer, thereby reducing the thickness of the semiconductor package.

[0158] According to an exemplary embodiment, between chips directly coupled to each other, an upper chip located at a relatively high position may include a concave side portion. The upper chip having the concave side portion can significantly reduce or prevent defects occurring in a process of forming a semiconductor package including a lower chip and an upper chip in direct contact with each other.

[0159] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor package, comprising: A lower structure, including an upper insulating layer and an upper pad; A semiconductor chip is disposed on the lower structure and includes a lower insulating layer and a lower pad; as well as a molding layer disposed on the lower structure, wherein the lower insulating layer contacts the upper insulating layer and is coupled to the upper insulating layer, and the lower pad contacts the upper pad and is coupled to the upper pad, wherein the side of the semiconductor chip extends between the upper side and the lower side of the semiconductor chip and comprises a concave portion and an upper vertical portion extending from the upper side to the concave portion along a first direction perpendicular to the upper side, wherein the concave portion includes a lower vertical portion extending from the edge of the lower side of the semiconductor chip along the first direction, a first curved portion extending from the lower vertical portion, and a second curved portion extending from the first curved portion to the upper vertical portion and different from the first curved portion, wherein the molding layer covers the entire side of the semiconductor chip, and A first portion of the upper insulating layer contacts the lower insulating layer, and a second portion of the upper insulating layer contacts the mold layer. 2 . The semiconductor package according to claim 1 , wherein the lower structure is wider than the semiconductor chip. 3 . The semiconductor package according to claim 1 , wherein the semiconductor chip further comprises a semiconductor body and a semiconductor internal circuit region interposed between the semiconductor body and both the lower insulating layer and the lower pad. 4 . The semiconductor package according to claim 3 , wherein the semiconductor internal circuit region is narrower than the upper side of the semiconductor chip. 5 . The semiconductor package according to claim 1 , wherein the lower structure further comprises a lower body and a lower internal circuit region interposed between the lower body and both the upper insulating layer and the upper pad. 6 . The semiconductor package according to claim 1 , wherein the lower structure further comprises a lower body and a lower internal circuit region, wherein the lower body is interposed between the lower internal circuit region and both the upper insulating layer and the upper pad.

7. The semiconductor package according to claim 1, wherein the lower structure further comprises a lower body and a through electrode, and The penetrating electrode is electrically connected to the upper pad and penetrates the lower body. The semiconductor package according to claim 7 , wherein the lower body comprises a silicon substrate. 9 . The semiconductor package according to claim 1 , further comprising a heat dissipation structure disposed on the molding layer and the semiconductor chip.

10. A semiconductor package, comprising: Lower structure; a semiconductor chip disposed on the lower structure and having an upper side and a lower side opposite to the upper side; as well as a molding layer disposed on the lower structure, The lower structure includes an upper pad and an upper insulating layer, wherein the semiconductor chip comprises a lower pad and a lower insulating layer disposed at the lower side of the semiconductor chip, wherein the lower pad contacts the upper pad and is coupled to the upper pad, wherein the lower insulating layer contacts the upper insulating layer and is coupled to the upper insulating layer, wherein the lower side of the semiconductor chip is narrower than the upper side of the semiconductor chip, wherein the side of the semiconductor chip extends between the upper side and the lower side of the semiconductor chip and comprises a concave portion and an upper vertical portion extending from the upper side to the concave portion along a first direction perpendicular to the upper side, wherein the concave portion includes a lower vertical portion extending from the edge of the lower side of the semiconductor chip along the first direction, a first curved portion extending from the lower vertical portion, and a second curved portion extending from the first curved portion to the upper vertical portion and different from the first curved portion, wherein the molding layer covers the entire side of the semiconductor chip extending between the upper side and the lower side, and A first portion of the upper insulating layer contacts the lower insulating layer, and a second portion of the upper insulating layer contacts the mold layer. The semiconductor package of claim 10 , wherein the lower structure is an interposer. 12 . The semiconductor package according to claim 10 , wherein the lower structure is another semiconductor chip different from the semiconductor chip.

13. A semiconductor package, comprising: Lower structure; as well as A plurality of semiconductor chips are disposed on the lower structure; as well as a molding layer disposed on the lower structure, The plurality of semiconductor chips include a first semiconductor chip and a second semiconductor chip that are in direct contact with each other, wherein the first semiconductor chip has a first upper side and a first lower side opposite to the first upper side, wherein the second semiconductor chip has a second upper side and a second lower side opposite to the second upper side, wherein the first semiconductor chip comprises an upper insulating layer and an upper pad disposed at the first upper side of the first semiconductor chip, wherein the second semiconductor chip comprises a lower insulating layer and a lower pad disposed at the second lower side of the second semiconductor chip, wherein the lower insulating layer and the upper insulating layer are in contact with each other and coupled to each other, wherein the lower pad and the upper pad are in contact with each other and coupled to each other, wherein the second lower side of the second semiconductor chip is narrower than the second upper side of the second semiconductor chip, wherein the side of the second semiconductor chip extends between the second upper side and the second lower side of the second semiconductor chip and comprises a concave portion and an upper vertical portion extending from the second upper side to the concave portion along a first direction perpendicular to the second upper side, wherein the concave portion includes a lower vertical portion extending from an edge of the second lower side of the second semiconductor chip along the first direction, a first curved portion extending from the lower vertical portion, and a second curved portion extending from the first curved portion to the upper vertical portion and different from the first curved portion, wherein the molding layer covers the entire side of the second semiconductor chip extending between the second upper side and the second lower side, and A first portion of the upper insulating layer contacts the lower insulating layer, and a second portion of the upper insulating layer contacts the mold layer. 14 . The semiconductor package according to claim 13 , wherein the second lower side of the second semiconductor chip is narrower than the first upper side of the first semiconductor chip.

15. The semiconductor package according to claim 14, wherein the first lower side of the first semiconductor chip and the second lower side of the second semiconductor chip have the same width, and The first upper side of the first semiconductor chip and the second upper side of the second semiconductor chip have the same width.

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