Semiconductor chip including alignment pattern

Abstract

A semiconductor chip including an alignment pattern is provided. The semiconductor chip includes a substrate, the substrate is associated with a main chip area of ​​a semiconductor wafer and includes a scribe line. A lower interlayer insulating layer is disposed on the substrate, a low-K layer including a dummy metal pattern is disposed on the lower interlayer insulating layer, an alignment pattern is disposed on the low-K layer, and a passivation layer covers the alignment pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of Korean Patent Application No. 10-2018-0126940 filed on October 23, 2018 in the Korean Intellectual Property Office (KIPO), the subject matter of which is incorporated herein by reference in its entirety. Technical Field

[0003] A device consistent with the exemplary embodiment relates to a semiconductor chip (hereinafter referred to as a “chip”) including an alignment pattern separated from a semiconductor wafer. A method consistent with the exemplary embodiment relates to separating the chip from the semiconductor wafer. Background Art

[0004] Many modern semiconductor devices include multiple patterns that are stacked vertically on top of each other and electrically connected to each other. During the stacking process, these stacked patterns must be accurately aligned. Therefore, an alignment key pattern (i.e., alignment mark) can be provided as a reference to correctly align the stacked patterns. The alignment key pattern can be formed in a scribe line arranged between chip areas, where the circuit pattern is mainly arranged in these chip areas in the wafer. The alignment key pattern can be formed in the process of forming the circuit pattern in the corresponding main chip area of ​​the semiconductor wafer.

[0005] The main chip regions of the semiconductor wafer may be separated from each other using a separation process (e.g., a sawing, cutting, and / or etching process) that divides adjacent main chip regions along a scribe line. In the separation process, a peeling phenomenon may occur due to an alignment key pattern provided in the scribe line. As a result, the quality of the product may be reduced. Summary of the invention

[0006] Embodiments of the inventive concept are directed to semiconductor chips respectively associated with main chip regions, which include a scribe street structure capable of preventing an oxide layer from being peeled off or not separated during a separation process.

[0007] In one embodiment, a semiconductor chip includes: a substrate, which is associated with a main chip area of ​​a semiconductor wafer and includes a scribe line; a lower interlayer insulating layer, which is arranged on the substrate; a low-K layer, which includes a dummy metal pattern arranged on the lower interlayer insulating layer; an alignment pattern, which is arranged on the low-K layer; and a passivation layer, which at least partially covers the alignment pattern.

[0008] In another embodiment, a semiconductor chip includes: a substrate, which is associated with a main chip area of ​​a semiconductor wafer and includes a scribe line surrounding the main chip area; a lower interlayer insulating layer, which is arranged on the substrate; an alignment key structure, which includes a low-K layer arranged on the lower interlayer insulating layer in the scribe line, an upper alignment pattern arranged on the low-K layer, and a passivation layer arranged on the upper alignment pattern; and a dummy pattern structure, which includes: a low-K pattern arranged on the lower interlayer insulating layer; and a lower dummy pattern arranged in the low-K pattern and arranged on at least one side surface of the alignment key structure.

[0009] In another embodiment, a semiconductor chip includes: a substrate, which is associated with a main chip area of ​​a semiconductor wafer and includes a scribe line; a low-K layer, which is configured to extend on the substrate along the scribe line; a lower dummy pattern, which is arranged in the low-K layer; a passivation layer, which is arranged on the low-K layer; an alignment pattern, which is arranged in the passivation layer; and an opening area, in which the low-K layer and the passivation layer are partially removed, wherein the lower dummy pattern and the alignment pattern are spaced apart from each other in the length direction of the scribe line. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a perspective view illustrating a semiconductor wafer according to an embodiment of the inventive concept.

[0011] Figure 2 yes Figure 1 Magnified view of area A shown in FIG.

[0012] Figure 3 is along Figure 2 A vertical cross-sectional view taken along line II' in FIG.

[0013] Figure 4 is along Figure 2 A vertical cross-sectional view taken along line II-II'.

[0014] Figure 5 is along Figure 2 A vertical cross-sectional view taken along line III-III'.

[0015] Figure 6 is along Figure 2 A vertical cross-sectional view taken along line IV-IV'.

[0016] Figure 7 yes Figure 1 Another enlarged view of area A in FIG.

[0017] Figure 8is along Figure 7 A vertical cross-sectional view taken along line V-V' in FIG.

[0018] Fig. 9 is to Figure 2 A vertical cross-sectional view of the separated semiconductor chips taken along the line II-II' when the semiconductor wafer is separated along the line II'.

[0019] Fig.10 is to Figure 2 A vertical cross-sectional view of the separated semiconductor chips taken along line III-III' in the case where the semiconductor wafer is separated along line II'.

[0020] Fig.11 is to Figure 2 A vertical cross-sectional view of a separated semiconductor chip taken along line IV-IV' when the semiconductor wafer is separated along line II'.

[0021] Fig.12 According to an embodiment Figure 1 Another enlarged view of area A in FIG.

[0022] Fig.13 is along Fig.12 A vertical cross-sectional view taken along line VI-VI'.

[0023] Fig.14 , Fig.15 , Fig.16 , Fig.17 It is shown that manufacturing has Figure 3 A corresponding cross-sectional view of the method of a semiconductor wafer in cross section is shown in FIG.

[0024] Fig.18 A portion of a separation process for singulating semiconductor chips from a semiconductor wafer is illustrated in a conceptual diagrammatic sequence. DETAILED DESCRIPTION

[0025] In the following description, the same reference numerals associated with the drawings denote the same or similar elements.

[0026] Figure 1 is a perspective view illustrating a semiconductor wafer 100 according to an embodiment of the inventive concept.

[0027] Reference Figure 1, the semiconductor wafer 100 may include a plurality of main chip regions (e.g., a matrix arrangement of the main chip regions across the main surface of the semiconductor wafer 100 along the first direction and the second direction). Each main chip region may include one or more semiconductor elements, components, circuits, and / or related connections sufficient to provide the intended function or purpose. Hereinafter, for the sake of brevity, any reasonable combination of semiconductor elements, components, circuits, and / or related connections will be referred to as a "circuit pattern".

[0028] Figure 1 The plurality of master chip regions shown in the figure include a first master chip region 110 and an adjacent second master chip region 120. In the following, it is assumed that the first master chip region 110 and the second master chip region 120 respectively include complete circuit patterns. All master chip regions (including the first master chip region 110 and the second master chip region 120) manufactured on the semiconductor wafer 100 may be substantially similar. That is, each master chip region may include substantially similar circuit patterns, such as a dynamic random access memory (DRAM) or a phase change RAM (PRAM).

[0029] The individual master chip regions can be fabricated in any reasonable size and shape on semiconductor wafer 100. For example, assuming Figure 1 The first master chip region 110 and the second master chip region 120 in FIG. 1 each have a quadrilateral shape and substantially similar sizes, but this need not be the case in other embodiments.

[0030] Also like Figure 1 As shown in , one or more scribe lanes SL can be used to geometrically define each master chip region (e.g., first master chip region 110) in its expected shape, size, and proximity to adjacent master chip regions. Recognizing that various scribe lanes of different complexity and / or geometric relationships can be used to define master chip regions, one or more scribe lanes shown in the following example embodiments will be referred to simply as "scribe lanes."

[0031] exist Figure 1 In the embodiment of the present invention, the scribe line SL may be understood as “separating” the first master chip region 110 from the second master chip region 120 (eg, being disposed between the first master chip region 110 and the second master chip region 120). Alternatively or additionally, Figure 1 The scribe lines SL in the diagram may be understood as individually or collectively “surrounding” the first master chip region 110 and the second master chip region 120. Therefore, it can be said that the first master chip region 110 and the second master chip region 120 are “spaced apart” from each other by the scribe lines SL.

[0032] The scribe lane SL may be variously defined in its geometry (e.g., width and length) according to one or more purposes. For example, the scribe lane SL may be used to define a "separation space" with which or according to which adjacent main chip regions may be physically separated into corresponding semiconductor chips 200. Alternatively or additionally, the scribe lane SL may include a process pattern or a test pattern.

[0033] Refer again Figure 1 , one or more processes (including, for example, physical segmentation, mechanical sawing, laser cutting, plasma etching, etc.) can be used to separate the main chip area of ​​the semiconductor wafer 100 into corresponding semiconductor chips 200. Hereinafter, the term "separation process" will be used to refer to one or more processes and techniques that can be used to separate the main chip area from the semiconductor wafer 100 to produce the semiconductor chips 200, regardless of their specific nature. Since various types and combinations of material layers can be used to manufacture the semiconductor wafer 100, the separation process can be changed accordingly.

[0034] In this regard and assuming that a mechanical saw or a laser saw is used for the separation process, the scribe line SL may include a sawing line or a sawing scribe line (see, e.g. Figure 1 ). Accordingly, in some embodiments, the scribe lanes SL may be disposed on or around the edge of the semiconductor chip 200. The scribe lanes SL may define the position of the resulting sidewalls of the semiconductor chip 200.

[0035] Figure 2 yes Figure 1 an enlarged plan view of the area "A" identified therein; Figure 3 is along Figure 2 A vertical cross-sectional view taken along line II' in FIG. Figure 4 is along Figure 2 A vertical cross-sectional view taken along line II-II'; Figure 5 is along Figure 2 A vertical cross-sectional view taken along line III-III'; Figure 6 is along Figure 2 A vertical cross-sectional view taken along line IV-IV'.

[0036] Collectively refer to Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6, region A of the semiconductor wafer 100 also shows a scribe line SL disposed between the first main chip region 110 and the second main chip region 120. Here, the width of the scribe line SL may be defined by a wrapping layer 90 disposed on respective edges of the first main chip region 110 and the second main chip region 120. The wrapping layer 90 may be disposed on respective top outer edge surface portions of the first main chip region 110 and the second main chip region 120. Thus, the wrapping layer 90 may be used to cover and protect a portion of a circuit pattern located near respective outer edges of the first main chip region 110 and the second main chip region 120, respectively. In this way, the wrapping layer 90 may also stably isolate the resulting semiconductor chip 200 (after segmentation), thereby protecting the semiconductor chip 200 from physical, chemical, and / or electrical damage.

[0037] In certain embodiments, the encapsulation layer 90 may include photosensitive polyimide (PSPI).

[0038] The divided portion of the semiconductor wafer 100 may form (or be used as) a substrate 10 associated with a specific semiconductor chip 200. That is, the substrate "associated with the main chip region" of the semiconductor wafer 100 may be understood as a component of the corresponding semiconductor chip 200. Therefore, the portion of the substrate 10 associated with (or including) the scribe line SL may include the alignment key region AKP, the dummy pad region DPR, and / or the opening region OPR.

[0039] For example, a lower interlayer insulating layer 20 may be provided on the substrate 10. The lower interlayer insulating layer 20 may include an oxide (eg, tetraethyl orthosilicate (TEOS)) or a high density plasma (HDP). Although not shown in the embodiment, transistors may be formed on the substrate 10, and the lower interlayer insulating layer 20 may include a lower interconnect layer electrically connected to the transistors.

[0040] The align key region AKP may be disposed between the dummy pad regions DPR in a first direction (eg, a length direction) of the scribe streets SL. The align key region AKP may be disposed between the package layers 90 in a second direction substantially perpendicular to the first direction.

[0041] In this regard, although Figure 3A case is shown in which the boundary of the alignment key area AKP is spaced apart from one side surface of the alignment pattern AP, but alternatively, the boundary of the alignment key area AKP may be aligned with the outer side wall of the alignment pattern AP. An alignment key structure AKS may be provided in the alignment key area AKP. The alignment key structure AKS may completely cover the alignment key area AKP within the scribe line defined with respect to the scribe line SL. When viewed from above, the upper and lower ends of one side surface of the alignment key structure AKS may be elongated in a first direction and extend to the dummy pad area DPR and the opening area OPR. In addition, the upper and lower ends of the other side surface of the alignment key structure AKS may be elongated in a direction opposite to the first direction and extend to the dummy pad area DPR and the opening area OPR.

[0042] In some embodiments, the alignment key structure AKS may include a low-K layer 30 , an upper interlayer insulating layer 40 , a passivation layer, and an alignment pattern AP. The passivation layer may include a first insulating layer 50 , a second insulating layer 60 , and a third insulating layer 70 .

[0043] The low-K layer 30 may include at least one low-K material. The low-K layer 30 may have a lower dielectric constant relative to silicon oxide (e.g., the low-K layer 30 may have a dielectric constant less than 3.9). For example, the low-K layer 30 may include a silicon oxide-based material doped with impurities, a porous silicon oxide, or an organic polymer. For example, the silicon oxide-based material doped with impurities may include a fluorine-doped silicon oxide film (or fluorosilicate glass (FSG)), a carbon-doped silicon oxide film, a silicon oxide film, hydrogen silsesquioxane (HSQ; SiO:H), methyl silsesquioxane (MSQ; SiO:CH3), or amorphous carbon silicon oxide (a-SiOC) (or SiOC:H). The organic polymer may include a polyallyl ether resin, a cyclic fluorine resin, a siloxane copolymer, a polyallyl ether fluoride-based resin, a poly(pentafluorostyrene), a polytetrafluorostyrene-based resin, a polyimide fluoride resin, a polynaphthalene fluoride, or a polyamide resin.

[0044] The upper interlayer insulating layer 40, the first insulating layer 50, and the third insulating layer 70 may include oxide or HDP, and the second insulating layer 60 may include nitride. For example, the upper interlayer insulating layer 40 and the third insulating layer 70 may include TEOS, the first insulating layer 50 may include HDP, and the second insulating layer 60 may include silicon nitride (SiN). However, various materials may be used alternatively or additionally.

[0045] In some embodiments, the alignment pattern AP may include an upper alignment pattern APa and a lower alignment pattern APb. The upper alignment pattern APa may be disposed on the upper interlayer insulating layer 40. For example, the upper alignment pattern APa may include a plurality of strip-shaped metal patterns disposed parallel to each other. However, the shape of the upper alignment pattern APa may vary depending on the design and may include discernible pattern shapes differently. The upper alignment pattern APa may include one or more conductive materials, such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), and / or combinations thereof.

[0046] The lower alignment pattern APb may variously penetrate the upper interlayer insulating layer 40. When viewed from above, the upper alignment pattern APa may overlap at least a portion of the lower alignment pattern APb so that an upper end of the lower alignment pattern APb may contact a lower end of the upper alignment pattern APa. The lower alignment pattern APb may be formed of the same or different materials as the upper alignment pattern APa.

[0047] The dummy pad region DPR may be disposed on each side of the alignment key region AKP, wherein the dummy pattern structure DPS may be disposed in the dummy pad region DPR. The dummy pattern structure DPS may be disposed in contact with the side surface of the alignment key structure AKS. The dummy pattern structure DPS may include, for example, a low-K layer 30, an upper interlayer insulating layer 40, a passivation layer, and dummy patterns 35, 45, and 55.

[0048] In some embodiments, the dummy patterns 35, 45 and 55 may include a lower dummy pattern 35 and upper dummy patterns 45 and 55. In some embodiments, the lower dummy pattern 35 may be disposed in the low-K layer 30, and may include a first lower dummy pattern 35a and a second lower dummy pattern 35b. The first lower dummy pattern 35a and the second lower dummy pattern 35b may have different or identical widths. The first lower dummy pattern 35a and the second lower dummy pattern 35b may be stacked alternately and repeatedly. The upper end of the uppermost one of the first lower dummy pattern 35a and the second lower dummy pattern 35b may be substantially at the same level as the upper end of the low-K layer 30. Here again, the first lower dummy pattern 35a and / or the second lower dummy pattern 35b may include at least one conductive material, such as copper, aluminum, tungsten, titanium and / or a combination thereof. The first lower dummy pattern 35a and the second lower dummy pattern 35b may be formed of the same or different materials.

[0049] The upper dummy patterns 45 and 55 may be disposed on the low-K layer 30. The upper dummy patterns 45 and 55 may be disposed at positions corresponding to the lower dummy patterns 35 in a cross-sectional view thereof. The upper dummy patterns 45 and 55 may include at least one conductive material, such as copper, aluminum, tungsten, titanium, and / or a combination thereof. The upper dummy patterns 45 and 55 and the lower dummy pattern 35 may be formed of the same or different materials.

[0050] The upper dummy patterns 45 and 55 may include a first upper dummy pattern 45 and a second upper dummy pattern 55. The first upper dummy pattern 45 may penetrate the upper interlayer insulating layer 40 so that the lower end of the first upper dummy pattern 45 contacts the upper end of the lower dummy pattern 35. The second upper dummy pattern 55 disposed on the upper interlayer insulating layer 40 may be disposed on the first upper dummy pattern 45. The lower end of the second upper dummy pattern 55 may be disposed to contact the upper end of the first upper dummy pattern 45. The first upper dummy pattern 45 and the second upper dummy pattern 55 may be formed of the same or different materials.

[0051] For a semiconductor chip including a structure like the lower dummy pattern 35 disposed in the low-K layer 30, vertical progress of material cracking associated with the substrate 10 may be promoted during a separation process for dividing the individual semiconductor chips 200 from the semiconductor wafer 100. Therefore, when the dummy pattern structure DPS including the lower dummy pattern 35 is disposed on both sides of the alignment key structure AKS, adjacent semiconductor chips 200 may be clearly separated without causing peeling of the alignment key structure AKS.

[0052] In one embodiment, the shortest distance between one sidewall of the lower dummy pattern 35 and the sidewall of the alignment key structure AKS in the first direction may be 8µm or less (i.e., not greater than 8µm). For example, when viewed from above, the distance between one sidewall of the second lower dummy pattern 35b disposed closest to the alignment key region AKP and the sidewall of the upper alignment pattern APa may be not greater than 8µm. However, when the distance between the lower dummy pattern 35 and the alignment key structure AKS exceeds 8µm, during the separation process for producing the individual semiconductor chips 200 from the semiconductor wafer 100, the vertical progression of the crack due to the dummy pattern may not adversely affect the alignment key structure AKS.

[0053] Figure 7 yes Figure 1 Another enlarged view of area A in Figure 2 For comparison, Figure 8 is along Figure 7 A vertical cross-sectional view taken along line V-V' in FIG.

[0054] Reference Figure 7 and Figure 8 And compare Figure 2 and Figure 3 It should be noted that in Figure 7 and Figure 8There are no dummy pattern structures DPS on both sides of the alignment key structure AKS. Therefore, during certain separation processes (e.g., back grinding of the semiconductor wafer 100), the possibility of material cracking associated with the substrate 10 occurring in the vertical direction is significantly lower, but may occur in the lateral direction. As a result, the insulating layer included in the alignment key structure AKS may not be clearly separated along the dicing streets (e.g., saw streets), but may be torn due to the peeling phenomenon.

[0055] Now refer to Figure 2 , Figure 3 and Figure 6 The opening region OPR may be disposed adjacent to the dummy pad region DPR. The opening region OPR may expose the sidewall of the dummy pattern structure DPS and the top surface of the lower interlayer insulating layer 20. In addition, the opening region OPR may also expose the sidewall of the align key structure AKS that may be elongated in the first direction.

[0056] Fig. 9 is to Figure 1 and Figure 2 A vertical cross-sectional view of the separated semiconductor chip taken along line II-II' when the semiconductor wafer 100 is separated along line II'. Similarly, Fig.10 is a vertical cross-sectional view taken along line III-III', Fig.11 It is a vertical cross-sectional view taken along line IV-IV'.

[0057] Reference Figure 1 , Figure 2 and Figure 3 , the semiconductor chips 200 separated from the semiconductor wafer 100 may have a four-sided, quadrangular shape and thus will have four exposed side surfaces. In some embodiments, at least one of the four exposed side surfaces of the separated semiconductor chips 200 may include Figure 3 For example, when the line I-I' (i.e., along Figure 2 When the semiconductor wafer 100 is subjected to a separation process by using the scribe line SL shown in FIG. 1 , one side surface of the separated semiconductor chip 200 may correspond to Figure 3 The cross section shown in .

[0058] Reference Figure 1 , Figure 2 and Fig. 9 , a side surface of the alignment pattern AP may be exposed through at least a portion of a side surface of the semiconductor chip 200. For example, a side surface of at least one of the upper alignment pattern APa and the lower alignment pattern APb of the alignment pattern AP may be exposed through one side surface of the semiconductor chip 200.

[0059] Reference Figure 1 , Figure 2 and Fig.10 , a side surface of at least one of the lower dummy pattern 35 and the upper dummy patterns 45 and 55 may be exposed through at least one side surface of the semiconductor chip 200. For example, a side surface of at least one of the first lower dummy pattern 35a and the second lower dummy pattern 35b of the lower dummy pattern 35 may be exposed through one side surface of the semiconductor chip 200. A side surface of at least one of the first upper dummy pattern 45 and the second upper dummy pattern 55 of the upper dummy patterns 45 and 55 may be exposed through one side surface of the semiconductor chip 200.

[0060] Reference Figure 1 , Figure 2 and Fig.11 , a step structure may be formed on one side surface of the semiconductor chip 200 to expose the top surface of the lower interlayer insulating layer 20 .

[0061] Fig.12 yes Figure 1 Another enlarged view of area A in Fig.13 is along Fig.12 A vertical cross-sectional view taken along line VI-VI'.

[0062] Reference Fig.12 and Fig.13 , the dummy pattern structures DPS can be respectively arranged on both sides of the alignment key structure AKS. Fig.13 , the alignment pattern AP may be completely covered by the first insulating layer 50, but the inventive concept is not limited thereto, and the sidewall of the alignment pattern AP may be exposed. The dummy pattern structure DPS may be disposed to be spaced apart from the alignment key structure AKS. The first opening portion OP1 may be disposed on one side of the dummy pattern structure DPS, and the second opening portion OP2 may be disposed on the other side of the dummy pattern structure DPS. The second opening portion OP2 may be formed between the dummy pattern structure DPS and the alignment key structure AKS. The first opening portion OP1 and the second opening portion OP2 may expose the top surface of the lower interlayer insulating layer 20 and the sidewall of the dummy pattern structure DPS. When the second opening portion OP2 is formed between the dummy pattern structure DPS and the alignment key structure AKS, the distance W1 between one sidewall of the lower dummy pattern 35 and one sidewall of the alignment key structure AKS in the first direction may be no greater than 8µm. When the distance W1 between the lower dummy pattern 35 and the alignment key structure AKS exceeds 8µm, the vertical progression of the cracking caused by the dummy pattern during the separation process needs not to adversely affect the alignment key structure AKS.

[0063] Fig.14 , Fig.15 , Fig.16 , Fig.17 These cross-sectional views further describe the manufacturing process. Figure 3 A cross-section of a semiconductor wafer is shown in the method.

[0064] Reference Fig.14 , a transistor (not shown), a lower interconnection (not shown), and a lower interlayer insulating layer 20 may be formed on the substrate 10. The substrate 10 may be Figure 1 The transistor may include a metal oxide semiconductor field effect transistor (MOSFET). The lower interlayer insulating layer 20 may include silicon oxide.

[0065] A low-K layer 31 may be formed on the lower interlayer insulating layer 20. The low-K layer 31 and the intermetallic dielectric layer (IML) 32 including different materials may be alternately and repeatedly stacked. For example, the low-K layer 31 may include a low-K dielectric, an ultra-low-K dielectric, silicon nitride (SiN), and / or a combination thereof. The IML 32 may include silicon carbonitride (SiCN). An insulating layer 33 having a small thickness and including silicon nitride (SiN) may be disposed on the uppermost IML 32. A lower dummy pattern 35 may be formed during the formation of the low-K layer 31 and the IML 32. Although not shown, a metal pattern electrically connected to the transistor and the lower interconnect may be formed together in the low-K layer 31.

[0066] Reference Fig.15 , an upper interlayer insulating layer 40 may be formed on the insulating layer 33. A first upper dummy pattern 45 may be formed in the upper interlayer insulating layer 40, and a second upper dummy pattern 55 may be formed on the upper interlayer insulating layer 40. A lower end of the first upper dummy pattern 45 may contact the insulating layer 33. Alternatively, the first upper dummy pattern 45 may penetrate the insulating layer 33 so that a lower end of the first upper dummy pattern 45 may contact an upper end of the lower dummy pattern 35.

[0067] Reference Fig.16 , a passivation layer may be formed. The passivation layer may include a first insulating layer 50, a second insulating layer 60, and a third insulating layer 70 sequentially stacked on the upper interlayer insulating layer 40. The first insulating layer 50 may cover the second upper dummy pattern 55 on the upper interlayer insulating layer 40. As an example, the first insulating layer 50 and the third insulating layer 70 may include oxide, and the second insulating layer 60 may include nitride.

[0068] Reference Figure 3 and Fig.17, a mask pattern 80 may be formed on the third insulating layer 70, and the passivation layer, the upper interlayer insulating layer 40, the low-K layer 31, the IML 32, and the insulating layer 33 may be partially removed by an etching process using the mask pattern 80 as an etching mask. The upper interlayer insulating layer 40 and the low-K layer 31 may be etched to form a stacked structure. That is, the alignment key structure AKS may be integrally formed with the dummy pattern structure DPS to form a stacked structure. Then, the mask pattern 80 may be removed.

[0069] Fig.18 Aspects of the foregoing are further described in a conceptual diagram sequence. Fig.18 , a laser beam of a limited wavelength with a transmittance to the semiconductor wafer can be projected to form a crack in the wafer substrate. Thereafter, during the back grinding of the semiconductor wafer, due to the pressure generated in the back grinding process, the crack may progress vertically toward the front surface of the wafer-this may be part of the separation process for dividing the semiconductor chip 200 from the semiconductor wafer 100. In this case, according to an embodiment of the present inventive concept, a dummy pattern can be set on both sides of the alignment key structure including the low-K layer. Therefore, cracks in the lateral direction caused by the low-K layer can be prevented.

[0070] According to certain embodiments of the present invention, when a semiconductor wafer including a low-K material is separated along a scribe line SL using, for example, laser cutting, peeling phenomenon in which an alignment key or an insulating layer covering the alignment key is torn can be prevented, and the resulting semiconductor chips can be cleanly and clearly separated from each other.

[0071] Although the embodiments of the present invention have been described with reference to the accompanying drawings, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention and without changing its basic features. Therefore, the above embodiments should be considered to be merely illustrative and not for the purpose of limitation.

Claims

1. A semiconductor chip, comprising: a substrate associated with the main chip region of the semiconductor wafer and including scribe lines; a lower interlayer insulating layer, the lower interlayer insulating layer being disposed on the substrate; a low-K layer, the low-K layer comprising a dummy metal pattern disposed on the lower interlayer insulating layer; an alignment pattern, wherein the alignment pattern is disposed on the low-K layer; as well as a passivation layer, the passivation layer at least partially covering the alignment pattern, The dummy metal pattern and the alignment pattern are spaced apart from each other in a length direction of the scribe line.

2. The semiconductor chip according to claim 1, wherein: The alignment pattern is disposed between the dummy metal patterns in a length direction of the scribe line.

3. The semiconductor chip according to claim 2, wherein: The shortest distance between the dummy metal pattern and the alignment pattern is no more than 8 μm.

4. The semiconductor chip according to claim 1, wherein: The dummy metal pattern includes a first lower dummy pattern and a second lower dummy pattern, and The uppermost end of the dummy metal pattern and the uppermost end of the low-K layer are substantially at the same level.

5. The semiconductor chip according to claim 4, further comprising: an upper interlayer insulating layer, the upper interlayer insulating layer being disposed between the low-K layer and the passivation layer, The dummy metal pattern further includes a first upper dummy pattern, the first upper dummy pattern penetrates the upper interlayer insulating layer and contacts the uppermost ends of the first lower dummy pattern and the second lower dummy pattern.

6. The semiconductor chip according to claim 5, wherein: The dummy metal pattern further includes a second upper dummy pattern disposed on the upper interlayer insulating layer and having a lower end contacting the first upper dummy pattern.

7. The semiconductor chip according to claim 1, wherein: The scribing lanes include: an alignment key area, wherein the alignment pattern is arranged in the alignment key area; a dummy pad region, wherein the dummy metal pattern is disposed in the dummy pad region; and An opening region is configured to expose a top surface of the lower interlayer insulating layer and a side surface of the low-K layer.

8. The semiconductor chip according to claim 7, wherein: The opening area includes: a first opening region, the first opening region being formed at one side of each of the dummy metal patterns; and A second opening region is formed between the dummy metal pattern and the alignment pattern.

9. The semiconductor chip according to claim 1, wherein: The passivation layer comprises: a first insulating layer, the first insulating layer being in contact with the alignment pattern; a second insulating layer, the second insulating layer being disposed on the first insulating layer; and A third insulating layer is disposed on the second insulating layer.

10. The semiconductor chip according to claim 9, wherein: The first insulating layer and the third insulating layer include oxide, and the second insulating layer includes nitride.

11. A semiconductor chip, comprising: a substrate associated with a main chip region of the semiconductor wafer and including scribe lines surrounding the main chip region; a lower interlayer insulating layer, the lower interlayer insulating layer being disposed on the substrate; an alignment key structure, the alignment key structure comprising a low-K layer disposed on the lower interlayer insulating layer in the scribe line, an upper alignment pattern disposed on the low-K layer, and a passivation layer disposed on the upper alignment pattern; as well as a dummy pattern structure, the dummy pattern structure comprising: a low-K pattern disposed on the lower interlayer insulating layer; and a lower dummy pattern disposed in the low-K pattern and disposed on at least one side surface of the alignment key structure, Wherein, the alignment pattern is spaced apart from the lower dummy pattern in the length direction of the scribe line.

12. The semiconductor chip according to claim 11, wherein: One side surface of the align key structure and one side surface of the dummy pattern structure face each other in a length direction of the scribe line and contact each other.

13. The semiconductor chip according to claim 11, wherein: The alignment key structure is spaced apart from the dummy pattern structure in a length direction of the scribe line.

14. The semiconductor chip according to claim 11, wherein: The shortest distance between the lower dummy pattern and the alignment key structure is no greater than 8 μm.

15. The semiconductor chip according to claim 11, wherein: The dummy pattern structure further includes: an upper interlayer insulating pattern disposed on the low-K pattern; and A passivation pattern is disposed on the upper interlayer insulating pattern.

16. The semiconductor chip according to claim 15, wherein: The dummy pattern structure further includes: a first upper dummy pattern, the first upper dummy pattern penetrating the upper interlayer insulating pattern; and a second upper dummy pattern, wherein the second upper dummy pattern is disposed on the first upper dummy pattern, wherein the first upper dummy pattern contacts each of the lower dummy pattern and the second upper dummy pattern.

17. The semiconductor chip according to claim 11, wherein: The alignment key structure further comprises: an upper interlayer insulating layer, the upper interlayer insulating layer being disposed between the low-K layer and the passivation layer; and A lower alignment pattern is disposed in the upper interlayer insulating layer and contacts a lower end of the upper alignment pattern.

18. A semiconductor chip, comprising: a substrate associated with the main chip region of the semiconductor wafer and including scribe lines; a low-K layer configured to extend on the substrate along the scribe line; a lower dummy pattern, the lower dummy pattern being arranged in the low-K layer; a passivation layer, the passivation layer being disposed on the low-K layer; an alignment pattern, wherein the alignment pattern is disposed in the passivation layer; as well as an opening region, in which the low-K layer and the passivation layer are partially removed, The lower dummy pattern and the alignment pattern are spaced apart from each other in a length direction of the scribe line.

19. The semiconductor chip according to claim 18, wherein: The shortest distance between the lower dummy pattern and the alignment pattern is no more than 8 μm.

20. The semiconductor chip according to claim 18, wherein A lower end of the alignment pattern is at a higher level than a lower end of the lower dummy pattern.

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