Wafer stacking method and wafer stacking structure

Abstract

The present disclosure provides a wafer stacking method and structure. The wafer stacking method includes: providing a first wafer, the upper surface of the first wafer includes a first pad configured to connect to a first signal; sequentially making a first lower redistribution layer and a first upper redistribution layer on the first wafer, the first lower redistribution layer includes a first wiring connected to the first pad, the first upper redistribution layer includes a second wiring connected to the first wiring, and the second wiring has a first lead pad; bonding a second wafer to the first upper redistribution layer, the upper surface of the second wafer includes a second pad configured to connect to a second signal and corresponding to the position of the first pad; making a first through-silicon via with a bottom connected to the first lead pad at a position of the second wafer corresponding to the first lead pad. The wafer stacking method provided by the present disclosure can improve the manufacturing yield of chips with a stacked structure.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a wafer stacking method capable of improving the electrical connection effect between chips, and a wafer stacking structure and a chip stacking structure manufactured using the wafer stacking method. Background Art

[0002] In the process of integrated circuit manufacturing, stacking multiple chips and establishing mechanical and electrical connections is an important method to reduce the size of integrated circuits. Figure 1A and Figure 1B As shown, TSV (Through Silicon Vias) is usually made for each chip to be stacked, and then a micro-bump is formed for each TSV. Finally, the chips are positioned and bonded using a chip-to-chip or chip-to-wafer method, and the electrical connection between the upper chip and the lower chip is achieved using the bumps and TSV.

[0003] First, the chip-to-chip or chip-to-wafer bonding process is inefficient, leading to high costs. Furthermore, the need to pre-fabricate TSVs and bumps on each chip increases the risk of misalignment and connection errors during the bonding process, which can easily lead to a disconnection in the electrical connection between the upper and lower chips, resulting in a decrease in product yield.

[0004] Therefore, a chip stacking method that can overcome the above problems is needed.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0006] The purpose of the present disclosure is to provide a wafer stacking method and a wafer stacking structure, which are used to at least to some extent overcome the shortcomings of chip stacking such as high cost, high probability of connection errors, and low yield rate caused by the limitations and defects of related technologies.

[0007] According to a first aspect of the present disclosure, there is provided a wafer stacking method, comprising:

[0008] Providing a first wafer, wherein the upper surface of the first wafer includes a first pad configured to connect a first signal;

[0009] Sequentially forming a first lower redistribution layer and a first upper redistribution layer on the first wafer, wherein the first lower redistribution layer includes a first wiring connected to the first pad, and the first upper redistribution layer includes a second wiring connected to the first wiring, wherein the second wiring has a first lead pad;

[0010] Bonding a second wafer to the first upper redistribution layer, wherein the upper surface of the second wafer includes a second pad configured to connect to a second signal and located corresponding to the first pad;

[0011] A first through silicon via having a bottom connected to the first lead pad is formed on the second wafer at a position corresponding to the first lead pad.

[0012] In an exemplary embodiment of the present disclosure, the step of forming a first through silicon via having a bottom portion connected to the first lead pad includes:

[0013] forming a through hole at a position of the second wafer corresponding to the first lead pad, wherein the bottom of the through hole exposes the first lead pad;

[0014] The through hole is filled with a conductive material, wherein the conductive material includes metal.

[0015] In an exemplary embodiment of the present disclosure, during the process of forming the through hole, a groove for forming the second lower redistribution layer is simultaneously formed.

[0016] In an exemplary embodiment of the present disclosure, further comprising:

[0017] A second lower redistribution layer and a second upper redistribution layer are sequentially fabricated on the second wafer, wherein the second lower redistribution layer includes a third wiring connected to the first through silicon via and a fourth wiring connected to the second pad, and the second upper redistribution layer includes a fifth wiring connected to the third wiring and a sixth wiring connected to the fourth wiring, wherein the fifth wiring and the sixth wiring include a second lead pad and a third lead pad, respectively.

[0018] In an exemplary embodiment of the present disclosure, a distance L1 between the first lead pad and the first pad in the horizontal direction is equal to a distance L3 between the third lead pad and the first pad in the horizontal direction, and L1=L3≠0.

[0019] According to a second aspect of the present disclosure, there is provided a wafer stacking structure, comprising:

[0020] A first wafer, the upper surface of which includes a first pad configured to connect to a first signal;

[0021] a first lower redistribution layer, located on the first wafer, comprising a first wiring electrically connected to the first pad;

[0022] a first upper redistribution layer, located above the first lower redistribution layer, comprising a second wiring electrically connected to the first wiring, wherein the second wiring has a first lead pad;

[0023] A second wafer, the bottom surface of which is bonded to the first upper redistribution layer, comprising a second pad configured to connect to a second signal and a first through-silicon via directly connected to the first lead pad at the bottom;

[0024] a second lower redistribution layer, located on the second wafer, comprising a third wiring electrically connected to the first through silicon via and a fourth wiring electrically connected to the second pad;

[0025] The second upper redistribution layer is located above the second lower redistribution layer and includes a fifth wiring electrically connected to the third wiring and a sixth wiring electrically connected to the fourth wiring. The fifth wiring and the sixth wiring include a second lead pad and a third lead pad, respectively.

[0026] In an exemplary embodiment of the present disclosure, a distance L1 between the first lead pad and the first pad in the horizontal direction is equal to a distance L3 between the third lead pad and the first pad in the horizontal direction, and L1=L3≠0.

[0027] In an exemplary embodiment of the present disclosure, the first through silicon via is fabricated after the second wafer is bonded to the first upper redistribution layer.

[0028] According to a third aspect of the present disclosure, a chip stacking method is provided, comprising:

[0029] Providing a wafer stacking structure according to any one of the above items;

[0030] The wafer stack structure is diced to form a preset number of chips with a stack structure.

[0031] According to a third aspect of the present disclosure, there is provided a chip stacking structure, comprising:

[0032] A first chip, the upper surface of which includes a first pad configured to connect to a first signal;

[0033] a first lower redistribution layer, located on the first chip, comprising a first wiring electrically connected to the first pad;

[0034] a first upper redistribution layer, located above the first lower redistribution layer, comprising a second wiring electrically connected to the first wiring, wherein the second wiring has a first lead pad;

[0035] A second chip, the bottom surface of which is bonded to the first upper redistribution layer, comprising a second pad configured to connect to a second signal and a first through-silicon via directly connected to the first lead pad at the bottom;

[0036] a second lower redistribution layer, located on the second chip, comprising a third wiring electrically connected to the first through-silicon via and a fourth wiring electrically connected to the second pad;

[0037] The second upper redistribution layer is located above the second lower redistribution layer and includes a fifth wiring electrically connected to the third wiring and a sixth wiring electrically connected to the fourth wiring. The fifth wiring and the sixth wiring include a second lead pad and a third lead pad, respectively.

[0038] In an exemplary embodiment of the present disclosure, a distance L1 between the first lead pad and the first pad in the horizontal direction is equal to a distance L3 between the third lead pad and the first pad in the horizontal direction, and L1=L3≠0.

[0039] In an exemplary embodiment of the present disclosure, the first through silicon via is fabricated after the second chip is bonded to the first upper redistribution layer.

[0040] The wafer stacking method provided by the embodiment of the present disclosure achieves signal lead-out between wafers by first bonding the wafers and then making TSVs and using two layers of redistribution layers. This can avoid the errors in mechanical alignment and electrical connection of TSVs in related technologies. Only mechanical connection between wafers is required to achieve signal lead-out of pads located at the same position on different layers of wafers, thereby reducing the negative impact of TSV electrical connection through bumps on the yield rate, reducing manufacturing costs and improving the yield rate.

[0041] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0043] Figure 1A and Figure 1B It is a schematic diagram of a chip stacking structure in related technology.

[0044] Figure 2 is a flow chart of a wafer stacking method in an exemplary embodiment of the present disclosure.

[0045] Figures 3A to 3D FIG. 1 is a schematic diagram of forming a wafer stacking structure by applying the wafer stacking method in an exemplary embodiment of the present disclosure.

[0046] Figure 4 is a flow chart of a wafer stacking method in yet another embodiment.

[0047] Figure 5A and Figure 5B yes Figure 4 Schematic diagram of a wafer stacking structure formed by the wafer stacking method shown.

[0048] Figure 6 is a schematic diagram of a wafer stacking structure in yet another embodiment.

[0049] Figure 7A and Figure 7B yes Figure 5B A top view of the wafer stack structure is shown.

[0050] Figure 8 is a flow chart of a chip stacking method in an exemplary embodiment of the present disclosure.

[0051] Figure 9 yes Figure 8 Schematic diagram of the chip stacking method shown.

[0052] Figure 10 FIG. 1 is a schematic diagram of a chip stacking structure in an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or that other methods, components, structures, steps, etc. may be employed. In other cases, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0054] In addition, the accompanying drawings are merely schematic illustrations of the present disclosure. Identical reference numerals in the drawings denote identical or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor architectures and / or microcontroller architectures.

[0055] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0056] Figure 2 The flowchart of the wafer stacking method in the exemplary embodiment of the present disclosure is schematically shown. Figure 2 , wafer stacking methods may include:

[0057] Step S102, providing a first wafer, wherein the upper surface of the first wafer includes a first pad configured to connect a first signal;

[0058] Step S104, sequentially forming a first lower redistribution layer and a first upper redistribution layer on the first wafer, wherein the first lower redistribution layer includes a first wiring connected to the first pad, and the first upper redistribution layer includes a second wiring connected to the first wiring, wherein the second wiring has a first lead pad;

[0059] Step S106, bonding a second wafer to the first upper redistribution layer, wherein the upper surface of the second wafer includes a second pad configured to connect a second signal and located corresponding to the first pad;

[0060] Step S108 , forming a first through silicon via (TSV) at a position of the second wafer corresponding to the first lead pad, the first through silicon via having a bottom connected to the first lead pad.

[0061] Figures 3A to 3D is used Figure 2 The chip stacking structure diagram produced by the chip stacking method shown.

[0062] Figure 3A The first wafer 1 provided in step S102 has an upper surface including first pads P1 - S1 configured to connect to a first signal S1 .

[0063] Figure 3B This is a schematic diagram of forming a first lower redistribution layer 11 and a first upper redistribution layer 12 on a first wafer 10 in step S104. The first lower redistribution layer 11 includes first wiring C1-S1 electrically connected to first pads P1-S1. The first upper redistribution layer 12 includes second wiring C2-S1 electrically connected to the first wiring C1-S1. The second wiring includes a first lead pad PV1 located on the upper surface of the first upper redistribution layer 12. The first wiring and the second wiring may be, for example, metal structures.

[0064] Although Figures 3A to 3D An embodiment in which the first wafer 10 does not include TSVs is shown. It is understandable that in other embodiments, the first wafer 10 may also include TSVs electrically connected to other signals. Accordingly, the first lower redistribution layer and the first upper redistribution layer may include wiring and lead pads connected to the other signals.

[0065] exist Figure 3B In the embodiment shown, the horizontal distance between the first lead pad PV1 and the first pad P1 - S1 is L1, and L1≠0. Those skilled in the art can set the relative position direction of the first lead pad PV1 and the first pad P1 - S1 by themselves.

[0066] Figure 3C FIG. 1 is a schematic diagram of step S106 of bonding the second wafer 20 to the first upper redistribution layer 12. The upper surface of the second wafer 20 includes second pads P2-S2 connected to the second signal S2 and corresponding in position to the first pads.

[0067] Those skilled in the art will understand that the bonding process may include first performing chemical mechanical polishing (CMP) on the upper surface of the first upper redistribution layer, then activating the surface of the first upper redistribution layer using plasma, and finally bonding the second wafer to the activated surface. The present disclosure will not be repeated here.

[0068] Figure 3C In the illustrated embodiment, a structure is required between the second wafer and the first upper redistribution layer to isolate the second wiring C2-S1 from the second wafer. For example, C2-S2 can be isolated from the second wafer by growing an oxide layer or other insulating layer on the upper surface of the first upper redistribution layer. Alternatively, in some embodiments, the position of C2-S2 can be controlled to be lower than the upper surface of the first upper redistribution layer during manufacture. This method can be achieved, for example, by depositing the dielectric material of the first upper redistribution layer on C2-S2 again after manufacturing C2-S2 using the Damascus process, so that the dielectric material covers C2-S2 and only exposes PV1. Alternatively, the second wafer or the bottom of the second wafer can also be insulated in advance. There are many ways of interlayer insulation, and those skilled in the art can set them according to actual conditions.

[0069] Figure 3D This is a schematic diagram illustrating step S108 of forming a first through-silicon via (TSV) at a location on the second wafer corresponding to the first lead pad, with the bottom portion connected to the first lead pad. In some embodiments, the process of forming the first TSV may include, for example, forming a through-hole at a location on the second wafer corresponding to the first lead pad, such that the bottom portion of the through-hole exposes the first lead pad, and then filling the through-hole with a conductive material, such as a metal.

[0070] Therefore, the first pad is electrically connected to the first through-silicon via through the first wiring and the second wiring, and the signal of the first pad can be brought out to the second wafer without making a bump, avoiding problems such as leakage, cold soldering, and inaccurate alignment that are easily caused by the chip stacking process in related technologies.

[0071] Furthermore, the wafer stacking method can also prepare for subsequent stacking. Figure 4 FIG. 1 is a flow chart of a chip stacking method according to another embodiment of the present disclosure. Figure 4 , the wafer stacking method may further include:

[0072] Step S110, forming a second lower redistribution layer on the second wafer, and forming a third wiring connected to the first through silicon via and a fourth wiring connected to the second pad in the second lower redistribution layer;

[0073] Step S112, making a second upper redistribution layer on the second lower redistribution layer, and making a fifth wiring connected to the third wiring and a sixth wiring connected to the fourth wiring in the second upper redistribution layer to form a second lead pad electrically connected to the first signal and a third lead pad electrically connected to the second signal, respectively.

[0074] Figure 5A and Figure 5B yes Figure 4 Schematic diagram of the steps shown.

[0075] refer to Figure 5A The process of making the second lower redistribution layer 21 and the third wiring C3-S1 and the fourth wiring C4-S2 on the second wafer 20 can be either to first make a first through-silicon via on the second wafer, then deposit a first dielectric on the second wafer and the first through-silicon via to form a second lower redistribution layer, and simultaneously make a third wiring electrically connected to the first through-silicon via and a fourth wiring electrically connected to the second pad in the second lower redistribution layer; or first deposit a first dielectric on the second wafer to form a second lower redistribution layer, then make a through hole at a position corresponding to the first lead pad on the second wafer and the second lower redistribution layer and fill it with conductive material to form a first through-silicon via with the bottom electrically connected to the first lead pad, and finally make a third wiring electrically connected to the first through-silicon via and a fourth wiring electrically connected to the second pad in the second lower redistribution layer. That is, for multi-layer chip stacking, the first through-silicon via can be made either before or after the second lower redistribution layer is formed, and the present disclosure does not impose any special restrictions on this. The first dielectric is, for example, an oxide.

[0076] refer to Figure 5B In order to prepare for the next step of wafer stacking, a second upper redistribution layer 21 can also be set up, and the corresponding positions of the lead pads connecting each signal can be adjusted through the fifth and sixth wirings therein to provide conditions for the signal lead-out of the pads with the same relative position.

[0077] After fabricating the fifth wiring C5-S1 and the sixth wiring C6-S2, the horizontal distance L1 between the first lead pad PV1 and the first pad is equal to the horizontal distance L3 between the third lead pad PV3 and the first pad, and L1 = L3 ≠ 0. Although the first and third lead pads are aligned in the disclosed embodiment to facilitate stacking and signal routing of wafers with the same circuits or the same type of pads, in other embodiments, those skilled in the art may stack wafers with different circuits and adjust the positions of the lead pads to provide greater design flexibility, and the disclosure is not limited thereto.

[0078] Thus, when the chip layers are stacked again with reference to steps S104 to S112, the following can be formed: Figure 6 The structure shown is that a third wafer (with third pads P3-S3 connected to a third signal S3 provided on its upper surface) is bonded to a second upper redistribution layer 22, and then second and third through-silicon vias TSV2 and TSV3 are fabricated. A third lower and third upper redistribution layers are fabricated on the through-silicon vias to form wiring that can route signals S1, S2, and S3 connected to the pads to the topmost layer (PV4, PV5, and PV6). In the disclosed embodiment, S1, S2, and S3 are, for example, chip select signals.

[0079] Figure 7A and Figure 7B The top views of the second lower redistribution layer and the second upper redistribution layer are shown respectively. Figure 7A 、 Figure 7B and Figure 5B , on the same plane, those skilled in the art can set the shape of each wiring by themselves.

[0080] In some other embodiments, the chip stacking structure may be manufactured by the following steps:

[0081] 1. Fabricate two redistribution layers on the first wafer to lead the signal of the first pad to the first lead pad;

[0082] 2. Bonding the second wafer to the first upper redistribution layer;

[0083] 3. depositing a first dielectric on the second wafer to form a second lower redistribution layer;

[0084] 4. Etching through holes in the second wafer and the second lower redistribution layer at positions corresponding to the first lead pads;

[0085] 5. Etching a lead groove connected to the through hole and a lead groove connected to the second pad in the second lower redistribution layer;

[0086] 6. Filling the through hole and the lead groove with a conductive material to form a first through silicon via, a third wiring electrically connected to the first through silicon via, and a fourth wiring electrically connected to the second pad;

[0087] 7. Perform CMP (chemical mechanical polishing) on the second lower redistribution layer;

[0088] 8. Depositing a second dielectric on the second lower redistribution layer to form a second upper redistribution layer;

[0089] 9. Etching lead grooves in the second upper redistribution layer and filling them with conductive material to form a fifth wiring electrically connected to the third wiring and the second lead pad, and a sixth wiring electrically connected to the fourth wiring and the third lead pad.

[0090] 10. Perform CMP on the second upper redistribution layer.

[0091] In the above process, the first medium and the second medium are both oxides, for example, and the materials of the two can be the same or different.

[0092] The disclosed embodiment bonds wafers first and then makes TSVs, and leads the signals of chip pads of each layer with the same relative position to the top layer through two layers of redistribution layers (RDL). This can achieve mechanical alignment and electrical connection of TSV to the lower layer signals at one time. Moreover, since there is no need to make bumps, it can effectively avoid the problem of decreased yield caused by related technologies and reduce manufacturing costs.

[0093] Figure 8 This is a flowchart of a chip stacking method provided by an embodiment of the present disclosure.

[0094] refer to Figure 8 , the chip stacking method may include:

[0095] Step S81, providing a wafer stacking structure according to the above embodiment;

[0096] Step S82 , dicing the wafer stack structure to form a preset number of chips having a stack structure.

[0097] Figure 9 is used Figure 8 The schematic diagram of the chip stacking method for manufacturing chips is shown, that is, the wafer stacking structure manufactured according to the above method embodiment is diced and cut to form unpackaged bare chips. It is worth mentioning that the wafer stacking structure provided by the present disclosure includes Figure 3D or Figure 5B The structure shown.

[0098] Figure 10 yes Figure 9 Schematic diagram of the chip structure fabricated in .

[0099] refer to Figure 10 , the chip structure 100 may include:

[0100] A first chip 1, the upper surface of which includes a first pad P1-S1 configured to connect to a first signal S1;

[0101] A first lower redistribution layer 2 is located on the first chip 1 and includes first wirings C1 - S1 electrically connected to the first pads P1 - S1 ;

[0102] A first upper redistribution layer 3 is located above the first lower redistribution layer and includes a second wiring C2 - S1 electrically connected to the first wiring C1 - S1 , wherein the second wiring C2 - S1 has a first lead pad PV1 ;

[0103] The second chip 4 has a bottom surface bonded to the first upper redistribution layer 3 and includes a second pad P2-S2 configured to connect to the second signal S2 and a first through-silicon via TSV1 directly connected to the first lead pad PV1 at the bottom;

[0104] A second lower redistribution layer 5 is located on the second chip 4 and includes a third wiring C3 - S1 electrically connected to the first through silicon via TSV1 and a fourth wiring C4 - S2 electrically connected to the second pad P2 - S2 ;

[0105] The second upper redistribution layer 6 is located above the second lower redistribution layer 5, and includes a fifth wiring C5-S1 electrically connected to the third wiring C3-S1 and a sixth wiring C6-S2 electrically connected to the fourth wiring C4-S2. The fifth wiring C5-S1 and the sixth wiring C6-S2 respectively include a second lead pad PV2 and a third lead pad PV3.

[0106] Although Figure 10 Only a stacking structure including two layers of chips is shown. It is understandable that those skilled in the art can set and Figure 10 The structure shown sets the number of layers of stacked chips, but the present disclosure is not limited thereto.

[0107] Figure 10 The chip shown does not have a bump structure. The chips are electrically connected through the redistribution layer and the TSV directly connected to the redistribution layer at the bottom, which has high reliability and can avoid the electrical connection instability problem that occasionally exists in chips in related technologies.

[0108] Furthermore, the above-described figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention and are not intended to be limiting. It is readily understood that the processes illustrated in the above-described figures do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0109] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope of the present disclosure is indicated by the claims.

Claims

1. A wafer stacking method, characterized in that: include: Providing a first wafer, wherein the upper surface of the first wafer includes a first pad configured to connect a first signal; Sequentially forming a first lower redistribution layer and a first upper redistribution layer on the first wafer, wherein the first lower redistribution layer includes a first wiring connected to the first pad, and the first upper redistribution layer includes a second wiring connected to the first wiring, wherein the second wiring has a first lead pad; First, a second wafer is bonded to the first upper redistribution layer, wherein the upper surface of the second wafer includes a second pad configured to connect to a second signal and located corresponding to the first pad; Then, forming a first through silicon via at a position of the second wafer corresponding to the first lead pad, the first through silicon via having a bottom connected to the first lead pad; The manufacturing of a first through silicon via having a bottom portion connected to the first lead pad comprises: forming a through hole at a position of the second wafer corresponding to the first lead pad, wherein the bottom of the through hole exposes the first lead pad; Filling the through hole with a conductive material, wherein the conductive material includes metal; In the process of forming the through hole, a groove for forming the second lower redistribution layer is simultaneously formed; A second lower redistribution layer and a second upper redistribution layer are sequentially fabricated on the second wafer, wherein the second lower redistribution layer includes a third wiring connected to the first through silicon via and a fourth wiring connected to the second pad, and the second upper redistribution layer includes a fifth wiring connected to the third wiring and a sixth wiring connected to the fourth wiring, wherein the fifth wiring and the sixth wiring include a second lead pad and a third lead pad, respectively.

2. The wafer stacking method according to claim 1, wherein: A distance L1 between the first lead pad and the first pad in the horizontal direction is equal to a distance L3 between the third lead pad and the first pad in the horizontal direction, and L1=L3≠0.

3. A wafer stacking structure formed by the wafer stacking method according to claim 1, characterized in that: include: A first wafer, the upper surface of which includes a first pad configured to connect to a first signal; a first lower redistribution layer, located on the first wafer, comprising a first wiring electrically connected to the first pad; a first upper redistribution layer, located above the first lower redistribution layer, comprising a second wiring electrically connected to the first wiring, wherein the second wiring has a first lead pad; A second wafer, the bottom surface of which is bonded to the first upper redistribution layer, comprising a second pad configured to connect to a second signal and a first through-silicon via directly connected to the first lead pad at the bottom; a second lower redistribution layer, located on the second wafer, comprising a third wiring electrically connected to the first through silicon via and a fourth wiring electrically connected to the second pad; The second upper redistribution layer is located above the second lower redistribution layer and includes a fifth wiring electrically connected to the third wiring and a sixth wiring electrically connected to the fourth wiring. The fifth wiring and the sixth wiring include a second lead pad and a third lead pad, respectively.

4. The wafer stacking structure according to claim 3, wherein: A distance L1 between the first lead pad and the first pad in the horizontal direction is equal to a distance L3 between the third lead pad and the first pad in the horizontal direction, and L1=L3≠0.

5. A chip stacking method, characterized in that: include: Providing a wafer stacking structure as claimed in claim 3 or 4; The wafer stack structure is diced to form a preset number of chips with a stack structure.

6. A chip stacking structure formed by the chip stacking method according to claim 5, characterized in that: include: A first chip, the upper surface of which includes a first pad configured to connect to a first signal; a first lower redistribution layer, located on the first chip, comprising a first wiring electrically connected to the first pad; a first upper redistribution layer, located above the first lower redistribution layer, comprising a second wiring electrically connected to the first wiring, wherein the second wiring has a first lead pad; A second chip, the bottom surface of which is bonded to the first upper redistribution layer, comprising a second pad configured to connect to a second signal and a first through-silicon via directly connected to the first lead pad at the bottom; a second lower redistribution layer, located on the second chip, comprising a third wiring electrically connected to the first through-silicon via and a fourth wiring electrically connected to the second pad; The second upper redistribution layer is located above the second lower redistribution layer and includes a fifth wiring electrically connected to the third wiring and a sixth wiring electrically connected to the fourth wiring. The fifth wiring and the sixth wiring include a second lead pad and a third lead pad, respectively.

7. The chip stacking structure according to claim 6, wherein: A distance L1 between the first lead pad and the first pad in the horizontal direction is equal to a distance L3 between the third lead pad and the first pad in the horizontal direction, and L1=L3≠0.

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