Composite default circuit and reset control method

Abstract

The present invention relates to a composite default circuit, comprising a physical button, one end of which is grounded for providing a ground signal; a CMOS clearing circuit, electrically connected to the physical button, for receiving a ground signal and clearing data in the CMOS when the system power supply is not connected; a cold restart circuit, electrically connected to the physical button, for receiving a ground signal and outputting a restart signal when the system power supply is connected; the CMOS clearing circuit and the cold restart circuit are both electrically connected to the system power supply. The present invention has the effect of simplifying the data clearing process.

Description

Technical Field

[0001] The present invention relates to the technical field of control circuits, and in particular to a composite default circuit and a reset control method. Background Art

[0002] Currently, when a computer freezes, it is usually restarted. When a computer is infected with a virus, the virus is removed by restoring the factory settings.

[0003] Existing computers are generally provided with a restart button, which can be used to restart the computer. After the computer is infected with a virus, the computer can be disassembled and the data in the CMOS can be cleared to complete the operation of restoring the factory settings.

[0004] The above-mentioned prior art solutions have the following defects: when clearing the data in the CMOS, the user needs to find a professional to disassemble the computer host and then clear the data, which makes the whole process more cumbersome. Summary of the invention

[0005] In view of the deficiencies in the prior art, an object of the present invention is to provide a composite default circuit and a reset control method, which has the effect of simplifying the data clearing process.

[0006] The above-mentioned invention object of the present invention is achieved through the following technical scheme: a composite default circuit, comprising:

[0007] A physical button, one end of which is grounded and used to provide a ground signal;

[0008] A CMOS clearing circuit, electrically connected to the physical button, for receiving a ground signal and clearing data in the CMOS when the system power supply is not connected;

[0009] A cold restart circuit, electrically connected to the physical button, for receiving a ground signal and outputting a restart signal when the system power is connected;

[0010] The CMOS clear circuit and the cold restart circuit are both electrically connected to a system power supply.

[0011] By adopting the above technical solution, when the physical button is pressed, if the CMOS clear circuit is not connected to the system power supply at this time, the CMOS clear circuit receives a ground signal, thereby clearing the data in the CMOS; if the CMOS clear circuit is connected to the system power supply at this time, the CMOS clear circuit cannot clear the data in the CMOS even if it receives a ground signal; if the cold restart circuit is connected to the system power supply at this time, the cold restart circuit receives a ground signal and outputs a restart signal, thereby completing the restart of the device; if the cold restart circuit is not connected to the system power supply at this time, the cold restart circuit cannot output a restart signal after receiving a ground signal, thereby completing two reset and restart operations through one physical button, and the two reset and restart operations do not interfere with each other, making the entire data clearing process simple and convenient.

[0012] In a preferred example, the present invention can be further configured as follows: the CMOS clear circuit includes:

[0013] The transistor has an input terminal electrically connected to the CMOS and is used to turn on or off the CMOS and the ground terminal;

[0014] A control circuit, the input end of which is electrically connected to the system power supply, and the output end of which is electrically connected to the control end of the transistor, for controlling the on and off of the transistor;

[0015] The isolation element has one end electrically connected to the output end of the transistor and the other end electrically connected to the physical button, and is used to isolate external signals.

[0016] By adopting the above technical solution, the control circuit connects the system power supply to the control end of the transistor, and realizes the on-off control of the transistor through the control end. When the transistor is turned on, the CMOS is connected to the ground end. At this time, if the physical button is pressed, the CMOS is grounded, thereby realizing the clearing of the CMOS data. When the transistor is turned off, the CMOS is disconnected from the ground end. At this time, if the physical button is pressed, the CMOS cannot be grounded, and the CMOS data is not cleared. The isolation element isolates the external signal, thereby making the CMOS not easily affected by the external signal.

[0017] In a preferred example, the present invention can be further configured as follows: the control circuit includes a first resistor R1 and a second resistor R2, the first resistor R1 and the second resistor R2 are connected in series, one end of the first resistor R1 away from the second resistor R2 is connected to the system power supply, the connection midpoint between the first resistor R1 and the second resistor R2 is electrically connected to the control end of the transistor, and the second resistor R2 is grounded.

[0018] By adopting the above technical solution, the first resistor R1 and the second resistor R2 are connected in series, and the connection midpoint between the two generates a reference voltage, thereby controlling the voltage difference between the control terminal and the input terminal of the transistor, so that the transistor is not easily turned on when powered by the system power supply, thereby preventing the CMOS clear circuit and the cold restart circuit from affecting each other.

[0019] In a preferred example, the present invention can be further configured as follows: the cold restart circuit includes an inverting chip, and the inverting chip is electrically connected to the physical button to isolate the external signal and output a restart signal.

[0020] By adopting the above technical solution, when the physical button is pressed, the ground signal is transmitted to the inverting chip, and the inverting chip inverts the electrical level, thereby outputting a restart signal for the device. The inverting chip has an isolation effect, so that the signal input end and the signal output end of the inverting chip are isolated from each other, making the signal accurate.

[0021] In a preferred example, the present invention can be further configured as follows: the inverter chip includes a first inverter and a second inverter, the input end of the first inverter is electrically connected to the physical key, the output end of the first inverter is electrically connected to the input end of the second inverter, and the output end of the second inverter outputs a restart signal.

[0022] By adopting the above technical solution, the first inverter converts the ground signal into a high-level signal after receiving the ground signal, and the second inverter outputs a low-level signal after receiving the high-level signal. The low-level signal is the restart signal. Through the two inverters, the input and output are completely isolated and are not easily affected by each other.

[0023] In a preferred example, the present invention can be further configured as follows: the cold restart circuit also includes a delay circuit, the delay circuit includes a third resistor R3 and a first capacitor C1, the third resistor R3 and the first capacitor C1 are connected in series, the first capacitor C1 is grounded, one end of the third resistor R3 away from the first capacitor C1 is electrically connected to the output end of the first inverter, and the input end of the second inverter is located at the connection midpoint of the third resistor R3 and the first capacitor C1.

[0024] By adopting the above technical solution, the third resistor R3 and the first capacitor C1 form a delay circuit. When the ground signal time input to the first inverter is short, the input end of the second inverter can maintain a high level for a long time through the third resistor R3 and the first capacitor C1, so that the output end of the second inverter outputs a low level, ensuring the normal output of the restart signal.

[0025] In a preferred example, the present invention can be further configured as follows: the cold restart circuit also includes a low-pole diode, the cathode of the low-pole diode is electrically connected to the output end of the first inverter, and the anode of the low-pole diode is located at the connection midpoint of the third resistor R3 and the first capacitor C1.

[0026] By adopting the above technical solution and setting the low-level diode, when the input end of the first inverter is not grounded, the output end of the first inverter is at a low level. At this time, due to the existence of the first resistor R3, it is difficult for the input end of the second inverter to completely become a low level. At this time, through the conduction of the low-level diode, the input end of the second inverter and the output end of the first inverter are in the same level state, thereby ensuring that the output end of the second inverter cannot output a low level, thereby preventing an incorrect restart.

[0027] In a preferred example, the present invention may be further configured as follows: an isolation fourth resistor R4 is electrically connected to the output end of the second inverter.

[0028] By adopting the above technical solution, the fourth resistor R4 isolates the external signal input from the device, so that the second inverter works normally.

[0029] The above-mentioned invention object of the present invention is achieved through the following technical scheme: a reset control method, comprising:

[0030] Get the power supply status of CMOS clear circuit and cold restart circuit;

[0031] Get the working status of the physical buttons;

[0032] Determine the working unit according to the working status and power supply conditions and perform reset operations.

[0033] By adopting the above technical solution, the power supply conditions of the CMOS clear circuit and the cold restart circuit are first obtained, and then the working status of the physical button is obtained. According to the working status and the power supply condition, the reset operation at this time can be determined, so that the reset operations of the CMOS clear circuit and the cold restart circuit do not interfere with each other.

[0034] In a preferred example, the present invention can be further configured as follows: the specific method of determining the working unit according to the working state and power supply condition and performing the reset operation includes:

[0035] If the working state is pressed, and the power supply condition is that both the CMOS clear circuit and the cold restart circuit are powered, then the cold restart circuit performs a reset operation;

[0036] If the working state is pressed, and the power supply condition is that neither the CMOS clear circuit nor the cold restart circuit is powered, then the CMOS clear circuit performs a reset operation, and the cold restart circuit does not perform a reset operation;

[0037] If the working state is not pressed, the CMOS clear circuit and the cold restart circuit will not perform a reset operation.

[0038] By adopting the above technical solution, if the physical button is not pressed, it cannot be grounded and no action occurs; if the physical button is pressed at this time, it indicates that both the CMOS clear circuit and the cold restart circuit receive the grounding signal. At this time, if both the CMOS clear circuit and the cold restart circuit are powered, since the CMOS clear circuit cannot perform a reset operation, the cold restart circuit is reset at this time. At this time, if both the CMOS clear circuit and the cold restart circuit are not powered, the cold restart circuit cannot perform a reset operation, and the CMOS clear circuit is reset at this time, thereby realizing two reset operations through one physical button, and the two reset operations do not affect each other.

[0039] In summary, the present invention includes at least one of the following beneficial technical effects:

[0040] 1. By setting a physical button, a CMOS clear circuit and a cold restart circuit, two reset modes can be realized through one physical button, and the two reset modes do not affect each other, making the entire reset operation process more convenient;

[0041] 2. By providing an inverting chip, an isolation element and a fourth resistor R4, mutual isolation between the terminals is achieved, so that the components are not likely to have mutual signal influence;

[0042] 3. Since the power supply requirements between the CMOS clearing circuit and the cold restart circuit are different, the CMOS clearing caused by touching the physical buttons during operation can be prevented. At the same time, since physical buttons are used, there is no need to disassemble the machine. By waterproofing the physical buttons, the waterproofness of the equipment using the circuit is also enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a schematic diagram of the circuit structure of the present invention.

[0044] Figure 2 This is a step diagram of the reset control method.

[0045] Figure numerals: 1. physical button; 2. CMOS clear circuit; 21. transistor; 22. control circuit; 23. isolation element; 3. cold restart circuit; 31. inverter chip; 32. delay circuit; 33. low-setting diode. DETAILED DESCRIPTION

[0046] The present invention is further described in detail below in conjunction with the accompanying drawings.

[0047] Reference Figure 1, which is a composite default circuit disclosed in the present invention, including a physical button 1, a CMOS clear circuit 2 and a cold restart circuit 3, the CMOS clear circuit 2 and the cold restart circuit 3 are electrically connected, and the CMOS clear circuit 2 and the cold restart circuit 3 are both electrically connected to the physical button 1.

[0048] The CMOS clearing circuit 2 includes a transistor 21, a control circuit 22 and an isolation element 23. The transistor 21 is a PMOS tube, and the S pole of the transistor 21 is electrically connected to the CMOS power supply. The control circuit 22 includes a first resistor R1 and a second resistor R2, the first resistor R1 and the second resistor R2 are connected in series, the G pole of the transistor 21 is electrically connected to the connection midpoint of the first resistor R1 and the second resistor R2, the end of the first resistor R1 away from the second resistor R2 is connected to the system power supply, and the end of the second resistor R2 away from the first resistor R1 is grounded. The isolation element 23 is a diode, and the positive pole of the isolation element 23 is electrically connected to the D pole of the transistor 21.

[0049] The physical key 1 includes a key body and an additional resistor R5, which are connected in series. One end of the key body away from the additional resistor R5 is grounded, and one end of the additional resistor R5 away from the key body is electrically connected to the negative electrode of the isolation element 23.

[0050] The cold restart circuit 3 includes an inverter chip 31, a delay circuit 32 and a low-down diode 33. The signal of the inverter chip 31 is NC7WZ14. The inverter chip 31 includes a first inverter and a second inverter. The first inverter and the second inverter are Schmidt inverters. The input end of the first inverter is electrically connected to the negative electrode of the isolation element 23, and the output end of the second inverter is electrically connected to the isolation resistor R4. The delay circuit 32 includes a third resistor R3 and a first capacitor C1, the third resistor R3 and the first capacitor C1 are connected in series, the end of the third resistor R3 away from the first capacitor C1 is electrically connected to the output end of the first inverter, and the end of the first capacitor C1 away from the third resistor R3 is grounded. The input end of the second inverter is electrically connected to the connection midpoint of the first capacitor C1 and the third resistor R3, the positive electrode of the low-down diode 33 is electrically connected to the connection midpoint of the first capacitor C1 and the third resistor R3, and the negative electrode is electrically connected to the output end of the first inverter.

[0051] The implementation principle of this embodiment is: when there is system power supply, the button body is pressed at this time, and the button body will ground the negative electrode of the isolation element 23, and the input end of the first inverter is grounded. At this time, since the system power supply is present at the G pole of the transistor 21, the voltage difference between the G pole and the S pole does not reach the conduction requirement, the transistor 21 is in the cut-off state, and the CMOS power supply is not grounded; at this time, the output end of the first inverter is high level, the input end of the second inverter is high level, and the output end of the second inverter is low level, so that the device is restarted.

[0052] When there is no system power supply, the button body is pressed at this time, and the button body will ground the negative pole of the isolation element 23, and the input end of the first inverter will be grounded. At this time, since there is no system power supply to the G pole of the transistor 21, the voltage difference between the G pole and the S pole reaches the conduction requirement, the transistor 21 is in the on state, and the CMOS power supply is grounded, thereby erasing the data in the CMOS; at this time, the inverter chip 31 cannot obtain the system power supply and cannot work, and the output end of the second inverter cannot become a low level, and the device cannot be restarted.

[0053] Reference Figure 2 , is a reset control method disclosed in the present invention, comprising:

[0054] Obtaining the power supply conditions of the CMOS clearing circuit 2 and the cold restart circuit 3;

[0055] Get the working status of physical button 1;

[0056] The working unit is determined according to the working state and the power supply condition and a reset operation is performed; if the working state is pressed, and the power supply condition is that both the CMOS clear circuit 2 and the cold restart circuit 3 are powered, then the cold restart circuit 3 performs a reset operation at this time; if the working state is pressed, and the power supply condition is that both the CMOS clear circuit 2 and the cold restart circuit 3 are not powered, then the CMOS clear circuit 2 performs a reset operation at this time, and the cold restart circuit 3 does not perform a reset operation; if the working state is not pressed, then neither the CMOS clear circuit 2 nor the cold restart circuit 3 performs a reset operation.

[0057] The implementation principle of this embodiment is: first, the power supply conditions of the CMOS clear circuit 2 and the cold restart circuit 3 are obtained, and then the working state of the physical button 1 is detected. When the physical button 1 is not pressed, it means that the restart operation is not required, and no operation is generated at this time; when the physical button 1 is pressed, if the power supply condition is that both the CMOS clear circuit 2 and the cold restart circuit 3 are powered, then the cold restart circuit 3 performs a reset operation at this time. If the power supply condition is that both the CMOS clear circuit 2 and the cold restart circuit 3 are not powered, then the CMOS clear circuit 2 performs a reset operation at this time.

[0058] The embodiments of this specific implementation method are all preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Therefore, any equivalent changes made based on the structure, shape, and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A composite default circuit, characterized in that: include, A physical button (1), one end of the physical button (1) being grounded and used to provide a ground signal; A CMOS clearing circuit (2), electrically connected to the physical button (1), for receiving a ground signal and clearing data in the CMOS when the system power supply is not connected; A cold restart circuit (3), electrically connected to the physical button (1), for receiving a ground signal and outputting a restart signal when connected to a system power supply; The CMOS clearing circuit (2) and the cold restart circuit (3) are both electrically connected to a system power supply; Wherein, the CMOS clearing circuit (2) comprises: A transistor (21), the input end of which is electrically connected to the CMOS and is used to turn on or off the CMOS and the ground end; A control circuit (22), the input end of which is electrically connected to a system power supply, and the output end of which is electrically connected to a control end of the transistor (21), and is used to control the on and off of the transistor (21); An isolation element (23), one end of which is electrically connected to the output end of the transistor (21), and the other end of which is electrically connected to the physical key (1), for isolating external signals; The transistor (21) is a PMOS tube, and the S pole of the transistor (21) is electrically connected to a CMOS power supply; The control circuit (22) comprises a first resistor R1 and a second resistor R2, the first resistor R1 and the second resistor R2 are connected in series, one end of the first resistor R1 away from the second resistor R2 is connected to a system power supply, a connection midpoint between the first resistor R1 and the second resistor R2 is electrically connected to a control end of the transistor (21), and the second resistor R2 is grounded.

2. The composite default circuit according to claim 1, characterized in that: The cold restart circuit (3) comprises an inverting chip (31), wherein the inverting chip (31) is electrically connected to the physical key (1) and is used to isolate external signals and output a restart signal.

3. The composite default circuit according to claim 2, characterized in that: The inverter chip (31) comprises a first inverter and a second inverter, the input end of the first inverter is electrically connected to the physical key (1), the output end of the first inverter is electrically connected to the input end of the second inverter, and the output end of the second inverter outputs a restart signal.

4. The composite default circuit according to claim 3, characterized in that: The cold restart circuit (3) further comprises a delay circuit (32), the delay circuit (32) comprising a third resistor R3 and a first capacitor C1, the third resistor R3 and the first capacitor C1 being connected in series, the first capacitor C1 being grounded, an end of the third resistor R3 away from the first capacitor C1 being electrically connected to the output end of the first inverter, and the input end of the second inverter being located at a connection midpoint between the third resistor R3 and the first capacitor C1.

5. The composite default circuit according to claim 3, characterized in that: The cold restart circuit (3) further comprises a low-pole diode (33), the cathode of the low-pole diode (33) being electrically connected to the output end of the first inverter, and the anode of the low-pole diode (33) being located at the connection midpoint between the third resistor R3 and the first capacitor C1.

6. The composite default circuit according to claim 3, characterized in that: An isolation fourth resistor R4 is electrically connected to the output end of the second inverter.

7. A reset control method for a composite default circuit according to any one of claims 1 to 6, characterized in that: include, Obtaining the power supply status of the CMOS clear circuit (2) and the cold restart circuit (3); Get the working status of the physical button (1); Determine the working unit according to the working status and power supply conditions and perform reset operations.

8. The reset control method according to claim 7, characterized in that: The specific method of determining the working unit and performing the reset operation according to the working state and power supply condition includes: If the working state is pressed, and the power supply condition is that both the CMOS clear circuit (2) and the cold restart circuit (3) are powered, then the cold restart circuit (3) performs a reset operation; If the working state is pressed, and the power supply condition is that neither the CMOS clear circuit (2) nor the cold restart circuit (3) is powered, then at this time, the CMOS clear circuit (2) performs a reset operation, and the cold restart circuit (3) does not perform a reset operation; If the working state is not pressed, then the CMOS clear circuit (2) and the cold restart circuit (3) do not perform a reset operation.

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