Processor and control method thereof
Patent Information
- Application Number
- CN201880061613.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2017-10-31
- Filing Date
- 2018-10-04
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2038-10-04
AI Technical Summary
When existing processors perform deep learning tasks, it is difficult to effectively reduce the amount of peak data movement from external memory, resulting in limited scalability of the processor, especially when multiple processors implement deep neural networks (DNNs). Path activity is very bursty and difficult to achieve through simple parallel connections.
A processor is designed, which includes a plurality of processing elements arranged in matrix form, first and second data input units, and a shifter through which instructions and data are input and processed between multiple rows of processing elements , reduce the amount of data movement between the processor and external memory, and improve the efficiency of the data path.
With this design, the amount of peak data movement from external memory to the processor is significantly reduced, the processor is improved scalability, the hardware design is simplified, and the processor integration and scalability is improved.
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Figure CN111133455B_ABST