Display device and inspection method thereof

Abstract

The present invention discloses a display device and an inspection method thereof. The display device includes: a display area configured to include a plurality of pixels and a plurality of data lines connected to the pixels; a hole area arranged in the display area; and a hole crack detection line arranged adjacent to the hole area and surrounding the hole area. The device also includes: a first detection line and a second detection line, the first detection line including a first detection transmission line and a first detection receiving line, the second detection line including a second detection transmission line and a second detection receiving line; and a test controller electrically connecting the first detection receiving line to the first data line, and electrically connecting the second detection receiving line to the second data line. The pixels connected to the first data line connected to the first bright line transistor and the pixels connected to the second data line connected to the second bright line transistor are configured to emit light when a crack occurs in the hole crack detection line.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and an inspection method thereof, and more particularly, to a display device including a display panel having a hole formed therein and an inspection method thereof. Background Art

[0002] A display device such as a liquid crystal display (LCD) or an organic light emitting diode display (OLED) includes a display panel having a plurality of pixels configured to display an image and a plurality of signal lines. Each pixel may include a pixel electrode for receiving a data signal. The pixel electrode may be connected to at least one transistor to receive the data signal. The display panel may include a plurality of stacked layers.

[0003] When the display panel is impacted, cracks may form on the substrate or on the stacked layers. The cracks may grow or spread to other layers or other areas over time, which can lead to poor display panel quality. For example, signal lines such as data lines or scan lines may be disconnected by cracks or may increase resistance, and moisture may penetrate into the display panel through the cracks, thereby reducing component reliability. As a result, various problems may occur, such as pixels of the display panel not emitting light, pixels emitting light incorrectly, etc.

[0004] In particular, recently developed flexible displays may be configured to be bent or curved during manufacturing or use. Therefore, even when a substrate or stacked layer of a display panel includes a relatively small crack, the small crack may develop into a larger crack due to the bending or curvature of the display panel.

[0005] Devices such as cameras, flashes, speakers, and optical sensors may be disposed in the display area of ​​the display device so as to minimize the non-display area on the front surface of the display device and maximize the display area to the entire front surface. For example, a hole may be formed in the display panel by stamping, and a camera, flash, speaker, photoelectric sensor, etc. may be mounted in the hole. Cracks may occur during the process of forming the hole in the display panel, or cracks may occur in a portion exposed through the hole. Summary of the invention

[0006] Exemplary embodiments of the present invention provide a display device and an inspection method thereof, which detect cracks that may occur in a display panel having a hole formed therein.

[0007] In an exemplary embodiment of the present invention, a display device includes: a display area including a plurality of pixels and a plurality of data lines connected to the pixels; a hole area arranged in the display area; a hole crack detection line arranged adjacent to the hole area, the hole crack detection line surrounding the hole area and having a first end and a second end spaced apart from each other; a first detection line including a first detection transmission line connected to the first end of the hole crack detection line and a first detection receiving line connected to the second end of the hole crack detection line; a second detection line including a second detection transmission line connected to the first end of the hole crack detection line and a second detection receiving line connected to the second end of the hole crack detection line; and a test controller configured to electrically connect the first detection receiving line to a first data line among the plurality of data lines, and to electrically connect the second detection receiving line to a second data line among the plurality of data lines.

[0008] In an exemplary embodiment of the present invention, a method for inspecting a display device is provided, the display device including a display area, the display area including a plurality of pixels and a plurality of data lines connected to the pixels. The method includes: applying a first test voltage to a first detection line, the first detection line connected to a hole crack detection line, the hole crack detection line being disposed adjacent to a hole area disposed in the display area of ​​the display device; applying a second test voltage to a second detection line, the second detection line being connected to the hole crack detection line; electrically connecting the first detection line to a first data line among a plurality of data lines through a first bright line transistor; and electrically connecting the second detection line to a second data line among a plurality of data lines through a second bright line transistor.

[0009] In an exemplary embodiment, a method for inspecting a display device is provided, the display device including a plurality of pixels and a hole area disposed in a display area. The method includes: emitting light through a plurality of pixels included in a first bright line and a second bright line, the first bright line and the second bright line being electrically connected to a hole crack detection line disposed adjacent to and surrounding the hole area. The first bright line and the second bright line are disposed at a central portion of the display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A top plan view of a display device according to an exemplary embodiment of the present invention is shown.

[0011] Figure 2 The exemplary embodiment of the present invention is shown along Figure 1 A cross-sectional view of the display device taken along line II-II'.

[0012] Figure 3 FIG. 1 is a diagram for illustrating an exemplary embodiment according to the present invention. Figure 1 A circuit diagram of a test controller in a display device.

[0013] Figure 4 A timing chart for illustrating an inspection method according to an exemplary embodiment of the present invention is shown.

[0014] FIG. 5A to FIG. 5C An example of a test result displayed in a display area when a test voltage is applied to a display device according to an exemplary embodiment of the present invention is shown.

[0015] Figure 6 A top plan view of a display device according to another exemplary embodiment of the present invention is shown.

[0016] Figure 7 The exemplary embodiment of the present invention is shown along Figure 6 A cross-sectional view of the display device taken along line VII-VII'.

[0017] Figure 8 FIG. 1 is a diagram for illustrating an exemplary embodiment according to the present invention. Figure 6 A circuit diagram of a test controller in a display device.

[0018] Fig. 9 1 shows a flow chart of the exemplary embodiment of the present invention when a test voltage is applied to the Figure 6 Example of test results displayed in the display area when the display device is displayed.

[0019] Fig.10 FIG. 1 is a diagram for illustrating an exemplary embodiment according to the present invention. Figure 6 A top plan view of a display panel cut along a perforation line in a display device. DETAILED DESCRIPTION

[0020] Exemplary embodiments of the present invention will be described more fully below with reference to the accompanying drawings. As those skilled in the art will appreciate, the described exemplary embodiments may be modified in various different ways without departing from the spirit or scope of the present invention.

[0021] In order to clearly describe the present invention, parts irrelevant to the description are omitted, and the same reference numerals refer to the same or similar constituent elements throughout the specification.

[0022] In addition, since the sizes and thicknesses of the constituent members shown in the drawings are arbitrarily given for better understanding and ease of description, the exemplary embodiments of the present invention are not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. may be exaggerated for clarity. In the drawings, the thicknesses of certain layers and regions may be exaggerated for better understanding and ease of description.

[0023] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element can be directly on the other element, or intervening elements may also be present. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements. In addition, the terms "above" or "on" mean being positioned above or below an object part, and do not necessarily mean being positioned on the upper side of an object part.

[0024] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprising” or “including” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0025] In the following, reference will be made to Figures 1 to 3 A display device according to an exemplary embodiment will be described, and reference will be made to Figure 4 and FIG. 5A to FIG. 5C A method of inspecting a display device according to an exemplary embodiment will be described.

[0026] Figure 1 A top plan view of a display device according to an exemplary embodiment of the present invention is shown.

[0027] refer to Figure 1 In an exemplary embodiment, the display device includes a display panel 100A including a display area DA, a peripheral area PA, and a hole area HA. ​​The display panel 100A may include a substrate 110. The substrate 110 may be divided into a display area DA and a peripheral area PA.

[0028] The display area DA is an area in which an image may be displayed. The display area DA includes a plurality of pixels PX and a plurality of signal lines arranged on a plane parallel to a first direction D1 and a second direction D2. The first direction D1 may be perpendicular to the second direction D2.

[0029] The signal lines include: a plurality of gate lines 121 configured to transmit gate signals; and a plurality of data lines 171 configured to transmit data signals. In an exemplary embodiment, the plurality of gate lines 121 may extend approximately in a first direction D1 and may be parallel to each other. The data lines 171 may extend approximately in a second direction D2 and may be parallel to each other. The gate lines 121 and the data lines 171 may cross each other in the display area DA.

[0030] Each pixel in the pixel PX may include at least one switching element and a pixel electrode connected thereto. Figure 2The pixel PX in the exemplary embodiment shown includes a switching element TRa and a pixel electrode 191. The switching element may be connected to at least one gate line 121 and at least one data line 171. The switching element may be a three-terminal element, such as a transistor integrated in the display panel 100A. The switching element may be turned on or off according to a gate signal transmitted by the gate line 121 to selectively transmit a data signal to the pixel electrode.

[0031] Each pixel in the pixel PX may be configured to emit light of one of the primary colors or white light. Examples of primary colors may include three primary colors of red, green, and blue. Other examples of primary colors may include yellow, cyan, and magenta.

[0032] The substrate 110 may include glass, plastic, etc. In some exemplary embodiments, the substrate may be flexible. For example, the substrate 110 may include various plastics, such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), polyarylate (PAR), polyetherimide (PEI), polyethersulfone, polyimide (PI), etc., or metal film, glass, etc.

[0033] The hole area HA may be provided in the display area DA. The hole area HA may be an area in which a hole is formed, for example, by punching the substrate 110 of the display panel. The hole area HA may provide an area in the display area DA for arranging devices such as a camera, a flash, a speaker, an optical sensor, etc.

[0034] The display area DA includes a hole crack detection line HCD disposed adjacent to the hole area HA. Figure 1 As shown, the hole crack detection line HCD may have a first end N1 and a second end N2 spaced apart from each other. The hole crack detection line HCD may be configured to surround the periphery of the hole area HA. ​​For example, in an exemplary embodiment, the hole crack detection line HCD may surround the periphery of the hole area HA in a shape similar to an inverted Ω (omega). The hole crack detection line HCD may be a wiring configured to detect cracks near the hole area HA.

[0035] The peripheral area PA may surround the display area DA and be located outside the display area DA. The peripheral area PA may include a first detection line M1, a second detection line M2, a test voltage line TVL, a detection control line DCL, a test controller 700, and a plurality of test pads P1, P2, and P3. The peripheral area PA may include a gate driver (not shown) connected to the gate line 121 to output a gate signal.

[0036] The first detection line M1 may include a first detection transmission line DT1 and a first detection receiving line DR1. The first detection transmission line DT1 may include a first end connected to the first test pad P1 and a second end connected to the first end N1 of the hole crack detection line HCD. The first detection receiving line DR1 may include a first end connected to the test controller 700 and a second end connected to the second end N2 of the hole crack detection line HCD.

[0037] The first detection transmission line DT1 and the first detection receiving line DR1 may be disposed in the peripheral area PA at the left side and the upper side of the display area DA. The first detection transmission line DT1 and the first detection receiving line DR1 may be connected to the hole crack detection line HCD. Each of the first detection transmission line DT1 and the first detection receiving line DR1 may include a portion configured to extend in the peripheral area PA along the left edge of the display area DA, and a portion configured to extend in the peripheral area PA along the upper edge of the display area DA. In an exemplary embodiment, the first detection transmission line DT1 and the first detection receiving line DR1 may extend in parallel on the peripheral area PA along the edge of the display area DA.

[0038] The second detection line M2 may include a second detection transmission line DT2 and a second detection receiving line DR2. The second detection transmission line DT2 may include a first end connected to the second test pad P2, and a second end connected to the first end N1 of the hole crack detection line HCD. The second detection receiving line DR2 may include a first end connected to the test controller 700, and a second end connected to the second end N2 of the hole crack detection line HCD.

[0039] The second detection transmission line DT2 and the second detection receiving line DR2 may be disposed in the peripheral area PA along the right side and the upper side of the display area DA. The second detection transmission line DT2 and the second detection receiving line DR2 may be connected to the hole crack detection line HCD. Each of the second detection transmission line DT2 and the second detection receiving line DR2 may include a portion disposed in the peripheral area PA and configured to extend along the right edge of the display area DA, and a portion disposed in the peripheral area PA and extending along the upper edge of the display area DA. In an exemplary embodiment, the second detection transmission line DT2 and the second detection receiving line DR2 may extend in parallel on the peripheral area PA along the edge of the display area DA.

[0040] The test voltage line TVL may include a first end connected to the first detection transmission line DT1, and a second end connected to the second detection transmission line DT2. The test voltage line TVL is configured to connect the first detection transmission line DT1 and the second detection transmission line DT2 to each other. The test voltage line TVL may be configured to transmit the detection voltage applied to the first detection transmission line DT1 and the second detection transmission line DT2 through the first test pad P1 and the second test pad P2 to the test controller 700.

[0041] The detection control line DCL may include a first end connected to the third test pad P3 , and a second end connected to the test controller 700 .

[0042] In an exemplary embodiment, the first, second, and third test pads P1, P2, and P3 may be arranged along a lower edge of the substrate 110 in the peripheral area PA.

[0043] The test controller 700 may be disposed in the peripheral area PA of the display panel 100A and connected to a plurality of data lines 171. The test controller 700 may be configured to electrically connect the first detection receiving line DR1 to one of the data lines 171 and to electrically connect the second detection receiving line DR2 to another of the data lines 171. In an exemplary embodiment, the test controller 700 may be directly formed on the substrate 110 together with constituent elements such as transistors of the pixel PX. A data driver (not shown) may be connected to the data lines 171. The data driver may be disposed in the peripheral area PA or on a printed circuit board (PCB) or the like connected to the peripheral area PA. In an exemplary embodiment, the test controller 700 may be disposed between the display area DA and the data driver. In this embodiment, the data line 171 may extend beyond the test controller 700 toward the data driver.

[0044] When the test voltage is applied to the first test pad P1, the second test pad P2, and the third test pad P3, the test controller 700 may be configured to control the pixel PX connected to the first data line of the data line 171 to emit light in response to the voltage transmitted through the first detection transmission line DT1, the hole crack detection line HCD, and the first detection receiving line DR1. When the test voltage is applied to the first test pad P1, the second test pad P2, and the third test pad P3, the test controller 700 may be configured to control the pixel PX connected to the second data line of the data line 171 to emit light in response to the voltage transmitted through the second detection transmission line DR2, the hole crack detection line HCD, and the second detection receiving line DR2. The first bright line may be displayed by emitting light from the pixel PX connected to the first data line of the data line 171. The second bright line may be displayed by emitting light from the pixel PX connected to the second data line of the data line 171. The display of the first bright line and / or the second bright line on the display indicates the presence of a hole crack, a first detection line defect, a second detection line defect, etc. Will refer to it later Figure 4 and FIG. 5A to FIG. 5C A detailed description of a method for inspecting such a display device will be described.

[0045] Figure 2 Shown along Figure 1 A cross-sectional view of the display device taken along line II-II'.

[0046] refer to Figure 2 , the barrier layer 120 may be disposed on the substrate 110. Figure 2 As shown in the exemplary embodiment of FIG. 1 , the barrier layer 120 may include a plurality of layers. Alternatively, the barrier layer 120 may be formed as a single layer.

[0047] The active patterns 130 and 130d may be disposed on the barrier layer 120. The active patterns 130 and 130d may include an active pattern 130 disposed in the display area DA and an active pattern 130d disposed in the peripheral area PA. Each of the active patterns 130 and 130d may include a source region, a drain region, and a channel region disposed therebetween. In an exemplary embodiment, the active pattern may include amorphous silicon, polycrystalline silicon, an oxide semiconductor, or the like.

[0048] The first insulating layer 141 may be disposed on the active patterns 130 and 130d. The first conductive layer may be disposed on the first insulating layer 141. The first conductive layer may include a conductor 155 overlapping the active pattern 130 disposed in the display area DA, a conductor 150d overlapping the active pattern 130d disposed in the peripheral area PA, and the gate line 121 described above (see Figure 1 )wait.

[0049] The active pattern 130 of the display area DA and the conductor 155 overlapping the active pattern may constitute a transistor TRa used as a switching element included in each pixel PX. The active pattern 130d of the peripheral area PA and the conductor 150d overlapping the active pattern may constitute a transistor TRd used as a switching element included in the gate driver.

[0050] The second insulating layer 142 may be disposed on the first conductive layer and the first insulating layer 141. The second conductive layer may be disposed on the second insulating layer 142. The second conductive layer may include a first detection line M1, a second detection line M2 (see Figure 1 ) and hole crack detection line HCD (see Figure 1 According to an exemplary embodiment, at least one of the first detection line M1, the second detection line M2, and the hole crack detection line HCD may be provided in a conductive layer other than the second conductive layer. For example, in an exemplary embodiment, the hole crack detection line HCD may be provided in a fourth conductive layer or a fifth conductive layer to be described later.

[0051] The third insulating layer 160 may be disposed on the second conductive layer and the second insulating layer 142 .

[0052] In an exemplary embodiment, at least one of the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160 may include a silicon nitride (SiN x ), silicon oxide (SiO x ) of inorganic insulating materials and / or organic insulating materials.

[0053] The first insulating layer 141 , the second insulating layer 142 , and the third insulating layer 160 may include contact holes 165 formed in source regions and / or drain regions of the transistors TRa and TRd.

[0054] The third conductive layer may be disposed on the third insulating layer 160. The third conductive layer may include a conductor 170 connected to the source region or drain region of the transistors TRa and TRd through the contact hole 165, a voltage transmission line 177, and the above-mentioned data line 171 (see Figure 1 ). The voltage transmission line 177 may be provided in the peripheral area PA to transmit a common voltage.

[0055] In an exemplary embodiment, at least one of the first conductive layer, the second conductive layer and the third conductive layer is made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), tantalum (Ta), and alloys of at least two metals thereof.

[0056] The passivation layer 180 may be formed on the third conductive layer and the third insulating layer 160. The passivation layer 180 may include an inorganic insulating material and / or an organic insulating material. In an exemplary embodiment, the organic insulating material may include a polyacrylic resin, a polyimide-based resin, etc. The top surface of the passivation layer 180 may be planarized. The passivation layer 180 may have a contact hole formed on the voltage transmission line 177 disposed in the peripheral area PA.

[0057] The pixel electrode layer may be disposed on the passivation layer 180. The pixel electrode layer may include a pixel electrode 191 corresponding to each pixel PX in the display area DA, and a voltage transmission electrode 197 disposed in the peripheral area PA. The voltage transmission electrode 197 may be physically and electrically connected to the voltage transmission line 177 through a contact hole of the passivation layer 180 to receive a common voltage. The pixel electrode layer may include a semi-transmissive and semi-reflective conductive material or a reflective conductive material.

[0058] The pixel defining layer 350 may be disposed on the passivation layer 180 and the pixel electrode layer. The pixel defining layer 350 may have an opening 351 disposed on the pixel electrode 191, and at least one dam portion 350d disposed in the peripheral area PA. In a plan view, the dam portion 350d may extend along the edge of the substrate 110. The spacer 360d may be further disposed on the dam portion 350d. The pixel defining layer 350 may include a photosensitive material, such as a polyacrylic resin or a polyimide-based resin.

[0059] like Figure 2 As shown in , the first inspection line M1 may be disposed outside the dam 350d (e.g., on a side farther from the display area DA). Similarly, the second inspection line M2 may be disposed outside the dam 350d. According to another exemplary embodiment, the first inspection line M1 and the second inspection line M2 may be disposed inwardly relative to the dam 350d (e.g., between the display area DA and the dam 350d).

[0060] The voltage transmission electrode 197 may include a portion that is not covered by the pixel defining layer 350 .

[0061] The emission layer 370 may be disposed on the pixel electrode 191. The emission layer 370 may include a portion disposed within the opening 351 of the pixel defining layer 350. The emission layer 370 may further include at least one dummy emission layer 370d disposed in the peripheral area PA and disposed on the pixel defining layer 350. In an exemplary embodiment, the emission layer 370 may include an organic emission material or an inorganic emission material.

[0062] The common electrode 270 may be disposed on the emission layer 370. The common electrode 270 may also be formed on the pixel defining layer 350 and may be continuously formed above the pixel PX. The common electrode 270 may be physically and electrically connected to the voltage transmission electrode 197 in the peripheral area PA to receive a common voltage. The common electrode 270 may include a conductive transparent material.

[0063] The pixel electrode 191, the emission layer 370, and the common electrode 270 of each pixel PX constitute a light emitting diode ED. Either the pixel electrode 191 or the common electrode 270 may function as an anode and the other as a cathode.

[0064] The encapsulation portion 380 configured to protect and encapsulate the light emitting diode ED may be disposed on the common electrode 270. The encapsulation portion 380 may include at least one of the inorganic layers 381 and 383, and at least one organic layer 382. At least one of the inorganic layers 381 and 383 and at least one organic layer 382 may be alternately stacked. The organic layer 382 may include an organic material and may have a planarization property. In an exemplary embodiment, the inorganic layers 381 and 383 may be made of a material such as aluminum oxide (AlO x ), silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiON) inorganic materials.

[0065] The planar area of ​​the inorganic layers 381 and 383 may be wider than the planar area of ​​the organic layer 382, ​​which allows the two inorganic layers 381 and 383 to contact each other in the peripheral area PA. In an exemplary embodiment, the inorganic layer 381 disposed at the lowest position of the inorganic layers 381 and 383 may contact the upper surface of the third insulating layer 160 in the peripheral area PA. However, the inventive concept is not limited thereto.

[0066] An edge of the organic layer 382 included in the encapsulation portion 380 may be disposed between the dam 350d and the display area DA. The dam 350d may serve to prevent an organic material from flowing out when the organic layer 382 of the encapsulation portion 380 is formed.

[0067] In an exemplary embodiment, a buffer layer 389 including an inorganic insulating material and / or an organic insulating material may be disposed on the encapsulation portion 380. However, the buffer layer 389 may be omitted.

[0068] The fourth conductive layer may be disposed on the buffer layer 389. The fourth conductive layer may include a first touch conductor TEa. The first touch insulating layer 391 may be disposed on the fourth conductive layer. The fifth conductive layer may be disposed on the first touch insulating layer 391. The fifth conductive layer may include a second touch conductor TEb. The second touch insulating layer 392 may be disposed on the fifth conductive layer. The first touch conductor TEa and the second touch conductor TEb constitute a capacitive touch sensor and may be configured to detect touch information such as the presence of a touch or a touched position when an external object is touched.

[0069] In the following, reference will be made to Figure 3 as well as Figure 1 The test controller is described in more detail in Figure 3 In an exemplary embodiment of Figure 1 The data lines 171 include m data lines DL1 to DLm, for example, DL1, DL2, DL3, ... DL(k-1), DLk, DL(k+1), ... DL(m-2), DL(m-1), and DLm.

[0070] refer to Figure 3 , the test controller 700 includes a plurality of test transistors T1 to Tm, for example, T1, T2, T3 ... T(k-1), Tk, T(k+1) ... T(m-2), T(m-1), and Tm. The test controller 700 may include a plurality of test transistors T1 to Tm corresponding to the number m of the plurality of data lines DL1 to DLm. Each of the test transistors T1 to Tm may be connected to the data lines DL1 to DLm, respectively. The test transistors T1 to Tm may be connected to Figure 2 The transistors TRa and TRd described in are formed together on the substrate 110 .

[0071] Each gate electrode of the test transistors T1 to Tm can be connected to the detection control line DCL. The first electrodes of the test transistors T1 to Tm can be connected to the data lines DL1 to DLm, respectively. The second electrode of the (k-1)th test transistor T(k-1) of the test transistors T1 to Tm can be connected to the first detection receiving line DR1, the second electrode of the (k+1)th test transistor T(k+1) can be connected to the second detection receiving line DR2, and the second electrodes of the other test transistors are connected to the test voltage line TVL. Here, k can be approximately m / 2, so that the transistors (e.g., T(k-1) and T(k+1)) connected to the data lines (e.g., DL(k-1) and DL(k+1)) are arranged in the approximate center portion of the display area DA among the data lines DL1 to DLm.

[0072] Hereinafter, among the test transistors T1 to Tm, the test transistor T(k-1) connected to the first detection receiving line DR1 is referred to as the first bright line transistor. The test transistor T(k+1) connected to the second detection receiving line DR2 is referred to as the second bright line transistor. The data line DL(k-1) connected to the first bright line transistor is referred to as the first test data line. The data line DL(k+1) connected to the second bright line transistor is referred to as the second test data line.

[0073] exist Figure 3 In the exemplary embodiment shown, the data line DL(k-1) connected to the first bright line transistor and the data line DL(k+1) connected to the second bright line transistor are separated by one data line DLk. However, the first bright line transistor and the second bright line transistor may be connected to data lines separated by a plurality of data lines. The interval between the first test data line connected to the first bright line transistor and the second test data line connected to the second bright line transistor may be configured so that the first bright line and the second bright line can be separated from the center of the display area DA by naked eyes.

[0074] In an exemplary embodiment, a plurality of test transistors T1 to Tm may be p-channel electric field effect transistors. The gate-on voltage for turning on the p-channel field effect transistor is a low-level voltage, and the gate-off voltage for turning off the p-channel field effect transistor is a high-level voltage. According to an exemplary embodiment, a plurality of test transistors T1 to Tm may be n-channel electric field effect transistors. The gate-on voltage for turning on the n-channel field effect transistor is a high-level voltage, and the gate-off voltage for turning off the n-channel field effect transistor is a low-level voltage. Hereinafter, an exemplary embodiment in which the test transistors T1 to Tm are p-channel electric field effect transistors will be described. In addition, the transistor TRa in each pixel included in the pixel PX may be a p-channel electric field effect transistor.

[0075] In the following, reference will be made to Figure 4 and FIG. 5A to FIG. 5C as well as Figure 1 and Figure 3 A method of inspecting a display device according to an exemplary embodiment of the present invention will be described.

[0076] refer to Figure 4 and FIG. 5A to FIG. 5CDuring the test period t1-t2 of the display device, a first test voltage P1(V) of a high level (H) may be applied to the first test pad P1, a second test voltage P2(V) of a high level may be applied to the second test pad P2, and a third test voltage P3(V) of a gate-on voltage may be applied to the third test pad P3. The first test voltage P1(V) and the second test voltage P2(V) may have the same voltage level. The third test voltage P3(V) may be a voltage different from the first test voltage P1(V) and the second test voltage P2(V).

[0077] The third test voltage P3 (V) applied to the third test pad P3 may be applied to the gate electrodes of the test transistors T1 to Tm included in the test controller 700 through the detection control line DCL. Since the test transistors T1 to Tm are p-channel field effect transistors, the third test voltage P3 (V) of the gate-on voltage may be a low level voltage (L). The test transistors T1 to Tm may be turned on by the third test voltage P3 (V) of the gate-on voltage.

[0078] During the test period t1-t2, the gate driver may apply a gate signal of a gate-on voltage to the gate line 121. Since the gate signal of the gate-on voltage is applied to the pixel PX, the first test voltage P1 (V) and the second test voltage P2 (V) of a high level voltage transmitted to the data lines DL1 to DLm through the turned-on test transistors T1 to Tm may be written into the pixel PX. The first test voltage P1 (V) and the second test voltage P2 (V) of the high level voltage turn off the transistor TRa (e.g., the driving transistor connected to the pixel electrode 191) included in each pixel in the pixel PX, so that the pixel PX appears black (does not emit light).

[0079] However, when a crack occurs in at least one of the first test line M1, the second test line M2, and the hole crack detection line HCD, a low level voltage may be applied to at least one of the first test data line and the second test data line by a voltage drop due to an increase in wiring resistance. Therefore, the pixel PX connected to the first test data line or the second test data line may emit white or gray.

[0080] For example, the first test voltage P1(V) of a high level voltage applied to the first test pad P1 can be applied to the second electrode of the first bright line transistor through the first detection transmission line DT1, the hole crack detection line HCD and the first detection receiving line DR1, and transmitted to the first test data line through the first bright line transistor. When a crack occurs in at least one of the first detection line M1 and the hole crack detection line HCD, a low level voltage lower than the first test voltage P1(V) can be applied to the first test data line through a voltage drop due to an increase in wiring resistance. The first test voltage P1(V) of a high level voltage is changed to a low level voltage through a crack in at least one of the first detection line M1 and the hole crack detection line HCD. Therefore, the pixel PX connected to the first test data line emits white or gray corresponding to the low level voltage. As shown in FIG. Figure 5A and Figure 5B As shown, the pixel array PC(k-1) including the pixels PX connected to the first test data line may be visually recognized as a first bright line.

[0081] For example, the second test voltage P2 (V), which is a high level voltage applied to the second test pad P2, is applied to the second electrode of the second bright line transistor through the second detection transmission line DT2, the hole crack detection line HCD, and the second detection receiving line DR2, and is transmitted to the second test data line through the second bright line transistor. When a crack occurs in at least one of the second detection line M2 and the hole crack detection line HCD, a low level voltage lower than the second test voltage P2 (V) may be applied to the second test data line through a voltage drop due to an increase in wiring resistance. The second test voltage P2 (V), which is a high level voltage, is changed to a low level voltage through a crack in at least one of the second detection line M2 and the hole crack detection line HCD. Therefore, the pixel PX connected to the second test data line emits white or gray corresponding to the low level voltage. As shown in FIG. Figure 5A and Figure 5C As shown, the pixel array PC(k+1) including the pixels PX connected to the second test data line may be visually recognized as a second bright line.

[0082] When Figure 5A As shown, when both the first bright line and the second bright line are visually identified, it indicates that a crack has occurred in the hole crack detection line HCD, which can be determined as a hole crack defect. Although cracks may occur in both the first detection line M1 and the second detection line M2, it is extremely rare for cracks to occur in both the first detection line M1 and the second detection line M2 in the manufacturing process of the display panel 100A. Therefore, when both the first bright line and the second bright line are visually identified, it indicates that a crack has occurred near the hole area HA, which can be determined as a hole crack defect.

[0083] When Figure 5B When the second bright line is not visually identified but the first bright line is visually identified, this indicates that no crack has occurred in the second inspection line M2 or the hole crack detection line HCD. The appearance of the first bright line on the display indicates that there is a defect in the first inspection line M1. This can be determined as a crack that has occurred near the edge of the display panel 100A where the first inspection line M1 extends.

[0084] When Figure 5C When the first bright line is not visually identified but the second bright line is visually identified, it indicates that no crack has occurred in the first inspection line M1 or the hole crack detection line HCD. The appearance of the second bright line can be determined as a defect of the second inspection line M2. The defect can be determined as a crack that has occurred near the edge of the display panel 100A where the second inspection line M2 extends.

[0085] In the following, reference will be made to Figures 6 to 8 A display device according to another exemplary embodiment of the present invention will be described, and reference will be made to Fig. 9 A method for inspecting a display device according to another exemplary embodiment of the present invention will be described. Figures 1 to 5C The differences between the aforementioned exemplary embodiments.

[0086] Figure 6 A top plan view of a display device according to another exemplary embodiment of the present invention is shown. Figure 7 Shown along Figure 6 A cross-sectional view of the display device taken along line VII-VII'. Figure 8 The diagram is shown for illustrating the Figure 6 A circuit diagram of a test controller in a display device. Fig. 9 shows that when the test voltage is applied to Figure 6 Example of test results displayed in the display area when the display device is displayed. Fig.10 is shown for illustrating the Figure 6 FIG. 1 is a top plan view of a display panel cut by a perforation line CL in a display device.

[0087] refer to Figure 6 In the exemplary embodiment of the display panel 100B shown in FIG, the peripheral area PA may include a bendable area BA configured to be bendable. For example, the bendable area BA may be an area in which the display panel 100B may be bent backward or forward. Figure 6 In the illustrated exemplary embodiment, it is shown as being disposed below the display area DA in the peripheral area PA, but the position, size, and number of the bendable area BA are not limited thereto.

[0088] The peripheral area PA may include a third inspection line M3 , a fourth inspection line M4 , a fifth inspection line M5 , and a sixth inspection line M6 , which may not be connected to the hole crack inspection line HCD.

[0089] The third inspection line M3 may include a first end connected to the fourth test pad P4, and a second end connected to the test controller 700'. The third inspection line M3 may be arranged in the peripheral area PA at the left and upper sides of the display area DA. The third inspection line M3 may be configured to extend along the left edge of the display area DA in the second direction D2 from the fourth test pad P4 in the peripheral area PA. Then, the third inspection line M3 may turn near the edge of the display panel 100B to extend along the upper edge of the display area DA in the first direction D1, and may turn at the central portion of the upper edge of the display area DA to return and connect to the test controller 700'. The third inspection line M3 may be arranged outside the first inspection line M1. For example, the first inspection line M1 may be arranged between the third inspection line M3 and the display area DA, and the third inspection line M3 may be arranged to be closer to the edge of the substrate 110 than the first inspection line M1.

[0090] The fourth inspection line M4 may include a first end connected to the fifth test pad P5, and a second end connected to the test controller 700'. The fourth inspection line M4 may be arranged in the peripheral area PA at the right and upper sides of the display area DA. The fourth inspection line M4 may be configured to extend along the right edge of the display area DA in the second direction D2 from the fifth test pad P5 in the peripheral area PA, and then, may turn near the edge of the display panel 100B to extend along the upper edge of the display area DA in a direction opposite to the first direction D1. The fourth inspection line M4 may turn at the central portion of the upper edge of the display area DA to return and connect to the test controller 700'. The fourth inspection line M4 may be arranged outside the second inspection line M2. For example, the second inspection line M2 may be arranged between the fourth inspection line M4 and the display area DA, and the fourth inspection line M4 may be arranged to be closer to the edge of the substrate 110 than the second inspection line M2.

[0091] The fifth inspection line M5 may include a first end connected to the sixth test pad P6, and a second end connected to the test controller 700'. The sixth inspection line M6 may include a first end connected to the seventh test pad P7, and a second end connected to the test controller 700'. In an exemplary embodiment, the fifth inspection line M5 and the sixth inspection line M6 may be arranged in the bendable area BA. For example, the fifth inspection line M5 may be arranged in the bendable area BA at the left edge of the display area DA, and the sixth inspection line M6 may be arranged in the bendable area BA at the right edge of the display area DA. The fifth inspection line M5 may extend from the sixth test pad P6 to the bendable area BA at the left edge of the substrate 110, and then, may return and be connected to the test controller 700'. The sixth inspection line M6 may extend from the seventh test pad P7 to the bendable area BA at the right edge of the substrate 110, and then, may return to be connected to the test controller 700'.

[0092] The third test pad P3 , the fourth test pad P4 , the fifth test pad P5 , the sixth test pad P6 , and the seventh test pad P7 may be arranged in the first direction D1 along a lower edge of the substrate 110 in the peripheral area PA.

[0093] Meanwhile, after a test process of the display device, a portion of the peripheral area PA of the substrate 110 may be cut along the perforation line CL. Figure 6 A portion of the peripheral area PA of the substrate 110 before being cut along the perforation line CL in an exemplary embodiment is shown. Fig.10 FIG. 2 shows a portion of the peripheral area PA of the substrate 110 after being cut along the perforation line CL in an exemplary embodiment. Figure 6 As shown, the perforation line CL may be disposed in the peripheral area PA, and may be positioned closer to the lower edge of the substrate 110 than the third to seventh test pads P3 to P7. The perforation line CL may extend in the first direction D1.

[0094] In an exemplary embodiment, the first test pad P1 and the second test pad P2 may be disposed on a portion of the peripheral area PA of the substrate 110, which is removed by cutting along the perforation line CL. The first test pad P1 and the second test pad P2 may be disposed at a position closer to the lower edge of the substrate 110 than the perforation line CL.

[0095] The fourth test pad P4 and the sixth test pad P6 may be connected to the first test pad P1. The first detection transmission line DT1 connected to the first test pad P1 may extend from the first test pad P1 toward the portion between the fourth test pad P4 and the sixth test pad P6. The fifth test pad P5 and the seventh test pad P7 may be connected to the second test pad P2. The second detection transmission line DT2 connected to the second test pad P2 may extend from the second test pad P2 toward the portion between the fifth test pad P5 and the seventh test pad P7.

[0096] like Figure 4 As shown in the exemplary embodiment shown in , the display device can be tested by applying a first test voltage P1 (V) to the first test pad P1, applying a second test voltage P2 (V) to the second test pad P2, and applying a third test voltage P3 (V) to the third test pad P3. As a result, the first test pad P1 can be used as a first common test pad, which can apply the first test voltage P1 (V) to the first detection line M1, the third detection line M3, and the fifth detection line M5. The second test pad P2 can be used as a second common test pad, which can apply the second test voltage P2 (V) to the second detection line M2, the fourth detection line M4, and the sixth detection line M6.

[0097] In addition, since the first test pad P1 and the second test pad P2 are removed after the test process of the display device, the first detection transmission line DT1 extends toward the portion between the fourth test pad P4 and the sixth test pad P6, and the second detection transmission line DT2 extends toward the portion between the fifth test pad P5 and the seventh test pad P7. In any case, the area of ​​the test pads and wiring used for the test process of the display device can be reduced.

[0098] In an exemplary embodiment, the first and second inspection lines M1 and M2 may be disposed in a conductive layer different from the third and fourth inspection lines M3 and M4. Figure 7 As shown in the exemplary embodiment shown in , the third detection line M3 can be set in the second conductive layer. Similarly, the fourth detection line M4 can also be set in the second conductive layer. In this embodiment, the first detection line M1 can be set in the fourth conductive layer. Similarly, the second detection line M2 can also be set in the fourth conductive layer. The first detection line M1 and the second detection line M2 can be set inwardly relative to the dam portion 350d (for example, between the display area DA and the dam portion 350d).

[0099] In another exemplary embodiment, the first and second inspection lines M1 and M2 may be disposed in the same second conductive layer as the third and fourth inspection lines M3 and M4. In this embodiment, the first and second inspection lines M1 and M2 may be disposed inside or outside the dam portion 350d in parallel with the third and fourth inspection lines M3 and M4.

[0100] refer to Figure 8 , among the test transistors T1 to Tm included in the test controller 700', the second electrode of the (ka)th test transistor T(ka) may be connected to the third detection line M3, the second electrode of the (k+a)th test transistor T(k+a) may be connected to the fourth detection line M4, the second electrode of the second test transistor T2 may be connected to the fifth detection line M5, and the second electrode of the (m-1)th test transistor T(m-1) may be connected to the sixth detection line M6. Here, "ka" is greater than 3 and less than "k-1", and "k+a" is greater than "k+1" and less than "m-2".

[0101] Hereinafter, among the test transistors T1 to Tm included in the test controller 700', the test transistor T(ka) connected to the third detection line M3 is referred to as the third bright line transistor. The test transistor T(k+a) connected to the fourth detection line M4 is referred to as the fourth bright line transistor. The test transistor T2 connected to the fifth detection line M5 is referred to as the fifth bright line transistor, and the test transistor T(m-1) connected to the sixth detection line M6 is referred to as the sixth bright line transistor. In addition, the data line DL(ka) connected to the third bright line transistor is referred to as the third test data line. The data line DL(k+a) connected to the fourth bright line transistor is referred to as the fourth test data line. The data line DL2 connected to the fifth bright line transistor is referred to as the fifth test data line. The data line DL(m-1) is referred to as the sixth test data line.

[0102] In order to test the display device, a first test voltage P1 (V) may be applied to the first test pad P1, a second test voltage P2 (V) may be applied to the second test pad P2, and a third test voltage P3 (V) may be applied to the third test pad P3. In this case, the first test voltage P1 (V) may be written into the pixel PX connected to the third test data line through the third detection line M3 and the third bright line transistor. The second test voltage P2 (V) may be written into the pixel PX connected to the fourth test data line through the fourth detection line M4 and the fourth bright line transistor. The first test voltage P1 (V) may be written into the pixel PX connected to the fifth test data line through the fifth detection line M5 and the fifth bright line transistor. The second test voltage P2 (V) may be written into the pixel PX connected to the sixth test data line through the sixth detection line M6 and the sixth bright line transistor.

[0103] When a crack occurs in the third inspection line M3, the pixel array PC(ka) including the pixels PX connected to the third test data line may be visually recognized as a third bright line, such as Fig. 9 When the third bright line is visually recognized, it indicates a crack defect at the left edge or the upper edge of the display panel 100B.

[0104] When a crack occurs in the fourth inspection line M4, the pixel array PC(k+a) including the pixels PX connected to the fourth test data line may be visually recognized as a fourth bright line, such as Fig. 9 When the fourth bright line is visually recognized, it indicates a crack defect at the right edge or upper edge of the display panel 100B.

[0105] When a crack occurs in the fifth inspection line M5, the pixel array PC2 including the pixels PX connected to the fifth test data line may be visually recognized as a fifth bright line, such as Fig. 9 When the fifth bright line is visually recognized, it indicates a crack defect in the left portion of the bendable area BA of the display panel 100B.

[0106] When a crack occurs in the sixth inspection line M6, the pixel array PC(m-1) including the pixels PX connected to the sixth test data line may be visually recognized as a sixth bright line, such as Fig. 9 When the sixth bright line is visually recognized, it indicates a crack defect in the right portion of the bendable area BA of the display panel 100B.

[0107] Since the first bright line and the second bright line are set at the central portion of the display area DA, the fifth bright line and the sixth bright line are set at the left and right edges within the display area DA, and the third bright line and the fourth bright line are set at the left central portion and the right central portion within the display area DA, when the display device is visually tested, the user can easily determine which portion of the display panel 100B has a crack defect.

[0108] Apart from these differences, the above reference Figure 1-5C The features of the described exemplary embodiments may be applied to Figure 6-Figure 10 All exemplary embodiments are described, and therefore redundant descriptions in these exemplary embodiments are omitted.

[0109] Although the exemplary embodiments of the inventive concept have been specifically shown and described with reference to the accompanying drawings, the specific terms used herein are only used for the purpose of describing the inventive concept and are not intended to define their meanings or limit the scope of the inventive concept set forth in the claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments of the inventive concept are feasible. Therefore, the true technical protection scope of the inventive concept must be determined based on the technical spirit of the attached claims.

Claims

1. A display device, include: A display area including a plurality of pixels and a plurality of data lines connected to the plurality of pixels; A hole area is arranged in the display area; a hole crack detection line disposed adjacent to the hole region, the hole crack detection line surrounding the hole region and having a first end and a second end spaced apart from each other; a first detection line, comprising a first detection transmission line connected to the first end of the hole crack detection line and a first detection receiving line connected to the second end of the hole crack detection line; a second detection line, comprising a second detection transmission line connected to the first end of the hole crack detection line and a second detection receiving line connected to the second end of the hole crack detection line; as well as The test controller is configured to electrically connect the first detection receiving line to a first data line among the plurality of data lines, and to electrically connect the second detection receiving line to a second data line among the plurality of data lines.

2. The display device according to claim 1, further comprising: include: A test voltage line includes a first end connected to the first detection transmission line and a second end connected to the second detection transmission line.

3. The display device according to claim 2, in, The test controller includes a plurality of test transistors connected to the plurality of data lines, The first electrode of the test transistor is connected to the corresponding data line, and The test transistor further comprises a second electrode, The second electrode of a first bright line transistor among the plurality of test transistors is connected to the first detection receiving line, and the second electrode of a second bright line transistor among the plurality of test transistors is connected to the second detection receiving line.

4. The display device according to claim 3, in, Each of the second electrodes of the test transistors, except the second electrode of the first bright line transistor and the second electrode of the second bright line transistor, is connected to the test voltage line.

5. The display device according to claim 3, in, The pixel connected to the first data line connected to the first bright line transistor is configured to emit light to display a first bright line when a crack occurs in the hole crack detection line, and The pixel connected to the second data line connected to the second bright line transistor is configured to emit light to display a second bright line when a crack occurs in the hole crack detection line.

6. The display device according to claim 5, in, The first bright line and the second bright line are disposed at a central portion of the display area.

7. The display device according to claim 3, in, The first detection transmission line is connected to a first test pad, a first test voltage is applied to the first test pad, and The second detection transmission line is connected to a second test pad, and a second test voltage is applied to the second test pad.

8. The display device according to claim 7, further comprising: include: The detection control line is configured to have a first end connected to the third test pad and a second end connected to the gate electrode of each of the plurality of test transistors.

9. The display device according to claim 8, further comprising: include: a third inspection line including a first end connected to a fourth test pad, wherein the third inspection line is configured to extend along an edge of a first side of the display area and return to connect to a second electrode of a third bright line transistor included in the test transistor; as well as a fourth inspection line configured to have a first end connected to the fifth test pad, wherein the fourth inspection line is configured to extend along an edge of the second side of the display area and return to be connected to a second electrode of a fourth bright line transistor included in the test transistor.

10. The display device according to claim 9, further comprising: include: a bendable area, arranged around the display area; a fifth inspection line including a first end connected to a sixth test pad, wherein the fifth inspection line is configured to extend to the bendable region and return to be connected to a second electrode of a fifth bright line transistor included in the test transistor; as well as A sixth inspection line includes a first end connected to the seventh test pad, wherein the sixth inspection line is configured to extend to the bendable region and return to be connected to a second electrode of a sixth bright line transistor included in the test transistor.

11. The display device according to claim 10, in, The fourth test pad and the sixth test pad are connected to the first test pad, wherein the first test pad serves as a first common test pad, and The fifth test pad and the seventh test pad are connected to the second test pad, wherein the second test pad serves as a second common test pad.

12. The display device according to claim 11, in, The first detection transmission line is configured to extend to a portion between the fourth test pad and the sixth test pad, and The second test transmission line is configured to extend to a portion between the fifth test pad and the seventh test pad.

13. The display device according to claim 11, in, At least one of the pixels connected to the data line connected to the third bright line transistor, the pixels connected to the data line connected to the fourth bright line transistor, the pixels connected to the data line connected to the fifth bright line transistor, and the pixels connected to the data line connected to the sixth bright line transistor is configured to emit light when a test voltage is applied to the first test pad and the second test pad.

14. A method for inspecting a display device, the display device comprising a display area, the display area comprising a plurality of pixels and a plurality of data lines connected to the plurality of pixels, the method include: applying a first test voltage to a first inspection line, the first inspection line being connected to a hole crack inspection line, the hole crack inspection line being disposed in the display area adjacent to a hole area disposed in the display area of ​​the display device; applying a second test voltage to a second detection line connected to the hole crack detection line; electrically connecting the first detection line to a first data line among the plurality of data lines through a first bright line transistor; as well as The second detection line is electrically connected to a second data line among the plurality of data lines through a second bright line transistor, wherein the first detection line comprises a first detection transmission line connected to a first end of the hole crack detection line and a first detection receiving line connected to a second end of the hole crack detection line, and The second detection line includes a second detection transmission line connected to the first end of the hole crack detection line and a second detection reception line connected to the second end of the hole crack detection line.

15. The method according to claim 14, further comprising: include: Light is emitted through at least one of the pixel connected to the first data line and the pixel connected to the second data line.

16. The method according to claim 15, further comprising: The following steps are involved: When a crack occurs in the hole crack detection line, emitting light through the pixel connected to the first data line connected to the first bright line transistor to display a first bright line; as well as When a crack occurs in the hole crack detection line, light is emitted through the pixel connected to the second data line connected to the second bright line transistor to display a second bright line.

17. The method according to claim 15, in, At a central portion of the display area, a first bright line emits light through the pixels connected to the first data line, and a second bright line emits light through the pixels connected to the second data line.

18. A method for inspecting a display device, the display device comprising a plurality of pixels and a hole area arranged in a display area, the method include: emitting light through a plurality of pixels included in a first bright line and a second bright line, the first bright line and the second bright line being electrically connected to a hole crack detection line, the hole crack detection line being disposed adjacent to the hole area in the display area and surrounding the hole area, and the hole crack detection line being connected to the first detection line and the second detection line, wherein the first bright line and the second bright line are arranged at the central portion of the display area, The first detection line includes a first detection transmission line connected to a first end of the hole crack detection line and a first detection reception line connected to a second end of the hole crack detection line, and The second detection line includes a second detection transmission line connected to the first end of the hole crack detection line and a second detection reception line connected to the second end of the hole crack detection line.

19. The method according to claim 18, further comprising: include: emitting light through pixels included in one of a third bright line and a fourth bright line electrically connected to a third or fourth detection line disposed along edges of opposite sides of the display area, The third bright line and the fourth bright line are respectively arranged on the left side and the right side in the display area.

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