Data storage device having operation based on temperature difference

Abstract

Embodiments of the present invention may relate to a memory controller that may include a memory interface and logic circuitry coupled to the memory interface. In some embodiments, the logic circuitry is used to program one or more NAND cells of a multi-level NAND memory array via the memory interface with a first set of data in a first pass, determine a first temperature of the multi-level NAND memory array associated with the first pass, determine a second temperature of the multi-level NAND memory array, determine a temperature difference between the second temperature and the first temperature, and perform one or more operations at least in part based on the result of the determination of the temperature difference. Other embodiments may be described and / or claimed.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Application No. 15 / 838,202, titled "DATA STORAGE DEVICE WITH OPERATION BASED ON TEMPERATURE", filed on Dec. 11, 2017. Technical Field

[0003] Embodiments of the present invention generally relate to the field of computing technologies, and more particularly to NAND memory programming. Background Art

[0004] The background description provided herein is to present the context of the disclosure in general. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not considered to be prior art included in this section.

[0005] Semiconductor memories can be classified as non-volatile memories and volatile memories. Non-volatile memories, such as NAND flash memories, can store and retain information even when not connected to a power supply. A NAND flash memory, or simply a NAND memory, or a NAND memory system, can be included in a storage device to store data. Bits can be stored in cells or memory cells of the NAND memory, and the cells can be composed of floating-gate transistors. Multi-level NAND memories can store multiple bits of data per cell and can include triple-level cells (TLC) that store three bits of data per cell, quad-level cells (QLC) that store four bits of data per cell, and other types of cells, such as multi-level cells (MLC) that store two bits of data per cell. TLC and QLC NANDs are typically programmed using multiple passes. In NAND devices, some non-idealities can cause an increase in the raw bit error rate (RBER). One of these non-idealities is the temperature dependence of NAND cells (e.g., when a cell is read at a temperature different from the temperature during which the cell was programmed, the threshold voltage of the cell can be lower or higher than the threshold voltage in the case where the cell is read at the same temperature). For example, an internal pre-read of 8 threshold voltage (VT) states during the third pass of a 2-8-16 technology can occur under different temperature conditions than when the states were programmed during the second pass. This can cause a high error rate and potential misalignment for the 16 VT states, which can lead to fatal errors that cannot be corrected by an external error correction code (ECC) engine on the system platform. Brief Description of the Drawings

[0006] The embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals represent like structural elements. The embodiments are illustrated in the drawings by way of example and not limitation.

[0007] Figure 1 An example electronic system in accordance with various embodiments is illustrated that includes a memory controller for programming a multi-level NAND memory array of a NAND memory system using temperature checks.

[0008] Figure 2 is a schematic diagram of threshold voltage distributions for four-level cells for multi-pass programming techniques and associated temperature readings in accordance with various embodiments.

[0009] Figure 3 A flowchart of a technique for programming memory cells in accordance with various embodiments is presented.

[0010] Figure 4 A flowchart of another technique for programming memory cells in accordance with various embodiments is shown.

[0011] Figure 5 A flowchart in accordance with various embodiments is shown that illustrates different options for programming a third pass of a 2-8-16 QLC programming technique.

[0012] Figure 6 is a block diagram in accordance with various embodiments that schematically illustrates a computing device.

[0013] Figure 7 An example storage medium having instructions configured to enable a device to practice various aspects of the present disclosure is illustrated in accordance with various embodiments. Detailed Description

[0014] Embodiments of the present invention may relate to a memory controller, which may include a memory interface and logic circuit components coupled to the memory interface. In some embodiments, the logic circuit components may program one or more NAND cells of a multi-level NAND memory array in a first pass using a first set of data via the memory interface, determine a first temperature of the multi-level NAND memory array, determine a second temperature of the multi-level NAND memory array, and determine a temperature difference between the second temperature and the first temperature. In various embodiments, the memory controller may perform one or more operations at least in part based on the result of the determination of the temperature difference. In some embodiments, the operations may include programming one or more NAND cells using a second set of data in a second pass in response to the temperature difference being less than a predefined threshold. In some embodiments, the operations may include sending a temperature difference exceeded flag to a host controller, facilitating an external data read of the one or more NAND cells, facilitating data correction associated with the one or more NAND cells, or facilitating recovery of data encoded by the one or more NAND cells in response to the temperature difference being greater than the predefined threshold.

[0015] In some embodiments, a NAND memory system may include a multi-level NAND memory array and a memory controller for controlling operations (e.g., read, write (program), erase) of the multi-level NAND memory array. In various embodiments, the memory controller may program the multi-level NAND memory array at least in part based on a temperature check. When the multi-level NAND memory array may include multiple dies, the multi-level NAND memory array may include multiple cells organized into pages, blocks, and planes on a die. The smallest operating unit of the multi-level NAND memory array may be referred to as a page. A page of data may be programmed into or read from the multi-level NAND memory array.

[0016] In some embodiments, a NAND memory system may be a storage device coupled to an external computing device to store data generated by the computing device. Additionally and alternatively, a NAND memory system may be part of a computing system for storing data generated by a processor of the computing system. Sometimes, data may be programmed into the multi-level NAND memory array by a computing system or a computing device in two or more passes to minimize the coupling effect from adjacent cells.

[0017] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, the same reference numerals throughout the drawings indicate the same parts, and in which embodiments that may be practiced are shown by way of example. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Accordingly, the following detailed description is not limiting, and the scope of the embodiments is defined by the appended claims and their equivalents.

[0018] The operations of the various methods may be described as a number of discrete actions or operations, which in turn are presented in a manner that is most helpful in understanding the claimed subject matter. However, the order of the description should not be construed as implying that these operations are necessarily order-dependent. In particular, these operations may not be performed in the order presented. The described operations may be performed in a different order than the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted, divided, or combined.

[0019] For the purposes of the present disclosure, the phrases “A or B” and “A and / or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0020] The description may use the phrases “in one embodiment” or “in embodiments,” which may both refer to one or more of the same or different embodiments. Additionally, the terms “including,” “comprising,” “having,” etc., used with respect to embodiments of the present disclosure are synonymous.

[0021] As used in the following including the claims, the term “module” or “routine” may refer to the following, a part of the following, or include the following: an application specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and / or memory (shared, dedicated, or group) that executes one or more software or firmware programs, combinational logic circuitry, and / or other suitable components that provide the described functionality.

[0022] Where the disclosure refers to “a” or “a first” element or the equivalent thereof, the disclosure includes one or more such elements, neither requiring nor precluding two or more such elements. Additionally, ordinal indicators (e.g., first, second, or third) used for the identified elements are used to distinguish those elements and do not denote or imply a required or limited number of such elements, nor do they denote a particular position or order of such elements, unless otherwise specifically stated.

[0023] The terms "coupled to" and "coupled with" and their derivatives may be used herein. "Coupled" may mean one or more of the following. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are coupled to each other. By way of example and not limitation, "coupled" may mean that two or more elements or devices are coupled by, for example, an electrical connection on a printed circuit (e.g., a motherboard). By way of example and not limitation, "coupled" may mean that two or more elements / devices cooperate and / or interact via one or more network links (e.g., wired and / or wireless networks). By way of example and not limitation, a computing device may include two or more computing devices that are "coupled" on a motherboard or via one or more network links.

[0024] As used herein, the term "circuitry" may refer to, may be part of, or may include the following components: an application specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and / or a memory (shared, dedicated, or group) that executes one or more software programs or firmware programs, combinational logic circuitry, and / or other suitable hardware components that provide the functionality. As used herein, a "computer-implemented method" may refer to any method performed by one or more processors, a computer system having one or more processors, a mobile device such as a smart phone, a tablet device, a laptop computer, a set-top box, a gaming console, etc.

[0025] Figure 1 An example electronic system 100 in accordance with various embodiments is illustrated, which includes a memory controller 111 for programming multiple pages of data into a multi-level NAND memory array 121. For clarity, features of the electronic system 100 in accordance with some embodiments may be described below, which may include a memory controller for programming multiple pages of data into a multi-level NAND memory array of a NAND memory system at least in part based on a temperature check. However, it should be understood that in various embodiments, more or fewer components may be included in the electronic system 100. Additionally, it should be understood that one or more of the devices and / or components within the electronic system 100 may include additional and / or different features in accordance with the following description.

[0026] In an embodiment, the electronic system 100 may include a NAND memory system 101 coupled to a host 103 by an interconnect 145 through an interface 133 on the host 103 and an interface 113 on the NAND memory system 101. The host 103 may include a host controller 131, wherein the host controller 131 may generate first page data 132, second page data 134, third page data 136, fourth page data 138, and one or more program commands 135 for programming the first page data 132, second page data 134, third page data 136, and fourth page data 138 into a multi-level NAND memory array 121 within the NAND memory system 101. In some embodiments, the first page data 132, second page data 134, third page data 136, and fourth page data 138 may be stored in a buffer 137. Although the multi-level NAND memory array 121 is shown as including quad-level cells (QLC), it should be understood that various embodiments may include other types of NAND memories, such as T1C NAND that stores three bits of data per cell, or MLC NAND that stores two bits of data per cell.

[0027] In an embodiment, the NAND memory system 101 may include a multi-level NAND memory array 121, a memory controller 111, and an interface 113, which are coupled to each other. In various embodiments, the memory controller 111 may include a memory interface 119 coupled to the NAND memory array 121. In some embodiments, the NAND memory system 101 may include a buffer 117 that may be located within the memory controller 111. In some embodiments, the memory controller 111 may receive the first page data 132, second page data 134, third page data 136, fourth page data 138, and store them as first page data 112, second page data 114, third page data 116, fourth page data 118 in the buffer 117, respectively. In various embodiments, the memory controller 111 may receive multi-page (e.g., pages 132, 134, 136, 138) data from the host 103 in separate communications, or may receive some or all of the multi-page data from the host 103 in a single communication. In some embodiments, the memory controller 111 may receive one or more program commands 135 and may store the received one or more program commands 135 as one or more program commands 115.

[0028] In some embodiments, the multi-level NAND memory array 121 can be formed by a plurality of cells arranged in an array. The multi-level NAND memory array 121 can include word lines 123, word lines 125, bit lines 127, and bit lines 129. In some embodiments, the bit lines 127 and 129 can represent a plurality of bit lines. There can be a plurality of pages, for example, a first page 142, a second page 144, a third page 146, and a fourth page 148, which are associated with the word line 123 and the bit line 127 and include the cells formed by the word line 123 and the bit line 127. Similarly, pages 152, 154, 156, 158 can be associated with the word line 123 and the bit line 129; pages 162, 164, 166, and 168 can be associated with the word line 125 and the bit line 127; and pages 172, 174, 176, and 178 can be associated with the word line 125 and the bit line 129.

[0029] The first page 142, the second page 144, the third page 146, and the fourth page 148 can be represented by the same set of cells associated with the same word line (e.g., word line 123). For example, the cell 143 can store a plurality of bits, such as four bits. In various embodiments, the first bit of the cell 143 can be included in the first page 142, the second bit of the cell 143 can be included in the second page 144, the third bit of the cell 143 can be included in the third page 146, and the fourth bit of the cell 143 can be included in the fourth page 148. In some embodiments, all the cells belonging to a word line can be included in one page, such that the first page 142 can extend to the entire word line 123. In some other embodiments, the cells associated with a word line can be divided into a plurality of pages. For example, the cells of the word line 123 can be respectively included in the pages 142 and 152. In various embodiments, the memory controller 111 can program the first page data 112, the second page data 114, the third page data 116, and the fourth page data 118 into the plurality of pages of the multi-level NAND memory array 121 in multiple passes. In some embodiments, the first page 142 can be a lower page (LP), the second page 144 can be an upper page (UP), the third page 146 can be an extra page (XP), and the fourth page 148 can be a top page (TP).

[0030] In various embodiments, the NAND memory system 101 may include a temperature sensor 190. In some embodiments, the temperature sensor 190 may be or include a temperature sensor circuit. In some embodiments, the temperature sensor 190 may be on the same chip as the multi-level NAND memory array 121. In various embodiments, one or more flag bytes 181 may be associated with the first page 142, one or more flag bytes 182 may be associated with the second page 144, one or more flag bytes 183 may be associated with the third page 146, and one or more flag bytes 184 may be associated with the fourth page 148. Similarly, one or more flag bytes 185 may be associated with page 152, one or more flag bytes 186 may be associated with page 154, one or more flag bytes 187 may be associated with page 156, and one or more flag bytes 158 may be associated with page 158. In a similar manner, one or more additional flag bytes (not shown for clarity) may be associated with each of pages 162, 164, 166, 168, 172, 174, 176, and 178.

[0031] In some embodiments, the temperature sensor 190 may sense a first temperature associated with a first programming pass, and the memory controller 111 may store the first temperature in one or more flag bytes. In some embodiments, the first temperature may be sensed simultaneously with the first programming pass, or may be sensed within a predetermined time period before or after the first programming pass. In various embodiments, the temperature sensor 190 may sense a second temperature before the memory controller 111 programs the NAND memory during a second programming pass. In some embodiments, the second temperature may be sensed at a time associated with an internal read of data programmed during the first programming pass.

[0032] In various embodiments, the memory controller 111 may determine whether the difference between the first temperature and the second temperature exceeds a predetermined maximum temperature difference. If the maximum temperature difference is not exceeded, the memory controller 111 may continue to program the NAND memory during the second pass. If the maximum temperature difference is exceeded, the memory controller 111 may send a maximum temperature difference exceeded flag to the host 103. In various embodiments, the host 103 may include an ECC engine 196, which may be instructed by the host controller 131 to perform an error correction operation in response to receiving the maximum temperature difference exceeded flag.

[0033] In various embodiments, the memory controller 111 may include logic circuitry 198 coupled to a memory interface 119. In some embodiments, the logic circuitry 198 may be used to program one or more NAND cells (e.g., including cell 143) in the multi-level NAND memory array 121 using a first set of data via the memory interface 119 in a first pass. In various embodiments, the logic circuitry 198 may be used to determine a first temperature of the multi-level NAND memory array 121 associated with the first pass. In some embodiments, the logic circuitry 198 may store the first temperature in a flag byte (e.g., flag byte 181) associated with a page (e.g., page 142). In some embodiments, the logic circuitry 198 may be used to determine a second temperature of the multi-level NAND memory array 121 and determine a temperature difference between the second temperature and the first temperature.

[0034] In various embodiments, the logic circuitry 198 may perform one or more operations at least in part based on the result of the determination of the temperature difference. In some embodiments, the one or more operations may include programming the one or more NAND cells using a second set of data in a second pass in response to the temperature difference being less than or equal to a predefined threshold. In some embodiments, the one or more operations may include, in response to the temperature difference being greater than the predefined threshold, one or more of the following: sending a temperature difference exceeded flag 131 to the host controller 131, facilitating data correction associated with one or more NAND cells, or facilitating recovery of data encoded by one or more NAND cells.

[0035] In some embodiments, the logic circuitry 198 may program one or more NAND cells using an 8-16 technique, wherein the first set of data may include first page data, second page data, and third page data (e.g., LP, UP, and XP); and the second set of data may include fourth page data (e.g., TP). In an embodiment, programming using the 8-16 technique may include programming each of the one or more NAND cells into one of eight levels at least in part based on the first set of data, and programming the one or more NAND cells into one of sixteen levels at least in part based on the first set of data and the second set of data.

[0036] In some embodiments, the logic circuit component 198 may utilize 2-8-16 technology to program one or more NAND cells, wherein a first set of data may include first page data (e.g., LP), a second set of data may include second and third page data (e.g., UP and XP), and a third set of data may include fourth page data (e.g., TP). In an embodiment, programming using 2-8-16 technology may include programming each of the one or more NAND cells into one of two levels based at least in part on the first set of data, programming each of the one or more NAND cells into one of eight levels based at least in part on the first set of data and the second set of data, and programming each of the one or more NAND cells into one of sixteen levels based at least in part on the first set of data, the second set of data, and the third set of data.

[0037] In various embodiments, for 2-8-16 technology, a predefined threshold may be a first predefined threshold, a temperature difference may be a first temperature difference, and a second temperature may be associated with a second pass. In an embodiment, the logic circuit component 198 may perform the following operations in response to the second temperature difference being less than or equal to a second predefined threshold: determine a third temperature of the multi-level NAND memory array, determine whether a second temperature difference between the third temperature and the second temperature is less than or equal to the second predefined threshold, and program the one or more NAND cells using the third set of data in a third pass. In an embodiment, in response to the second temperature difference being greater than the second predefined threshold, the logic circuit component 198 may send a temperature difference exceeded flag to the host controller 131.

[0038] In some embodiments, for a three-pass technology such as 2-8-16 technology, a first temperature check before the second-pass data is programmed may compare a first temperature sensed at the time of programming data in the first pass with a second temperature sensed when data from the first pass is internally read. In some embodiments, if the second temperature is sensed within a predefined time period for programming the second-pass data, the second temperature may be stored in one or more flag bytes associated with one or more page addresses corresponding to the second-pass data. A third temperature may be sensed when internally reading data from the second pass, and thereafter a temperature check comparing the third temperature with the second temperature may be performed before programming the third-pass data. In some embodiments, if the second temperature is not sensed within the predefined time period for programming the second-pass data, another temperature may be sensed during programming of the second-pass data, which is then stored in one or more flag bytes for later comparison with the above-mentioned third temperature instead of comparing the second temperature with the third temperature.

[0039] In an embodiment, the electronic system 100 can be a system-on-chip (SOC) that integrates the host 103 and the NAND memory system 101, as well as other components such as caches, random access memory (RAM), peripheral functions, or other functions, onto one chip. In some embodiments, the NAND memory system 101 can be a storage device, and the host 103 can be an external computing device coupled to the NAND memory system 101. Alternatively, in some embodiments, the electronic system 100 can be a computing system, and the host controller 131 can be a processor of the computing system that is coupled to the memory controller 111 with or without the interfaces 113 and 133. In various embodiments, the electronic system 100 can be used for various applications such as wireless communication, digital signal processing, security, and other applications.

[0040] In an embodiment, the host 103 can be a computing system, a storage system, or any other system that can program multiple pages of data into a multi-level NAND memory array. In some examples, the host 103 can be implemented by a personal computer (e.g., a desktop computer, a laptop computer, etc.). However, the host 103 can be implemented by any other hardware and / or software. For example, the host 103 can be a smart phone, a television, a set-top box, a printer, a home automation system, etc. In an embodiment, the host 103 can be any type of computing system capable of programming data into the NAND memory system 101. In some embodiments, the host 103 can be a storage system such as a solid state drive (SSD) system, and the host controller 131 can be an SSD controller. When the host 103 is an SSD system, the host 103 can be coupled to another computer system, where data (e.g., the first page of data 132, the second page of data 134, the third page of data 136, and the fourth page of data 138) can be generated by the other computer system or by the host 103.

[0041] In an embodiment, host 103 may include an interface 133 that communicates with an interface 113 of NAND memory system 101 using an interconnect 145. In an embodiment, the interface 113 of NAND memory system 101 may receive first page data 132, second page data 134, third page data 136, and fourth page data 138 to be stored in buffer 117. In an embodiment, any other type of communication interconnect or link may additionally or alternatively be used for interconnect 145, interface 133, and / or interface 113, such as a Parallel Advanced Technology Attachment (PATA) interconnect developed by the American National Standards Institute (ANSI) as standard number x3.211-1994, a Serial Advanced Technology Attachment (SATA) interconnect developed by the Serial ATA International Organization, a Small Computer System Interface (SCSI) interconnect, a Serial Attached SCSI (SAS) interconnect developed by the T10 group as a standard document of the International Committee for Information Technology Standards (INCITS), a Peripheral Component Interconnect (PCI) Express (PCIe) interconnect developed by the PCI Special Interest Group (PCI-SIG) as a PCI high-speed basic specification, or a Non-Volatile Memory (NVMe) interconnect, etc.

[0042] In an embodiment, memory controller 111, logic circuitry 198, and / or host controller 131 may be implemented by or include a hardware processor, such as a silicon-based processor, such as a microcontroller, a 16-bit processor, a 32-bit processor, a 64-bit processor, a single-core processor, a multi-core processor, a digital signal processor, an embedded processor, or any other processor. Additionally, any other type of circuit may be used additionally or alternatively, such as analog or digital circuits, logic circuits, programmable processors, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), and / or field-programmable logic devices (FPLDs).

[0043] In some embodiments, buffer 117 and / or buffer 137 may be implemented as an application-specific integrated circuit (ASIC). However, other methods may be used additionally or alternatively to implement the buffer. For example, buffer 117 and / or buffer 137 may be implemented in a memory die.

[0044] Figure 2Schematic diagram of the threshold voltage distribution 200 of QLC cells (e.g., cell 143) for multi-pass programming techniques and associated temperature readings according to various embodiments. In some embodiments, the threshold voltage distribution 200 may include a first threshold voltage distribution 202 associated with a 4-16 multi-pass programming technique, a second threshold voltage distribution 204 associated with an 8-16 multi-pass programming technique, and / or a third threshold voltage distribution 206 associated with a 2-8-16 multi-pass programming technique. In some embodiments, some or all of the multi-pass channel programming techniques performed on the threshold voltage distribution 200 may be by components shown and / or described with respect to the electronic system 100 in Figure 1 and the computing device 600 in Figure 6 , or may be practiced by some other components described with respect to Figure 1 and / or Figure 6 - 7 in

[0045] Programming a multi-level NAND component per cell (such as MLC, T1C, or QLC) can be performed in multiple passes to minimize interference from adjacent word lines (WLs). In some embodiments, programming of QLC cells can be performed in two passes according to a 4-16 programming technique, as shown with respect to the first threshold voltage distribution 202. In the first pass 210, two pages of data can be provided, and the cells of the corresponding WL can be programmed into one of four levels encoding two-bit information according to the two pages of data. In the second pass 212, two more pages of data can be provided, the two pages of data programmed in the first pass can be internally read, and the cells of the corresponding WL can be programmed into one of sixteen levels encoding four-bit information.

[0046] Alternatively, programming of QLC cells can be performed in two passes according to an 8-16 programming technique, which is shown with respect to the second threshold voltage distribution 204. In the first pass 214, three pages of data can be provided, and the cells of the corresponding WL can be programmed into one of eight levels encoding three-bit information according to the three pages of data. In the second pass 216, one more page of data can be provided, the three pages of data programmed in the first pass can be internally read, and the cells of the corresponding WL can be programmed into one of sixteen levels encoding four-bit information.

[0047] In another alternative, programming of the QLC cells can be performed in three passes according to the 2-8-16 technique, which is illustrated with respect to the third threshold voltage distribution 206. In the first pass 218, one page of data can be provided and used to program the cells of the corresponding WL into one of two levels encoding one bit of information. In the second pass 220, two more pages of data can be provided, the one page of data programmed in the first pass can also be internally read, and the cells can be programmed into one of eight levels encoding three bits of information. In the third pass 222, one more page of data can be provided, the three pages of data from the second pass can be internally read, and the cells can be programmed into one of sixteen levels encoding four bits of information.

[0048] Generally, the successful placement of cells in each pass depends on correctly reading the data programmed in the previous pass. Any errors that occur during reading of data from the previous pass may cause the cells to be programmed into incorrect levels in subsequent passes. The requirements specified for the RBER allowed for the final placement of the cells can determine the RBER allowed for the internal read operations performed on the data programmed in the previous pass. For example, according to some embodiments, if the acceptable RBER for the final placement is 5e-3, the allowable RBER for internally reading data from the previous pass can be 5e-4.

[0049] In a conventional read operation (e.g., an external read command issued by an SSD controller (e.g., host controller 131)), data is typically fed into an error correction engine (e.g., an ECC engine 196), such as a low density parity check (LDPC) engine. In an embodiment, the engine can determine whether the data is correctable. If the data is correctable, the error correction engine will correct the data. Otherwise, the SSD controller can re-attempt to read the data according to a series of data recovery processes. Such data recovery processes can include re-reading, adjusting the read level (e.g., read voltage) using one or more lookup tables, reading adjacent WLs and using the adjusted read level based on the content of the adjacent WLs, obtaining soft bit read information, and any other suitable data recovery processes. However, when data from a previous programming pass is internally read (e.g., by a memory controller) in preparation for programming a subsequent pass in a multi-pass programming technique according to the single row conventional method, if the ECC engine determines that the data is incorrect, there is no opportunity to use the error correction engine to correct the data and use suitable data recovery processes.

[0050] Various embodiments may include one or more temperature checks that occur after one or more internal reads (by the memory controller 111) of data programmed during one or more passes of a multi-pass programming technique and before additional data is programmed during a subsequent pass of the multi-pass programming technique. In some embodiments, a temperature check may be performed prior to programming data in the second pass 212 by comparing temperature information recorded at the time the data was programmed in the first pass 210 with the temperature sensed when internally reading the first pass data in preparation for the second pass 212. Similarly, a temperature check may be performed prior to programming data in the second pass 216 by comparing temperature information recorded at the time the data was programmed in the first pass 214 with the temperature sensed when internally reading the first pass data in preparation for the second pass 216. In various embodiments, a three-pass programming technique may include two temperature checks, such as a first temperature check prior to programming data in the second pass 220 and a second temperature check prior to programming data in the third pass 222. If a maximum allowable temperature difference is exceeded during the temperature check, a temperature difference exceeded flag may be sent to the host controller, which may perform one or more error correction and / or data recovery procedures. In various embodiments, this may improve data integrity and / or RBER as compared to typical conventional methods.

[0051] Figure 3 is a flowchart of a technique 300 for programming QLC cells in a two-pass 8 - 16 programming technique according to various embodiments. In some embodiments, some or all of the technique 300 is practiced by components shown and / or described with respect to Figure 1 the electronic system 100 in Figure 6 or the computing device 600 of Figure 1 and / or Figure 6 - 7 or some other components described in

[0052] In various embodiments, at block 302, technique 300 may include receiving first, second, and third page data in a first pass. In some embodiments, the three pages may be LP, UP, and XP. In some embodiments, memory controller 111 may receive the first, second, and third page data from host controller 131. At block 304, technique 300 may include obtaining a first temperature T1. In various embodiments, temperature T1 may be obtained by memory controller 111 from an on-chip temperature sensor (e.g., temperature sensor 190). At block 306, technique 300 may include programming the first, second, and third page data, and the T1 information at a specified address. In various embodiments, logic circuitry 198 of memory controller 111 may program the cells in WL corresponding to the first, second, and third page addresses (e.g., including cell 143) and the T1 information in the first pass of programming. In some embodiments, the T1 information may be programmed into a location corresponding to one or more page addresses, such as one or more flag bytes (e.g., flag bytes 181, 182, 183) associated with the programmed page addresses (e.g., the page addresses of first page 142, second page 144, third page 146).

[0053] At block 308, technique 300 may include receiving fourth page data in a second pass. In an embodiment, the fourth page may be TP. At block 310, technique 300 may include internally reading the first, second, and third page data from the specified address, and reading temperature information T1 from the location used to store data during the first pass. At block 312, technique 300 may include extracting the T1 information from the internally read data. At block 314, technique 300 may include obtaining a second temperature T2. In various embodiments, the second temperature T2 may be associated with the internal reading of the first, second, and third page data at block 310, and / or may be obtained within a predefined time of reading the first, second, and third page data.

[0054] At decision block 316, technique 300 can include determining whether the difference between T1 and T2 is greater than a predefined maximum temperature difference ΔTmax. If it is determined that the difference between T1 and T2 is less than or equal to ΔTmax, technique 300 can include programming the first, second, third, and fourth pages at a specified address in a second pass at block 318. If it is determined at block 316 that the difference between T1 and T2 is greater than ΔTmax, technique 300 can include failing at block 320 due to an excessive temperature difference condition. In some embodiments, failing due to an excessive temperature difference condition can include sending a temperature difference exceeded flag (e.g., from memory controller 111 to host controller 131). In an embodiment, the temperature difference exceeded flag can be indicated with a status bit. In various embodiments, memory controller 111 can perform a temperature check that includes automatically determining the difference between T1 and T2 without receiving a temperature check command from host controller 131.

[0055] In various embodiments, when receiving a temperature difference exceeded flag at block 320, host controller 131 (e.g., SSD controller) can perform one or more of error correction or data recovery procedures (e.g., using ECC engine 196). In various embodiments, host controller 131 can issue read commands for externally reading LP, UP, and XP data and correct them through ECC engine 196. In some embodiments, host controller 131 can send the corrected data back to the NAND device (e.g., memory controller 111) to issue program commands using the externally provided LP, UP, and XP and TP data. In an embodiment, if ECC engine 196 determines that the data is not correctable, host controller 131 can perform other data recovery procedures, such as automatic read calibration, corrective reads using a lookup table to adjust read parameters, soft bit reads, and / or any other suitable data recovery procedures.

[0056] Figure 4 is a flowchart of technique 400 for programming QLC cells in a two-step 8-16 programming technique. In some embodiments, some or all of technique 400 can be practiced by components shown and / or described with respect to Figure 1 electronic system 100 in Figure 6 or computing device 600 in Figure 1 and / or Figure 6 - 7 or some other components described in

[0057] In various embodiments, at block 402, technique 400 may include receiving first, second, and third page data in a first pass. At block 404, technique 400 may include obtaining a first temperature T1. In various embodiments, temperature T1 may be obtained by memory controller 111 from an on-chip temperature sensor, such as temperature sensor 190. At block 406, technique 400 may include programming the first, second, and third page data, and the T1 information, at a specified address. In various embodiments, the logic circuitry 198 of memory controller 111 may program the cells in WL corresponding to the first, second, and third page addresses (e.g., including cell 143), and the T1 information in the first pass programming. In some embodiments, the T1 information may be programmed into a location corresponding to one or more page addresses, such as one or more flag bytes (e.g., flag bytes 181, 182, 183) associated with the programmed page addresses (e.g., the page addresses of first page 142, second page 144, third page 146).

[0058] At block 408, technique 400 may include receiving a temperature check command (e.g., at memory controller 111 from host controller 131). In various embodiments, host controller 131 (e.g., SSD controller) may issue a temperature check command before issuing a program command for a second pass. At block 410, technique 400 may include internally reading data from a location for storing the first pass temperature information. At block 412, technique 400 may include extracting the T1 information from the internally read data. At block 414, technique 400 may include obtaining a second temperature T2. At a decision block 416, technique 400 may include determining whether the difference between T1 and T2 is greater than a preset maximum temperature difference. If it is determined that the difference between T1 and T2 is less than or equal to ΔTmax, then technique 400 may include, at block 418, sending a pass status to the host controller and receiving, in response, a fourth page data (e.g., TP). In various embodiments, the fourth page data and a program command specifying to internally read the first, second, and third page data (e.g., LP, UP, and XP) may be received from the host controller. At block 420, technique 400 may include internally reading the first, second, and third pages. At block 422, technique 400 may include programming the first, second, and fourth pages at a specified address in a second pass.

[0059] If, at block 416, it is determined that the difference between T1 and T2 is greater than △Tmax, then technique 400 can include failing at block 424 due to an excessive temperature condition. In some embodiments, failing due to an excessive temperature difference condition can include sending a temperature difference exceed flag (e.g., from memory controller 111 to host controller 131). In an embodiment, a status bit can be utilized to indicate the temperature difference exceed flag.

[0060] In various embodiments, when the host controller 131 (e.g., SSD controller) receives an excessive temperature difference flag at block 424, it can perform one or more of error correction or data recovery procedures. In various embodiments, the host controller 131 can issue read commands for externally reading LP, UP, and XP data and correct it via the ECC engine 196. In some embodiments, the host controller 131 can send the corrected data back to the NAND device (e.g., memory controller 111) to issue program commands using the externally provided LP, UP, and XP and TP data. In an embodiment, if the ECC engine 196 determines that the data is uncorrectable, the host controller 131 can perform other data recovery procedures, such as auto read calibration, corrective reads that use a look-up table to adjust read parameters, soft bit reads, and / or any other suitable data recovery procedure.

[0061] In various embodiments, if the data is correctable or recoverable after failing due to an excessive temperature difference condition, the host controller 131 can issue a program command to the memory controller 111 to use the first, second, and third page data (e.g., LP, UP, and XP) read and corrected externally and the fourth page (e.g., TP). Then, the memory controller 111 can proceed to program the first, second, third, and fourth pages at the specified address.

[0062] Although with respect to Figure 3 technique 300 described and with respect to Figure 4The described technique 400 is described using 8-16 QLC programming, but it should be understood that various embodiments can use any suitable multi-pass programming technique, including different multi-pass techniques for TLC or QLC NAND devices. In some embodiments, for triple-pass QLC programming based on the 2-8-16 technique, the memory controller 111 can determine whether there is an excessive temperature difference between the second pass (wherein the NAND cells are programmed from a 2-level state to an 8-level state) and the third pass (wherein the 8-level content of the cells is internally read and the cells are programmed from an 8-level state to a 16-level state). In various embodiments, the temperature can be determined by the memory controller 111 using the temperature sensor 190 and can be stored in one or more locations, such as a flag byte associated with one or more page addresses (e.g., one or more of flag bytes 181, 182, 183, 184, 185, 186, 187, 188).

[0063] Figure 5 A flowchart in accordance with various embodiments is shown that illustrates different options for programming the third pass of a 2-8-16 QLC programming technique based at least in part on a temperature check of a NAND memory device. In some embodiments, some or all of technique 500 can be practiced by components shown and / or described with respect to the electronic system 100 in Figure 1 or the computing device 600 in Figure 6 or by some other components described in Figure 1 and / or Figure 6 - 7

[0064] In various embodiments, the third pass 500 can include a temperature check at block 501. In some embodiments, prior to performing the temperature check at block 501, the first two passes of the 2-8-16 QLC programming technique can have been performed and the temperature of the NAND memory device associated with the second pass programming can have been stored (e.g., in one or more of flag bytes 181, 182, 183). At block 501, performing the temperature check can include receiving, at the memory controller 111, a temperature check command from the host controller 131. In response to the temperature check command, the memory controller 111 can obtain the current temperature (e.g., from the temperature sensor 190) and compare the current temperature with the temperature information stored during the second pass of the 2-8-16 QLC programming technique (e.g., by reading flag bytes 181, 182, 183).

[0065] ​If the difference between the current temperature and the temperature stored during the second pass is less than or equal to a predefined maximum temperature difference threshold, the temperature check can be considered passed, and the third pass 500 can proceed to the first option 502. In various embodiments, the first option 502 can include receiving fourth page data at block 504 and a third pass program command 506 (e.g., from host controller 131). In some embodiments, memory controller 111 can program the NAND in the third pass using the internally read first, second, and third pages and the fourth page data received at block 504 in response to the third pass program command received at block 506.

[0066] If the difference between the current temperature and the temperature stored during the second pass is greater than the predefined maximum temperature difference threshold, the temperature check can be considered failed, and the third pass 500 can proceed to block 508, which can include receiving fourth page data (e.g., at memory controller 111 from host controller 131). In various embodiments, if the temperature check at block 502 fails, memory controller 111 can send an excessive temperature difference flag to host controller 131. In some embodiments, memory controller 111 can notify host controller 131 (e.g., SSD controller) to perform error correction and recovery operations. In response to the excessive temperature difference flag, the host controller can perform an external read of the third page (e.g., XP) at block 510, which may result in the third page data output at block 512.

[0067] In some embodiments, at decision block 514, an evaluation of the error correction performed on the third page can be executed to determine whether the third page result is sufficient to proceed without additional error correction. If it is determined that the result is sufficient to proceed without additional error correction, the third pass 500 can proceed to the second option 516. In various embodiments, the second option can include receiving third page data at block 518 and a third pass program command 520. In some embodiments, memory controller 111 can program the NAND in the third pass using the third page data received at block 518 and the fourth page data received at block 508 in response to the third pass program command received at block 520.

[0068] In some embodiments, if it is determined at decision block 514 that the result is not sufficient to proceed without additional error correction, a third pass may proceed to additional error correction blocks. Block 522 may include receiving in corrected third page data. Block 524 may include performing an external read of the second page, followed by transferring out the second page data at block 526 (e.g., to host controller 131). In various embodiments, the third pass 500 may proceed to a third option 534, which may include transferring the first page data to the memory controller at block 536 as the first page data is received after being verified (e.g., by the ECC engine). The third option 534 may also include receiving a third pass program command at block 538. In some embodiments, the memory controller 111 may, in the third pass, program the NAND using the first page data received at block 536, the error-corrected second page data received at 538, the error-corrected third page data received at block 522, and the fourth page data received at block 508.

[0069] In some embodiments, if the temperature check performed at block 501 fails, the first, second, and third page data may be externally read so that the check at decision block 514 is not performed, and the third option 534 may be followed. In such embodiments, the second option 516 may not be included.

[0070] Figure 6 A block diagram of an example computing device 600 according to various embodiments is shown, which is suitable for use with Figure 1 various components of, with respect to Figure 2 the multi-pass programming techniques described with respect to Figure 3 technique 300 of, Figure 4 technique 400 of, and / or Figure 5 the third pass 500 of. For example, the computing device 600 may be, or may include or otherwise be connected to the electronic system 100, the memory controller 111, the host controller 131, and / or with respect to Figure 1One or more other components shown and / or described. As shown, computing device 600 may include one or more processors or processor cores 602 and system memory 604. For the purposes of this application, including the claims, the terms "processor" and "processor core" may be considered synonymous unless the context clearly requires otherwise. Processor 602 may include any type of processor, such as a central processing unit (CPU), a microprocessor, etc. Processor 602 may be implemented as an integrated circuit with multiple cores, e.g., a multi-core microprocessor. In some embodiments, in addition to cores, processor 602 may further include hardware accelerators, e.g., hardware accelerators implemented using field programmable gate arrays (FPGAs). Computing device 600 may include a mass storage device 606, e.g., a magnetic disk, a hard disk drive, non-volatile memory (NVM) (e.g., compact disc read-only memory (CD-ROM), digital versatile disc (DVD), any other type of suitable NVM, etc.). Generally, system memory 604 and / or mass storage device 606 may be any type of temporary and / or persistent storage device, including but not limited to volatile and non-volatile memory, optical, magnetic, and / or solid-state mass storage devices, etc. Volatile memory may include but not be limited to static and / or dynamic random access memory (DRAM). Non-volatile memory may include but not be limited to electrically erasable programmable read-only memory, phase change memory, resistive memory, etc.

[0071] Computing device 600 may also include I / O devices 608 (e.g., a display (e.g., a touch screen display), a keyboard, a cursor control, a remote control, a game controller, an image capture device, etc.) and a communication interface 610 (e.g., a network interface card, a modem, an infrared receiver, a wireless receiver (e.g., Bluetooth), etc.), one or more antennas, and / or any other suitable components.

[0072] The communication interface 610 may include a communication chip (not shown) that may be configured to operate the device 600 in accordance with the following: a local area network (LAN) (e.g., Ethernet) and / or a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or Long Term Evolution (LTE) network. The communication chip may also be configured to operate in accordance with the following: Enhanced Data rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip may be configured to operate in accordance with the following: Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO) and its derivatives, and any other wireless protocol designated as 3G, 4G, 5G, and above. In other embodiments, the communication interface 610 may operate in accordance with other wireless protocols.

[0073] In various embodiments, the computing device 600 may include a data storage device 652, which may be configured in a manner similar to that of Figure 1 the electronic system 100 described above. In some embodiments, the data storage device 652 may be coupled to other components of the computer device 600. In some embodiments, the data storage device 652 may include a memory controller 654, which may be configured in a manner similar to that of Figure 1 the memory controller 111 described above. In some embodiments, the memory controller 654 may include logic circuit components 656, which may be configured in a manner similar to that of Figure 1 the logic circuit components 198 described above.

[0074] The components of the computing device 600 described above may be coupled to each other via a system bus 612, which may represent one or more buses. In the case of multiple buses, they may be bridged by one or more bus bridges (not shown). Each of these elements may perform its conventional functions known in the art. In particular, the system memory 604 and the mass storage device 606 may be used to store temporary and permanent copies of programming instructions for operating the various components of the computing device 600, including but not limited to the operating system of the computing device 600, one or more applications, and / or operations associated with the computing device 600 acting as a memory controller 111, a host controller 131, and / or a logic circuit component 198 (collectively referred to as the computing logic unit 622). The various elements may be supported by the processor 602 or a high-level language that can be compiled into such instructions. In some embodiments, the computing device 600 may be implemented as a fixed-function ASIC, an FPGA, or any other suitable device with or without programmability or configuration options.

[0075] The permanent copies of the programming instructions may be placed in the mass storage device 606 at the factory or in the field via a distribution medium such as a compact disc (CD) (not shown) or via a communication interface (from a distributed server (not shown)). That is, one or more distribution media with an implementation of the agent program may be used to distribute the agent and to program the various computing devices.

[0076] Depending on whether the computing device 600 is used as a stationary computing device (e.g., a set-top box or a desktop computer) or a mobile computing device (e.g., a tablet computing device, a laptop computer, a gaming console, or a smart phone), the number, function, and / or capacity of the elements 608, 610, 612 may vary. Their composition is well known and will not be described further.

[0077] In some embodiments, the logic circuit component 198, the memory controller 111, and / or the host controller 131 may be included with a hardware accelerator of the computing logic unit 622 or the processor 602. For certain embodiments, at least one of the processors 602 may be packaged together with the computing logic unit 622 configured to implement aspects of the embodiments described herein to form a system-in-package (SiP) or a system-on-chip (SoC).

[0078] In various implementations, computing device 600 can include one or more components of a data center, a laptop computer, a netbook, a notebook computer, a superbook, a smart phone, a tablet device, a super mobile PC, or a mobile phone. In some embodiments, computing device 600 can include one or more components of a server. In additional implementations, computing device 600 can be any other electronic device that processes data.

[0079] As will be appreciated by those skilled in the art, the present disclosure can be implemented as a method or a computer program product. Accordingly, in addition to being implemented in the hardware described previously, the present disclosure can take the form of an entirely software embodiment (including firmware, resident software, microcode, etc.) or a form of an embodiment combining aspects of hardware and software, which can generally be referred to as a "circuit", "module", or "system".

[0080] Figure 7 Illustrated is an example computer-readable storage medium 702 according to various embodiments, having instructions configured to practice all or selected operations associated with: the computing device 600 described previously with respect to Figure 6 ; the electronic system 100, memory controller 111, logic circuit components 198, and / or host controller 131 described with respect to Figure 1 ; the technique 300 of Figure 3 ; the technique 400 of Figure 4 ; and / or the third pass 500 of Figure 5 described with respect to. As shown, the computer-readable storage medium 702 can include a plurality of programming instructions 704. The storage medium 702 can be a broad range of non-transitory persistent storage media known in the art, including but not limited to flash memory, dynamic random access memory, static random access memory, optical discs, magnetic disks, etc. The programming instructions 704 can be configured to enable a device (e.g., memory controller 111, host controller 131, and / or other components of the electronic system 100) to perform, in response to execution of the programming instructions 704, operations such as but not limited to the various operations described with respect to the computing device 600 of Figure 6 ; the technique 300 of Figure 3 ; the technique 400 of Figure 4 ; and / or the operations shown and / or described with respect to the third pass 500 of Figure 5 . In alternative embodiments, the programming instructions 704 can be arranged on a plurality of computer-readable storage media 702. In alternative embodiments, the storage medium 702 can be transitory, e.g., a signal encoded with the programming instructions 704.

[0081] Referring back to Figure 6, For one embodiment, at least one of the processors 602 may be packaged with a memory having all or part of a computational logic unit 622, the computational logic unit being configured to practice aspects shown or described for the computer device 600 of Figure 6 with respect to Figure 3 the technology 300 of Figure 4 the technology 400 of, and / or Figure 5 the operations shown and / or described for the third pass 500 of Figure 6 . For one embodiment, at least one of the processors 602 may be packaged with a memory having all or part of a computational logic unit 622, the computational logic unit being configured to practice aspects described for the computer device 600 of Figure 3 with respect to Figure 4 the technology 300 of Figure 5 the technology 400 of, and / or Figure 6 the operations shown and / or described for the third pass 500 of Figure 3 to form a system in package (SiP). For one embodiment, at least one of the processors 602 may be integrated on a die with a memory having all or part of a computational logic unit 622, the computational logic unit being configured to practice aspects described for the computer device 600 of Figure 4 with respect to Figure 5 the technology 300 of Figure 6 the technology 400 of, and / or Figure 3 the operations shown and / or described for the third pass 500 of Figure 4 to form a system on chip (SoC). For one embodiment, at least one of the processors 602 may be packaged with a memory having all or part of a computational logic unit 622, the computational logic unit being configured to practice the aspects of the computer device 600 of Figure 5 with respect to

[0082] Examples

[0083] Example 1 may include a memory controller that includes: a memory interface; and logic circuitry coupled to the memory interface, wherein the logic circuitry is configured to perform the following operations: in a first pass, program one or more NAND cells of a multi-level NAND memory using a first set of data via the memory interface; determine a first temperature of the multi-level NAND memory array associated with the first pass; determine a second temperature of the multi-level NAND memory array; determine a temperature difference between the second temperature and the first temperature; and perform one or more operations at least in part based on a result of the determination of the temperature difference.

[0084] Example 2 may include the subject matter of Example 1, wherein the one or more operations include one or more of the following operations: in response to the temperature difference being less than or equal to a predefined threshold, program the one or more NAND cells using a second set of data in a second pass; and in response to the temperature difference being greater than the predefined threshold, send a temperature difference exceeded flag to a host controller, facilitate external data reading of the one or more NAND cells, facilitate data correction associated with the one or more NAND cells, or facilitate recovery of data encoded by the one or more NAND cells.

[0085] Example 3 may include the subject matter of any one of Examples 1-2, wherein the logic circuitry is configured to store the first temperature in a flag byte associated with a page address.

[0086] Example 4 may include the subject matter of any one of Examples 1-3, wherein the logic circuitry is configured to, in response to the temperature difference being less than or equal to the predefined threshold, program the one or more NAND cells using a second set of data in a second pass.

[0087] Example 5 may include the subject matter of Example 4, wherein: the one or more NAND cells are quad-level cells; the first set of data includes first page data and second page data; the second set of data includes third page data and fourth page data; the first pass includes programming each of the one or more NAND cells into one of four levels at least in part based on the first set of data; and the second pass includes programming each of the one or more NAND cells into one of sixteen levels at least in part based on the first set of data and the second set of data.

[0088] Example 6 may include the subject matter of Example 4, wherein: the one or more NAND cells are four-level cells; the first set of data includes first page data, second page data, and third page data; the second set of data includes fourth page data; the first pass includes programming each of the one or more NAND cells into one of eight levels based at least in part on the first set of data; and the second pass includes programming the one or more NAND cells into one of sixteen levels based at least in part on the first set of data and the second set of data.

[0089] Example 7 may include the subject matter of Example 4, wherein: the predefined threshold is a first predefined threshold, the temperature difference is a first temperature difference, the second temperature is associated with the second pass, and the logic circuit component is further configured to: determine a third temperature of the multi-level NAND memory array; determine whether a second temperature difference between the third temperature and the second temperature is less than or equal to a second predefined threshold; and in response to the second temperature difference being less than or equal to the second predefined threshold, program the one or more NAND cells using a third set of data in a third pass.

[0090] Example 8 may include the subject matter of Example 7, wherein: the one or more NAND cells are four-level cells; the first set of data includes first page data; the second set of data includes second page data and third page data; the third set of data includes fourth page data; the first pass includes programming each of the one or more NAND cells into one of two levels based at least in part on the first set of data; the second pass includes programming each of the one or more NAND cells into one of eight levels based at least in part on the first set of data and the second set of data; the third pass includes programming each of the one or more NAND cells into one of sixteen levels based at least in part on the first set of data, the second set of data, and the third set of data.

[0091] Example 9 may include the subject matter of any one of Examples 1-3, wherein the logic circuit component is configured to send a temperature difference exceeded flag to the host controller in response to the temperature difference being greater than the predefined threshold.

[0092] Example 10 may include the subject matter of any one of Examples 1-9, wherein the logic circuit component is configured to determine the second temperature and determine whether the temperature difference between the second temperature and the first temperature is less than or equal to the predefined threshold in response to a temperature check command received from the host.

[0093] Example 11 may include the subject matter of any one of Examples 1-10, wherein the logic circuit component includes a processor.

[0094] Example 12 may include a data storage device including: a multi-level NAND memory array including one or more NAND cells associated with word lines; a memory controller coupled to the multi-level NAND array, wherein the memory controller is configured to: program the one or more NAND cells with a first set of data in a first pass; determine a first temperature of the multi-level NAND memory array associated with the first pass; determine a second temperature of the multi-level NAND memory array; determine whether a temperature difference between the second temperature and the first temperature is less than or equal to a predefined threshold; and in response to the temperature difference being less than or equal to the predefined threshold, program the one or more NAND cells with a second set of data in a second pass.

[0095] Example 13 may include the subject matter of Example 12, further including a temperature sensor, wherein the memory controller is configured to determine the first temperature and the second temperature at least in part based on the temperature sensed by the temperature sensor.

[0096] Example 14 may include the subject matter of any one of Examples 12-13, wherein the memory controller is further configured to store the first temperature in a flag byte associated with a page address.

[0097] Example 15 may include the subject matter of any one of Examples 12-14, wherein: the one or more NAND cells are four-level cells; the first set of data includes first page data and second page data; the second set of data includes third page data and fourth page data; the first pass includes programming each of the one or more NAND cells into one of four levels at least in part based on the first set of data; and the second pass includes programming each of the one or more NAND cells into one of sixteen levels at least in part based on the first set of data and the second set of data.

[0098] Example 16 may include the subject matter of any one of Examples 12-14, wherein the predefined threshold is a first predefined threshold, the temperature difference is a first temperature difference, the second temperature is associated with the second pass, and the logic circuit component is further configured to: determine a third temperature of the multi-level NAND memory array; determine whether a second temperature difference between the third temperature and the second temperature is less than or equal to a second predefined threshold; and perform one or more operations at least in part based on the result of the determination of the second temperature difference.

[0099] Example 17 may include the subject matter of any one of Examples 12 - 16, further including a host controller communicatively coupled to the memory controller, wherein the host controller is configured to send the first set of data to the memory controller.

[0100] Example 18 may include the subject matter of Example 17, wherein the memory control is configured to send a temperature difference exceeded flag to the host controller in response to the temperature difference being greater than the predefined threshold.

[0101] Example 19 may include the subject matter of Example 18, wherein the host controller is configured to perform an external data read to correct an error in the first set of data in response to the temperature difference exceeded flag.

[0102] Example 20 may include the subject matter of any one of Examples 17 - 19, wherein: the host control is configured to send a temperature check command to the memory controller; and the memory control is configured to determine whether the temperature difference between the second temperature and the first temperature is less than or equal to the predefined threshold in response to the temperature check command.

[0103] Example 21 may include the subject matter of any one of Examples 17 - 20, wherein the device is a solid state drive (SSD) and the host controller is an SSD controller.

[0104] Example 22 may include a method that includes: receiving a first set of data from a host controller; using a memory controller to program one or more NAND cells associated with word lines of a multi - level NAND memory array with the first set of data in a first pass; determining, by the memory controller, a first temperature of the multi - level NAND memory array associated with the first pass; determining, by the memory controller, a second temperature of the multi - level NAND memory array; determining, by the memory controller, whether the temperature difference between the second temperature and the first temperature is less than or equal to a predefined threshold; and performing, by the memory controller, one of the following: programming the one or more NAND cells with a second set of data in a second pass in response to the temperature difference being less than or equal to the predefined threshold; or sending a temperature difference exceeded flag to the host controller in response to the temperature difference being greater than the predefined threshold.

[0105] Example 23 may include the subject matter of Example 22, wherein the method includes storing the first temperature in a flag byte associated with a page address, and wherein determining whether the temperature difference between the second temperature and the first temperature is less than or equal to the predefined threshold includes reading the flag byte associated with the page address to obtain the stored first temperature.

[0106] Example 24 may include the subject matter of Example 22, wherein the multi-level NAND memory array is a triple-level cell (T1C) array, a quad-level cell (QLC) array, or a multi-level cell (MLC) array.

[0107] Example 25 may include the subject matter of Example 22, wherein the host controller is a solid-state drive (SSD) controller.

[0108] Example 26 may include an apparatus, comprising: a module for receiving a first set of data from a host controller; a module for programming, using a memory controller, one or more NAND cells associated with a word line of a multi-level NAND memory array in a first pass using the first set of data; a module for determining, by the memory controller, a first temperature of the multi-level NAND memory array associated with the first pass; a module for determining, by the memory controller, a second temperature of the multi-level NAND memory array; a module for determining, by the memory controller, whether a temperature difference between the second temperature and the first temperature is less than or equal to a predefined threshold; and a module for performing one of the following operations: programming the one or more NAND cells with a second set of data in a second pass in response to the temperature difference being less than or equal to the predefined threshold; or sending a temperature difference exceeded flag to the host controller in response to the temperature difference being greater than the predefined threshold.

[0109] Example 27 may include the subject matter of Example 26, wherein the apparatus includes a module for storing the first temperature in a flag byte associated with a page address, and wherein the module for determining whether the temperature difference between the second temperature and the first temperature is less than or equal to the predefined threshold includes a module for reading the flag byte associated with the page address to obtain the stored first temperature.

[0110] Example 28 may include the subject matter of any one of Examples 26-27, wherein the multi-level NAND memory array is a triple-level cell (T1C) array, a quad-level cell (QLC) array, or a multi-level cell (MLC) array.

[0111] Example 29 may include one or more non-transitory machine-readable media including instructions that, responsive to execution of the instructions by the memory controller, cause the memory controller to: using the memory controller, program one or more NAND cells associated with word lines of a multi-level NAND memory array in a first pass using the first set of data; determine a first temperature of the multi-level NAND memory array associated with the first pass; determine a second temperature of the multi-level NAND memory array associated with an internal read of the first set of data; determine a temperature difference between the second temperature and the first temperature; and perform one or more operations based at least in part on a result of the determination of the temperature difference.

[0112] Example 30 may include the subject matter of Example 29, wherein the one or more operations include one or more of the following: responsive to the temperature difference being less than or equal to a predefined threshold, program the one or more NAND cells in a second pass using a second set of data; and responsive to the temperature difference being greater than the predefined threshold, send a temperature difference exceeded flag to a host controller, facilitate an external data read of the one or more NAND cells, facilitate data correction associated with the one or more NAND cells, or facilitate recovery of data encoded by the one or more NAND cells.

[0113] Various embodiments may include any suitable combination of the embodiments described above, including alternative embodiments of the embodiments described above (and) in a conjunctive form (and) described (e.g., "and" may be "and / or"). Additionally, some embodiments may include one or more articles of manufacture (e.g., non-transitory media that are not computer-readable) storing instructions that, when executed, may cause the actions of any of the embodiments described above. Additionally, some embodiments may include an apparatus or system having any suitable means for performing the various operations of the embodiments described above.

[0114] The implementations described above, including those described in the abstract, are not exhaustive and do not limit the embodiments of the present disclosure to the precise forms disclosed. While specific implementations and examples described herein are for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as will be understood by those skilled in the art.

[0115] Based on the foregoing detailed description, these modifications may be made to the embodiments of the present disclosure. The terms used in the following claims should not be construed to limit the various embodiments of the present disclosure to the specific embodiments disclosed in the specification and claims. Instead, their scope should be determined entirely by the following claims, which should be interpreted according to established principles of claim interpretation.

Claims

1. A memory controller, comprising: A memory interface; And Logic circuit components coupled to the memory interface, wherein the logic circuit components are configured to perform the following operations: In a first pass, program one or more NAND cells of a multi-level NAND memory array using a first set of data via the memory interface; Determine a first temperature of the multi-level NAND memory array associated with the first pass; Determine a second temperature of the multi-level NAND memory array after determining the first temperature; Determine a temperature difference between the second temperature and the first temperature; and Perform one or more operations at least in part based on the result of the determination of the temperature difference, wherein the one or more operations include one or more of the following operations: In response to the temperature difference being less than or equal to a predefined threshold, program the one or more NAND cells using a second set of data in a second pass; and in response to the temperature difference being greater than the predefined threshold, send a flag indicating that the temperature difference exceeds the predefined threshold to a host controller to facilitate external data reading of the one or more NAND cells, data correction associated with the one or more NAND cells, or recovery of data encoded by the one or more NAND cells.

2. The memory controller according to claim 1, wherein, The logic circuit components are configured to store the first temperature in a flag byte associated with a page address.

3. The memory controller according to claim 1, wherein: The one or more NAND cells are quad-level cells; The first set of data includes first page data and second page data; The second set of data includes third page data and fourth page data; The first pass includes programming each of the one or more NAND cells into one of four levels at least in part based on the first set of data; and The second pass includes programming each of the one or more NAND cells into one of sixteen levels at least in part based on the first set of data and the second set of data.

4. The memory controller according to claim 1, wherein: The one or more NAND cells are quad-level cells; The first set of data includes first page data, second page data, and third page data; The second set of data includes fourth page data; The first pass includes programming each of the one or more NAND cells into one of eight levels at least in part based on the first set of data; and The second pass includes programming the one or more NAND cells into one of sixteen levels at least in part based on the first set of data and the second set of data.

5. The memory controller according to claim 1, wherein, The predefined threshold is a first predefined threshold, the temperature difference is a first temperature difference, the second temperature is associated with the second pass, and the logic circuit components are further configured to perform the following operations: Determine a third temperature of the multi-level NAND memory array after determining the second temperature; Determine whether a second temperature difference between the third temperature and the second temperature is less than or equal to a second predefined threshold; and In response to the second temperature difference being less than or equal to the second predefined threshold, program the one or more NAND cells in a third pass using a third set of data.

6. The memory controller according to claim 5, wherein: The one or more NAND cells are quad-level cells; The first set of data includes first page data; The second set of data includes second page data and third page data; The third set of data includes fourth page data; The first pass includes programming each of the one or more NAND cells into one of two levels based at least in part on the first set of data; The second pass includes programming each of the one or more NAND cells into one of eight levels based at least in part on the first set of data and the second set of data; The third pass includes programming each of the one or more NAND cells into one of sixteen levels based at least in part on the first set of data, the second set of data, and the third set of data.

7. The memory controller according to claim 1, wherein, The logic circuit component is configured to determine the second temperature and determine whether the temperature difference between the second temperature and the first temperature is less than or equal to the predefined threshold in response to a temperature check command received from a host.

8. The memory controller according to any one of claims 1-7, wherein, The logic circuit component includes a processor.

9. A data storage device, comprising: A multi-level NAND memory array including one or more NAND cells associated with word lines, wherein the one or more NAND cells are quad-level cells; A memory controller coupled to the multi-level NAND memory array, wherein the memory controller is configured to: Program the one or more NAND cells in a first pass using a first set of data, wherein the first set of data includes first page data and second page data, and the first pass includes programming each of the one or more NAND cells into one of four levels based at least in part on the first set of data; Determine a first temperature of the multi-level NAND memory array associated with the first pass; Determine a second temperature of the multi-level NAND memory array after determining the first temperature; Determine whether a temperature difference between the second temperature and the first temperature is less than or equal to a predefined threshold; and In response to the temperature difference being less than or equal to the predefined threshold, program the one or more NAND cells in a second pass using a second set of data, wherein the second set of data includes third page data and fourth page data, and the second pass includes programming each of the one or more NAND cells into one of sixteen levels based at least in part on the first set of data and the second set of data.

10. The device according to claim 9 further comprises a temperature sensor, wherein, The memory controller is used to determine the first temperature and the second temperature at least partially based on the temperature sensed by the temperature sensor.

11. The apparatus according to claim 9, wherein, The memory controller is further used to store the first temperature in a flag byte associated with the page address.

12. The device according to claim 9, wherein, The predefined threshold is a first predefined threshold, the temperature difference is a first temperature difference, the second temperature is associated with the second pass, and the logic circuit component is further used to perform the following operations: Determine a third temperature of the multi-level NAND memory array after determining the second temperature; Determine whether a second temperature difference between the third temperature and the second temperature is less than or equal to a second predefined threshold; And Perform one or more operations at least partially based on the result of the determination of the second temperature difference.

13. The apparatus according to any one of claims 9-12, further comprising a host controller communicatively coupled to the memory controller, wherein, The host controller is used to send the first set of data to the memory controller.

14. The apparatus according to claim 13, wherein, The memory control is used to send a temperature difference exceeded flag to the host controller in response to the temperature difference being greater than the predefined threshold.

15. The apparatus according to claim 14, wherein, The host controller is used to perform an external data read to correct errors in the first set of data in response to the temperature difference exceeded flag.

16. The apparatus according to claim 13, wherein: The host control is used to send a temperature check command to the memory controller; and The memory control is used to determine whether the temperature difference between the second temperature and the first temperature is less than or equal to the predefined threshold in response to the temperature check command.

17. The device according to claim 13, wherein The apparatus is a solid state drive (SSD) and the host controller is an SSD controller.

18. A method, comprising: Receiving a first set of data from a host controller; Using a memory controller to program one or more NAND cells associated with word lines of a multi-level NAND memory array with the first set of data in a first pass; Determining, by the memory controller, a first temperature of the multi-level NAND memory array associated with the first pass; Storing, by the memory controller, the first temperature in a flag byte associated with the page address; Determining, by the memory controller, a second temperature of the multi-level NAND memory array; Determining, by the memory controller, whether a temperature difference between the second temperature and the first temperature is less than or equal to a predefined threshold, including reading the flag byte associated with the page address to obtain the stored first temperature; And Performing, by the memory controller, one of the following operations: In response to the temperature difference being less than or equal to the predefined threshold, programming the one or more NAND cells with a second set of data in a second pass; Or In response to the temperature difference being greater than the predefined threshold, sending a temperature difference exceeded flag to the host controller.

19. The method according to claim 18, wherein, The multi-level NAND memory array is a triple-level cell (TLC) array, a quad-level cell (QLC) array, or a multi-level cell (MLC) array.

20. The method according to any one of claims 18-19, wherein, The host controller is a solid state drive (SSD) controller.

Images