Memory device and method of operating the same

Abstract

Disclosed is an operation method of a memory device, including: sequentially receiving an active command and a precharge command from an external device, during a first time interval, applying a first activation voltage to a selected word line in response to the active command, after a first time interval has elapsed from a first time point when the first active command is received, applying a second activation voltage to the selected word line, and applying a first deactivation voltage to the selected word line in response to the precharge command. The second activation voltage is lower than the first activation voltage and higher than the first deactivation voltage.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2018 - 0138085, filed with the Korean Intellectual Property Office on November 12, 2018, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Embodiments of the inventive concept described herein relate to semiconductor memories, and more particularly, to memory devices and methods of operating the same. Background Art

[0004] Semiconductor memory devices can be classified as volatile memory devices or non - volatile memory devices. In volatile memory devices, stored data is lost when the power is turned off, such as static random access memory (SRAM) or dynamic random access memory (DRAM). In non - volatile memory devices, stored data is retained even when the power is turned off, such as flash memory devices, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM).

[0005] Since DRAM devices have a fast operation speed, DRAM devices are widely used as buffer memories, system memories, or working memories of computing systems. Under the control of a controller, a general DRAM device activates a word line and performs read / write operations on memory cells connected to the activated word line. In this case, due to the high voltage applied to the word line, various interferences may occur within the memory device, thereby reducing the reliability of the memory device. Summary of the Invention

[0006] Embodiments of the inventive concept provide a memory device and a method of operating the same with improved reliability.

[0007] According to an exemplary embodiment, a method of operating a memory device includes receiving an active command from an external device during a first time interval and applying a first activation voltage to a selected word line in response to the active command. After a first time interval has elapsed from a first time point at which the active command is received, a second activation voltage is applied to the selected word line. A pre - charge command is received from the external device, and a first de - activation voltage is applied to the selected word line in response to the pre - charge command. The second activation voltage is lower than the first activation voltage and higher than the first de - activation voltage.

[0008] According to an example embodiment, a memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines; control logic circuitry that receives an active command from an external device; and a word line voltage control circuit. Under the control of the control logic circuitry that has received the active command, the word line voltage control circuit applies a first activation voltage to a selected word line among the plurality of word lines, and after a first time interval has elapsed from the time point at which the active command was received, applies a second activation voltage lower than the first activation voltage to the selected word line.

[0009] According to an example embodiment, a method of operating a memory device includes: receiving an active command from an external device during a first time interval, and in response to the active command, applying a first activation voltage to a selected word line and a first deactivation voltage to an unselected word line, after a first time interval has elapsed from the time point at which the active command was received, applying a second activation voltage lower than the first activation voltage to the selected word line and a second deactivation voltage lower than the first deactivation voltage to at least a first word line among the unselected word lines, receiving a precharge command from the external device, and in response to the precharge command, applying the first deactivation voltage to the selected word line and the unselected word lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the inventive concept will become apparent by describing example embodiments of the inventive concept in detail with reference to the accompanying drawings.

[0011] Figure 1 is a block diagram showing a memory system according to an example embodiment of the inventive concept.

[0012] Figure 2 is a diagram showing Figure 1 a block diagram of a memory device.

[0013] Figure 3 is a diagram showing Figure 2 a memory cell array.

[0014] Figure 4 is a diagram showing an operation of a memory device according to an example embodiment Figure 2 a flowchart of an operation of a memory device.

[0015] Figure 5 is a diagram for describing an operation of a memory device according to an example embodiment of the inventive concept.

[0016] Figures 6A to 6C is a diagram for describing an operation of a memory device according to an example embodiment Figure 2 a diagram of an operation of a memory device.

[0017] Figure 7 is a diagram showing an operation of a memory device according to an example embodiment Figure 2 a flowchart of an operation of a memory device.

[0018] Figure 8 is a diagram for describing operations of a flowchart according to Figure 7 of an example embodiment.

[0019] Figure 9 is a diagram for describing a method of applying a deactivation voltage to a memory device according to an example embodiment of the inventive concept.

[0020] Figure 10 is a block diagram showing a memory device according to an embodiment of the inventive concept.

[0021] Figure 11 is a flowchart showing operations of a memory device according to an example embodiment of Figure 10 of an example embodiment.

[0022] Figure 12A and Figure 12B is a diagram for describing operations of a memory device of a flowchart according to an example embodiment of Figure 11 of an example embodiment.

[0023] Figure 13 is a block diagram showing a memory device according to an embodiment of the inventive concept.

[0024] Figure 14 is a flowchart showing operations of a memory device according to an example embodiment of Figure 13 of an example embodiment.

[0025] Figure 15 is a diagram for describing operations of a memory device of a flowchart according to an example embodiment of Figure 14 of an example embodiment.

[0026] Figure 16 is a block diagram showing a word line voltage control circuit according to an example embodiment of Figure 13 of an example embodiment.

[0027] Figure 17A and Figure 17B is a diagram for describing operations of a memory device according to an example embodiment of Figure 2 of an example embodiment.

[0028] Figure 18 is a block diagram showing a memory module according to an example embodiment of the inventive concept.

[0029] Figure 19 is a block diagram showing an electronic system according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0030] Hereinafter, example embodiments of the inventive concept will be described in detail and clearly so that those of ordinary skill in the art can easily implement the inventive concept.

[0031] Figure 1 is a block diagram showing a memory system according to an exemplary embodiment of the inventive concept. Referring to Figure 1 , the memory system 10 may include a memory controller 11 and a memory device 100. The memory controller 11 may send an address ADDR and a command CMD to the memory device 100 to store data “DATA” in the memory device 100 or read data “DATA” stored in the memory device 100.

[0032] In an exemplary embodiment, the address ADDR may include a row address RA, a column address CA, a bank address BA, etc., and the command CMD may include an active command ACT, a write command WR, a read command RD, or a precharge command PRE. However, the inventive concept is not limited thereto, and the address ADDR and the command CMD may include various forms of addresses and commands.

[0033] Under the control of the memory controller 11, the memory device 100 may store data “DATA” provided from the memory controller 11 or may provide the stored data “DATA” to the memory controller 11.

[0034] Hereinafter, to easily describe the inventive concept, it is assumed that the memory device 100 is a dynamic random access memory (DRAM), and the memory controller 11 and the memory device 100 communicate with each other based on a double data rate (DDR) interface. However, the inventive concept is not limited thereto. The memory device 100 may be any one of various memory devices such as a static random access memory (SRAM), a synchronous DRAM (SDRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), a resistive random access memory (ReRAM), and a phase change random access memory (PRAM), and the memory controller 11 and the memory device 100 may communicate with each other based on any one of various interfaces such as a low power DDR (LPDDR) interface, a universal serial bus (USB) interface, a multimedia card (MMC) interface, a peripheral component interconnect (PCI) interface, a rapid PCI (PCI-E) interface, an advanced technology attachment (ATA) interface, a serial ATA (SATA) interface, a parallel ATA (PATA) interface, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), and an integrated drive electronics (IDE) interface.

[0035] In an exemplary embodiment, the memory device 100 may include a word line voltage control circuit 110. The word line voltage control circuit 110 may be configured to control various voltages to be provided to a plurality of word lines included in the memory device 100.

[0036] A conventional DRAM device applies an activation voltage of a high voltage to a selected word line among a plurality of word lines in response to an active command ACT from a memory controller 11, and applies a deactivation voltage to an unselected word line in response to a precharge command PRE from the memory controller 11. In a case where a time interval (e.g., tRAS) (hereinafter referred to as a “word line activation period”) between the active command ACT and the precharge command PRE increases, memory cells may deteriorate because the activation voltage is a high voltage.

[0037] A memory device 100 according to an embodiment of the inventive concept may apply a first activation voltage to a selected word line in response to an active command ACT from a memory controller 11, and may apply a second activation voltage lower than the first activation voltage to the selected word line after a reference time has elapsed. In this case, even if a time interval (i.e., tRAS period) between the active command ACT and the precharge command PRE increases, deterioration of the memory cells may be reduced because a voltage level applied to the selected word line decreases. Hereinafter, a method of controlling a word line voltage according to an embodiment of the inventive concept will be described more fully with reference to the accompanying drawings.

[0038] Figure 2 is a block diagram of a Figure 1 memory device. Referring to Figure 1 and Figure 2 , the memory device 100 may include a word line voltage control circuit 110, a memory cell array 120, a control logic circuit 130, and an input / output circuit 140.

[0039] The word line voltage control circuit 110 may be configured to control voltages to be provided to a plurality of word lines of the memory cell array 120, respectively. For example, the word line voltage control circuit 110 may be configured to generate a plurality of activation voltages VA and a plurality of deactivation voltages VDA.

[0040] The memory cell array 120 may include a plurality of memory cells. The plurality of memory cells may be connected to a plurality of word lines and a plurality of bit lines. The word lines may be connected to an X decoder X-DEC, and the bit lines may be connected to a Y decoder Y-DEC.

[0041] The control logic circuit 130 may control components of the memory device 100 in response to a command CMD from the memory controller 11. For example, the control logic circuit 130 may control the word line voltage control circuit 110 in response to an active command ACT from the memory controller 11 such that a first activation voltage VA1 of a plurality of activation voltages VAs is applied to a selected word line among a plurality of word lines. In an exemplary embodiment, after a reference time has elapsed from the time point when the active command ACT is received, the control logic circuit 130 may control the word line voltage control circuit 110 such that a second activation voltage VA2 lower than the first activation voltage VA1 is applied to the selected word line. The control logic circuit 130 may control the word line voltage control circuit 110 in response to a precharge command PRE from the memory controller 11 such that a deactivation voltage VDA is applied to the selected word line. For example, the deactivation voltage VDA may be a ground voltage VSS or a negative voltage.

[0042] In some examples, the first activation voltage VA1 and the second activation voltage VA2 may be generated through a pumping operation based on a power supply voltage VCC. In this case, a voltage level of each of the first activation voltage VA1 and the second activation voltage VA2 is higher than the power supply voltage VCC. In some examples, the first activation voltage VA1 may be generated through a pumping operation based on the second activation voltage VA2. In this case, the second activation voltage VA2 is the power supply voltage VCC.

[0043] In an exemplary embodiment, the control logic circuit 130 may control components of the memory device 100 in response to an operation command (e.g., a read command RD and a write command WR) from the memory controller 11 such that an operation corresponding to the operation command (e.g., a read operation or a write operation) is performed.

[0044] The input / output circuit 140 may be connected to the Y decoder Y-DEC and may temporarily store data to be stored in the memory cell array 120 or data provided from the memory controller 11. The input / output circuit 140 may exchange data “DATA” with the memory controller 11.

[0045] Figure 3 is a diagram showing Figure 2 the memory cell array. For ease of description, Figure 3 some memory cells of the memory cell array 120 are shown, but the inventive concept is not limited thereto. In addition, Figure 3 a memory cell MC as a DRAM cell is shown, but the inventive concept is not limited thereto.

[0046] Refer to Figure 2 and Figure 3, the memory cell array 120 may include a plurality of memory cells MC. Each memory cell MC may include an access transistor TR and a storage capacitor "C". A first end of the access transistor TR of the memory cell MC is connected to a plurality of bit lines BL1 to BLm, and a second end of the memory cell MC is connected to a first end of the corresponding storage capacitor "C" of the memory cell MC. A gate of the access transistor TR of the memory cell MC is connected to a plurality of word lines WL1 to WLn. A second end of the capacitor "C" may be connected to a voltage terminal. The voltage terminal may be connected to a voltage at a specific level (e.g., ground voltage or 1 / 2 of the power supply voltage VCC).

[0047] In an example embodiment, any one of the plurality of word lines WL1 to WLn may be selected in response to an active command ACT and a row address RA from the memory controller 11, and the selected word line may be activated when a first activation voltage VA1 is applied to the selected word line. When the selected word line is activated, data stored in the memory cells connected to the selected word line may be provided to the input / output circuit 140 through the plurality of bit lines BL1 to BLm.

[0048] Figure 4 is a flowchart showing the operation of a Figure 2 memory device according to an example embodiment. Referring to Figures 1 to 4 , in operation S110, the memory device 100 may receive an active command ACT from the memory controller 11. In an example embodiment, the memory device 100 may receive a row address RA together with the active command ACT from the memory controller 11.

[0049] In operation S120, the memory device 100 may apply a first activation voltage VA1 to the selected word line. For example, the memory device 100 may select any one of the plurality of word lines WL1 to WLn based on the row address RA received together with the active command ACT. The memory device 100 may apply the first activation voltage VA1 to the selected word line such that the selected word line is activated. In an example embodiment, the first activation voltage VA1 may be a high voltage sufficient to turn on the access transistor TR included in each memory cell MC connected to the selected word line.

[0050] In an example embodiment, the memory device 100 may apply a deactivation voltage VDA to the unselected word lines among the plurality of word lines. The deactivation voltage VDA may be a low voltage (e.g., ground voltage or negative voltage) sufficient to turn off the access transistor TR included in each memory cell MC connected to the unselected word line.

[0051] In operation S130, after a reference time interval T_ref has elapsed from the time point when the active command ACT is received, the memory device 100 may apply a second activation voltage VA2 to the selected word line. For example, the second activation voltage VA2 may be a voltage that is lower than the first activation voltage VA1 by a given level (or a predetermined level). In some examples, after a reference time interval T_ref has elapsed from the time point when the active command ACT is received, the memory device 100 may reduce the voltage of the selected word line from the first activation voltage VA1 to the second activation voltage VA2. In some examples, after a reference time interval T_ref has elapsed from the time point when the first activation voltage VA1 is applied, the memory device 100 may reduce the voltage of the selected word line from the first activation voltage VA1 to the second activation voltage VA2.

[0052] In an exemplary embodiment, the second activation voltage VA2 may have a level that turns on the access transistors TR of each memory cell MC connected to the selected word line, but the level may be lower than the first activation voltage VA1 and higher than the deactivation voltage VDA. For example, compared to the case of applying the first activation voltage VA1, when the second activation voltage VA2 having a level lower than the first activation voltage VA1 is applied to the selected word line, the degradation of the memory cells connected to the selected word line or any other word line adjacent to the selected word line may be reduced.

[0053] In operation S140, the memory device 100 may receive a precharge command PRE from the memory controller 11. In operation S150, the memory device 100 may apply a deactivation voltage VDA to the selected word line. For example, the memory device 100 may apply the deactivation voltage VDA to the selected word line in response to the precharge command PRE in order to deactivate the selected word line. For example, the deactivation voltage VDA may be applied to all word lines in response to the precharge command PRE.

[0054] Although not shown in the figure, the memory device 100 may receive various operation commands (e.g., a read command RD and a write command WR) from the memory controller 11 during the time interval between the active command ACT and the precharge command PRE. The memory device 100 may perform operations corresponding to the received operation commands.

[0055] Although not shown in the figure, after a time interval (e.g., a row precharge time tRP) has elapsed from the time point when the precharge command PRE is received, the memory device 100 may also receive an additional active command ACT from the memory controller 11.

[0056] Figure 5It is a diagram for describing the operation of a memory device according to an exemplary embodiment of the inventive concept. Hereinafter, in order to easily describe the technical concept of the inventive concept, embodiments of the inventive concept will be described with reference to an active command ACT and a precharge command PRE from a memory controller 11. However, the inventive concept is not limited thereto. For example, the memory device 100 may receive various operation commands (e.g., a read command RD, a write command WR, etc.) from the memory controller 11 between the active command ACT and the precharge command PRE, and may perform various operations corresponding to the received operation commands.

[0057] In the following drawings, for simplicity of illustration, signal waveforms are schematically depicted. However, the inventive concept is not limited thereto. For example, actual signal / voltage waveforms may be different from the signal / voltage waveforms of the graphs shown in the figures.

[0058] Reference Figure 1 、 Figure 2 and Figure 5 , a first graph GR1 shows the voltage applied to a selected word line of a conventional DRAM device. A second graph GR2 shows the voltage applied to a selected word line of the memory device 100 according to an exemplary embodiment of the inventive concept.

[0059] As understood from the first graph GR1, a conventional DRAM device receives an active command ACT and a row address RA (not shown) from the memory controller 11 at a 0th time point t0, and in response to the received active command ACT and row address RA, applies a first activation voltage VA1 to a selected word line. The conventional DRAM device maintains the voltage of the selected word line using the first activation voltage VA1 until a precharge command PRE is received (i.e., an nth time point tn). Then, in response to the precharge command PRE, a deactivation voltage VDA is applied to the selected word line.

[0060] In an exemplary embodiment, as understood from the second graph GR2, during a word line activation period tRAS, the memory device 100 may apply a first activation voltage VA1 to a selected word line in response to an active command ACT and a row address RA (not shown), and may apply a second activation voltage VA2 to the selected word line, for example, at a first time point t1 after a reference time interval T_ref has elapsed from the 0th time point t0 when the active command ACT is received. In the exemplary embodiment, the second activation voltage VA2 may be a voltage lower than the first activation voltage VA1 and higher than the deactivation voltage VDA.

[0061] In some examples, during a reference time interval T_ref, the memory device 100 may restore data in memory cells connected to a selected word line in response to an active command, and read data from / write data to the memory cells in response to read / write commands received from the memory controller 11.

[0062] For example, referring to the first graph GR1, as the word line activation period tRAS from the 0th time point t0 when the active command ACT is received to the nth time point tn when the precharge command PRE is received increases, the period during which the first activation voltage VA1 is applied to the selected word line may increase. In this case, since the high-voltage first activation voltage VA1 is applied to the selected word line for a long time, degradation may occur in the memory cells connected to or adjacent to the selected word line.

[0063] In an exemplary embodiment, referring to the second graph GR2, the first activation voltage VA1 is applied to the selected word line only during the reference time interval T_ref, and a second activation voltage VA2 lower than the first activation voltage VA1 is applied to the selected word line during the remaining word line activation period (i.e., the time interval from the first time point t1 to the nth time point tn). For example, compared with a conventional DRAM device, even if the word line activation period tRAS from the 0th time point t0 when the active command ACT is received to the nth time point tn when the precharge command PRE is received increases, since the first activation voltage VA1 is applied only during the reference time interval T_ref, degradation of the memory cells can be reduced.

[0064] In an exemplary embodiment, the difference ΔVA between the first activation voltage VA1 and the second activation voltage VA2 may be less than the difference between the second activation voltage VA2 and the deactivation voltage VDA. In an exemplary embodiment, the second activation voltage VA2 may be a voltage higher than the threshold voltage of the access transistor TR included in each memory cell MC. For example, as the voltage applied to the selected word line decreases from the first activation voltage VA1 to the second activation voltage VA2, degradation of the memory cells connected to or adjacent to the selected word line can be reduced.

[0065] In an example embodiment, the reference time interval T_ref may vary with the operation of the memory device 100. In an example embodiment, the reference time interval T_ref may be a period of time required to establish data from a memory cell connected to a selected word line in the input / output circuit 140. For example, during the reference time interval T_ref, the memory device 100 may read data from a memory cell connected to a selected word line and may establish the read data in the input / output circuit 140. Alternatively, during the reference time interval T_ref, the memory device 100 may read data from a memory cell connected to a selected word line, may establish the read data in the input / output circuit 140, and may restore the established data in the memory cell connected to the selected word line.

[0066] Figures 6A to 6C is a diagram for describing the operation of a memory device according to an example embodiment. First, referring to Figure 2 FIGs. Figure 1 , Figure 2 and Figures 6A to 6C , at the 0th time point t0, the memory device 100 may receive an active command ACT from the memory controller 11 and may apply a first activation voltage VA1 to a selected word line in response to the received active command ACT. At a first time point t1 after a first reference time interval T_ref1 has elapsed since the 0th time point t0, the memory device 100 may apply a second activation voltage VA2 to the selected word line. For example, the memory device 100 may reduce the voltage level applied to the selected word line after a first reference time interval T_ref1 has elapsed since the 0th time point t0.

[0067] As Figure 6A shown, at a second time point t2 after a second reference time interval T_ref2 has elapsed since the first time point t1, the memory device 100 may apply the first activation voltage VA1 to the selected word line again. For example, in the case where the second activation voltage VA2 is applied during the second reference time interval T_ref2, current may leak from the memory cell connected to the selected word line. Due to the leakage current, the data stored in the memory cell connected to the selected word line may be lost. In this case, the memory device 100 may perform a restore operation on the memory cell connected to the selected word line by applying the first activation voltage VA1 to the selected word line at the second time point t2.

[0068] In an exemplary embodiment, the speed of memory cell operation when the first activation voltage VA1 is applied to a selected word line can be higher (or faster) than the speed of memory cell operation when the second activation voltage VA2 is applied to the selected word line. The reason is that the access transistor of each memory cell operates quickly when a higher voltage is applied to the corresponding word line. For example, by increasing the voltage of the selected word line from the second activation voltage VA2 to the first activation voltage VA1 within a specific time interval, a specific operation (e.g., a recovery operation) can be quickly performed on the memory cell.

[0069] In an exemplary embodiment, the second time point t2 at which the first activation voltage VA1 is applied can be determined by a command from the memory controller 11 instead of the second reference time interval T_ref2. For example, the memory device 100 can receive various operation commands (e.g., a read command RD and a write command WR) from the memory controller 11 during a word line activation period tRAS between an active command ACT and a precharge command PRE, and can perform various operations corresponding to the received operation commands.

[0070] For example, in the case where the memory device 100 receives a write command WR from the memory controller 11 at the second time point t2, the memory device 100 can perform an operation corresponding to the write command WR. The write operation includes writing data into the memory cells connected to the selected word line. To perform the write operation, the memory device 100 can apply the first activation voltage VA1 to the selected word line at the second time point t2. Since the first activation voltage VA1 is higher than the second activation voltage VA2, the speed of the write operation can be increased when the first activation voltage VA1 is applied to the selected word line. After completing the write operation, for example, at the third time point t3, the memory device 100 can apply the second activation voltage VA2 to the selected word line.

[0071] For example, in the case where the memory device 100 receives a read command RD from the memory controller 11 at a second time point t2, the memory device 100 may perform an operation corresponding to the read command RD. The read operation includes reading data from memory cells connected to a selected word line. To perform the read operation, the memory device 100 may apply a first activation voltage VA1 to the selected word line at the second time point t2. Since the first activation voltage VA1 is higher than the second activation voltage VA2, the speed of the read operation may be increased when the first activation voltage VA1 is applied to the selected word line. After completing the read operation, for example, at a third time point t3, the memory device 100 may apply the second activation voltage VA2 to the selected word line. In an exemplary embodiment, in response to the read command RD, the memory device 100 may output the read data without supplying the first activation voltage VA1 to the selected word line. For example, data stored in the memory cells connected to the selected word line may be set in the I / O circuit 140 through various operations at a first reference time interval T_ref1. Thus, even without supplying the first activation voltage VA1 to the selected word line, the data set in the I / O circuit 140 may be output to the memory controller 11.

[0072] In an exemplary embodiment, the memory device 100 according to the inventive concept may repeatedly apply the first activation voltage VA1 and the second activation voltage VA2 to the selected word line during a word line activation period tRAS between an active command ACT and a precharge command PRE. The time interval for applying the first activation voltage VA1 and the second activation voltage VA2 may be variously changed or modified according to a given reference time and an operation command from the memory controller 11.

[0073] As Figure 6B shown, the memory device 100 may maintain the second activation voltage VA2 of the selected word line from a first time point t1 to an nth time point tn (i.e., the time point at which the precharge command PRE is received). In response to the precharge command PRE, the memory device 100 may apply the first activation voltage VA1 to the selected word line from the nth time point tn to the (n + 1)th time point tn+1, for example, during a reference time interval T_ref. In this case, the amount of the reference time interval T_ref may be variable. Thereafter, the memory device 100 may apply a deactivation voltage VDA to the selected word line.

[0074] For example, in response to a precharge command PRE, the memory device 100 may complete the operation being executed and then may perform a precharge operation on the bit lines. Before precharging the bit lines, the memory device 100 may perform a recovery operation to retain the data stored in the memory cells connected to the selected word line. In this case, to increase the speed of the recovery operation, the memory device 100 may apply a first activation voltage VA1 to the selected word line.

[0075] As Figure 6C shown, during a word line activation period tRAS, the memory device 100 may repeatedly apply a first activation voltage VA1 and a second activation voltage VA2 to the selected word line. After that, in response to the precharge command PRE, the memory device 100 may apply the first activation voltage VA1 to the selected word line. Refer to Figure 6A and Figure 6B the description Figure 6C of the operation of the memory device 100 shown (i.e., the operation of repeatedly applying the first activation voltage VA1 and the second activation voltage VA2 during the word line activation period tRAS and the operation of applying the first activation voltage VA1 in response to the precharge command PRE), and thus, additional description will be omitted to avoid redundancy.

[0076] As described above, during the word line activation period tRAS, the memory device 100 may repeatedly apply the first activation voltage VA1 and the second activation voltage VA2 to the selected word line. In this way, since the time interval of applying the high voltage first activation voltage VA1 during the word line activation period tRAS is reduced, the degradation of the memory cells due to the high voltage first activation voltage VA1 can be reduced. Accordingly, a memory device having improved reliability and improved performance is provided.

[0077] Figure 7 is a flowchart illustrating the operation of a Figure 2 memory device according to an exemplary embodiment. Figure 8 is a diagram for describing the operation of a flowchart according to an exemplary embodiment according to Figure 7 the flowchart.

[0078] Refer to Figure 2 , Figure 7 and Figure 8 , in operation S210, the memory device 100 may receive an active command ACT from the memory controller 11.

[0079] In operation S220, the memory device 100 may apply a first activation voltage VA1 to the selected word line and may apply a first deactivation voltage VDA1 to the unselected word lines. For example, as described above, the memory device 100 may receive an active command ACT together with a row address RA from the memory controller 11. The memory device 100 may determine the word line corresponding to the row address RA among the plurality of word lines WL1 to WLn as the selected word line and may determine the remaining word lines as unselected word lines. To activate the selected word line, the memory device 100 may apply the first activation voltage VA1 to the selected word line and may apply the first deactivation voltage VDA1 to the unselected word lines.

[0080] In operation S230, after a reference time interval T_ref has elapsed from the 0th time point, the memory device 100 may apply a second deactivation voltage VDA2 to the unselected word lines. The first deactivation voltage VDA1 may be a voltage sufficient to turn off the access transistor TR included in each memory cell MC (e.g., a ground voltage or a negative voltage). The second deactivation voltage VDA2 may be a voltage lower than the first deactivation voltage VDA1. For example, when the second deactivation voltage VDA2 lower than the first deactivation voltage VDA1 is applied to the unselected word lines, degradation occurring at the memory cells connected to the unselected word lines due to the high voltage of the selected word line (i.e., the first activation voltage VA1) may be reduced.

[0081] For example, as Figure 8 shown, at the 0th time point t0, the memory device 100 may apply the first activation voltage VA1 to the selected word line and may apply the first deactivation voltage VDA1 to the unselected word lines. At a first time point t1 after a reference time interval T_ref has elapsed from the 0th time point t0, the memory device 100 may apply the second deactivation voltage VDA2 to the unselected word lines. For example, at the first time point t1, the memory device 100 may reduce the voltage of the unselected word lines from the first deactivation voltage VDA1 to the second deactivation voltage VDA2. In some examples, at the 0th time point t0, the memory device 100 may reduce the voltage of the unselected word lines from the first deactivation voltage VDA1 to the second deactivation voltage VDA2.

[0082] In this case, even if the word line activation period tRAS increases, since the voltage of the unselected word lines is maintained at the relatively low second deactivation voltage VDA2, degradation of the memory cells connected to the unselected word lines may be reduced.

[0083] In operation S240, the memory device 100 may receive a precharge command PRE from the memory controller 11. In operation S250, the memory device 100 may apply the first deactivation voltage VDA1 to the selected word line and the unselected word lines.

[0084] As described above, during the word line activation period tRAS, the memory device 100 may reduce the voltage of the unselected word line from the first deactivation voltage VDA1 to the second deactivation voltage VDA2. In this way, the degradation of the memory cells connected to the unselected word line due to the high voltage of the selected word line (i.e., the first activation voltage VA1) during the word line activation period tRAS can be reduced.

[0085] Figure 9 is a diagram for describing a method of applying a deactivation voltage to a memory device according to an exemplary embodiment of the inventive concept. For ease of description, components unnecessary for describing the method of applying the deactivation voltage are omitted, and it is assumed that the memory device 100 includes first to eighth word lines WL1 to WL8. However, the inventive concept is not limited thereto.

[0086] Refer to Figure 2 、 Figure 8 and Figure 9 , the memory device 100 may apply the first activation voltage VA1 to the selected word line (e.g., the fourth word line WL4) in response to the active command ACT. In this case, the remaining word lines other than the selected word line (e.g., the first word line WL1, the second word line WL2, the third word line WL3, the fifth word line WL5, the sixth word line WL6, the seventh word line WL7, and the eighth word line WL8) may be unselected word lines.

[0087] The memory device 100 may apply the first deactivation voltage VDA1 or the second deactivation voltage VDA2 to the unselected word line. For example, the memory device 100 may apply the second deactivation voltage VDA2 to the unselected word lines adjacent to the selected word line (e.g., the third word line WL3 and the fifth word line WL5), and may apply the first deactivation voltage VDA1 to the remaining unselected word lines (e.g., the first word line WL1, the second word line WL2, the sixth word line WL6, the seventh word line WL7, and the eighth word line WL8). For example, the memory device 100 may apply a relatively low deactivation voltage (e.g., the second deactivation voltage VDA2) to the unselected word lines adjacent to the selected word line, and may apply a relatively high deactivation voltage (e.g., the first deactivation voltage VDA1) to the remaining unselected word lines.

[0088] Although not shown in Figure 9 , the adjacent unselected word lines may also indicate one or more unselected word lines physically adjacent to the selected word line. In the exemplary embodiment, the memory device 100 may be configured to control the word line voltage under the condition that a plurality of word lines are classified into groups.

[0089] Figure 10is a block diagram showing a memory device according to an embodiment of the inventive concept. Refer to Figure 10 , the memory device 300 may include a word line voltage control circuit 310, a memory cell array 320, a control logic circuit 330, an input / output circuit 340, and an active command counter 350. The word line voltage control circuit 310, the memory cell array 320, the control logic circuit 330, and the input / output circuit 340 have been described above, and thus additional descriptions will be omitted to avoid redundancy.

[0090] The active command counter 350 of the memory device 300 may count active commands ACT from the memory controller 11 (refer to Figure 1 ). For example, the active command counter 350 may count the number of active commands ACT received from the memory controller 11 regarding a specific word line during a predetermined time period. For example, the active command counter 350 may count the number of active commands ACT accumulated for each of a plurality of word lines.

[0091] The word line voltage control circuit 110 may generate various word line voltages, such as an activation voltage Vas, a deactivation voltage VDA, and a variable deactivation voltage VDA_v, according to the counting result of the active command counter 350. For example, the word line voltage control circuit 310 may adjust the variable deactivation voltage VDA_v based on the counting result of the active command counter 350.

[0092] In an exemplary embodiment, as the count value of the active command counter 350 increases, the variable deactivation voltage VDA_v may decrease. For example, in the case where active commands ACT are frequently repeated regarding a specific word line (i.e., in the case where access to a specific word line is frequently repeated), a high voltage may be frequently applied to the specific word line, resulting in deterioration of memory cells connected to one or more adjacent word lines. In this case, deterioration of memory cells connected to one or more adjacent word lines (i.e., one or more unselected word lines) may be reduced by decreasing the deactivation voltage to be applied to the one or more adjacent word lines.

[0093] Figure 11 is a flowchart showing the operation of a Figure 10 memory device according to an exemplary embodiment. Figure 12A and Figure 12B are diagrams for describing the operation of a memory device according to a flowchart according to an exemplary embodiment according to Figure 11 the flowchart.

[0094] Refer to Figure 10 , Figure 11 , Figure 12A and Figure 12B, in operation S310, the memory device 300 may receive an active command ACT.

[0095] In operation S320, the memory device 300 may determine the number of active commands ACT during a predetermined period. For example, the active command counter 350 of the memory device 300 may count the number of active commands ACT received from the memory controller 11 (refer to Figure 1 ). In an exemplary embodiment, the number of active commands ACT may be managed for each word line or each group of word lines. For example, the active command counter 350 may count the number of active commands ACT for each of a plurality of word lines.

[0096] In operation S330, the memory device 300 may adjust the variable deactivation voltage VDA_v based on the determined result. For example, as Figure 2 shown. Referring to Figure 12A , when the number (i.e., the count value) of activation instructions ACT associated with the selected word line is "a", the memory device 300 may adjust the variable deactivation voltage VDA_v to a first variable deactivation voltage VDA_v1.

[0097] As Figure 12B shown, when the number (i.e., the count value) of activation instructions ACT associated with the selected word line is "b" (where the value of "b" is greater than the value of "a"), the memory device 100 may adjust the variable deactivation voltage VDA_v to a second variable deactivation voltage VDA_v2 lower than the first variable deactivation voltage VDA_v1. For example, as the number of active commands ACT increases, the memory device 300 may decrease the level of the variable deactivation voltage VDA_v.

[0098] In operation S340, the memory device 300 may apply a first activation voltage VA1 to the selected word line at a 0th time point t0 in response to the active command ACT, and may apply the adjusted variable deactivation voltage VDA_v to the unselected word lines. In some examples, after a reference time interval T_ref has elapsed from the 0th time point t0 when the active command ACT is received, the memory device 300 may apply the first variable deactivation voltage VDA_v1 to the unselected word lines at a first time point t1. In some examples, after a reference time interval T_ref has elapsed from the 0th time point t0 when the active command ACT is received, the memory device 300 may apply the second variable deactivation voltage VDA_v2 to the unselected word lines at a first time point t1.

[0099] In operation S350, the memory device 300 may receive a precharge command PRE. In operation S360, the memory device 300 may apply a deactivation voltage VDA to the selected word line and the unselected word lines. In an exemplary embodiment, the first variable deactivation voltage VDA_v1 and the second variable deactivation voltage VDA_v2 may be lower than the deactivation voltage VDA.

[0100] As described above, the memory device 300 according to an embodiment of the inventive concept may adjust the level of the deactivation voltage to be applied to the unselected word lines according to the number of activation commands ACT. In this way, in the case where the activation command ACT is frequently repeated with respect to a specific word line (i.e., in the case where access to a specific word line is frequently repeated), deterioration of the memory cells connected to the unselected word lines due to the high voltage repeatedly applied to the specific word line may be reduced by reducing the level of the deactivation voltage to be applied to the unselected word lines.

[0101] Figure 13 is a block diagram showing a memory device according to an embodiment of the inventive concept. Refer to Figure 13 , the memory device 400 may include a word line voltage control circuit 410, a memory cell array 420, a control logic circuit 430, an input / output circuit 440, and a timer 450. The word line voltage control circuit 410, the memory cell array 420, the control logic circuit 430, and the input / output circuit 440 have been described above, and thus, additional descriptions will be omitted to avoid redundancy.

[0102] The timer 450 may be configured to detect an elapsed time that has elapsed since a time point when an activation command ACT is received from the memory controller 11 (refer to Figure 1 ). The word line voltage control circuit 410 may be configured to adjust the variable deactivation voltage VDA_v based on the elapsed time detected from the timer 450. For example, as time continues from the time point when the activation command ACT is received, the word line voltage control circuit 410 may reduce the level of the variable deactivation voltage to be applied to the unselected word lines. The reduction of the variable deactivation voltage can prevent deterioration of the memory cells connected to the unselected word lines that occurs when a high voltage (e.g., a first activation voltage VA1) is applied to the selected word line during a word line activation period tRAS and a certain time has elapsed.

[0103] For example, since the word line voltage control circuit 410 reduces the voltage (e.g., the variable deactivation voltage) to be applied to the unselected word lines according to the time elapsed since the time point when the activation command ACT is received, deterioration of the memory cells connected to the unselected word lines due to the high voltage applied to the selected word line is reduced.

[0104] Figure 14is a flowchart showing the operation of a memory device according to an exemplary embodiment. Figure 13 of the memory device. Figure 15 is a diagram for describing the operation of a memory device according to the flowchart according to an exemplary embodiment. Figure 15 of the memory device.

[0105] Referring Figures 13 to 15 , in operation S410, the memory device 400 may receive an active command ACT.

[0106] In operation S420, the memory device 400 may apply a first activation voltage VA1 to the selected word line and may apply a variable deactivation voltage VDA_v to the unselected word lines. In operation S430, the memory device 400 may decrease the level of the variable deactivation voltage VDA_v over time. In operation S440, the memory device 400 may receive a precharge command PRE. In operation S450, the memory device 400 may apply a deactivation voltage VDA to the selected word line and the unselected word lines.

[0107] For example, as Figure 15 shown, at the 0th time point t0 when the active command ACT is received, the memory device 400 may apply a first activation voltage VA1 to the selected word line and may apply a first variable deactivation voltage VDA_v1 to the unselected word lines. After a given time, for example, at the first time point t1, the memory device 400 may decrease the voltage of the unselected word line from the first variable deactivation voltage VDA_v1 to a second variable deactivation voltage VDA_v2. After a given time, for example, at the second time point t2 and the third time point t3, the memory device 400 may decrease the voltage of the unselected word line to a third variable deactivation voltage VDA_v3 and a fourth variable deactivation voltage VDA_v4, respectively. At the nth time point tn, the memory device 400 may receive a precharge command PRE and may apply a deactivation voltage VDA to the selected word line and the unselected word lines in response to the received precharge command PRE.

[0108] In an exemplary embodiment, the first variable deactivation voltage VDA_v1 applied to the unselected word lines in response to the active command ACT may be lower than or equal to the deactivation voltage VDA. In an exemplary embodiment, the level of the first variable deactivation voltage VDA_v1 applied to the unselected word lines in response to the active command ACT may be determined according to the number of active commands ACT associated with the selected word line. For example, as the number of active commands ACT associated with the selected word line increases, the level of the first variable deactivation voltage VDA_v1 may be decreased.

[0109] In an example embodiment, a decrement of the first variable deactivation voltage VDA_v1 may be predetermined, or a decrement of the first variable deactivation voltage VDA_v1 may be set during operation of the memory device 400. For example, as the number of active commands ACT associated with the selected word line increases, the memory device 400 may increase the decrement of the variable deactivation voltage.

[0110] Figure 16 is a block diagram showing a Figure 13 word line voltage control circuit according to an example embodiment. Referring to Figure 13 , Figure 15 and Figure 16 , the word line voltage control circuit 410 may include a voltage generator 411 and a charge pump 412.

[0111] The voltage generator 411 may be configured to generate a first activation voltage VA1 and a deactivation voltage VDA.

[0112] The charge pump 412 may be configured to generate and output a variable deactivation voltage VDA_v based on the deactivation voltage VDA. For example, the timer 450 may be configured to periodically output a reference signal RS based on a detection time elapsed from a time point when the active command ACT is received. The charge pump 412 may be configured to pump the deactivation voltage VDA in a negative direction in response to the reference signal RS from the timer 450.

[0113] In some examples, the voltage generator 411 may generate the first activation voltage VA1 in response to the reference signal RS from the timer 450.

[0114] Specifically, as Figure 15 shown, the timer 450 may output the reference signal RS at a first time point tⱼ that is a given time after a 0th time point t₀ when the active command ACT is received. The charge pump 412 may perform one or more charge pumping operations in response to the reference signal RS to reduce the variable deactivation voltage VDA_v from a first variable deactivation voltage VDA_v₁ to a second variable deactivation voltage VDA_v₂. Similarly, the timer 450 may output the reference signal RS at a second time point t₂, and the charge pump 412 may reduce the variable deactivation voltage VDA_v from the second variable deactivation voltage VDA_v₂ to a third variable deactivation voltage VDA_v₃ in response to the reference signal.

[0115] Although not shown in Figure 16As shown, the word line voltage control circuit 410 may further include an additional charge pump. The additional charge pump may be used to generate the activation voltage VA or to adjust the level of the activation voltage VA. In some examples, the voltage generator 411 may include an additional charge pump configured to generate a first activation voltage VA1 based on a second activation voltage VA2 or a power supply voltage VCC.

[0116] In an example embodiment, the word line voltage control circuit 410 may adjust the variable deactivation voltage by performing a charge pumping operation based on the count value of the active command counter 350 described above. Figure 10 described above.

[0117] Figure 17A and Figure 17B are diagrams for describing the operation of a memory device according to an example embodiment. Below, for ease of description, a memory device 100 according to Figure 2 is described with reference to the graphs of Figure 2 and Figure 17A and Figure 17B of the inventive concept, but the inventive concept is not limited thereto.

[0118] Examples of adjusting the voltage of a selected word line (i.e., activation voltage) during a word line activation period tRAS are described with reference to Figure 4 , Figure 5 , Figure 6A and Figure 6C , and examples of adjusting the voltage of an unselected word line (i.e., deactivation voltage) are described with reference to Figures 7 to 11 , Figure 12A , Figure 12B and Figures 13 to 16 . However, the inventive concept is not limited thereto.

[0119] For example, with reference to Figure 2 and Figure 17A , in response to an active command ACT, the memory device 100 may apply a first activation voltage VA1 to a selected word line and may apply a first deactivation voltage VDA1 to an unselected word line. After a reference time interval T_ref has elapsed from the 0th time point t0 at which the active command ACT is received (i.e., at a first time point t1), the memory device 100 may reduce the voltage of the selected word line from the first activation voltage VA1 to a second activation voltage VA2 and may reduce the voltage of the unselected word line from the first deactivation voltage VDA1 to a second deactivation voltage VDA2. In some examples, at the 0th time point t0, the memory device 100 may reduce the voltage of the unselected word line from the first deactivation voltage VDA1 to the second deactivation voltage VDA2. At the nth time point tn, the memory device 100 may apply the first deactivation voltage VDA1 to the selected word line and the unselected word line in response to a precharge command PRE.

[0120] Alternatively, referring to Figure 2 and Figure 17B in response to an active command ACT, the memory device 100 may apply a first activation voltage VA1 to a selected word line and may apply a first variable deactivation voltage VDA_v1 to an unselected word line. After a given time has elapsed from the 0th time point t0 at which the active command ACT is received (i.e., at a first time point t1), the memory device 100 may reduce the voltage of the selected word line from the first activation voltage VA1 to a second activation voltage VA2 and may reduce the voltage of the unselected word line from the first variable deactivation voltage VDA_v1 to a second variable deactivation voltage VDA_v2. Thereafter, as time elapses, the memory device 100 may reduce the voltage of the unselected word line to a third variable deactivation voltage VDA_v3 at a second time point t2 and may reduce the voltage of the unselected word line to a fourth variable deactivation voltage VDA_v4 at a third time point t3. The memory device 100 may re-apply the first activation voltage VA1 in response to a precharge command PRE at an nth time point tn and may apply a deactivation voltage VDA to the selected word line and the unselected word line in response to the precharge command PRE at an (n + 1)th time point tn+1.

[0121] In an exemplary embodiment, various parameters such as the magnitude of the second activation voltage VA2, the magnitude of the first variable deactivation voltage VDA_v1, the reduction of the variable deactivation voltage, and the reference time may be preset or may be updated while the memory device 100 is operating. In an exemplary embodiment, the parameters may be determined based on the number of active commands ACT input to the memory device 100 with respect to a specific word line during a predetermined period.

[0122] According to Figure 17A and Figure 17B the inventive concept of the graph is exemplary, and the inventive concept is not limited thereto. For example, a memory device according to the inventive concept may operate in a manner based on making various changes or combinations to the above-described embodiments without departing from the technical concept of the inventive concept. For example, a memory device according to an embodiment of the inventive concept may adjust the voltage of a selected word line and the voltage of an unselected word line in various ways during a word line activation period tRAS.

[0123] Figure 18 is a block diagram showing a memory module according to an exemplary embodiment of the inventive concept. Referring to Figure 18, the memory module 1000 may include a register clock driver (RCD) 1100, a plurality of DRAM devices 1210 to 1290, and a plurality of data buffers DB. The RCD 1100 may receive a command / address CA and a clock signal CK from an external device (e.g., a host or a memory controller). In response to the received signals, the RCD 1100 may send the command / address CA to the plurality of DRAM devices 1210 to 1290 and may control the plurality of data buffers DB.

[0124] The plurality of DRAM devices 1210 to 1290 may be respectively connected to the plurality of data buffers DB through memory data lines MDQ. In an exemplary embodiment, each of the plurality of DRAM devices 1210 to 1290 may be a memory device described in reference Figures 1 to 5 , Figure 6A , Figure 6B , Figures 7 to 11 , Figure 12A , Figure 12B , Figures 13 to 16 , Figure 17A and Figure 17B , or may operate according to the operation methods described in reference Figures 1 to 5 , Figure 6A , Figure 6B , Figures 7 to 11 , Figure 12A , Figure 12B , Figures 13 to 16 , Figure 17A and Figure 17B . The plurality of data buffers DB may send data to and receive data from an external device (e.g., a host or a memory controller) through a plurality of data lines DQ.

[0125] In an exemplary embodiment, Figure 18 the memory module 1000 shown may have a form factor of a load-reduced dual in-line memory module (LRDIMM). However, the inventive concept is not limited thereto. For example, the memory module 1000 may have a form factor of a registered DIMM (RDIMM) that does not include a plurality of data buffers DB.

[0126] Figure 19 is a block diagram showing an electronic system according to an exemplary embodiment of the inventive concept. Referring to Figure 19 , the electronic system 2000 may be implemented in the form of a portable communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, or a wearable device, or in the form of a computing system such as a personal computer, a server, a workstation, or a notebook computer.

[0127] The electronic system 2000 may include an application processor 2100 (or a central processing unit), a display 2220, and an image sensor 2230. The application processor 2100 may include a DigRF master 2110, a Display Serial Interface (DSI) host 2120, a Camera Serial Interface (CSI) host 2130, and a physical layer 2140.

[0128] The DSI host 2120 may communicate with the DSI device 2225 of the display 2220 via DSI. In an example embodiment, an optical serializer SER may be implemented in the DSI host 2120. For example, an optical deserialzier DES may be implemented in the DSI device 2225. The CSI host 2130 may communicate with the CSI device 2235 of the image sensor 2230 via CSI. In an example embodiment, an optical deserialzier DES may be implemented in the CSI host 2130. For example, an optical serializer SER may be implemented in the CSI device 2235.

[0129] The electronic system 2000 may communicate with the application processor 2100 and may further include a Radio Frequency (RF) chip 2240. The RF chip 2240 includes a physical layer 2242, a DigRF slave 2244, and an antenna 2246. In an example embodiment, the physical layer 2242 of the RF chip 2240 and the physical layer 2140 of the application processor 2100 may exchange data with each other via a MIPI DigRF interface.

[0130] The electronic system 2000 may further include a working memory 2250 and an embedded / card storage device 2255. The working memory 2250 and the embedded / card storage device 2255 may store data provided from the application processor 2100. The working memory 2250 and the embedded / card storage device 2255 may provide the data stored therein to the application processor 2100. The working memory 2250 may temporarily store data that has been or will be processed by the application processor 2100. In an example embodiment, the working memory 2250 may be the memory device described in reference Figures 1 to 5 、 Figure 6A 、 Figure 6B 、 Figures 7 to 11 、 Figure 12A 、 Figure 12B 、 Figures 13 to 16 、[[ID=2)) Figure 17A and Figure 17B described. Alternatively, the working memory 2250 may be based on reference Figures 1 to 5 、 Figure 6A 、 Figure 6B 、 Figures 7 to 11 、 Figure 12A 、 Figure 12B 、 Figures 13 to 16 、 Figure 17A andFigure 17B Operate according to the described operation method.

[0131] The electronic system 2000 can communicate with an external system through Worldwide Interoperability for Microwave Access (WiMAX) 2260, Wireless Local Area Network (WLAN) 2262, and Ultra-Wideband (UWB) 2264.

[0132] The electronic system 2000 may further include a speaker 2270 and a microphone 2275 to process voice information. The electronic system 2000 may further include a Global Positioning System (GPS) device 2280 for processing location information. The electronic system 2000 may further include a bridge chip 2290 for managing connections between peripheral devices.

[0133] According to the above-described disclosed embodiments of the inventive concept, a memory device may control various voltages (e.g., an activation voltage or a deactivation voltage) to be provided to a selected word line or an unselected word line during a word line activation period tRAS. In this way, since the time interval of applying the activation voltage of a high voltage is reduced or the voltage applied to the unselected word line is reduced, degradation occurring at the memory cell may be reduced. Accordingly, a memory device having improved reliability and improved performance is provided.

[0134] According to the above-described disclosed embodiments of the inventive concept, a memory device may adjust the level of an activation voltage or a deactivation voltage to be provided to a selected word line or an unselected word line during a word line activation period tRAS. In this way, degradation of the memory cell due to the activation voltage of a high voltage may be reduced. Accordingly, a memory device having improved reliability and improved performance and an operation method thereof are provided.

[0135] Although the inventive concept has been described with reference to exemplary embodiments of the present invention, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A method of operating a memory device, the method comprising: Receiving an active command from an external device; During a first time interval, applying a first activation voltage to a selected word line in response to the active command; After the first time interval has elapsed from a first time point when the active command is received, applying a second activation voltage to the selected word line; During the first time interval, applying a second deactivation voltage to unselected word lines in response to the active command; And After the first time interval, applying a third deactivation voltage lower than the second deactivation voltage to the unselected word lines; After a second time interval has elapsed from the first time interval, applying a fourth deactivation voltage lower than the third deactivation voltage to the unselected word lines; Receiving a precharge command from the external device; During a third time interval, reapplying the first activation voltage to the selected word line in response to the precharge command; And After the third time interval, applying a first deactivation voltage to the selected word line, Wherein the second activation voltage is lower than the first activation voltage and higher than the first deactivation voltage, Wherein a recovery operation is performed on memory cells connected to the selected word line during the third time interval, Wherein the second deactivation voltage is lower than the first deactivation voltage, Wherein, during a predetermined period, the number of active commands accumulated for the selected word line is counted, and Wherein the level of the second deactivation voltage decreases as the number of accumulated active commands increases, and as the number of accumulated active commands increases, the decrement of the level of the second deactivation voltage increases.

2. The method of operation according to claim 1, further comprising: After a fourth time interval has elapsed from a second time point when the second activation voltage is applied to the selected word line, reapplying the first activation voltage to the selected word line.

3. The method of operation according to claim 1, further comprising: In response to the precharge command, applying the first deactivation voltage to the unselected word lines.

4. The operating method according to claim 1, wherein The difference between the first activation voltage and the second activation voltage is less than the difference between the second activation voltage and the first deactivation voltage.

5. The operating method according to claim 1, wherein, The selected word line is connected to a plurality of dynamic random access memory (DRAM) cells.

6. A memory device, comprising: An array of memory cells including a plurality of memory cells connected to a plurality of word lines; ​ ​ ​ ​ ​ ​ ​ After the third time interval, a first deactivation voltage is applied to the selected word line, wherein, during the third time interval, a recovery operation is performed on the memory cells connected to the selected word line, wherein the word line voltage control circuit is further configured to: During the first time interval, in response to the active command, apply a second deactivation voltage to the unselected word lines among the plurality of word lines; During a second time interval after the first time interval, apply a third deactivation voltage lower than the second deactivation voltage to the unselected word lines; and After the second time interval, apply a fourth deactivation voltage lower than the third deactivation voltage to the unselected word lines, and wherein the second deactivation voltage is lower than the first deactivation voltage, wherein the memory device further includes: an active command counter configured to count the number of active commands accumulated for the selected word line during a predetermined period, wherein the word line voltage control circuit causes the level of the second deactivation voltage to decrease as the number of accumulated active commands increases, and as the number of accumulated active commands increases, the amount of decrease in the level of the second deactivation voltage increases.

7. The memory device according to claim 6, further comprising: a timer configured to periodically output a reference signal based on the time elapsed since the time point when the active command is received, wherein the word line voltage control circuit includes a charge pump configured to lower the second deactivation voltage by a given level in response to the reference signal.

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