A low-power successive approximation analog-to-digital converter and analog-to-digital conversion method

Abstract

A successive approximation analog-to-digital converter includes a first capacitor array, a second capacitor array, a comparator, and a successive approximation logic control circuit. The reference voltage of the second capacitor array is half of the maximum input voltage. The successive approximation logic control circuit adopts a monotonic switching strategy, thereby reducing the power consumption of the analog-to-digital conversion. The successive approximation analog-to-digital converter disclosed in this application can solve the problem of high energy consumption of the traditional SAR ADC in the prior art. This application also correspondingly discloses an analog-to-digital conversion method for a successive approximation analog-to-digital converter.

Description

Technical Field

[0001] This application generally relates to the field of integrated circuits, and more particularly to a successive approximation analog-to-digital converter. Background Art

[0002] A successive approximation register analog-to-digital converter (SAR ADC) is an ADC based on a binary search approximation algorithm. Its basic working principle is to use a binary weighted capacitor array to attenuate a reference voltage to achieve a binary division of the total charge on the capacitor array, thereby implementing the binary approximation search algorithm.

[0003] Traditional charge redistribution SAR ADCs mainly include a capacitor array, a comparator, and a successive approximation logic control circuit. Among them, the capacitor array is one of the important sources of power consumption in SAR ADCs. The capacitor array and switch scheme adopted by traditional SAR ADCs with traditional structures have the problem of high power consumption. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a low-power successive approximation analog-to-digital converter that can solve the problem of high power consumption in the prior art.

[0005] In a first aspect, this application provides an n-bit successive approximation analog-to-digital converter, including a first capacitor array, a second capacitor array, a comparator, and a successive approximation logic control circuit. The first capacitor array is connected to the first input terminal of the comparator and the successive approximation logic circuit. The second capacitor array is connected to the second input terminal of the comparator and the successive approximation logic circuit. The output terminal of the comparator is connected to the successive approximation logic control circuit. The successive approximation logic control circuit outputs a digital signal;

[0006] The first capacitor array includes capacitors C a0 ~C a(n-1) connected in parallel. The second capacitor array includes capacitors C b0 ~C b(n-1) connected in parallel, where C a0 = C b0 = C, C ai = C bi = 2 i-1 C, i = 1 to (n - 1), and C is the basic unit of capacitance;

[0007] All upper plates of the first capacitor array are connected to the first input terminal of the comparator. The first input terminal of the comparator is connected to the input voltage signal V through the switch S a0 ​IN is connected, and the lower plate of capacitor C a0 is connected to the reference voltage signal V REF , and capacitor C a1 ~C a(n-1) are respectively connected to the reference voltage signal V through switches S a1 ~S a(n-1) ; all the upper plates of the second capacitor array are connected to the second input terminal of the comparator, and the second input terminal of the comparator is connected to the reference voltage signal V through switch S REF is connected, and the lower plate of capacitor C b0 is connected to the reference voltage signal V REF is connected, and capacitor C b0 's lower plate is connected to the reference voltage signal V REF , capacitor C b1 ~C b(n-1) are respectively connected to the reference voltage signal V through switches S b1 ~S b(n-1) ; REF ;

[0008] The successive approximation logic control circuit outputs a control signal according to the comparison result of the comparator to control the switching of switches S a1 ~S a(n-1) and S b1 ~S b(n-1) .

[0009] In a second aspect, the present application provides an analog-to-digital conversion method, which is applicable to the n-bit successive approximation analog-to-digital converter described in the present application. The analog-to-digital conversion method includes:

[0010] Reset the successive approximation logic control circuit and store the comparator offset voltage;

[0011] Sample and hold;

[0012] Successively compare to determine the values of each significant bit of the digital signal; and

[0013] Output the digital signal and the conversion end signal.

[0014] For the n-bit successive approximation analog-to-digital converter provided by the present application, the capacitor array uses half of the maximum input voltage as the reference voltage, which reduces the voltage swing on the capacitor and thus reduces the energy consumed by the capacitor charging and discharging. Moreover, a monotonic switch switching strategy is adopted to avoid the charge loss caused by the search failure of the traditional SAR ADC, thereby reducing the power consumption of the analog-to-digital conversion and solving the problem of high energy consumption of the traditional SAR ADC with a traditional structure in the prior art. Description of the Drawings

[0015] Figure 1 is the structural block diagram of the successive approximation analog-to-digital converter SAR ADC in the embodiment of the present application;

[0016] Figure 2 Schematic diagram of the capacitor array structure in the embodiment of the present application;

[0017] Figure 3 Circuit structure diagram of the comparator in the embodiment of the present application;

[0018] Figure 4 Circuit structure diagram of the pre - operational amplifier in the embodiment of the present application;

[0019] Figure 5 Circuit structure diagram of the dynamic comparator in the embodiment of the present application;

[0020] Figure 6 Flowchart of an analog - to - digital conversion method in the embodiment of the present application;

[0021] Figure 7 Flowchart of successively comparing to determine the values of each significant bit of the digital signal in the embodiment of the present application. Detailed implementation manners

[0022] Symbol description

[0023] ADC: Analog - to - Digital Converter, analog - to - digital converter

[0024] SAR: Successive Approximation Register, successive approximation register

[0025] CMOS: Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor

[0026] MSB: Most Significant Bit, most significant bit

[0027] LSB: Least Significant Bit, least significant bit

[0028] EOC: End of Conversion, conversion end

[0029] V P : Upper - plate voltage of the first capacitor array

[0030] V N : Upper - plate voltage of the second capacitor array

[0031] V IN : Input voltage

[0032] V IN-MAX : Maximum input voltage, full - scale input voltage

[0033] V REF : Reference voltage

[0034] Preamp: Pre - amplifier, pre - operational amplifier

[0035] CLKC: Clock signal

[0036] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related invention and do not limit the invention. Additionally, it should be noted that for the convenience of description, only the parts related to the invention are shown in the drawings.

[0037] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the drawings and embodiments.

[0038] In an embodiment of the present application, a type of n - bit successive approximation analog - to - digital converter (SAR ADC) is provided. As Figure 1 shown, it is a structural block diagram of a 12 - bit successive approximation analog - to - digital converter (SAR ADC) in an embodiment of the present application. It should be understood that in this embodiment, a 12 - bit SAR ADC is taken as an example to illustrate the present application. The successive approximation analog - to - digital converter (SAR ADC) provided by the present application can be applicable to different resolutions, such as 8 - bit, 10 - bit, n - bit, etc. The disclosure herein does not constitute a limitation on the application scope of the present application.

[0039] As Figure 1 shown, a 12 - bit successive approximation analog - to - digital converter (SAR ADC) 100 includes, but is not limited to: a capacitor array 110, a comparator 120, and a successive approximation logic control circuit 130. Among them, the capacitor array 110 includes a first capacitor array 111 and a second capacitor array 112. The first capacitor array 111 is connected to the first input terminal of the comparator 120 and the successive approximation logic control circuit 130. The second capacitor array 112 is connected to the second input terminal of the comparator 120 and the successive approximation logic control circuit 130. The output terminal of the comparator 120 is connected to the successive approximation logic control circuit 130.

[0040] The capacitor array 110 is used to sample and hold the input voltage V IN . The comparator 120 is used to compare the output voltage of the first capacitor array 111 and the output voltage of the second capacitor array 112. The successive approximation logic control circuit 130 outputs a control signal according to the comparison output result of the comparator 120. The control signal is used to control the switches in the capacitor array 110. After the ADC conversion is completed, the successive approximation logic control circuit 130 outputs a digital signal D 11~D0, and send out an End of Conversion (EOC) signal to notify the backend circuit that the ADC has completed the conversion.

[0041] Figure 2 The structural schematic diagram of the capacitor array 110 is shown. The first capacitor array 111 includes 12 parallel capacitors C a0 ~C a11 , and the second capacitor array 112 includes 12 parallel capacitors C b0 ~C b11 , C a0 =C bo =C, where C is the basic capacitor unit, C ai =C bi =2 i-1 C, and i = 1 to 11. It should be understood that Figure 2 This is only the structural schematic diagram of the capacitor array in a 12-bit successive approximation analog-to-digital converter, and does not constitute a limitation on the application scope of this application. It is easy for those of ordinary skill in the art to obtain that in an n-bit successive approximation analog-to-digital converter, there are two capacitor arrays. The first capacitor array includes n parallel capacitors C a0 ~C a(n-1) , and the second capacitor array includes n parallel capacitors C b0 ~C b(n-1) , where C a0 =C b0 =C, C ai =C bi =2 i-1 C, and i = 1 to (n - 1). C is the basic capacitor unit. It can be known that the total capacitance value C a =C b =2 11 C.

[0042] All the upper plates of the first capacitor array 111 are connected to the first input terminal of the comparator 120. That is, the upper plate voltage V P of the first capacitor array 111 serves as the signal of the first input terminal of the comparator 120. The first input terminal of the comparator 120 is connected to the input voltage signal V a0 through the switch S IN . The lower plate of the capacitor C a0 is connected to the reference voltage signal V REF , and C a1 ~C a(n-1) The capacitors are respectively connected to the reference voltage signal V a1 ~S a11 through the switches S REFOr grounded. All upper plates of the second capacitor array 112 are connected to the second input terminal of the comparator 120, that is, the voltage V of the upper plates of the second capacitor array 112 N serves as the signal of the second input terminal of the comparator 120. The second input terminal of the comparator 120 is connected to the reference voltage signal V b0 through the switch S REF . The lower plate of the C b0 capacitor is connected to the reference voltage signal V REF , and the lower plates of the C b1 ~C b(n-1) capacitors are respectively connected to the reference voltage signal V b1 ~S b11 or grounded. The successive approximation logic control circuit 130 outputs a control signal according to the comparison result of the comparator 120, and the control signal is used to control the switches S REF ~S a1 and S a11 ~S b1 ~S b11 .

[0043] In an embodiment of the present application, since the first capacitor array 111 and the second capacitor array 112 adopt the upper plate sampling technology for sampling, the influence of the parasitic capacitance of the lower plate of the capacitor on the accuracy of the SAR ADC is reduced. In addition, the reference voltage signal V REF is half of the maximum input voltage V IN-MAX . Therefore, the successive approximation analog-to-digital converter SAR ADC 100 only needs half of the maximum input voltage V IN-MAX as the reference voltage signal V REF , and the full-scale input of the input voltage V IN can be realized, reducing the voltage swing on the capacitor and thus reducing the energy consumed by the charging and discharging of the capacitor.

[0044] In an embodiment of the present application, the switches in the capacitor array 110 are implemented by CMOS switches. The CMOS switches have a full swing voltage input range, a small layout area, and a certain inhibitory effect on the channel charge injection effect and the clock feedthrough effect. The sizes of the switches S a1 ~S a11 in the first capacitor array 111 decrease sequentially in proportion from the high bit to the low bit, ensuring that the time constants of the RC networks formed by the single capacitors and the corresponding switches are close. Similarly, the sizes of the switches S b1 ~S b11 in the second capacitor array 112 decrease sequentially in proportion from the high bit to the low bit, ensuring that the time constants of the RC networks formed by the single capacitors and the corresponding switches are close.

[0045] Figure 3The circuit structure diagram of the comparator 120 in the embodiment of the present application is shown. The comparator 120 includes three identical pre-amplifiers (Pre-amplifier, Preamp) Preamp121, Preamp122, Preamp123 connected in sequence and a dynamic comparator 124. The upper plate voltage VP of the first capacitor array 111 and the upper plate voltage VN of the second capacitor array 112 are used as input signals, and VOUT is the output signal. The pre-amplifier has a low gain and a high bandwidth. The high bandwidth improves the comparison speed of the comparator. At the same time, the gain is increased by cascading operational amplifiers, improving the resolution of the comparator for the input voltage. At the same time, the comparator adopts input offset cancellation and output offset cancellation technologies to reduce the offset voltage of the comparator.

[0046] Figure 4 The circuit structure diagram of the pre-amplifier Preamp in the embodiment of the present application is shown. PM2 and PM3 are input transistors, and NM1 to NM4 form the load of the amplifier. NM2 and NM3 are connected in a cross-coupled manner, which can improve the gain of the amplifier. At the same time, the size of NM1 is larger than that of NM2, which can prevent the amplifier from entering the latch state. NM5 and NM6 are connected to the circuit in the form of diodes to clamp the output voltage, which can reduce the reset time of the comparator and improve the comparison speed.

[0047] Figure 5 The circuit structure diagram of the dynamic comparator in the embodiment of the present application is shown. The function of the dynamic comparator 124 is to amplify the output of the pre-amplifier into high and low levels recognizable by digital circuits. The circuit of the dynamic comparator 124 includes a tail current source PM1, differential input PMOS transistors PM2 and PM3, cross-coupled inverters PM8, NM3 and PM9, NM4, NMOS switches NM5 and NM6, and inverters PM4, NM1 and PM5, NM2. The functions of the dynamic comparator 124 include reset and comparison.

[0048] Reset: When the clock signal CLKC is 1, the circuit is reset, the switches NM5 and NM6 are turned on, and the input and output levels of the inverter load are pulled to 0;

[0049] Comparison: When the clock signal CLKC is 0, the switches NM5 and NM6 are turned off, and the circuit compares the input voltages. When V P is greater than V N , the current flowing through PM2 is less than that of PM4, the voltage rising speed of point V3 is lower than that of point V4. Through the positive feedback of the cross-coupled inverter, V3 is pulled low to ground, V4 is pulled high to VDD, and through the inverter output, VOUT is pulled high to VDD, that is, the digital signal 1, and VNOUT is pulled low to ground, that is, the digital level 0; when V P is less than V NAt this time, similarly, VOUT is pulled down to the ground, that is, the digital level 0, and VNOUT is pulled up to VDD, that is, the digital signal 1, and there is no static power consumption during the entire working process.

[0050] Figure 6 The following shows a flowchart of an analog-to-digital conversion method in an embodiment of the present application. The analog-to-digital conversion method is applicable to the successive approximation analog-to-digital converter provided by the present application as Figure 1 shown.

[0051] S601, reset the successive approximation logic control circuit and store the comparator offset voltage. The successive approximation logic control circuit 130 performs a reset operation under the action of a reset signal, sets D 11 ~D0 to 0, and sets switches S a1 ~S a11 and S b1 ~S b11 to 1, so that the lower plates of all capacitors are connected to the reference voltage V REF . At the same time, the offset voltage of the comparator is stored.

[0052] S602, sample and hold. First, switches S a0 and S b0 are closed. The upper plates of the capacitors in the first capacitor array 111 are connected to the input voltage signal V IN , and the upper plates of the capacitors in the second capacitor array 112 are connected to the reference voltage signal V REF . The voltage of the upper plate of the first capacitor array 111 is charged to V IN , and the voltage of the upper plate of the second capacitor array 112 is charged to V REF . Then, S a0 and S b0 are disconnected, and the ADC enters the hold stage. The voltage V P of the upper plate of the first capacitor array 111, the total charge Q P , the voltage V N of the upper plate of the second capacitor array 112, and the total charge Q N are respectively shown as the following formulas:

[0053] V P =V IN

[0054] Q P =(V IN -V REF )×C P =(V IN -V REF )×2 11 C

[0055] V N =V REF

[0056] Q N = 0

[0057] S603, determine the values of each significant bit of the digital signal by successive comparison.

[0058] In an embodiment of the present application, the specific process of determining the values of each significant bit of the digital signal by successive comparison is as Figure 7 shown. First, the comparator 120 directly performs the first (k = 1, k represents the number of comparisons) comparison of V p and V N to obtain the most significant bit (MSB).

[0059] If V P > V N , that is, V IN > V REF , then the MSB value is 1; otherwise, the MSB value is 0.

[0060] If the MSB is 1, the successive approximation logic control circuit 130 generates a control signal, and the control signal sets the switch S a11 to 0, and the other switches remain unchanged. Then, the lower plate of the capacitor C a11 is connected to the ground, and the total charge on the upper plate of the first capacitor array 111 is:

[0061] Q P = (V P - V REF ) × (C P - C a11 ) + V P × C a11

[0062] Combining the formulas, we can get:

[0063]

[0064] And at this time, V N = V REF . Based on this, the comparator 120 compares V P and V N again to determine the value of the second most significant bit.

[0065] Conversely, if the MSB is 0, the successive approximation logic control circuit 130 generates a control signal, and the control signal sets the switch S b11 to 0, and the other switches remain unchanged. Then, the lower plate of the capacitor C b11 is connected to the ground, and the total charge on the upper plate of the second capacitor array 112 is:

[0066] Q N = (VN -V REF )×(C N -C b11 )+V N ×C b11

[0067] By solving the simultaneous equations, we get:

[0068]

[0069] At this time, V P =V IN . Based on this, comparator 120 compares V P and V N again to determine the value of the second highest significant bit.

[0070] And so on. After the k (k < 12) -th comparison, if D (12-k) is 1, connect the lower plate of C a(12-k) to ground and then perform the (k + 1)-th comparison. Otherwise, connect the lower plate of C b(12-k) to ground and then perform the (k + 1)-th comparison. When k = 12, the least significant bit (LSB) is generated. Thus, the values of each significant bit D 11 ~D0 of the digital signal are determined one by one.

[0071] When the last comparison is completed, the total voltage charge Q P of the upper plate of the first capacitor array 111 and the total voltage charge Q N of the upper plate of the second capacitor array 112 are respectively shown as follows:

[0072]

[0073]

[0074] It can be obtained that:

[0075]

[0076]

[0077] When the successive approximation process ends and the values of V P and V N are equal, it can be obtained that:

[0078]

[0079] Connect C P , C N , C ai and C biSubstituting the value of (i=0-11) into the above formula, we can get:

[0080]

[0081] It should be understood that the above description is based on a 12-bit successive approximation analog-to-digital converter as an example. It is known to those skilled in the art that, in the workflow of an n-bit successive approximation analog-to-digital converter, in k(k <n)次比较后,若D (n-k) If C a(n-k) After the lower plate of C is connected to the ground, the (k+1)th comparison is performed. Otherwise, C b(n-k) The lower plate of the digital signal is connected to the ground and the (k+1)th comparison is performed. When k=n, the least significant bit (LSB) is generated. n-1 ~D0 values ​​are determined one by one.

[0082] When the last comparison of the n-bit SAR ADC is completed, the total charge Q of the voltage on the upper plate of the first capacitor array 111 is P and the total charge Q of the voltage on the upper plate of the second capacitor array 112 N They are shown as follows:

[0083]

[0084]

[0085] It can be concluded that:

[0086]

[0087]

[0088] When the successive approximation process is completed, V P and V N If the values ​​of are equal, we can conclude that:

[0089]

[0090] C P , C N , C ai and C bi Substituting the value of (i=0~(n-1)) into the above formula, we can get:

[0091]

[0092] S604, outputting a digital signal and a conversion completion signal.

[0093] Back to Figure 6As shown, after determining the values of the valid bits of the digital signal in step 603, in step 604, the digital signal is output and the conversion end EOC signal is output to notify the backend circuit that the ADC has completed the conversion.

[0094] In the traditional differential structure SAR ADC, the lower plates of the capacitor array are used to sample the input voltage. After sampling is completed, all the lower plate switches of the capacitors are grounded and the upper plate switches are disconnected. After entering the conversion stage, first, the MSB is judged. The lower plate switch of the highest bit capacitor is connected to Vref, and the comparator compares the input voltage. If the former is greater than the latter, then MSB = 1, and the lower plate switch of the highest bit capacitor remains unchanged. The lower plate switch of the second highest bit capacitor is connected to Vref, and the judgment of the second highest bit starts; if the former is less than the latter, then MSB = 0, the lower plate switch of the highest bit is re-grounded, and then the lower plate switch of the second highest bit capacitor is connected to Vref, and the judgment of the second highest bit starts. And so on until the conversion is completed. The number of switch operations during the conversion process is [i + 2*(12 - i)], where i is the number of 1s in D0~D in the output digital signal. 11 in the output digital signal.

[0095] During the analog-to-digital conversion process of the successive approximation analog-to-digital converter applicable to 12 bits provided by the present application, a total of 12 comparison operations and 11 switch operations are performed. Compared with the traditional differential SAR ADC, the capacitor array 110 of the SAR ADC provided by the present application uses the upper plate for sampling. To obtain the value of the MSB, no switch operation is required, eliminating the dynamic power consumption of the step of using the lower plate sampling to obtain the MSB in the traditional structure. Moreover, during the successive approximation process, the successive approximation logic control circuit 130, according to the comparison result of the previous bit, adopts a monotonic switch switching strategy to control the switches in the first capacitor array 111 or the second capacitor array 112 to be grounded, with only one charge flow, avoiding the problem that the lower plate switch of the capacitor in the traditional structure control logic needs to be re-grounded according to the comparison result. In an embodiment of the present application, the reference voltage signal V REF takes half of the maximum input voltage V REF i.e., V IN-MAX = V REF / 2. The reference voltage of the traditional differential SAR ADC is equal to the maximum input voltage. Therefore, the SAR ADC provided by the present application only needs half of the maximum input voltage V IN-MAX as the reference voltage signal V IN-MAX to achieve full-scale input of the input voltage, reducing the voltage swing on the capacitor and thus reducing the energy consumed by the charging and discharging of the capacitor. REF

[0096] ​In summary, the successive approximation analog-to-digital converter provided by this application uses half of the maximum input voltage as the reference voltage and combines it with a monotonic switching strategy, which reduces the power consumption of each analog-to-digital conversion and greatly reduces the dynamic energy consumption compared with the traditional structure.

[0097] The above-disclosed is only a preferred embodiment of the present invention. Of course, the scope of the rights of the present invention cannot be limited thereby. Those of ordinary skill in the art can understand all or part of the processes of implementing the above embodiments, and the equivalent changes made according to the claims of the present invention still fall within the scope covered by the invention.

Claims

1. An n-bit successive approximation analog-to-digital converter, comprising a first capacitor array, a second capacitor array, a comparator and a successive approximation logic control circuit. The first capacitor array is connected to the positive input terminal of the comparator and the successive approximation logic control circuit. The second capacitor array is connected to the negative input terminal of the comparator and the successive approximation logic control circuit. The output terminal of the comparator is connected to the successive approximation logic control circuit. The successive approximation logic control circuit outputs a digital signal, and is characterized in that: The first capacitor array includes capacitors C a0 ~C a(n-1) , and the second capacitor array includes capacitors C b0 ~C b(n-1) , where C a0 = C b0 = C, C ai = C bi = 2 i-1 C, i = 1 to (n - 1), and C is the basic unit of capacitance; All upper plates of the first capacitor array are connected to the positive input terminal of the comparator, and the positive input terminal of the comparator is connected to the positive input terminal of the comparator through the switch S a0 With the input voltage signal V IN connected, capacitor C a0 The lower plate is connected to the reference voltage signal V REF , capacitor C a1 ~C a(n-1) Through the switch S a1 ~S a(n-1) Connect to reference voltage signal V REF , all the upper plates of the second capacitor array are connected to the inverting input terminal of the comparator, and the inverting input terminal of the comparator is connected to the inverting input terminal of the comparator through the switch S b0 With the reference voltage signal V REF connected, capacitor C b0 The lower plate is connected to the reference voltage signal V REF , capacitor C b1 ~C b(n-1) Through the switch S b1 ~S b(n-1) Connect to reference voltage signal V REF ; The successive approximation logic control circuit outputs a control signal according to the comparison result of the comparator to control the switching of switches S a1 ~S a(n-1) and S b1 ~S b(n-1) ; The reference voltage signal V REF is half of the maximum input voltage signal; All the lower plates of the first capacitor array are connected to all the upper plates of the second capacitor array through a switch AOZ.

2. The analog-to-digital converter according to claim 1, wherein The switch S a0 , S a1 ~S a(n-1) , S b0 , S b1 ~S b(n-1) employs a CMOS switch.

3. The analog-to-digital converter according to claim 1, wherein The comparator comprises three identical preamplifiers connected in sequence and a dynamic comparator.

4. The analog-to-digital converter according to claim 3, characterized in that, The comparator adopts input offset cancellation and output offset cancellation techniques.

5. The analog-to-digital converter according to claim 1, wherein The successive approximation logic control circuit outputs a control signal according to the comparison result of the comparator to control the switches S a1 ~S a(n-1) and S b1 ~S b(n-1) for switching, specifically including: The comparator performs the k-th (k < n) comparison. When the output result of the comparator is 1, the control signal grounds the switch S a(n-k) ; when the output result of the comparator is 0, the control signal grounds the switch S b(n-k) .

6. A method for analog-to-digital conversion, applicable to the successive approximation analog-to-digital converter according to any one of claims 1-5, characterized in that, The analog-to-digital conversion method comprises: Resetting the successive approximation logic control circuit and storing the comparator offset voltage; Sampling and holding; Successively comparing to determine the values of the valid bits of the digital signal; and Outputting the digital signal and a conversion end signal; The reference voltage signal V REF is half of the maximum input voltage signal, and the input voltage is a full-scale input.

7. The analog-to-digital conversion method according to claim 6, characterized in that, The sampling includes closing switches S a0 and S b0 . The upper plates of the capacitors in the first capacitor array are connected to the input voltage signal V IN . The upper plates of the capacitors in the second capacitor array are connected to the reference voltage signal V REF . The voltage of the upper plates of the first capacitor array is charged to V IN , and the voltage of the upper plates of the second capacitor array is charged to V REF . The holding includes disconnecting switches S a0 and S b0 . At this time, the voltage of the upper plates of the first capacitor array remains V P , and the voltage of the upper plates of the second capacitor array remains V N .

8. The analog-to-digital conversion method according to claim 6, characterized in that The successive comparison to determine the values of the valid bits of the digital signal comprises: The first comparison directly compares V P and V N to determine the most significant bit (MSB) of the digital signal. If V P >V N , the MSB value is 1, and switch S a(n-1) is grounded. Otherwise, the MSB value is 0, and switch S b(n-1) is grounded; Perform the second to the (n - 1)-th comparison in sequence (let k be the number of comparisons, that is, 1 < k < n) to determine the second highest significant bit to the second lowest significant bit of the digital signal. Specifically, for the k-th comparison, if V P >V N then the value of the (n - k)-th significant bit is 1, and switch S a(n-k) is grounded. Otherwise, the value of the (n - k)-th significant bit is 0, and switch S b(n-k) is grounded; The nth comparison determines the least significant bit (LSB) of the digital signal. If V P >V N , the value of the LSB is 1; otherwise, the value of the LSB is 0.

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