A self-powered energy harvesting circuit with maximum power point tracking, dual-input and dual-output

Abstract

The present invention relates to a self-powered dual-input dual-output energy harvesting circuit with maximum power tracking, which includes a DC-DC boost circuit, an AC-DC rectifier doubler circuit, a dual-output self-powered circuit, and a switch control module. For the designed dual-source input circuit, it can track the maximum power point of the power output of the DC source circuit in real time, greatly improving the energy extraction efficiency. In the loop of the AC energy source input, a voltage doubler rectifier structure is adopted, and the circuit does not require a power supply for power supply. The entire rectifier boost conversion circuit can be regarded as the parallel connection of two rectifier conversion circuits, one is an efficient active converter and the other is a low-efficiency passive converter, and the latter only works at startup. The adoption of the voltage doubler structure not only effectively improves the efficiency of the rectifier circuit, but also enables the overall circuit to start at a lower input voltage. The dual-source input-output self-powered effectively improves the applicability of the circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and particularly relates to a self-powered dual-input dual-output energy harvesting circuit with maximum power tracking. Background Art

[0002] Energy harvesting technology mainly refers to the technology of collecting unused light, heat, piezoelectric and other energies in the environment and converting them into directly utilizable electrical energy. In recent years, with the development of emerging industries such as the Internet of Things, intelligent sensors, wireless modules, and intelligent wearable devices, it has greatly promoted the development of energy harvesting technology. Because in these applications, traditional battery power supply can no longer meet the actual needs. The available lifespan of a sensor network depends on the available lifespan of the battery. Batteries generally can work continuously for 3 to 5 years, and they are expensive components in each sensor. It is difficult to replace the battery in these applications, and the cost of replacing the battery is high. Using a self-powered system in a wireless sensor network can achieve the purpose of replacing the battery or extending the lifespan of the battery. For example, CN205092768U discloses an energy harvesting circuit that receives an input voltage from a transducer and uses a single inductor operating in the charging mode of a DC-DC converter to generate a charging current at a first output terminal coupled to an energy storage device storing a supply voltage. The energy harvesting circuit further receives the supply voltage from the energy storage device and uses the same inductor operating in the regulation mode of the DC-DC converter to generate a load current at a second output terminal provided with a regulated load voltage. The energy harvesting circuit switches between the charging mode and the regulation mode according to a discontinuous mode (DCM) control process, but there are still the following deficiencies: the above energy harvesting circuit has a single input source and a single output. A single energy source makes the energy source single, and the energy stability is not good, and the applicable range is limited. In addition, it is for collecting DC sources, and some weak AC sources cannot be well combined and utilized. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a self-powered dual-input dual-output energy harvesting circuit with maximum power tracking that can simultaneously harvest energy from DC sources and AC sources and makes up for the defects of a single energy source.

[0004] To solve the above technical problem, the present invention discloses a self-powered dual-input dual-output energy harvesting circuit with maximum power tracking, including a DC-DC boost circuit, an AC-DC rectifier doubler circuit, a dual-output self-powered circuit, and a switch control module;

[0005] The DC-DC boost circuit includes a DC input source model VO1 and R, a maximum power tracking circuit A2, an oscillator A1, a capacitor Ci1, an inductor L, and an NMOS transistor NS1;

[0006] The DC input power supply model VO1 and R are connected to the maximum power point tracking circuit to generate the output voltages Vin and Vmppt. The maximum power point tracking circuit is connected to the oscillator A1. The voltage Vin is respectively connected to one end of the capacitor Ci1 and the inductor L. The capacitor Ci1 is grounded at the same time. The source of the NMOS transistor NS1 is grounded, the gate is controlled by the signal SW1R generated by the switch control module, and the drain is connected to the other end of the inductor L. The drain of the NMOS transistor NS1 and the other end of the inductor L are also respectively connected to the DC part input terminal of the dual-output self-powered circuit;

[0007] The AC-DC rectifier voltage doubling circuit includes the AC input power supply model VO2 and Ci2, two unbalanced comparators CMP2 and CMP3, the NMOS transistor NS2, the capacitor CS, and the PMOS transistor PS7;

[0008] The AC input power supply model VO2 and Ci2 are respectively connected to the drain of the NMOS transistor NS2, the inverting input terminal of the unbalanced comparator CMP2, the inverting input terminal of the unbalanced comparator CMP3, and the drain of the PMOS transistor PS7. The source of the NMOS transistor NS2 and the non-inverting input terminal of the unbalanced comparator CMP2 are both grounded. The gate of the NMOS transistor NS2 is connected to the output control signal of the unbalanced comparator CMP2. The output signal of the unbalanced comparator CMP3 is connected to the gate of the PMOS transistor PS7. The non-inverting input terminal of the unbalanced comparator CMP3 is respectively connected to the source of the PMOS transistor PS7 and the capacitor CS. The capacitor CS is grounded at the same time. The non-inverting input terminal of the unbalanced comparator CMP3, the capacitor CS, and the source of the PMOS transistor PS7 are also respectively connected to the AC part input terminal of the dual-output self-powered circuit;

[0009] The input terminal of the switch control module is connected to the voltage Vin and Vmppt, the signal Clk generated by the oscillator A1, and the node voltage in the dual-output self-powered circuit.

[0010] Preferably, in the above solution, the dual-output self-powered circuit includes PMOS transistors PS6, PS5, PS4, PS2, PS3, and PS1, the capacitor Cv, the load capacitors CL2 and CL1, and the loads 2 and 1;

[0011] The source of PMOS transistor PS4 is connected to capacitor CS, the non-inverting input terminal of non-balanced comparator CMP3, and the source of PMOS transistor PS7 respectively. Its gate is controlled by signal SW7R generated by the switch control module, and its drain is connected to capacitor Cv; the source of PMOS transistor PS5 is connected to the source of PMOS transistor PS4, its gate is controlled by signal SW6R generated by the switch control module, and its drain is connected to load capacitor CL2 and the source of PMOS transistor PS6 respectively; the drain of PMOS transistor PS6 is connected to load 2, and its gate is controlled by signal SW5R generated by the switch control module; the drain of PMOS transistor PS3 is connected to the source of PMOS transistor PS6 and the drain of PMOS transistor PS5 respectively, its gate is controlled by signal SW4R generated by the control module, and its source is connected to the source of PMOS transistor PS1, the other end of inductor L, and the drain of NMOS transistor NS1 respectively; the drain of PMOS transistor PS1 is connected to load capacitor CL1 and the source of PMOS transistor PS2 respectively, its gate is controlled by signal SW2R generated by the switch control module; the drain of PMOS transistor PS2 is connected to load 1, and its gate is controlled by signal SW3R generated by the switch control module; capacitor Cv, load capacitors CL1 and CL2, and loads 1 and 2 are also grounded.

[0012] Preferably, in the above solution, the switch control module includes a switch control circuit and a buffer, wherein the switch control circuit includes an input signal detection circuit and an output signal control circuit;

[0013] The signal detection circuit includes rising edge detection circuits I1, I2 and I11, a zero-crossing comparator I6, comparators I12, a NAND gate I3, an inverter I4 and an RS flip-flop;

[0014] Among them, input signal Clk is connected to rising edge detection circuit I2; input signals V1 and V2 are connected to the input of zero-crossing comparator I6. The output of zero-crossing comparator I6 is connected to rising edge detection circuit I1. The output signals of rising edge detection circuits I1 and I2 are connected to the input of NAND gate I3. The output of NAND gate I3 is connected to the input of inverter I4. The output of inverter I4 is connected to the S terminal of the RS flip-flop. Input signals Vin and Vmppt are connected to the non-inverting input terminal and the inverting input terminal of comparator I12 respectively. The output of comparator I12 is connected to rising edge detection circuit I11. The output terminal of rising edge detection circuit I11 is connected to the R terminal of the RS flip-flop. The output Q terminal of the RS flip-flop controlled by the output of inverter I4 and the output of rising edge detection circuit I11 is used as an enable signal to control the working state of zero-crossing comparator I6;

[0015] The output signal control circuit includes comparators I10, I22, I23, I24 and I28, inverters I8, I9, I17, I18, I20, I25 and I27, NOR gates I7, I16, I19 and I26, and AND gates I15 and I21;

[0016] The non-inverting input terminal and the inverting input terminal of comparator I10 are respectively connected to the reference voltage 1.22V and V2, and the output of comparator I10 is connected to the input of inverter I9; the output signals of zero-crossing comparator I6 and inverter I9 are both connected to NOR gate I7, the output of NOR gate I7 is connected to the input of inverter I8, the output of inverter I8 generates control signal SW2, the output signal of inverter I8 and Vdd are connected to NOR gate I13, the output of NOR gate I13 is connected to inverter I14, the output signals of inverter I14 and comparator I28 are both connected to AND gate I15, the output signal of AND gate I15 and the output signal P of zero-crossing comparator I6 are both connected to NOR gate I16, the output signal of NOR gate I16 is connected to the input terminal of inverter I17, and inverter I17 generates control signal SW4; the non-inverting input terminal of comparator I22 is connected to the reference voltage 1.6V, the inverting input terminal is connected to V3, the non-inverting input terminal of comparator I23 is connected to the reference voltage 1.62V, the inverting input terminal is connected to V3, the output signals of comparators I22 and I23 are both connected to AND gate I21, the output signal of AND gate I21 is connected to the input terminal of inverter I20, the output signals of inverter I20 and comparator I12 are both connected to the input terminal of NOR gate I19, the output signal of NOR gate I19 is connected to inverter I18, and inverter I18 generates control signal SW1; the output of comparator I22 generates control signal SW5, the non-inverting input terminal of comparator I24 is connected to the reference voltage 1.2V, the inverting input terminal is connected to Vdd, the output signal of comparator I24 is connected to the input signal of inverter I25, the output signals of inverter I25 and comparator I22 are both connected to the input terminal of NOR gate I26, the output signal of NOR gate I26 is connected to the input signal of inverter I27, the output terminal of inverter I27 generates control signal SW6, the output of comparator I24 generates control signal SW7, the non-inverting input terminal of comparator I28 is connected to the reference voltage 1.2V, the inverting input terminal is connected to V2, and the output of comparator I28 generates control signal SW3;

[0017] Control signals SW1, SW2, SW3, SW4, SW5, SW6, and SW7 are connected to a buffer, and the buffer outputs control signals SW1R, SW2R, SW3R, SW4R, SW5R, SW6R, and SW7R;

[0018] Among them, V1 and V2 are the two voltages on the right side of inductor L, V3 is the voltage on load capacitor CL2, and Vdd is the voltage on capacitor Cv.

[0019] Compared with the prior art, the present invention has the following advantages:

[0020] 1. The dual-input and dual-output energy harvesting circuit of the present invention can simultaneously harvest energy from a DC source and an AC source, making up for the deficiencies of a single energy source. In terms of power supply, a voltage doubling structure is adopted in the self-starting of the AC-DC rectifier circuit, reducing the input AC voltage source voltage, so that the input AC source has a lower input voltage; while providing power for the stable operation of the circuit, it also provides an additional output. Compared with traditional battery-assisted starting or battery power supply, the present invention avoids the use of batteries, and the circuit can provide two stable output voltages; whether in the input source or the dual outputs, the applicable range of the circuit is effectively improved.

[0021] 2. With dual-source input, while the circuit harvests energy from the DC source, the AC source is connected to the circuit as a secondary energy source after passing through a voltage doubling rectification structure. While providing a stable output, it can supply power to the overall circuit, enabling the overall circuit to start and operate normally.

[0022] 3. At the output of the overall circuit, after harvesting energy from the DC source, a stable voltage is output for the load to use as a whole. After reaching stability, the excess energy is supplied to the second output, enabling both outputs to have stable outputs. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is the overall structural topology diagram of a self-powered dual-input and dual-output energy harvesting circuit with maximum power tracking according to the present invention;

[0024] Figure 2 is the waveform schematic diagram of some signals in the circuit;

[0025] Figure 3 is the circuit diagram of the switch control circuit of the present invention;

[0026] Figure 4 is the conversion efficiency curve diagram of the AC-DC rectifier voltage doubling circuit;

[0027] Figure 5 is the power tracking efficiency curve diagram of the DC input source. DETAILED DESCRIPTION OF THE INVENTION

[0028] In order to make the objectives and advantages of the present invention clearer, the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0029] The present invention discloses a self-powered dual-input and dual-output energy harvesting circuit with maximum power tracking, as shown in Figure 1As shown, in the DC source energy harvesting, a comparator is used to control the switching of the NMOS transistor and the inductance and capacitance, so as to achieve the boost conversion of the energy source from low voltage to high voltage. By comparing the input energy source with the voltage at its maximum power point through the comparator, the maximum power tracking function of the DC source is realized. The zero-crossing comparator is used to control the PMOS transistor to achieve the boost function. For the AC source, a voltage multiplier structure is used, and two active comparators are used to achieve the voltage multiplication function, and the output voltage is used to supply power to the overall circuit.

[0030] As Figure 1 shown, the energy harvesting circuit of the present invention includes: a DC-DC boost circuit, an AC-DC rectifying and voltage multiplying circuit, a dual-output self-powered circuit, and a switch control module.

[0031] Among them, the DC-DC boost circuit includes a DC input source model VO1 and R, a maximum power tracking circuit A2, an oscillator A1, a capacitor Ci1, an inductor L, and an NMOS transistor NSNS1. The AC-DC rectifying and voltage multiplying circuit includes an AC input source model VO2 and Ci2, two unbalanced comparators CMP2 and CMP3, an NMOS transistor NS2, a capacitor CS, and a PMOS transistor PS7. The dual-output self-powered circuit includes PMOS transistors PS6, PS5, PS4, PS2, PS3, and PS1, a capacitor Cv, load capacitors CL2 and CL1, and loads 2 and 1.

[0032] The DC input power supply model VO1 and R are connected to the maximum power point tracking circuit to generate the output voltages Vin and Vmppt. The voltage Vin is connected to one end of the capacitor Ci1 and the inductor L respectively, and the capacitor Ci1 is grounded at the same time. The maximum power point tracking circuit is connected to the oscillator A1. The source of the NMOS transistor NS1 is grounded, the gate is connected to the control signal SW1R generated by the switch control module, and the drain is connected to the other end of the inductor L, the sources of the PMOS transistors PS1 and PS3 respectively. The gate of the PMOS transistor PS1 is connected to the control signal SW2R generated by the switch control module, and the drain is connected to the capacitor CL1 and the source of the PMOS transistor PS2 respectively, and the capacitor CL1 is grounded at the same time. The gate of the PMOS transistor PS2 is connected to the control signal SW3R generated by the switch control module, and the drain is connected to the load 1, and the load 1 is grounded at the same time. The gate of the PMOS transistor PS3 is connected to the control signal SW4R generated by the switch control module, and the drain is connected to the load capacitor CL2, the drain of the PMOS transistor PS5, and the source of the PMOS transistor PS6 respectively, and the load capacitor CL2 is grounded at the same time. The AC input power supply model VO2 and Ci2 are connected to the drain of the NMOS transistor NS2, the inverting input terminal of the unbalanced comparator CMP2, the inverting input terminal of the unbalanced comparator CMP3, and the drain of the PMOS transistor PS7 respectively. The source of the NMOS transistor NS2 and the non-inverting input terminal of the unbalanced comparator CMP2 are grounded, and the gate of the NMOS transistor NS2 is connected to the output control signal of the unbalanced comparator CMP2. The output signal of the unbalanced comparator CMP3 is connected to the gate of the PMOS transistor PS7, and the non-inverting input terminal is connected to the source of the PMOS transistor PS7, the capacitor CS, and the source of the PMOS transistor PS4 respectively, and the capacitor CS is grounded at the same time. The drain of the PMOS transistor PS4 is connected to the power supply capacitor Cv, the gate is connected to the control signal SW7R generated by the switch control module, and the source is also connected to the source of the PMOS transistor PS5. The gate of the PMOS transistor PS5 is connected to the control signal SW6R generated by the switch control module, and the drain is connected to the capacitor CL2 and the source of the PMOS transistor PS6 respectively, and the capacitor CL2 is grounded at the same time. The drain of the PMOS transistor PS6 is connected to the load 2, and the gate is controlled by the signal SW5R generated by the switch control module, and the load 2 is grounded at the same time.

[0033] As Figure 3 shown, the switch control module includes a switch control circuit and a buffer. The switch control circuit includes an input signal detection circuit and an output signal control circuit, which are mainly implemented by a rising edge detection circuit, a zero-crossing comparator ZCD, a general comparator, an RS flip-flop, and digital logic gates to precisely control the power switching transistors (NMOS transistors, PMOS transistors).

[0034] Among them, the input signals V1 and V2 are Figure 1The two voltages on the right side of the medium inductor L, Clk is the signal generated by the oscillator, Vin and Vmppt are generated by the maximum power tracking circuit, the input voltages of the non-inverting terminals of the comparators are respectively generated by the reference voltage source, and V3 is Figure 1 the voltage on CL2 in the medium, and Vdd is Figure 1 the voltage on the capacitor Cv in the medium provides a stable power supply for the overall circuit.

[0035] The signal detection circuit includes rising edge detection circuits I1, I2 and I11, a zero-crossing comparator I6, comparators I12, a NAND gate I3, an inverter I4 and an RS flip-flop; wherein the input signal Clk is connected to the rising edge detection circuit I2; the input signals V1 and V2 are connected to the input of the zero-crossing comparator I6, the output of the zero-crossing comparator I6 is connected to the rising edge detection circuit I1, the output signals of the rising edge detection circuits I1 and I2 are connected to the input of the NAND gate I3, the output of the NAND gate I3 is connected to the input of the inverter I4, the output of the inverter I4 is connected to the S terminal of the RS flip-flop, the input signals Vin and Vmppt are respectively connected to the non-inverting terminal and the inverting terminal of the comparator I12, the output of the comparator I12 is connected to the rising edge detection circuit I11, the output terminal of the rising edge detection circuit I11 is connected to the R terminal of the RS flip-flop, and the output Q terminal of the RS flip-flop controlled by the output of the inverter I4 and the output of the rising edge detection circuit I11 is used as an enable signal to control the working state of the zero-crossing comparator I6.

[0036] The output signal control circuit includes comparators I10, I22, I23, I24, and I28, inverters I8, I9, I17, I18, I20, I25, and I27, nor gates I7, I16, I19, and I26, and AND gates I15 and I21. The non-inverting input and inverting input of comparator I10 are connected to the reference voltage of 1.22V and V2 respectively, and the output of comparator I10 is connected to the input of inverter I9. The output signals of zero-crossing comparator I6 and inverter I9 are both connected to nor gate I7. The output of nor gate I7 is connected to the input of inverter I8, and the output of inverter I8 generates control signal SW2. The output signal of inverter I8 and Vdd are connected to nor gate I13, and the output of nor gate I13 is connected to inverter I14. The output signals of inverter I14 and comparator I28 are both connected to AND gate I15. The output signal of AND gate I15 and the output signal P of zero-crossing comparator I6 are both connected to nor gate I16. The output signal of nor gate I16 is connected to the input of inverter I17, and inverter I17 generates control signal SW4. The non-inverting input of comparator I22 is connected to the reference voltage of 1.6V, and the inverting input is connected to V3. The non-inverting input of comparator I23 is connected to the reference voltage of 1.62V, and the inverting input is connected to V3. The output signals of comparators I22 and I23 are both connected to AND gate I21. The output signal of AND gate I21 is connected to the input of inverter I20. The output signal of inverter I20 and the output signal of comparator I12 are both connected to the input of nor gate I19. The output signal of nor gate I19 is connected to inverter I18, and inverter I18 generates control signal SW1. The output of comparator I22 generates control signal SW5. The non-inverting input of comparator I24 is connected to the reference voltage of 1.2V, and the inverting input is connected to Vdd. The output signal of comparator I24 is connected to the input signal of inverter I25. The output signal of inverter I25 and the output signal of comparator I22 are both connected to the input of nor gate I26. The output signal of nor gate I26 is connected to the input signal of inverter I27, and the output of inverter I27 generates control signal SW6. The output of comparator I24 generates control signal SW7. The non-inverting input of comparator I28 is connected to the reference voltage of 1.2V, and the inverting input is connected to V2. The output of comparator I28 generates control signal SW3.

[0037] Control signals SW1, SW2, SW3, SW4, SW5, SW6, and SW7 are connected to a buffer, and the buffer outputs control signals SW1R, SW2R, SW3R, SW4R, SW5R, SW6R, and SW7R.

[0038] Generation of the above control signal SW1: Signals output by comparator I22 and comparator I23 are respectively connected to the inputs of AND gate I21. The output of AND gate I21 is connected to the input of inverter I20. The outputs of inverter I20 and comparator I12 are respectively connected to the inputs of NOR gate I19. The output of NOR gate I19 is connected to the input of inverter I18. The control signal SW1 is generated at the output terminal of inverter I18.

[0039] Generation of the above control signal SW2: The output of zero-crossing comparator I6 is connected to rising-edge detector I1, Clk is connected to rising-edge detector I2, Vin is connected to the non-inverting input of comparator I12, Vmppt is connected to the inverting input of comparator I12, and its output signal is connected to rising-edge detector I11. The outputs of rising-edge detectors I1 and I2 are respectively connected to NAND gate I3, and its output is connected to inverter I4. The outputs of inverter I4 and rising-edge detector I11 are respectively connected to the S terminal and R terminal of RS flip-flop I5. The output Q of RS flip-flop I5 serves as an enable signal to control zero-crossing comparator I6. The output of comparator I10 is connected to the input of inverter I9. The outputs of inverter I9 and zero-crossing comparator I6 are respectively connected to NOR gate I7. The output of NOR gate I7 is connected to the input of inverter I8. The control signal SW2 is generated at the output terminal of inverter I8.

[0040] Generation of the above control signal SW3: The voltage V2 on capacitor CL1 is connected to the inverting input of comparator I28, and the reference voltage of 1.2V is connected to the non-inverting input of comparator I28. The control signal SW3 is generated at the output terminal of comparator I28.

[0041] Generation of the above control signal SW4: The outputs of inverter I8 and Vdd are respectively connected to NOR gate I13. The output of NOR gate I13 is connected to the input of inverter I14. The outputs of inverter I14 and comparator I28 are respectively connected to the inputs of AND gate I15. The outputs of AND gate I15 and zero-crossing comparator I6 are respectively connected to the inputs of NOR gate I16, and its output is connected to inverter I17. The control signal SW4 is generated at the output terminal of inverter I17.

[0042] Generation of the above control signal SW5: The signal V3 is connected to the inverting input of comparator I22 and compared with the reference voltage of 1.6V to generate the control signal SW5.

[0043] Generation of the above control signal SW6: The output of comparator I24 is connected to inverter I25. The outputs of inverter I25 and comparator I22 are respectively connected to the inputs of NOR gate I26. The output of NOR gate I26 is connected to the input of inverter I27. The control signal SW6 is generated at the output of inverter I27.

[0044] Generation of the above control signal SW7: The voltage Vdd on the capacitor Cv is connected to the inverting terminal of the comparator I24, and the reference voltage of 1.2V is connected to the non-inverting terminal of I24. The comparator I24 outputs to generate the control signal SW7.

[0045] The working principle of the present invention is as follows:

[0046] This energy harvesting circuit performs maximum power point tracking boost on energy sources with different internal resistances and different power levels in a DC-DC boost circuit and combines it with an AC-DC voltage doubling rectifier circuit for an AC source to achieve the harvesting of different types of environmental energy.

[0047] Figure 1 In the shown circuit, the DC input energy sources VO1 and R first pass through the maximum power point tracking circuit A2 to sample in real time to generate the input inductor voltage Vin and the voltage Vmppt at the maximum power point. Vin and Vmppt are compared through the Figure 3 comparator I11 in it, so that the input voltage Vin is always stabilized near the maximum power point voltage (0.5 times the open-circuit voltage for a thermoelectric energy source and 0.7 times the open-circuit voltage for a photovoltaic energy source), thereby enabling the circuit to have a high tracking efficiency for the energy source VO1. In each sampling period, when the circuit starts to work normally, the oscillator A1 generates a clock signal to sample the input voltage in real time through the maximum power point tracking circuit A2. Vin and Vmppt are compared through the comparator I12. When Vin is greater than Vmppt, the comparator I12 outputs a high level, and the power switch transistor NS1 is controlled to charge the inductor L. When the current in the inductor L reaches the peak current, the NMOS transistor NS1 is turned off. From the above Figure 3 circuit, the rising edge detection circuit I1, the rising edge detection circuit I2, and the rising edge detection circuit I11 respectively detect the output signal of the zero-crossing comparator I6, the rising edge signal of Clk, and the rising edge signal of the output signal of the comparator I12. The first two rising edge signals are respectively connected through the NAND gate I3, and the output of the NAND gate I3 is connected to the input of the inverter I4. The output of the RS flip-flop I5 is used as the trigger enable signal to control the working state of the zero-crossing comparator I6. When the RS flip-flop I5 outputs a low level, the zero-crossing comparator I6 works normally and outputs a low level to detect the voltages of V1 and V2 to discharge the inductor L to the subsequent circuit. When it is detected that the current on the line where V1 is located is 0, the zero-crossing comparator I6 turns to a high level to stop the inductor L from discharging to the subsequent circuit. In such a cycle, the boost process from input to output within a cycle is completed by constantly collecting the input voltage and charging and discharging the inductor.

[0048] In Figure 1 the shown circuit, the entire circuit completes a cycle of boost. Through Figure 3Comparator I28 in it controls the magnitude of the output terminal voltage. The non-inverting terminal of comparator I28 is connected to the reference voltage of 1.2V, and the inverting terminal is connected to V2. When the zero-crossing comparator I6 is at a low level, V2 is boosted. When V2 reaches 1.2V, comparator I28 generates a low-level signal to control PMOS transistor PS2 to supply power to load 1.

[0049] In Figure 1 the circuit shown, when the voltage of V2 reaches the power supply required by load 1, comparator I10 in Figure 3 generates a low level. The output of comparator I10 is connected to the output of inverter I9, which outputs a high level. The output of zero-crossing comparator I6 and the input of inverter I9 are connected to the NOR gate I7, and the output of NOR gate I7 is at a low level. Through inverter I8, a high level is output to control PMOS transistor PS1 not to work, and the excess energy is connected to load capacitor CL2 through PMOS transistor PS3, completing the entire boost working process of DC-DC.

[0050] In Figure 1 the circuit shown, for the AC input source model VO2, Ci2, first, the NMOS transistor NS2 controlled by comparator CMP3 charges capacitor Ci2 with the current in the negative half cycle. The drain of NMOS transistor NS2 is connected to the energy source and the inverting terminal of comparator CMP2. The source of NMOS transistor NS2 and the non-inverting terminal of comparator CMP2 are grounded, and the gate of NMOS transistor NS2 is connected to the output of comparator CMP2. In the negative half cycle, comparator CMP2 outputs a high level, and NMOS transistor NS2 conducts to charge capacitor Ci2. When entering the positive half cycle, the input voltage at the inverting terminal of comparator CMP2 is higher than the input voltage at the non-inverting terminal, comparator CMP2 outputs a low level, NMOS transistor NS2 disconnects, and PMOS transistor PS7 conducts to charge capacitor CS. The drain of PMOS transistor PS7 is connected to the inverting terminal of comparator CMP3, and the source is connected to the non-inverting terminal of comparator CMP3 and capacitor CS. The voltage on capacitor CS is twice the peak voltage of the AC input source.

[0051] In Figure 1 the circuit shown, the power supply for the overall circuit is provided by the voltage on capacitor Cv. Capacitor Cv is connected to the drain of PMOS transistor PS4, and the source of PMOS transistor PS4 is connected to capacitor CS. In Figure 3 comparator I24, the non-inverting terminal is connected to the reference voltage of 1.2V, and the inverting terminal is connected to Vdd. When the circuit starts, comparator I24 outputs a low level to control the gate of PMOS transistor PS4 to conduct and charge capacitor CS. When the voltage reaches 1.2V, comparator I23 outputs a high level. The voltage on capacitor CS provides a stable power supply for the overall circuit, enabling the overall circuit to work properly.

[0052] In Figure 1In the circuit shown, the voltage V3 on the capacitor CL2 provides the output voltage for the load. The capacitor CL2 is connected to the drains, drains, and sources of the PMOS transistors PS3, PS5, and PS6 respectively. After Vdd reaches a stable voltage, in Figure 3 the comparator I22 outputs a low level, controlling the PMOS transistor PS5 to conduct and charge the capacitor CL2 to provide the output for load 2. If the AC energy source does not reach the voltage required by load 2 after voltage doubling rectification, the PMOS transistor PS3 conducts to continue powering the capacitor CL2 until it reaches the voltage required by the load. In Figure 3 the output of the inverter I8 and Vdd are respectively connected to the NOR gate I13. The output of the NOR gate I13 is connected to the inverter I14. The outputs of the inverter I14 and the comparator I28 are respectively connected to the AND gate I15. The output of the AND gate I15 and the P terminal are respectively connected to the NOR gate I16, and the control signal SW4 for the PMOS transistor PS3 is generated through the inverter I17.

[0053] Figure 3 The circuit shown is Figure 1 the specific control unit of the switch control circuit described in Figure 2 which precisely controls the circuit through a combination of a rising edge detection circuit, a comparator, a zero-crossing detection comparator, and digital logic gates. The timing control signals of some main control signals can be seen in

[0054] The present invention relates to a self-powered dual-input and dual-output energy harvesting circuit with maximum power tracking. For the designed dual-source input circuit, it can track the maximum power point of the power output of the DC source circuit in real time, greatly improving the energy extraction efficiency. In the loop of the AC energy source input, a voltage multiplier rectification structure is adopted, and the circuit does not require a power supply for power supply. When the circuit starts, the energy on the capacitor CS is not sufficient to supply the active devices. In this case, the operation of the AC-DC is ensured by the body-source diodes of the NMOS power switch tube and the PMOS power switch tube. The entire rectifier boost conversion circuit can be regarded as the parallel connection of two rectifier conversion circuits, one is an efficient active converter and the other is a low-efficiency passive converter, and the latter only works during startup. The adoption of the voltage multiplier structure not only effectively improves the efficiency of the rectifier circuit, but also enables the overall circuit to start at a lower input voltage, because a part of the rectified output voltage provides power for the overall circuit, enabling the overall circuit to work properly. The dual-source input and output self-power supply effectively improves the applicability of the circuit.

[0055] As a specific implementation, based on the Cadence Virtuoso Spectre simulation of the TSMC 180nm process, in the DC boost circuit, the DC source VO1 simulates a thermoelectric generator (TEG) or a photovoltaic cell (PV) and a biofuel cell (BFC). The internal resistance of the input source is fixed at 200Ω, and the input range of the input source VO1 is 200mV - 1V. Figure 4 It can be seen that the maximum power tracking efficiency is between 96.64% and 98.93%. When the input voltage is 300mV, the input power is 112.5uW, the tracked power is 111.3uW, and the tracking efficiency is 98.93%. In the AC source voltage multiplier rectification structure, the AC source VO2 simulates a piezoelectric energy source. The input AC voltage source VO2 of the circuit has an input range of 600mV - 1V, the input frequency is fixed at 200HZ, and the input capacitance is fixed at 15uF. Figure 5 We can see that when the AC input source ranges from 600mV to 1V, the peak conversion efficiency of the circuit is 89% - 95.6%. For the overall circuit simulation, when the DC input source is 500mV and the AC input source is 800mV, the output power is approximately 10.23mW, and the circuit conversion efficiency is 76.7%.

[0056] The above embodiments are only specific examples for further detailed description of the purpose, technical solutions, and beneficial effects of the present invention, and the present invention is not limited thereto. Any modifications, equivalent replacements, improvements, etc. made within the scope of the disclosure of the present invention are included in the protection scope of the present invention.

Claims

1. A self-powered dual-input dual-output energy harvesting circuit with maximum power point tracking, characterized in that: It includes a DC-DC boost circuit, an AC-DC rectifier doubler circuit, a dual-output self-powered circuit, and a switch control module; The DC-DC boost circuit includes a DC input power supply model VO1, R, a maximum power point tracking circuit A2, an oscillator A1, a capacitor Ci1, an inductor L, and an NMOS transistor NS1; The DC input power supply model VO1 and R are connected to the maximum power point tracking circuit to generate an output voltage Vin and Vmppt. The maximum power point tracking circuit is connected to the oscillator A1. The voltage Vin is connected to one end of the capacitor Ci1 and the inductor L respectively. The capacitor Ci1 is grounded at the same time. The source of the NMOS transistor NS1 is grounded, the gate is controlled by the signal SW1R generated by the switch control module, and the drain is connected to the other end of the inductor L. The drain of the NMOS transistor NS1 and the other end of the inductor L are also respectively connected to the DC part input terminal of the dual-output self-powered circuit; The AC-DC rectifier doubler circuit includes an AC input power supply model VO2, Ci2, two unbalanced comparators CMP2 and CMP3, an NMOS transistor NS2, a capacitor CS, and a PMOS transistor PS7; The AC input power supply model VO2 and Ci2 are respectively connected to the drain of the NMOS transistor NS2, the inverting terminal of the unbalanced comparator CMP2, the inverting terminal of the unbalanced comparator CMP3, and the drain of the PMOS transistor PS7. The source of the NMOS transistor NS2 and the non-inverting terminal of the unbalanced comparator CMP2 are both grounded. The gate of the NMOS transistor NS2 is connected to the output control signal of the unbalanced comparator CMP2. The output signal of the unbalanced comparator CMP3 is connected to the gate of the PMOS transistor PS7. The non-inverting terminal of the unbalanced comparator CMP3 is respectively connected to the source of the PMOS transistor PS7 and the capacitor CS. The capacitor CS is grounded at the same time. The non-inverting terminal of the unbalanced comparator CMP3, the capacitor CS, and the source of the PMOS transistor PS7 are also respectively connected to the other DC part input terminal of the dual-output self-powered circuit; The input terminal of the switch control module is connected to the voltage Vin and Vmppt, the signal Clk generated by the oscillator A1, and the V1 node voltage at the S terminal of the MOS transistor PS1, the V2 node voltage at the D terminal of the MOS transistor PS1, the V3 node voltage at the D terminal of the MOS transistor PS5, and the Vdd node voltage at the D terminal of the MOS transistor PS4 in the dual-output self-powered circuit; The dual-output self-powered circuit includes PMOS transistors PS6, PS5, PS4, PS2, PS3, and PS1, a capacitor Cv, load capacitors CL2 and CL1, and loads 2 and 1; The source of PMOS transistor PS4 is connected to capacitor CS, the non-inverting input terminal of non-balanced comparator CMP3, and the source of PMOS transistor PS7 respectively. Its gate is controlled by the signal SW7R generated by the switch control module, and its drain is connected to capacitor Cv; the source of PMOS transistor PS5 is connected to the source of PMOS transistor PS4, its gate is controlled by the signal SW6R generated by the switch control module, and its drain is connected to load capacitor CL2 and the source of PMOS transistor PS6 respectively; the drain of PMOS transistor PS6 is connected to load 2, and its gate is controlled by the signal SW5R generated by the switch control module; the drain of PMOS transistor PS3 is connected to the source of PMOS transistor PS6 and the drain of PMOS transistor PS5 respectively, its gate is controlled by the signal SW4R generated by the control module, and its source is connected to the source of PMOS transistor PS1, the other end of inductor L, and the drain of NMOS transistor NS1 respectively; the drain of PMOS transistor PS1 is connected to load capacitor CL1 and the source of PMOS transistor PS2 respectively, its gate is controlled by the signal SW2R generated by the switch control module; the drain of PMOS transistor PS2 is connected to load 1, and its gate is controlled by the signal SW3R generated by the switch control module; capacitor Cv, load capacitors CL1 and CL2, and loads 1 and 2 are also grounded.

2. The self-powered maximum power point tracking dual-input dual-output energy harvesting circuit according to claim 1, characterized in that: The switch control module includes a switch control circuit and a buffer, where the switch control circuit includes an input signal detection circuit and an output signal control circuit; The signal detection circuit includes rising edge detection circuits I1, I2, and I11, a zero-crossing comparator I6, comparators I12, a NAND gate I3, an inverter I4, and an RS flip-flop; Among them, the input signal Clk is connected to the rising edge detection circuit I2; the input signals V1 and V2 are connected to the input of the zero-crossing comparator I6, the output of the zero-crossing comparator I6 is connected to the rising edge detection circuit I1, the output signals of the rising edge detection circuits I1 and I2 are connected to the input of the NAND gate I3, the output of the NAND gate I3 is connected to the input of the inverter I4, the output of the inverter I4 is connected to the S terminal of the RS flip-flop, the input signals Vin and Vmppt are connected to the non-inverting input terminal and the inverting input terminal of the comparator I12 respectively, the output of the comparator I12 is connected to the rising edge detection circuit I11, the output terminal of the rising edge detection circuit I11 is connected to the R terminal of the RS flip-flop, and the output Q terminal of the RS flip-flop is used as an enable signal to control the working state of the zero-crossing comparator I6 through the output of the inverter I4 and the output of the rising edge detection circuit I11; The output signal control circuit includes comparators I10, I22, I23, I24, and I28, inverters I8, I9, I17, I18, I20, I25, and I27, NOR gates I7, I16, I19, and I26, and AND gates I15 and I21; The non-inverting input terminal and the inverting input terminal of comparator I10 are respectively connected to the reference voltage 1.22V and V2, and the output of comparator I10 is connected to the input of inverter I9; the output signals of zero-crossing comparator I6 and inverter I9 are both connected to NOR gate I7, the output of NOR gate I7 is connected to the input of inverter I8, and the output of inverter I8 generates control signal SW2. The output signal of inverter I8 and Vdd are connected to NOR gate I13, the output of NOR gate I13 is connected to inverter I14, and the output signals of inverter I14 and comparator I28 are both connected to AND gate I15. The output signal of AND gate I15 and the output signal P of zero-crossing comparator I6 are both connected to NOR gate I16, and the output signal of NOR gate I16 is connected to the input terminal of inverter I17, and inverter I17 generates control signal SW4; the non-inverting input terminal of comparator I22 is connected to the reference voltage 1.6V, the inverting input terminal is connected to V3, the non-inverting input terminal of comparator I23 is connected to the reference voltage 1.62V, the inverting input terminal is connected to V3, and the output signals of comparators I22 and I23 are both connected to AND gate I21. The output signal of AND gate I21 is connected to the input terminal of inverter I20, and the output signals of inverter I20 and comparator I12 are both connected to the input terminal of NOR gate I19. The output signal of NOR gate I19 is connected to inverter I18, and inverter I18 generates control signal SW1; the output of comparator I22 generates control signal SW5. The non-inverting input terminal of comparator I24 is connected to the reference voltage 1.2V, the inverting input terminal is connected to Vdd, and the output signal of comparator I24 is connected to the input signal of inverter I25. The output signal of inverter I25 and the output signal of comparator I22 are both connected to the input terminal of NOR gate I26. The output signal of NOR gate I26 is connected to the input signal of inverter I27, and the output terminal of inverter I27 generates control signal SW6. The output of comparator I24 generates control signal SW7. The non-inverting input terminal of comparator I28 is connected to the reference voltage 1.2V, the inverting input terminal is connected to V2, and the output of comparator I28 generates control signal SW3; Control signals SW1, SW2, SW3, SW4, SW5, SW6, and SW7 are connected to a buffer, and the buffer outputs control signals SW1R, SW2R, SW3R, SW4R, SW5R, SW6R, and SW7R; Among them, the voltage V1 at the S terminal and the voltage V2 at the D terminal of MOS transistor PS1 are the two voltages on the right side of inductor L. The voltage V3 at the D terminal of MOS transistor PS5 is the voltage on the upper plate of load capacitor CL2. The voltage Vdd at the D terminal of MOS transistor PS4 is the voltage on capacitor Cv.

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