Temperature-stable oscillator

Abstract

Embodiments of the present disclosure relate to temperature-stable oscillators. The oscillator circuit includes a first current generator circuit and a second current generator. The first current generator circuit generates a current that is complementary to absolute temperature, and the second current generator generates a current that is proportional to absolute temperature. The temperature ramp control circuit adjusts the slopes of the current complementary to absolute temperature and the current proportional to absolute temperature in a complementary manner, and adds the current complementary to absolute temperature and the current proportional to absolute temperature after slope control to generate a temperature-independent current. The current control circuit adjusts the amplitude of the temperature-independent current to generate an amplitude-adjusted temperature-independent current. The current-controlled oscillator generates an output signal based on the amplitude-adjusted temperature-independent current.

Description

Technical Field

[0001] This disclosure relates to the field of amorphous-based temperature-stable oscillators. Background Art

[0002] Microelectromechanical devices (referred to as MEMS devices) are becoming increasingly ubiquitous in modern technologies such as smart phones, smart watches, and picoprojectors. Of particular concern for MEMS devices is that their performance remains consistent or constant over a certain temperature range. This in turn requires that the oscillators used to generate the clock signals used by such MEMS devices provide a stable and constant frequency output over a certain temperature range.

[0003] Although ordinary quartz crystals can provide this function, typical MEMS devices lack the available space to accommodate quartz crystals. Thus, there is a need to generate on-chip clock signals through amorphous-based oscillators that can provide the required stable and constant frequency output over a certain temperature range.

[0004] One existing method is to design an RC oscillator that utilizes a resistor made of a material having a resistance that is constant with temperature. However, this temperature independence tends to exist only under ordinary operating conditions, and under certain conditions, the resistance may undergo an undesired change, resulting in a change in the frequency of the generated clock signal. To address this problem, this existing method further employs a resistor trimming circuit.

[0005] Although this trimming is effective, it requires testing at different temperatures in order to properly tune the trimming circuit. Unfortunately, this testing at temperature is difficult in a production environment because the thermal cycling involved consumes a significant amount of time and is costly. Additionally, temperature measurement of the chip itself is difficult. Moreover, it is difficult and expensive to move wafers between different devices. Taken together, the fact is that measurement errors may be introduced, depending on the calibration of the device.

[0006] Therefore, there is a need to design new amorphous-based oscillators that can provide a stable and consistent output over temperature. Moreover, there is also a need for faster and cheaper methods of testing such oscillators. Summary of the Invention

[0007] This disclosure relates to an electronic device that includes: a first current generator circuit configured to generate a current complementary to absolute temperature; a second current generator configured to generate a current proportional to absolute temperature; a temperature slope control circuit configured to adjust, in a complementary manner, the slope of the current complementary to absolute temperature and the slope of the current proportional to absolute temperature, and add the adjusted-slope current complementary to absolute temperature and the adjusted-slope current proportional to absolute temperature to generate a temperature-independent current; a current control circuit configured to adjust the amplitude of the temperature-independent current to generate a temperature-independent current with an adjusted amplitude; and a current-controlled oscillator configured to generate an output signal based on the temperature-independent current with the adjusted amplitude.

[0008] The feedback control circuit may be configured to: influence the adjustment of the slopes of the current complementary to absolute temperature and the current proportional to absolute temperature based on the output signal.

[0009] The heating circuit may be configured to change the temperature of a component of the current-controlled oscillator.

[0010] The temperature slope control circuit may adjust the slopes of the current complementary to absolute temperature and the current proportional to absolute temperature in response to a first control signal.

[0011] The current control circuit may adjust the amplitude of the temperature-independent current in response to a second control signal.

[0012] The built-in self-test circuit may be configured to receive the output signal to: compare the frequency of the output signal with a desired frequency and send the result of the comparison to an automatic test equipment. The first control signal and the second control signal may be received from the automatic test equipment.

[0013] The heating circuit may be configured to: change the temperature of a component of the current-controlled oscillator in response to a third control signal received from the automatic test equipment.

[0014] The built-in self-test circuit may be configured to: receive the output signal and generate the first control signal and the second control signal based on the frequency of the output signal.

[0015] The heating circuit may be configured to: change the temperature of a component of the current-controlled oscillator in response to a third control signal received from the built-in self-test circuit.

[0016] The present disclosure also discloses some method embodiments. One method embodiment is a method for calibrating an oscillator. The method includes: generating a current complementary to the absolute temperature; generating a current proportional to the absolute temperature; generating a temperature-independent current based on the current complementary to the absolute temperature and the current proportional to the absolute temperature; generating an output signal based on the temperature-independent current; measuring the frequency of the output signal; and if the frequency of the output signal is not within a coarse threshold of a desired frequency, adjusting the slopes of the current complementary to the absolute temperature and the current proportional to the absolute temperature in a complementary manner until the frequency of the output signal is within the coarse threshold of the desired frequency.

[0017] After the frequency of the output signal is within the coarse threshold of the desired frequency, the method may include: adjusting the amplitude of the temperature-independent current; activating a self-heating circuit to change the temperature of at least a part of the oscillator; and if the frequency of the output signal is not within a fine threshold of the desired frequency, adjusting the amplitude of the temperature-independent current and / or adjusting the temperature of at least a part of the oscillator until the frequency of the output signal is within the fine threshold of the desired frequency. Description of the Drawings

[0018] Figure 1 is a block diagram of the oscillator circuit disclosed herein.

[0019] Figure 2 shows tuning in a complementary manner Figure 1 the influence of the slopes of IPTAT and IPTAT in Figure 1 and the influence of adjusting the amplitude of current I1 in

[0020] Figure 3 is a top view of an integrated circuit of the oscillator circuit including Figure 1 .

[0021] Figure 4A shows when the self-heating circuit is not used Figure 1 the frequency stability of the output signal in

[0022] Figure 4B shows when the self-heating circuit is used Figure 1 the frequency stability of the output signal in

[0023] Figure 4C shows Figure 4B a partial enlarged view of a part of the illustration

[0024] Figure 5 is Figure 1 a schematic block diagram of a first embodiment of the oscillator circuit

[0025] Figure 6 isFigure 1 Schematic block diagram of a second embodiment of an oscillator circuit.

[0026] Figure 7A Shows Figure 5 and Figure 6 Illustration of the comparison of ICTAT therebetween.

[0027] Figure 7B Shows Figure 5 and Figure 6 Illustration of the comparison of the frequency of the output signal of the CCO therebetween.

[0028] Figure 7C Shows Figure 5 and Figure 6 Illustration of the comparison of the current I2 therebetween.

[0029] Figure 8A Shows Figure 5 Illustration of the normalized frequency error of the output signal of the CCO in

[0030] Figure 8B Shows Figure 6 Illustration of the normalized frequency error of the output signal of the CCO in

[0031] Figure 9 Includes Figure 1 Block diagram of an integrated circuit of an oscillator circuit when connected to an automatic test equipment.

[0032] Figure 10 Is Figure 9 Timing diagram of a first test operation performed using the arrangement shown.

[0033] Figure 11 Is Figure 10 Flowchart of a method for performing a first test operation.

[0034] Figure 12 Is Figure 9 Timing diagram of a second test operation performed using the arrangement shown.

[0035] Figure 13 Is Figure 12 Flowchart of a method for performing a second test operation.

[0036] Figure 14 Includes Figure 1 Block diagram of an alternative arrangement of an integrated circuit of an oscillator circuit when connected to an automatic test equipment.

[0037] Figure 15 Is Figure 1 Schematic diagram of a third embodiment of the oscillator circuit in DETAILED DESCRIPTION

[0038] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. Without departing from the spirit and scope of the disclosure herein, the general principles described herein can be applied to other embodiments and applications in addition to the embodiments and applications detailed above. The present disclosure is not intended to be limited to the embodiments shown, but should be accorded the broadest scope consistent with the principles and features disclosed or suggested herein.

[0039] Disclosed herein is an oscillator circuit that generates a stable output within a certain temperature change range, which can achieve this without using a crystal oscillator and can be fabricated in a sufficiently small size to fit within a MEMS circuit package. First, the oscillator circuit will be described, and then, the testing and tuning of the oscillator circuit will be described.

[0040] A. Description of the Oscillator Circuit

[0041] Reference Figure 1 As shown, oscillator circuit 100 includes a current generator circuit 102 that generates a current ICTAT complementary to absolute temperature and a current IPTAT proportional to absolute temperature.

[0042] The temperature slope control circuit 104 (which in some cases can be considered a digital-to-analog converter (DAC)) adjusts the slopes of ICTAT and IPTAT in a complementary manner based on the feedback control signal 103. After slope adjustment, the temperature slope control circuit 104 adds ICTAT and IPTAT to produce a current I1 independent of temperature. The slope of ICTAT is corrected by a constant K1, and the slope of IPTAT is corrected by N - K1, so I1 = K1 * ICTAT+(N - K1) * IPTAT.

[0043] The current control circuit 106 (which can be considered a digital-to-analog converter in some cases) receives I1 and adjusts the magnitude of its slope to produce an amplitude-adjusted current I2 independent of temperature. The magnitude of the slope of I1 is corrected by a constant K2, such that I2 = K2 * [K1 * ICTAT+(N - K1) * IPTAT]. I2 is used to control a current-controlled oscillator (CCO) 108, which generates an output signal Fout with a current of Iout. Iout can be expressed as Iout = KVCO * K2 * [K1 * ICTAT+(N - K1) * IPTAT].

[0044] The feedback control circuit 110 receives Fout and generates a feedback-based control signal 103 for the temperature slope control circuit 104 from Fout.

[0045] In Figure 2The influence of the tuning of K1 can be seen in traces A and B. The arrows on the right side of the traces indicate that the different traces are different frequency versions of the output signal, with the difference being the value of K1. In Figure 2 The influence of the tuning of K2 can be seen in traces A and B. The arrows on the left side of traces A and B show that, based on the tuning of K2, the traces can move from position A to position B. Thus, K1 adjusts the slope of the output signal (in terms of frequency versus temperature), while K2 adjusts the amplitude of the output signal.

[0046] The self-heating device 112 is used to change the temperature of the current-controlled oscillator 108 to assist in generating different output frequencies of the CCO at different temperatures. The self-heating device can be a heating element (such as a resistor) placed around the CCO 108, as Figure 3 shown. Assuming a thermal resistance of the chip package of 125 °C / W, a 32.4 Ω resistor powered by 3.6 V can achieve a power loss of 0.4 W, and this results in a potential temperature increase of 50 °C, which allows for sufficient temperature offset on the A and B diagrams to further fine-tune and tune the temperature consistency of the output signal frequency.

[0047] From Figures 4A - 4C it can be seen the influence of temperature changes (whether originating from the surrounding environment or forced by the self-heating device 112) on the output signal. In Figure 4A shown, the output signal presented is not fine-tuned. As a result, the frequency stability of the output signal with respect to temperature can be ±2%. However, when fine-tuning is applied, the frequency stability of the output signal with respect to temperature can be improved to ±0.15%, as Figures 4B - 4C shown. To achieve this accuracy, the fine-tuning process requires probing the CCO frequency at two different frequencies that are completely different from each other. The self-heating device 112 is advantageously used to achieve this without the need for complex external instruments outside the chip, but rather simply by locally self-heating the CCO and obtaining the temperature increase as derived above (e.g., 50 degrees in the example).

[0048] Now refer to Figure 5A first exemplary embodiment of the oscillator circuit 100 is described. The first current generator circuit 102a generates ICTAT. The first current generator circuit 102a includes PMOS transistors MP1 and MP2 connected in a current mirror relationship, where their sources are connected to VDD, and their gates are interconnected and connected to the drain of transistor MP2. NMOS transistors MN1 and MN2 are connected in a cascode configuration, where their gates are interconnected. The drain of transistor MN1 is connected to the drain of transistor MP1, while the drain of transistor MN2 is connected to the drain of transistor MP2. The gates of transistors MN1 and MN2 are connected to the drains of transistors MP1 and MN1. The source of transistor MN2 is connected to ground through resistor R1. The NPN transistor QN1 has a collector connected to the source of transistor MN1, a base connected to its collector, and an emitter connected to ground.

[0049] In operation, once in the steady state, the current mirror formed by transistors MP1 and MP2 forces the drain currents of transistors MN1 and MN2 to be equal, and thus forces the gate-source voltages Vgs of transistors MN1 and MN2 to be equal. This results in the base-emitter voltage Vbe of QN1 being applied at the source of transistor MN2. The resulting current ICTAT flowing through resistor R1 is complementary to the absolute temperature (CTAT), and can be calculated as ICTAT = VbeQN1 / R1.

[0050] The second current generator circuit 102b generates the current IPTAT. The second current generator circuit 102b includes PMOS transistors MP3 and MP4 connected in a current mirror relationship, where their sources are connected to VDD, and their gates are interconnected and connected to the drain of transistor MP4. NMOS transistors MN3 and MN4 are connected in a cascode configuration, where their gates are interconnected. The drain of transistor MN3 is connected to the drain of transistor MP3, while the drain of transistor MN4 is connected to the drain of transistor MP4. The gates of transistors MN3 and MN4 are connected to the drain of transistor MN3. The source of transistor MN3 is connected to the collector of the NPN transistor QN2. The emitter of transistor QN2 is connected to ground, while the base of transistor QN2 is connected to its collector. The source of transistor MN4 is connected to resistor R2, which in turn is connected to the collector of the NPN transistor QN3. The emitter of transistor QN3 is connected to ground, while the base of transistor QN3 is connected to its collector.

[0051] Once operating in the steady state, the current mirror formed by transistors MP3 and MP4 forces the drain currents of transistors MN3 and MN4 to be equal, and thus forces the gate-source voltages Vgs of transistors MN3 and MN4 to be equal. This causes the base-emitter voltage of transistor QN3 to be applied at the source of transistor MN3. Since resistor R1 is between the base-emitter voltages of transistors QN2 and QN3, the voltage across resistor R2 is VbeQN3 - VbeQN2, and can be referred to as ΔVbe. The resulting current IPTAT flowing through resistor R1 is proportional to the absolute temperature (PTAT), and flows into transistor QN2 due to the current mirror formed by transistors MN3 and MN4. IPTAT can be calculated as:

[0052] IPTAT = ΔVbe / R1

[0053] The temperature slope control circuit 104 is arranged as a digital-to-analog converter and has an ICTAT branch 104a and an IPTAT branch 104b, the outputs of both being added at a summing node N1. The ICTAT branch 104a includes n PMOS transistors Q1...Qn, the source of each PMOS transistor being connected to VDD, its drain being connected to the first terminal of a corresponding one of n switches Sc1...Scn, and its gate being connected to the gates of transistors MP1 and MP2. The second terminals of switches Sc1…Scn are connected to node N1, so the switches Sc1…Scn are used to selectively couple transistors Q1…Qn to node N1. The IPTAT branch 104b includes m PMOS transistors NQ1...NQm, the source of each PMOS transistor being connected to VDD, its drain being connected to the first terminal of a corresponding one of m switches Sp1...Spm, and its gate being connected to the gates of MP3 and MP4. The second terminals of switches Sp1...Spm are connected to node N1, so the switches Sp1...Spm are used to selectively connect transistors NQ1...NQm to node N1. Switches Sc1…Scn and Sp1...Spm are controlled by a control signal 103 (which is a data bus) from the feedback control circuit 110, and K1 is tuned by changing the states of switches Sc1...Scn and Sp1...Spm in a complementary manner (i.e., for example, if Sc1 is closed, then Sp1 is open, and if Sc1 is open, then Sp1 is closed). Thus, current I1 flows from node N1 to the current control circuit 106.

[0054] The description of the current control circuit 106, CCO 108, and self-heating device 112 is the same as the above description with reference to Figure 1 and thus no further description is required.

[0055] Now refer to Figure 6 a second exemplary embodiment of the oscillator circuit 100’. The second current generator circuit 102b’ generates IPTAT, and will be described first.

[0056] The second current generator circuit 102b’ includes PMOS transistors MP7 and MP8. The sources of the PMOS transistors MP7 and MP8 are connected to VDD, and their gates are connected to each other. The amplifier 120 has a non-inverting terminal, an inverting terminal, and an output. Its non-inverting terminal is connected to the drain of the transistor MP7, and its inverting terminal is connected to the drain of the transistor MP8. Its output is connected to the gates of the transistors MP7 and MP8. The NPN transistor QN4 has a collector, an emitter, and a base. Its collector is connected to the source of the transistor MP7, its emitter is connected to ground, and its base is connected to its collector. The resistor R4 is connected between the inverting terminal of the amplifier 120 and the emitter of the NPN transistor QN5. The transistor QN5 has a collector and a base. Its collector is connected to ground, and its base is connected to its emitter. Note that the transistor MP6 has a source and a drain. Its source is connected to VDD, and its drain is connected to the summing node N2, but there is no intermediate switch.

[0057] In operation, once the steady state is reached, the amplifier 120 forces the drain voltages of the transistors MP7 and MP8 to be equal. As a result, the base-emitter voltage of the NPN transistor QN4 is applied at the drain of the transistor MP8, that is, R4 is between the base-emitter voltages of the transistors QN4 and QN5. Therefore, the voltage across the resistor R4 is VbeQN4 - VbeQN5, and can be referred to as ΔVbe. The resulting current IPTAT flowing through the resistor R4 is proportional to the absolute temperature (PTAT), and flows into the transistor QN4 due to the current mirror effectively formed by the transistors MP7 and MP8. IPTAT can be calculated as:

[0058] IPTAT = ΔVbe / R4

[0059] The first current generator 102a’ generates ICTAT, and will now be described. The first current generator 102a’ includes PMOS transistors MP5 and MP6. The sources of the PMOS transistors MP5 and MP6 are connected to VDD, and their gates are connected to each other. The amplifier 118 has a non-inverting terminal and an inverting terminal, where its non-inverting terminal is connected to the drain of the transistor MP5, and its inverting terminal is connected to the collector of the transistor QN4 in the second current generator circuit 102b’. The resistor R3 is connected between the non-inverting terminal of the amplifier 118 and ground.

[0060] In operation, once a steady state is reached, amplifier 118 uses VbeQN4 as the reference voltage for feedback, forcing the drain voltage of MP5 to the value of VbeQN4. This in turn causes a current ICTAT, which is complementary to absolute temperature, to flow through resistor R3. This current is then mirrored to the drain of transistor MP6 via the current mirror relationship imposed on transistors MP5 and MP6 by amplifier 118. ICTAT can be calculated as ICTAT = VbeQN4 / R3. Note that due to the mismatch between the ICTAT and IPTAT currents, using VbeQN4 to generate ICTAT helps reduce system dissipation as it removes a source of mismatched devices. Also note that in the second embodiment, the voltage applied across resistor R3, the voltage applied across transistor QN4, and the voltage applied across resistor R4 in series with transistor QN5 are strictly equal, while in the first embodiment, the above voltages are subject to the mismatch and variation of Vgs(MN1, MN2, MN3, MN4). Thus, while the second embodiment is still not ideal in this regard, it exhibits better performance, especially linear for the variation of the total current generated with temperature.

[0061] The temperature slope control circuit 104 is arranged as a digital-to-analog converter and has an ICTAT branch 104a and an IPTAT branch 104b, the respective outputs of which are added at a summing node N2. The ICTAT branch 104a includes n PMOS transistors Q1...Qn, the source of each PMOS transistor being connected to VDD, its drain being connected to the first terminal of a respective one of n switches Sc1...Scn, and its gate being connected to the gates of transistors MP5 and MP6. The second terminals of switches Sc1…Scn are connected to node N2, so that switches Sc1…Scn are used to selectively couple transistors Q1…Qn to node N2. The IPTAT branch 104b includes m PMOS transistors NQ1...NQm, the source of each PMOS transistor NQ1...NQm being connected to VDD, its drain being connected to the first terminal of a respective one of m switches Sp1...Spm, and its gate being connected to the gates of MP7 and MP8. The second terminals of switches Sp1...Spm are connected to node N2, so that switches Sp1...Spm are used to selectively connect transistors NQ1…NQm to node N2. Although not shown in Figure 5is shown, but note that switches Sc1…Scn and Sp1...Spm are controlled by control signal 103 from feedback control circuit 110, and K1 is tuned by changing the states of switches Sc1...Scn and Sp1...Spm in a complementary manner (i.e., for example, if Sc1 is closed, then Sp4 is open, and if Sp4 is open, then Sp1 is closed). As a result, current I1 flows from node N2 to current control circuit 106.

[0062] The descriptions of current control circuit 106, CCO 108, and self-heating device 112 are the same as the above description with reference to Figure 1 and thus no further description is required.

[0063] Figure 5 the oscillator circuit 100 in Figure 6 and the oscillator circuit 100’ in Figures 7A - 7C both provide stability far exceeding that of the prior art. However, as can be seen in Figure 5 compared with the oscillator circuit 100 of Figure 6 the oscillator circuit 100’ in Figure 5 provides a higher frequency stability of the output signal Fout with respect to temperature. For example, compared with the ICTAT ( Figure 7A referred to as “V1” in Figure 6 ) generated by the oscillator circuit 100 in Figure 7A the ICTAT ( Figure 6 ) generated by the oscillator circuit 100’ in Figure 7C referred to as “V2” in Figure 5 has a higher linearity with respect to temperature. Additionally, Figure 6 the I2 ( Figure 7B referred to as “the final bias current of the oscillator” in Figure 5 ) generated by oscillator 100’ in Figure 6 has a higher linearity with respect to temperature than the I2 generated by the oscillator circuit 100 in Figure 5 . Moreover,

[0064] Figure 6 the frequency of the output signal generated by the oscillator circuit 100’ in Figure 8A (which shows Figure 5 ) has a higher linearity with respect to temperature than the frequency of the output signal generated by the oscillator circuit 100 in Figure 8B (which showsFigure 6 from the decrease in the frequency error with temperature of the oscillator circuit 100' as shown. By using the self-heating device 112, the Figure 6 linear frequency variation of the oscillator circuit 100' can be easily corrected. In fact, since the variation is linear, two-point correction can be easily performed, and the self-heating device is sufficient to operate to heat the chip at two different temperatures. As long as the difference between the two temperatures is large enough to allow interpolation between the two operating points, it is not necessary to know them precisely.

[0065] Reference Figure 15 , now another embodiment of the oscillator circuit 100” will be described. The oscillator circuit 100” includes an ICTAT generation circuit 102a” that generates ICTAT and an IPTAT generation circuit 102b” that generates IPTAT.

[0066] The temperature slope control circuit 104” adjusts the slopes of ICTAT and IPTAT in a complementary manner based on a feedback signal (not shown in this figure, but denoted as 103 in Figure 1 ). After the slope adjustment, the temperature slope control circuit 104” adds ICTAT and IPTAT to generate a current I1 that is independent of temperature. The slope of ICTAT is corrected by a constant K1, and the slope of IPTAT is corrected by N - K1. Thus, I1 = K1 * ICTAT+(N - K1) * IPTAT.

[0067] The current control circuit 106” receives I1 and adjusts the amplitude of its slope to generate an amplitude-adjusted current I2 that is independent of temperature. The amplitude of the slope of I1 is corrected by a constant K2, so I2 = K2 * [K1 * ICTAT+(N - K1) * IPTAT]. I2 is used to control the CCO 108”, which generates an output signal Fout with a current Iout. Iout can be expressed as Iout = KVCO * K2 * [K1 * ICTAT+(N - K1) * IPTAT].

[0068] The feedback control circuit (not shown in this figure, but denoted as 110 in Figure 1 ) receives Fout and generates a feedback-based control signal for the temperature slope control circuit 104”.

[0069] The "ICTAT generation circuit 102a" includes PMOS transistors MP10 and MP11. The sources of transistors MP10 and MP11 are coupled to VDD, and their gates are coupled to each other. The drain of transistor MP10 is coupled to ground through resistor R5, and the drain of transistor MP11 is coupled to the drain of NMOS transistor MN10 (described below) through resistor R7. Amplifier 118" has a non-inverting terminal and an inverting terminal, where the non-inverting terminal is coupled to the drain of transistor MP10, and its inverting terminal is coupled to the collector of NPN transistor QN10. Transistor QN10 has an emitter coupled to ground and a base coupled to its collector.

[0070] In operation, amplifier 118" makes the drain voltage of transistor MP10 equal to the collector voltage of bipolar transistor QN10, resulting in the voltage across resistor R5 being VbeQN10. The resulting ICTAT flows through resistor R5 and is mirrored to the drain of transistor MP11 via the current mirror arrangement formed by transistors MP10 and MP11.

[0071] The "IPTAT generation circuit 102b" includes PMOS transistors MP12 and MP13. The sources of transistors MP12 and MP13 are coupled to VDD, and their gates are coupled to each other. The drain of transistor MP12 is coupled to the collector of transistor QN10 and the non-inverting terminal of amplifier 120". The inverting terminal of amplifier 120" is coupled to the drain of transistor MP13 and is coupled to the collector of NPN transistor QN11 through resistor R6. Transistor QN11 has a collector coupled to its base and an emitter coupled to ground. PMOS transistor MP14 has a source coupled to VDD and a drain coupled to resistor R8 (described below). Amplifier 120" also has a non-inverting terminal and an inverting terminal, whose non-inverting terminal is coupled to the collector of transistor QN10 and whose inverting terminal is coupled to the drain of transistor MP13.

[0072] In operation, amplifier 120" makes the drain voltage of transistor MP13 equal to VbeQN10, and thus resistor R6 is between VbeQN10 and VbeQN11, and IPTAT flows through resistor R6. Through the current mirror arrangement among transistors MP12, MP13, and MP14, IPTAT is mirrored to the drain of transistor MP14.

[0073] The "temperature slope control circuit 104" includes a resistor R7, and the resistor R7 receives ICTAT from the ICTAT generation circuit 102a". The resistor R7 is coupled to the drain of the NMOS transistor MN10, and the source of the transistor MN10 is coupled to the drain of the NMOS transistor MN11. The source of the transistor MN11 is coupled to ground, and its gate is coupled to the drain of the transistor MN10. The gate of the transistor MN10 is coupled to the drain of the transistor MP11.

[0074] The "temperature slope control circuit 104" further includes a resistor R8, and the resistor R8 receives IPTAT from the IPTAT generation circuit 102b". The resistor R8 is coupled to the drain of the NMOS transistor MN28 and the gate of the NMOS transistor MN29. The drain of the transistor MN28 is coupled to the resistor R8, its gate is coupled to the drain of the transistor MP14, and its source is coupled to the drain of the transistor MN29. The source of the transistor MP29 is coupled to ground, and its gate is coupled to the resistor R8.

[0075] The "temperature slope control circuit 104" includes a switching transistor circuit 151, which is coupled to the gates of the transistors MN10, MN11, MN28, and MN29, and includes a given even number of pairs of NMOS transistors connected in series, where the drains of the upper transistors in the series-connected NMOS transistors are coupled to each other, the sources of the upper transistors in the series-connected NMOS transistors are coupled to the drains of the lower transistors in the series-connected NMOS transistors, and the sources of the lower transistors in the series-connected NMOS transistors are coupled to ground. The gates of the upper transistors in the series-connected NMOS transistors are coupled to the gates of the transistors MN10 and MN28. The gates of the lower transistors in the series-connected NMOS transistors are selectively coupled to each other and to the gates of the transistors MN11 and MN29 through switches. These switches are set by a feedback control signal ( Figure 1 shown as 103 in the figure), and the settings of these switches are to adjust K1, and thus adjust the slopes of ICTAT and IPTAT.

[0076] The current control DAC 106" includes a resistor R9, and the resistor R9 is coupled to a transistor circuit 151 for receiving the current I1. The source of the PMOS transistor MP15 is coupled to VDD, and its drain is coupled to the source of the PMOS transistor MP16. The drain of the transistor MP16 is coupled to the resistor R9.

[0077] The "current-controlled DAC 106" further includes a switching transistor circuit 153, which is coupled to the gates of transistors MP15, MP16, MP23, and MP24, and includes a given even number of pairs of PMOS transistors connected in series. The source of the upper transistor in the series-connected PMOS transistors is coupled to VDD, the drain of the upper transistor in the series-connected PMOS transistors is coupled to the source of the lower transistor in the series-connected PMOS transistors, and the drains of the lower transistors in the series-connected PMOS transistors are interconnected. The gates of the lower transistors in the series-connected PMOS transistors are coupled to the gates of transistors MP16 and MP24. The gates of the upper transistors in the series-connected PMOS transistors are selectively coupled to each other and to the gate of transistor MP16 through switches. These switches are set by control signals ( Figure 1 shown as 105 in), and the settings of these switches are to adjust K2, and thus adjust the amplitude of I1.

[0078] As explained, the current-controlled oscillator 108" generates an output signal Fout based on I2 received from the current-controlled DAC 106".

[0079] B. Description of Testing and Tuning of Oscillator Circuit

[0080] Reference Figure 9 , now describe a first tuning arrangement 250 for tuning K1 and K2 in the oscillator circuit 100 or oscillator circuit 100'. The tuning arrangement 250 includes an automatic test equipment (ATE) 252, which includes an FPGA or other form of firmware control. A chip current control circuit or package 254 is connected to the ATE 252, and the chip current control circuit or package 254 includes the oscillator circuit 100 or oscillator circuit 100' and a built-in self-test (BIST) circuit 256 and a register set 258. Note that the ATE 252 provides a heating control signal Heating_Control to the self-heating device 112, and provides a control signal 103 for tuning K1 and a control signal 105 for tuning K2.

[0081] Now refer to Figures 10 - 13 to describe the operation of the first tuning arrangement 250. At time t1, the test enable signal TEST_EN fed to the BIST 256 rises (see Figure 10 ), which is generally as described in step 301 (see Figure 11 ): receiving an external signal for starting a self-test. As described in step 302 (see Figure 11 ), at time t2, the precise timing window signal T_Precise fed to the BIST 256 rises (seeFigure 10 )。As described in step 303 (see Figure 11 ), at time t3, at the falling edge of T_Precise (see Figure 10 ), BIST 256 measures the output frequency of CCO 108 (CCO 108 generates Fout). Then, as described in step 304 (see Figure 11 ), the output frequency of CCO 108 is stored in register bank 258.

[0082] If the output frequency is not within the desired threshold of the target frequency stored in register bank 258, as described in step 305 (see Figure 11 ), then ATE 252 changes control signal 105 to tune K2 and feeds it to current control circuit 106, as described in step 307 (see Figure 11 ). Then, at time t4 (see Figure 10 ), as described in step 308 (see Figure 11 ), the next rising edge of T_Precise is received, and the operation loop returns to step 303.

[0083] If the output frequency is within the desired threshold of the target frequency stored in register bank 258, as described in step 305 (see Figure 11 ), then at time t5 (see Figure 12 ), the self-heating process is activated, as described in step 306 (see Figure 11 ).

[0084] During the self-heating process, as described in step 311 (see Figure 13 ), at time t5 (see Figure 12 ), the next rising edge of T_Precise is received, and then at time t6 (see Figure 12 ), i.e., at the falling edge of T_Precise, as described in step 312 (see Figure 13 ), BIST 256 measures the output frequency of CCO 108. Then, as described in step 313 (see Figure 13 ), the output frequency of CCO 108 is stored in register bank 258. As described in step 314 (see Figure 13 ), if the output frequency is within the desired fine threshold of the target frequency, then the tuning is completed in step 315. However, if the output frequency is not within the desired fine threshold of the target frequency, then the control signal 103 that controls K1 is changed by ATE 252, and at time t7 (see Figure 12 ), the self-heating device 112 is activated by the assertion of the Heating_Control signal, as described in step 316 (see Figure 13) as described. Then, the operation loop returns to step 311 and continues until, in the iteration of step 314 (see Figure 13 ), the output frequency is within the desired fine threshold of the target frequency, at which point the tuning is completed in step 315.

[0085] Figure 14 An alternative tuning arrangement 250' is shown in. The difference between the tuning arrangement 250' and the tuning arrangement 250 is that the BIST 256' outputs control signals 103 and 105 and the Heating_Control signal. Additionally, the operation is the same as that of the tuning arrangement 250. The advantage of this tuning arrangement 250' is that it reduces the dependence on the ATE 252', that is, fewer probes are required, thus potentially reducing the production cost.

[0086] Although the present disclosure has been described with respect to a limited number of embodiments, those skilled in the art who benefit from the present disclosure will understand that other embodiments can be envisioned without departing from the scope of the disclosure as disclosed herein. Therefore, the scope of the present disclosure is defined only by the appended claims.

Claims

1. An electronic device, comprising: a first current generator circuit configured to generate a current complementary to absolute temperature; a second current generator configured to generate a current proportional to absolute temperature; a temperature slope control circuit configured to: adjust the slope of the current complementary to absolute temperature and the slope of the current proportional to absolute temperature in a complementary manner, and add the adjusted-slope current complementary to absolute temperature and the adjusted-slope current proportional to absolute temperature to generate a temperature-independent current, wherein the temperature slope control circuit adjusts the slope of the current complementary to absolute temperature and the slope of the current proportional to absolute temperature in response to a first control signal; a current control circuit configured to adjust the amplitude of the temperature-independent current to generate a temperature-independent current with an adjusted amplitude, wherein the current control circuit adjusts the amplitude of the temperature-independent current in response to a second control signal; a current-controlled oscillator configured to generate an output signal based on the temperature-independent current with the adjusted amplitude; and a built-in self-test circuit configured to receive the output signal to: compare the frequency of the output signal with a desired frequency and send the result of the comparison to an automatic test equipment, wherein the first control signal and the second control signal are received from the automatic test equipment.

2. The electronic device according to claim 1, further comprising a feedback control circuit configured to: affect the adjustment of the slope of the current complementary to absolute temperature and the slope of the current proportional to absolute temperature based on the output signal.

3. The electronic device according to claim 1, further comprising a heating circuit configured to change the temperature of a component of the current-controlled oscillator.

4. The electronic device according to claim 1, further comprising a heating circuit configured to: change the temperature of a component of the current-controlled oscillator in response to a third control signal received from the automatic test equipment.

5. An electronic device, comprising: a first current generator circuit configured to generate a current complementary to absolute temperature; a second current generator configured to generate a current proportional to absolute temperature; a temperature slope control circuit configured to: adjust the slope of the current complementary to absolute temperature and the slope of the current proportional to absolute temperature in a complementary manner, and add the adjusted-slope current complementary to absolute temperature and the adjusted-slope current proportional to absolute temperature to generate a temperature-independent current, wherein the temperature slope control circuit adjusts the slope of the current complementary to absolute temperature and the slope of the current proportional to absolute temperature in response to a first control signal; A current control circuit configured to adjust the amplitude of the temperature-independent current to produce a temperature-independent current with an adjusted amplitude, wherein the current control circuit adjusts the amplitude of the temperature-independent current in response to a second control signal; A current controlled oscillator configured to generate an output signal based on the temperature-independent current with the adjusted amplitude; and A built-in self-test circuit configured to receive the output signal and generate the first control signal and the second control signal based on the frequency of the output signal.

6. The electronic device according to claim 5, further comprising a heating circuit configured to change the temperature of a component of the current controlled oscillator in response to a third control signal received from the built-in self-test circuit.

7. A method of calibrating an oscillator, comprising: Generating a current complementary to absolute temperature; Generating a current proportional to absolute temperature; Generating a temperature-independent current from the current complementary to absolute temperature and the current proportional to absolute temperature; Generating an output signal based on the temperature-independent current; Measuring the frequency of the output signal; If the frequency of the output signal is not within a coarse threshold of a desired frequency, adjusting the slope of the current complementary to absolute temperature and the slope of the current proportional to absolute temperature in a complementary manner until the frequency of the output signal is within the coarse threshold of the desired frequency; and After the frequency of the output signal is within the coarse threshold of the desired frequency: Adjusting the amplitude of the temperature-independent current; Activating a self-heating circuit to change the temperature of at least a portion of the oscillator; and If the frequency of the output signal is not within a fine threshold of the desired frequency, adjusting the amplitude of the temperature-independent current and / or adjusting the temperature of at least a portion of the oscillator until the frequency of the output signal is within the fine threshold of the desired frequency.

8. An electronic device, comprising: A temperature slope control circuit configured to adjust the slope of a current complementary to absolute temperature and the slope of a current proportional to absolute temperature, and add the current complementary to absolute temperature with the adjusted slope and the current proportional to absolute temperature with the adjusted slope to produce a temperature-independent current, wherein the temperature slope control circuit adjusts the slope of the current complementary to absolute temperature and the slope of the current proportional to absolute temperature in response to a first control signal; A current control circuit configured to adjust the amplitude of the temperature-independent current to produce a temperature-independent current with an adjusted amplitude, wherein the current control circuit adjusts the amplitude of the temperature-independent current in response to a second control signal; A current controlled oscillator configured to generate an output signal based on the temperature-independent current with the adjusted amplitude; and A test circuit configured to receive the output signal to: compare the frequency of the output signal with a desired frequency and send the result of the comparison to test equipment, wherein the first control signal and the second control signal are received from the test equipment.

9. The electronic device according to claim 8, wherein the slopes of the current complementary to absolute temperature and the current proportional to absolute temperature are adjusted according to the output signal.

10. The electronic device according to claim 8, further comprising a heating circuit configured to change the temperature of components of the current controlled oscillator.

11. The electronic device according to claim 8, further comprising a heating circuit configured to: in response to a third control signal received from the test equipment, change the temperature of components of the current controlled oscillator.

12. An electronic device comprising: A temperature slope control circuit configured to: adjust the slopes of the current complementary to absolute temperature and the current proportional to absolute temperature, and add the current complementary to absolute temperature with the adjusted slope and the current proportional to absolute temperature with the adjusted slope to generate a temperature-independent current, wherein the temperature slope control circuit adjusts the slopes of the current complementary to absolute temperature and the current proportional to absolute temperature in response to a first control signal; A current control circuit configured to adjust the amplitude of the temperature-independent current to generate a temperature-independent current with an adjusted amplitude, wherein the current control circuit adjusts the amplitude of the temperature-independent current in response to a second control signal; A current controlled oscillator configured to generate an output signal according to the temperature-independent current with the adjusted amplitude; and A test circuit configured to: receive the output signal and generate the first control signal and the second control signal based on the frequency of the output signal.

13. The electronic device according to claim 12, further comprising a heating circuit configured to: in response to a third control signal received from the test circuit, change the temperature of components of the current controlled oscillator.

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