A digital-analog hybrid storage and computing integrated chip and computing device

Abstract

The present invention provides a digital-analog hybrid storage and computing integrated chip and a computing device, comprising: a plurality of flash memory processing arrays and an on-chip memory connected to the plurality of flash memory processing arrays; each of the flash memory processing arrays reads data in the on-chip memory and performs computing on the data to obtain a computing result; the on-chip memory stores the computing result and the input data of the digital-analog hybrid storage and computing integrated chip, thereby realizing the digital-analog hybrid storage and computing integrated function. The digital-analog hybrid storage and computing integrated chip provided by the present invention can effectively reduce design complexity and manufacturing costs, is conducive to large-scale industrialization, increases design flexibility, prolongs the service life of flash memory, and can be used in occasions such as neural network computing.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and in particular to the design of a digital-analog hybrid storage and computing chip and a computing device. Background Art

[0002] In recent years, integrated memory and computing chip architectures have garnered widespread attention and research. The basic idea behind traditional integrated memory and computing chip architectures is to integrate logical computing units within memory, thereby performing simple but data-intensive logical computing functions within the memory itself. This reduces the amount of data transmitted between the memory and the processor, as well as the transmission distance. However, integrating logical computing units within memory is both extremely complex and expensive, making it difficult to commercialize on a large scale. Summary of the Invention

[0003] The present invention provides a digital-analog hybrid storage and computing integrated chip to solve the problems existing in the existing storage and computing integrated chips.

[0004] In order to solve the above problems, the present invention adopts the following technical solutions:

[0005] In a first aspect, a digital-analog hybrid storage and computing integrated chip is provided, comprising: a plurality of flash memory processing arrays and an on-chip memory connected to the plurality of flash memory processing arrays;

[0006] Each flash memory processing array reads data from the on-chip memory and performs calculations on the data to obtain calculation results;

[0007] The on-chip memory stores the calculation results and the input data of the digital-analog hybrid storage and computing chip.

[0008] Furthermore, the digital-analog hybrid storage and computing chip also includes:

[0009] A write circuit, connected between the flash memory processing array and the on-chip memory, for writing the operation result into the on-chip memory;

[0010] The reading circuit is connected between the flash memory processing array and the on-chip memory, and is used for reading data and transmitting the data to the flash memory processing array.

[0011] Furthermore, the digital-analog hybrid storage and computing chip also includes:

[0012] ADC, connected between the flash memory processing array and the writing circuit, for converting the operation result into a digital signal and transmitting it to the writing circuit;

[0013] The DAC is connected between the flash memory processing array and the read circuit, and is used to convert the read data into an analog signal and transmit it to the flash memory processing array.

[0014] Furthermore, the on-chip memory includes: SRAM, DRAM, and FLASH.

[0015] Further, each flash memory processing array includes a plurality of programmable semiconductor devices arranged in an array;

[0016] The sources of all programmable semiconductor devices in each column are connected to the same analog voltage input terminal, and multiple columns of programmable semiconductor devices are correspondingly connected to multiple analog voltage input terminals for receiving data;

[0017] The drains of all programmable semiconductor devices in each column are connected to the same analog current output terminal, and multiple columns of programmable semiconductor devices are correspondingly connected to multiple analog current output terminals for outputting calculation results;

[0018] The gates of all programmable semiconductor devices in each row are connected to the same bias voltage input terminal, and multiple rows of programmable semiconductor devices are correspondingly connected to multiple bias voltage input terminals;

[0019] The threshold voltage of each programmable semiconductor device is adjustable.

[0020] Further, each flash memory processing array includes a plurality of programmable semiconductor devices arranged in an array;

[0021] The gates of all programmable semiconductor devices in each row are connected to the same analog voltage input terminal, and multiple rows of programmable semiconductor devices are correspondingly connected to multiple analog voltage input terminals for receiving data;

[0022] The drains of all programmable semiconductor devices in each column are connected to the same first terminal, and multiple columns of programmable semiconductor devices are correspondingly connected to multiple first terminals;

[0023] The sources of all programmable semiconductor devices in each column are connected to the same second terminal, and multiple columns of programmable semiconductor devices are connected to multiple second terminals.

[0024] The threshold voltage of each programmable semiconductor device can be adjusted;

[0025] The first end is the bias voltage input end; the second end is the analog current output end, which is used to output the operation result;

[0026] Alternatively, the first end is an analog current output end for outputting a calculation result; and the second end is a bias voltage input end.

[0027] Furthermore, the digital-analog hybrid storage and computing chip also includes:

[0028] The programming circuit is connected to the source, gate and / or substrate of each programmable semiconductor device in the flash memory processing array and is used to adjust the threshold voltage of the programmable semiconductor device.

[0029] Furthermore, the programming circuit includes: a voltage generating circuit and a voltage control circuit, the voltage generating circuit is used to generate a programming voltage or an erasing voltage, and the voltage control circuit is used to load the programming voltage to the source of the selected programmable semiconductor device, or to load the erasing voltage to the gate or substrate of the selected programmable semiconductor device to regulate the threshold voltage of the programmable semiconductor device.

[0030] Furthermore, the digital-analog hybrid storage and computing chip also includes:

[0031] The controller is connected to each flash memory processing array, the write circuit, the read circuit, and the programming circuit, and is used to control the working state of each flash memory processing array, the threshold voltage of each programmable semiconductor device in the flash memory processing array, the write address of the write circuit, and the read address of the read circuit.

[0032] Furthermore, the programmable semiconductor device uses a floating gate transistor.

[0033] In a second aspect, a computing device for a neural network is provided. The neural network comprises multiple layers of neurons, each layer of neurons performs corresponding operations based on the output results of the neurons in the previous layer. The computing device comprises the above-mentioned digital-analog hybrid storage and computing integrated chip.

[0034] In the digital-analog hybrid storage and computing chip, each flash memory processing array is used to implement the calculations of some neurons in the neural network and store the calculation results in the on-chip memory.

[0035] The digital-analog hybrid storage and computing integrated chip provided by the present invention realizes the digital-analog hybrid storage and computing integrated function by integrating an on-chip memory, and can effectively reduce the design complexity and manufacturing cost, which is conducive to large-scale industrialization. The on-chip memory is used to store input data and data to be processed. The flash memory processing array reads data from the on-chip memory for calculation and processing, and stores the calculation result as the data to be processed in the on-chip memory. If other flash memory processing arrays need to perform further calculation processing on the processing result, they can read the processing result in the on-chip memory. There is no need to cascade the various flash memory processing arrays so that each flash memory processing array can operate independently. Then, each flash memory processing array can be selectively used according to different needs to realize different functions, thereby increasing the flexibility of the design. In addition, because the number of read and write times of the flash memory is limited, storing the data to be processed by the integrated on-chip memory can effectively reduce the number of read and write times of the flash memory and increase the service life of the flash memory.

[0036] On the other hand, the computing device for a neural network provided by the present invention adopts a digital-analog hybrid storage and computing integrated chip and utilizes multiple flash memory processing arrays to realize the computing of multiple layers of neurons in a neural network, wherein one flash memory processing array can be used to realize the computing of one layer of neurons, or multiple flash memory processing arrays can be used to realize the computing of one layer of neurons (wherein each flash memory processing array realizes the computing of part of the neurons in the layer of neurons), or one flash memory processing array can be used to realize the computing of multiple layers of neurons (a part of the flash memory processing array realizes the computing of one layer of neurons, and multiple parts realize the computing of multiple layers of neurons), and the flash memory processing array stores the computing results of the corresponding layer of neurons in the on-chip memory, and the flash memory processing array corresponding to the next layer of neurons realizes the computing of the next layer of neurons by reading the computing results. By adopting the above method, the data between the neurons in each layer of the neural network is transferred through the on-chip memory instead of being directly cascaded, so that the neural network structure (including network size, number of network layers and connection order, etc.) can be flexibly adjusted. In addition, since the calculation results of each flash memory processing array are transferred downward through the on-chip memory, there is no need to match the inputs of each flash memory processing array, making the computing device not only suitable for relatively simple network structures such as fully connected networks, but also for deep learning neural networks with a large amount of data to be processed, such as convolutional neural networks commonly used in image processing and speech processing.

[0037] In order to make the above and other objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 This is a diagram showing the overall architecture of a digital-analog hybrid storage and computing chip according to an embodiment of the present invention;

[0040] Figure 2 This is a partial circuit structure diagram of a digital-analog hybrid storage and computing chip according to an embodiment of the present invention;

[0041] Figure 3 A circuit for a flash memory processing array in a digital-analog hybrid storage and computing integrated chip according to an embodiment of the present invention Figure 1 ;

[0042] Figure 4 A circuit for a flash memory processing array in a digital-analog hybrid storage and computing integrated chip according to an embodiment of the present invention Figure 2 ;

[0043] Figure 5 A circuit for a flash memory processing array in a digital-analog hybrid storage and computing integrated chip according to an embodiment of the present invention Figure 3 ;

[0044] Figure 6 A circuit for a flash memory processing array in a digital-analog hybrid storage and computing integrated chip according to an embodiment of the present invention Figure 4 ;

[0045] Figure 7 A circuit for a flash memory processing array in a digital-analog hybrid storage and computing integrated chip according to an embodiment of the present invention Figure 5 ;

[0046] Figure 8 Schematic diagram of the operation of a single neuron;

[0047] Figure 9 The embodiment of the present invention is used to implement a digital-analog hybrid storage and computing integrated chip. Figure 8 Schematic diagram of the operation of a single neuron shown;

[0048] Figure 10 This is a diagram of the deep learning neural network structure;

[0049] Figure 11 To realize the digital-analog hybrid storage and computing integrated chip using the embodiment of the present invention Figure 10 System diagram of the neural network operation shown;

[0050] Figure 12 A structural diagram of an electronic device using a digital-analog hybrid storage and computing integrated chip according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0051] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0052] The design complexity and manufacturing cost of the existing integrated storage and computing chip architecture are very high. In addition, the chip structure is fixed and inflexible, making it difficult to adjust during use. This results in limited scalability and versatility, making it difficult to complete complex computing tasks, such as those in convolutional neural networks.

[0053] To solve the above problems, the present invention provides a digital-analog hybrid storage and computing integrated chip, the overall architecture of which is as follows: Figure 1As shown, the digital-analog hybrid storage and computing integrated chip 1 includes: multiple flash memory processing arrays 2 and an on-chip memory 3 connected to the multiple flash memory processing arrays.

[0054] Each flash memory processing array 2 reads the data in the on-chip memory 3, performs calculations on the data, obtains calculation results, and transmits the calculation results to the on-chip memory 3; the on-chip memory 3 is used to store the calculation results and the input data of the digital-analog hybrid storage and computing chip 1.

[0055] The flash memory processing array 2 includes a NOR type flash memory processing array and a NAND type flash memory processing array. Of course, the present invention is not limited thereto.

[0056] In addition, the on-chip memory 3 may be SRAM, DRAM, FLASH, etc., including but not limited to these.

[0057] Those skilled in the art will appreciate that, in actual applications, some or all of the multiple flash memory processing arrays may be used for computational processing, with the number of flash memory processing arrays used depending on computational requirements. Similarly, for each flash memory processing array, some or all of its components may be used for computational processing, with the number of components used depending on computational requirements.

[0058] The digital-analog hybrid storage and computing integrated chip 1 provided by the present invention realizes the digital-analog hybrid storage and computing integrated function by integrating an on-chip memory 3, and can effectively reduce the design complexity and manufacturing cost, which is conducive to large-scale industrialization.

[0059] In addition, the on-chip memory 3 is used to store input data and data to be processed (i.e., the calculation results of each flash memory processing array 2). The flash memory processing array 2 reads data from the on-chip memory 3 for calculation processing as needed. If a flash memory processing array needs to perform further calculation processing on the processing results of other flash memory processing arrays, it is sufficient to read the processing results stored in the on-chip memory 3. There is no need to cascade the flash memory processing array with other flash memory processing arrays. Therefore, the independent decoupling of each flash memory processing array is achieved. When the digital-analog hybrid storage and computing integrated chip 1 is used in different application scenarios, some or all of the multiple flash memory processing arrays can be selectively used according to different calculation requirements to achieve different calculation functions, thereby increasing the flexibility of use of the digital-analog hybrid storage and computing integrated chip 1 and having good applicability.

[0060] In addition, because the number of read and write times of the flash memory is limited, the digital-analog hybrid storage and computing chip 1 provided in the embodiment of the present invention stores the data to be processed through the integrated on-chip memory 3, which can effectively reduce the number of read and write times of the flash memory and increase the service life of the flash memory.

[0061] Figure 2 This is a partial circuit structure diagram of a digital-analog hybrid storage and computing integrated chip according to an embodiment of the present invention. Figure 2 As shown, in Figure 1 Based on the digital-analog hybrid storage and computing integrated chip 1 shown, it also includes: a writing circuit 5, a reading circuit 6, a DAC 7, and an ADC 4.

[0062] The output of the flash memory processing array 2 is sequentially connected to the ADC 4, the write circuit 5, and the on-chip memory 3. Because the calculation results output by the flash memory processing array 2 are analog data, the ADC 4 is connected to the output of the flash memory processing array 2 to convert the analog calculation results into digital signals that can be stored in the on-chip memory 3. This digital signal is written to a predetermined address in the on-chip memory 3 by the write circuit 5, thereby enabling the use of the digital memory 3 to store the analog data.

[0063] The output end of the on-chip memory 3 is connected to the read circuit 6, DAC7, and flash memory processing array 2 in sequence. The read circuit 6 is used to read the data required by the flash memory processing array 2 from the on-chip memory 3. Since the on-chip memory 3 is a digital memory, the signal read by the read circuit 6 is a digital signal, which is converted into the analog input signal required by the flash memory processing array 2 using the DAC7.

[0064] Among them, in an optional embodiment, among the multiple flash memory processing arrays in the digital-analog hybrid storage and computing integrated chip, each flash memory processing array interacts with the on-chip memory through the corresponding ADC, DAC, write circuit, and read circuit. However, although this method can realize the interaction between the flash memory processing array and the on-chip memory, the number of ADCs, DACs, write circuits, and read circuits required is relatively large, resulting in a complex structure, large area, and high cost of the digital-analog hybrid storage and computing integrated chip.

[0065] In a preferred embodiment, multiple flash memory processing arrays in the digital-analog hybrid storage and computing integrated chip share a set of ADCs, DACs, write circuits, and read circuits to interact with the on-chip memory. Because the on-chip memory is time-shared, multiple flash memory processing arrays share a set of ADCs, DACs, write circuits, and read circuits without affecting the chip function. It can also simplify the chip structure, reduce the chip area, and reduce the chip cost.

[0066] The following combination Figures 3 to 7 The process of implementing the operation of the flash memory processing array 2 is described in detail:

[0067] Figure 3 FIG1 shows a circuit diagram of a flash memory processing array using a gate coupling and source summing topology. Figure 3 As shown, the flash memory processing array includes: a plurality of programmable semiconductor devices arranged in an array.

[0068] The gates of all programmable semiconductor devices in each row are connected to the same analog voltage input terminal, and M rows of programmable semiconductor devices are correspondingly connected to M analog voltage input terminals for receiving data to be processed (i.e., data read from the on-chip memory after digital-to-analog conversion).

[0069] The drains of all programmable semiconductor devices in each column are connected to the same bias voltage input terminal. N columns of programmable semiconductor devices are correspondingly connected to N bias voltage input terminals for inputting bias voltage. The bias voltages of programmable semiconductor devices in each column can be the same or different and can be selected according to needs.

[0070] The sources of all programmable semiconductor devices in each column are connected to the same analog current output terminal. N columns of programmable semiconductor devices are correspondingly connected to N analog current output terminals for outputting operation results.

[0071] The threshold voltage of each programmable semiconductor device is adjustable. N is a positive integer greater than or equal to zero, and M is a positive integer greater than or equal to zero. M and N can be equal or different.

[0072] Through the above circuit connection method, a gate-coupled and source-summed topology is formed.

[0073] Among them, the threshold voltage V of each programmable semiconductor device is dynamically adjusted according to certain rules in advance. TH Each programmable semiconductor device can be regarded as a variable equivalent analog weight (denoted as W k,j , where 0<k<M and 0<j<N represent the row number and column number respectively), which is equivalent to storing an analog data, and the flash memory processing array stores an analog data array

[0074] When the circuit is working, a column of analog voltage signals (that is, the data read from the on-chip memory after digital-to-analog conversion) V1~V M are applied to M rows of programmable semiconductor devices, wherein the gates of all programmable semiconductor devices in the Kth row receive an analog voltage signal V k , drain input bias voltage V b , the source outputs current signal I k,1 ~I k,N According to the characteristics of programmable semiconductor devices, I = V × W. The source output current of each programmable semiconductor device is equal to the gate voltage multiplied by the weight of the programmable semiconductor device, that is, I k,1 =V k W k,1 , I k,N =V k W k,N, because the sources of all programmable semiconductor devices in each column are connected to the same analog current output terminal, according to Kirchhoff's law, the current I j is the sum of the source currents of all programmable semiconductor devices in the column, which is Multiple analog current output terminals output multiple currents and (i.e. the result of the operation) to realize the matrix multiplication operation function.

[0075] In the above technical solution, because programmable semiconductor devices have high integration, fast response speed and low power consumption, the calculation processing implemented by programmable semiconductor devices can effectively improve the integration and calculation speed of the digital-analog hybrid storage and computing chip, and its processing performance is greatly improved.

[0076] Figure 4 FIG1 shows a circuit diagram of a flash memory processing array using a gate coupling and drain summing topology. Figure 4 As shown, the flash memory processing array circuit includes: a plurality of programmable semiconductor devices arranged in an array.

[0077] The gates of all programmable semiconductor devices in each row are connected to the same analog voltage input terminal. M rows of programmable semiconductor devices are correspondingly connected to M analog voltage input terminals for receiving data to be processed (i.e., data read from an on-chip memory after digital-to-analog conversion).

[0078] The sources of all programmable semiconductor devices in each column are connected to the same bias voltage input terminal. N columns of programmable semiconductor devices are correspondingly connected to N bias voltage input terminals for inputting bias voltages. The bias voltages of programmable semiconductor devices in each column can be the same or different and can be selected as needed.

[0079] The drains of all programmable semiconductor devices in each column are connected to the same analog current output terminal. N columns of programmable semiconductor devices are correspondingly connected to N analog current output terminals for outputting operation results.

[0080] The threshold voltage of each programmable semiconductor device is adjustable. N is a positive integer greater than or equal to zero, and M is a positive integer greater than or equal to zero. M and N can be equal or different.

[0081] Through the above circuit connection method, a gate-coupled and drain-summed topology is formed.

[0082] Among them, the threshold voltage V of each programmable semiconductor device is dynamically adjusted according to certain rules in advance. TH Each programmable semiconductor device can be regarded as a variable equivalent analog weight (denoted as W k,j, where 0<k<M and 0<j<N represent the row number and column number respectively), which is equivalent to storing an analog data, and the flash memory processing array stores an analog data array

[0083] When the circuit is working, a series of analog voltage signals V1~V M are applied to M rows of programmable semiconductor devices, wherein the gates of all programmable semiconductor devices in the Kth row receive an analog voltage signal V k , source input bias voltage V b , the drain outputs current signals I k,1 ~I k,N , where, according to the characteristics of programmable semiconductor devices, I = V × W. The drain output current of each programmable semiconductor device is equal to the gate voltage multiplied by the weight of the programmable semiconductor device, that is, I k,1 =V k W k,1 , I k,N =V k W k,N , because the drains of all programmable semiconductor devices in each column are connected to the same analog current output terminal, according to Kirchhoff's law, the current I j is the sum of the drain currents of all programmable semiconductor devices in the column, which is Multiple analog current output terminals output multiple currents and (i.e. the result of the operation) to realize the matrix multiplication operation function.

[0084] In this embodiment, since the gate-source voltage V GS The output current of the programmable semiconductor device is determined. The output current of the programmable semiconductor device is very sensitive to the source voltage, which may cause calculation errors. However, this embodiment adopts a gate-coupled, drain-summed topology. Even if the source voltage fluctuates, it will not cause calculation errors, which can improve the accuracy of the calculation.

[0085] Figure 5 A circuit for a flash memory processing array in a digital-analog hybrid storage and computing integrated chip according to an embodiment of the present invention Figure 3 The flash memory processing array includes Figure 3 or Figure 4 The flash memory processing array shown may further include: a conversion device 21, which is connected before the multiple analog voltage input terminals and is used to convert the multiple analog current input signals into analog voltage input signals respectively and input them to the corresponding analog voltage input terminals.

[0086] In an optional embodiment, the conversion device 21 includes a plurality of programmable semiconductor devices.

[0087] The gate and drain of each programmable semiconductor device are connected to the corresponding analog voltage input terminal.

[0088] A source of each programmable semiconductor device is connected to a first bias voltage.

[0089] It can be understood that the first bias voltage connected to the source can be a ground voltage, that is, the source is grounded.

[0090] In this embodiment, the gate and drain of each programmable semiconductor device are connected to receive an analog current input signal.

[0091] When the circuit is working, a column of analog current input signal I in1 ~I inM The conversion device 21 converts the analog voltage input signals V1 to V M By providing a conversion device, the flash memory processing array in the embodiment of the present invention is not only suitable for analog voltage input signals, but also for analog current input signals, which can increase the applicability of the digital-analog hybrid storage and computing integrated chip.

[0092] In an optional embodiment, the conversion device 21 may also be implemented by using a plurality of resistors, and the plurality of resistors are connected to the plurality of analog voltage input terminals in a one-to-one correspondence.

[0093] One end of each resistor is connected to the corresponding analog voltage input end, and the other end is connected to the first bias voltage. It can be understood that the first bias voltage can be a ground voltage, that is, the other end of the resistor is grounded.

[0094] When the circuit is working, a column of analog current input signal I in1 ~I inM The conversion device 21 converts the analog voltage input signals V1 to V M Then they are applied to M rows of programmable semiconductor devices respectively.

[0095] It is worth noting that the above-mentioned implementation of the conversion device is only an example, and any circuit structure or circuit element that can convert a current input signal into a voltage input signal can be used to implement the conversion device, such as a metal semiconductor field effect transistor.

[0096] Figure 6 A circuit for a flash memory processing array in a digital-analog hybrid storage and computing integrated chip according to an embodiment of the present invention Figure 4 .like Figure 6 As shown, the flash memory processing array 2 includes a plurality of programmable semiconductor devices arranged in an array.

[0097] The sources of all programmable semiconductor devices in each column are connected to the same analog voltage input terminal, and N columns of programmable semiconductor devices are correspondingly connected to N analog voltage input terminals for receiving data to be processed (i.e., data read from the on-chip memory after digital-to-analog conversion).

[0098] The gates of all programmable semiconductor devices in each row are connected to the same bias voltage input terminal. M rows of programmable semiconductor devices are correspondingly connected to M bias voltage input terminals for inputting bias voltage. The bias voltages of programmable semiconductor devices in each column can be the same or different and can be selected according to needs.

[0099] The drains of all programmable semiconductor devices in each column are connected to the same analog current output terminal. N columns of programmable semiconductor devices are correspondingly connected to N analog current output terminals for outputting operation results.

[0100] The threshold voltage of each programmable semiconductor device is adjustable. N is a positive integer greater than or equal to zero, and M is a positive integer greater than or equal to zero. M and N can be equal or different.

[0101] Through the above circuit connection method, a matrix multiplication circuit topology structure with source coupling and drain summation is formed.

[0102] Among them, the threshold voltage V of each programmable semiconductor device is dynamically adjusted according to certain rules in advance. TH Each programmable semiconductor device can be regarded as a variable equivalent analog weight (denoted as W k,j , where 0<k<M and 0<j<N represent the row number and column number respectively), which is equivalent to storing an analog data, and the flash memory processing array stores an analog data array

[0103] When the circuit is working, a line of analog voltage signals (i.e. data to be processed) V1~V N are applied to N columns of programmable semiconductor devices, wherein the sources of all programmable semiconductor devices in the Kth column receive an analog voltage signal V k , gate input bias voltage V b , the drain outputs current signals I k,1 ~I k,N , where, according to the characteristics of programmable semiconductor devices, I = V × W. The drain output current of each programmable semiconductor device is equal to the source voltage multiplied by the weight of the programmable semiconductor device, that is, I k,1 =V k W k,1 , I k,N =V k W k,N, because the drains of all programmable semiconductor devices in each column are connected to the same analog current output terminal, according to Kirchhoff's law, the current I j is the sum of the drain currents of all programmable semiconductor devices in the column, which is Multiple analog current output terminals output multiple currents and Implement matrix multiplication function.

[0104] In addition, since the gate-source voltage V GS The output current of the programmable semiconductor device is determined. The output current of the programmable semiconductor device is very sensitive to the source voltage, which may cause calculation errors. However, this embodiment adopts a source-coupled, drain-summed topology. Even if the source voltage fluctuates, it will not cause calculation errors, which can improve the accuracy of the calculation.

[0105] Figure 7 A circuit for a flash memory processing array in a digital-analog hybrid storage and computing integrated chip according to an embodiment of the present invention Figure 5 .like Figure 7 As shown, the flash memory processing array 2 includes Figure 6 Based on the flash memory processing array shown, it can also include: a conversion device 20, which is connected before multiple analog voltage input terminals and is used to convert multiple analog current input signals (i.e., data to be processed) into analog voltage input signals respectively and input them to the corresponding analog voltage input terminals.

[0106] In an optional embodiment, the conversion device 20 includes: a plurality of operational amplifiers and a plurality of programmable semiconductor devices connected to the plurality of operational amplifiers in a one-to-one correspondence.

[0107] The inverting input terminal of each operational amplifier is connected to the drain of the corresponding programmable semiconductor device, and the non-inverting input terminal is connected to the first fixed bias voltage Vd.

[0108] The output terminal of the operational amplifier is connected to the source of the programmable semiconductor device and is also connected to the corresponding analog voltage input terminal.

[0109] The gate of the programmable semiconductor device is connected to a first fixed bias voltage Vd. In this embodiment, the inverting input terminal of the operational amplifier is used to receive the analog current input signal I in1 ~I inN .

[0110] When the circuit is working, a line of analog current input signal I in1 ~I inN The conversion device 20 converts the analog voltage input signal V1 to V NBy providing a conversion device, the flash memory processing array in the embodiment of the present invention is not only suitable for analog voltage input signals, but also for analog current input signals, which can increase the applicability of the entire digital-analog hybrid storage and computing integrated chip.

[0111] It is worth noting that the implementation method of the above-mentioned conversion device is only an example. Any circuit structure or circuit element that can convert a current input signal into a voltage input signal can be used to implement the conversion device. It can be understood that the programmable semiconductor device in the above-mentioned conversion device can also be implemented using resistors, metal semiconductor field effect transistors and other devices.

[0112] The above combination Figures 3 to 7 The principle and implementation method of using flash memory processing array to realize matrix multiplication operation are described. Combined with the above description, those skilled in the art can understand that: Therefore, in practical applications, all divisions can be converted into multiplications. Therefore, the principle and implementation method of using the above circuit to implement the division operation can be found in the above content and will not be repeated here.

[0113] In addition, when the threshold voltage V TH Set to 1, that is, weight W = 1, then the output current I of the programmable semiconductor device = V, because the output terminals of multiple programmable semiconductor devices are connected to the same analog current output terminal, according to Kirchhoff's law, the current I at the analog current output terminal j is the sum of the output currents of all programmable semiconductor devices in the column, i.e., I j =I1+I2……I n , thus realizing the addition operation. The principle of subtraction operation is the same as that of addition operation, so I will not go into details here.

[0114] In an optional embodiment, a programmable semiconductor device can be implemented using a floating gate transistor, which includes a substrate, an insulating layer, a gate G, a source S, a drain D and a floating gate F. The floating gate is arranged between the gate and the insulating layer, and the insulating layer is arranged between the floating gate and the substrate to protect electrons in the floating gate from leaking. Electrons can be stored in the floating gate. By adjusting the number of electrons in the floating gate, the threshold voltage of the floating gate transistor is dynamically adjusted. Due to the structural characteristics of the floating gate transistor, it can be regarded as a variable equivalent analog weight to store analog data.

[0115] Specifically, the floating-gate transistor may be a SONOS floating-gate transistor, a split-gate floating-gate transistor, or a charge-trapping floating-gate transistor, including but not limited to these. All transistors that can adjust the threshold voltage of the transistor itself by adjusting the number of electrons in the floating gate fall within the scope of protection of the embodiments of the present invention.

[0116] In an optional embodiment, the digital-analog hybrid storage and computing chip may further include:

[0117] The programming circuit is connected to the source, gate and / or substrate of each programmable semiconductor device in the flash memory processing array and is used to adjust the threshold voltage of the programmable semiconductor device.

[0118] Among them, the programming circuit may include: a voltage generating circuit and a voltage control circuit, the voltage generating circuit is used to generate a programming voltage or an erasing voltage, and the voltage control circuit is used to load the programming voltage to the source of the selected programmable semiconductor device, or to load the erasing voltage to the gate or substrate of the selected programmable semiconductor device to regulate the threshold voltage of the programmable semiconductor device.

[0119] Specifically, the programming circuit utilizes the hot electron injection effect to apply a high voltage to the source of the programmable semiconductor device according to the threshold voltage requirement data of the programmable semiconductor device, accelerating the channel electrons to a high speed to increase the threshold voltage of the programmable semiconductor device. When reducing the threshold voltage, the tunneling effect is utilized to apply a high voltage to the gate or substrate of the programmable semiconductor device, thereby reducing the threshold voltage of the programmable semiconductor device.

[0120] In an optional embodiment, the digital-analog hybrid storage and computing chip may further include:

[0121] The controller is connected to each flash memory processing array, the write circuit, the read circuit, and the programming circuit, and is used to control the working state of each flash memory processing array, the threshold voltage of each programmable semiconductor device in the flash memory processing array, the write address of the write circuit, and the read address of the read circuit.

[0122] The working state includes a running state and a stopped state. Specifically, when the digital-analog hybrid storage and computing chip is operating in an environment with a large amount of computing, all flash memory processing arrays can be controlled to be put into operation. When the digital-analog hybrid storage and computing chip is operating in an environment with a small amount of computing, some flash memory processing arrays can be controlled to be put into operation, thereby achieving flexible adjustment of the chip architecture and effectively increasing the applicability of the digital-analog hybrid storage and computing chip.

[0123] Preferably, the controller may include: a row-column decoder for selecting the programmable semiconductor device to be programmed and controlling the read circuit to read data according to the read address and controlling the write circuit to write data according to the write address.

[0124] In an optional embodiment, the digital-analog hybrid storage and computing integrated chip may further include: a bias voltage generating circuit for generating a preset bias voltage, which is input to the bias voltage input terminal. It can be understood that the digital-analog hybrid storage and computing integrated chip may also not be provided with a bias voltage generating circuit, and by multiplexing the voltage generating circuit in the programming circuit, the voltage generating circuit is controlled to generate a preset bias voltage, which is input to the bias voltage input terminal.

[0125] The digital-analog hybrid storage and computing integrated chip provided in the embodiment of the present invention can be used to perform related calculations in terminals such as computers, mobile phones, and tablet computers. The other essential components of the digital-analog hybrid storage and computing integrated chip should be understood by ordinary technicians in this field and will not be elaborated here, nor should they be used as limitations on the present invention.

[0126] In addition, when the digital-analog hybrid storage and computing integrated chip provided by the present invention does not need to perform calculations, the flash memory processing array can be used as a flash memory or an electrically erasable programmable read-only memory, thereby realizing the reuse of electrical components, improving component utilization efficiency, and saving the hardware cost of integrated circuits.

[0127] The digital-analog hybrid storage and computing integrated chip provided by the present invention realizes the functions of computing and storage directly within the chip by integrating the flash memory processing array and the on-chip memory, realizing the digital-analog hybrid storage and computing integrated function without frequent interaction with the outside of the chip, thereby improving processing performance, reducing power consumption and cost overhead, and effectively reducing design complexity and manufacturing costs, which is conducive to large-scale industrialization. The on-chip memory is used to store input data and data to be processed. The flash memory processing array reads data from the on-chip memory for computing and processing, and stores the computing results as data to be processed in the on-chip memory. If other flash memory processing arrays need to perform further computing on the processing results, they can read the processing results in the on-chip memory. There is no need to cascade the various flash memory processing arrays, so that each flash memory processing array can operate independently. Then, each flash memory processing array can be selectively used according to different needs to realize different functions, thereby increasing the flexibility of the design. In addition, because the read and write times of the flash memory are limited, storing the data to be processed by the integrated on-chip memory can effectively reduce the read and write times of the flash memory and increase the service life of the flash memory.

[0128] In recent years, artificial intelligence (AI) technology has developed rapidly. Neural network technology, as a major branch of AI, has been widely applied, and various neural network algorithms have emerged. However, the current implementation of neural network algorithms mainly relies on computers or large-scale processors, which limits the size of terminal devices and increases costs, hindering the widespread application of neural networks.

[0129] An embodiment of the present invention further provides a computing device for a neural network, comprising the digital-analog hybrid storage and computing integrated chip described in any of the above embodiments.

[0130] In the digital-analog hybrid storage and computing chip, each flash memory processing array is used to implement the calculations of some neurons in the neural network and store the calculation results in the on-chip memory.

[0131] The computing device provided in this embodiment realizes neural network computing by adopting a digital-analog hybrid storage and computing integrated chip, and has high integration and small size, which is conducive to integration in electronic devices, greatly reducing the hardware cost of neural network computing. In addition, by integrating on-chip memory inside the chip, the interaction with external devices of the chip is reduced.

[0132] Among them, multiple flash memory processing arrays are used to implement the operation of multiple layers of neurons in a neural network. Among them, one flash memory processing array can be used to implement the operation of one layer of neurons, or multiple flash memory processing arrays can be used to implement the operation of one layer of neurons (wherein each flash memory processing array implements the operation of part of the neurons in the layer of neurons), or one flash memory processing array can be used to implement the operation of multiple layers of neurons (a part of the flash memory processing array implements the operation of one layer of neurons, and multiple parts implement the operation of multiple layers of neurons), and the flash memory processing array stores the operation results of the corresponding layer of neurons in the on-chip memory, and the flash memory processing array corresponding to the next layer of neurons implements the operation of the next layer of neurons by reading the operation results. By adopting the above method, the data between the layers of neurons in the neural network are transferred through the on-chip memory instead of being directly cascaded, which can realize flexible adjustment of the neural network structure (including network size, number of network layers and connection order, etc.).

[0133] Moreover, since the calculation results of each flash memory processing array are transferred downward through the on-chip memory, there is no need to match the inputs of each flash memory processing array. This makes the digital-analog hybrid storage and computing chip not only suitable for relatively simple network structures such as fully connected networks, but also for deep learning neural networks with a large amount of data to be processed, such as convolutional neural networks commonly used in image processing and speech processing.

[0134] The following combination Figures 8 to 10 The application of the digital-analog hybrid storage and computing integrated chip provided by the embodiment of the present invention in neural networks is specifically described.

[0135] Figure 8 The diagram below shows the operation of a single neuron. Figure 8 As shown, in this single neuron, X1~X n Indicates n input data, b indicates the offset, W1~W n Represents the weight, and the output f(x) of a single neuron is shown in Formula 1:

[0136]

[0137] From the above formula, we can see that the operations of neurons in the neural network mainly include weighted summation operations and addition operations.

[0138] When the digital-analog hybrid storage and computing integrated chip provided by the embodiment of the present invention is used to realize the computing function of a single neuron, a flash memory cell array is used for implementation, such as Figure 9 As shown, the flash memory cell array includes: n+1 programmable semiconductor devices, which are arranged in a row, and the output ends are connected together to form a total operation result output end.

[0139] Specifically, the weights W1~W n The corresponding values ​​are stored in n programmable semiconductor devices, that is, by adjusting the threshold voltage of the i-th programmable semiconductor device in the n programmable semiconductor devices, the threshold voltage is equal to the corresponding weight W i , which is equivalent to storing the weight W in a programmable semiconductor device i When the input signal X1~X n The kth input signal X in i After inputting into the programmable semiconductor device, according to the programmable semiconductor device characteristic: I = V × W (the output current of the programmable semiconductor device is equal to the input voltage multiplied by the impedance of the programmable semiconductor device, and the impedance is represented by the threshold voltage), the output current I of the programmable semiconductor device can be obtained. i =X i ×W i Because the output terminals of n programmable semiconductor devices are connected in series, according to Kirchhoff's law, after the output terminals of the n programmable semiconductor devices are connected in series, the output current I j is the sum of the output currents of n programmable semiconductor devices, that is:

[0140]

[0141] In addition, by adjusting the threshold voltage of the n+1th programmable semiconductor device so that the threshold voltage is equal to 1, it is equivalent to storing the weight 1 in the programmable semiconductor device. When the bias signal b is input to the programmable semiconductor device, according to the programmable semiconductor device characteristic: I=V×W (the output current of the programmable semiconductor device is equal to the input voltage multiplied by the impedance of the programmable semiconductor device, and the impedance is represented by the threshold voltage), the output current I of the programmable semiconductor device can be obtained. n+1 = b, because the output terminals of n+1 programmable semiconductor devices are connected in series to form a total operation result output terminal, so according to Kirchhoff's law, the current I output by the total operation result output terminal is 总 is the sum of the output currents of n+1 programmable semiconductor devices, that is:

[0142]

[0143] And thus achieved Figure 8 The output of the operation of the neuron shown.

[0144] It can be seen from the above technical solution that the embodiment of the present invention sets the threshold voltage of each programmable semiconductor device, which is equivalent to storing weight data in the programmed semiconductor device. By inputting the input data into the programmed semiconductor device, the operation result can be obtained at the output end, thereby realizing the operation of neurons, and is suitable for application in neural network operations.

[0145] Figure 10 This is a diagram of the deep learning neural network structure. Figure 10 As shown in the figure, the deep neural network includes t layers, namely Layer1 to Layer(t), each layer includes multiple neurons, each neuron receives the output of multiple neurons in the previous layer as input, performs certain operations on the received data, obtains the output of the neuron, and inputs it to multiple neurons in the next layer as input to the corresponding neurons in the next layer. Through gradual and progressive learning between multiple layers, complex operation recognition and other functions are realized.

[0146] Among them, Layer1 is used as the input layer to input the data to be processed, Layer(t) is used as the output layer to output the calculation results, and Layer2 to Layer(t-1) are used as hidden layers to implement the calculation processing process.

[0147] Below, Figure 11 As an example, combined with the above Figure 9 The description of using a flash memory processing array to implement single neuron operations described in the text illustrates the process of implementing deep learning neural network operations using a hybrid analog-digital computing chip provided by an embodiment of the present invention.

[0148] Figure 11To realize the digital-analog hybrid storage and computing integrated chip using the embodiment of the present invention Figure 10 The system diagram of the neural network operation is shown in Figure 2. Figure 11 As shown, the digital-analog hybrid storage and computing chip 1 includes: an on-chip memory 2 and multiple flash memory processing arrays.

[0149] The plurality of flash memory processing arrays are grouped to obtain t-2 flash memory processing array groups, and the first flash memory processing array group to the t-2 flash memory processing array group are respectively used to implement Figure 10 Layer 2 to Layer (t-1) layers are shown in FIG.

[0150] Of course, those skilled in the art will understand that Figure 10 The above is only one embodiment. In actual application, the flash memory processing array may not correspond one-to-one with each layer in the neural network. Therefore, one flash memory processing array can be used to implement the operation of one layer of neurons ( Figure 10 In the case shown in FIG1 , multiple flash memory processing arrays can be used to implement the operation of a layer of neurons (where each flash memory processing array implements the operation of part of the neurons in the layer of neurons), or one flash memory processing array can be used to implement the operation of multiple layers of neurons (a part of the flash memory processing array implements the operation of a layer of neurons, and multiple parts implement the operation of multiple layers of neurons). Here, we will not give all the examples for each case in detail. Figure 10 The principle and concept of the present invention are explained by taking the illustrated situation as an example. Figure 10 It should not be understood as limiting the present invention.

[0151] On-chip memory is used to implement Figure 10 The Layer 1 and Layer (t) layers shown receive the data to be processed from the external device and output the calculation results obtained by the Layer (t-1) layer. On this basis, the on-chip memory is also used to store the data to be processed of each flash memory processing array.

[0152] Specifically, the number of flash memory processing arrays contained in each flash memory processing array group is equal to the number of neurons in the corresponding neural network layer, and each flash memory processing array is used to implement the operation of the corresponding neuron. The principle is described above. Figure 9 The description of is omitted here. Furthermore, each flash memory processing array group implements the operation of the corresponding neural network layer. For example, Figure 11 Flash memory processing array group 1 corresponds to Figure 10 Layer 2 in the memory contains 4 neurons, and the flash memory processing array group 1 contains 4 flash memory processing arrays, each of which realizes the computing function of a neuron.

[0153] The on-chip memory receives and stores the data to be processed. The four flash memory processing arrays in the flash memory processing array group 1 read part or all of the data to be processed from the on-chip memory, perform calculations, and return the calculation results to the on-chip memory respectively. Each flash memory processing array in the flash memory processing array group 2 reads part or all of the calculation results returned by the flash memory processing array group 1 from the on-chip memory, performs calculations, and then returns its calculation results to the on-chip memory. This process is repeated until the flash memory processing array group t-2. The flash memory processing array group t-2 returns the calculation results to the on-chip memory as the final calculation results of the neural network. The on-chip memory stores and outputs the calculation results.

[0154] Neural network technology is mainly divided into two parts: neural network training and neural network application.

[0155] When the neural network is a qualified neural network, the network structure is fixed. The digital-analog hybrid storage and computing chip can be used for model applications. That is, according to the weight parameters of the qualified trained neural network, the threshold voltage of each programmable semiconductor device is set, and then the data to be processed is input into the digital-analog hybrid storage and computing chip for calculation, thereby realizing the forward propagation application process of the neural network. The final calculation result is used as the actual result for subsequent processes.

[0156] When the neural network is unqualified, it needs to be trained. At this time, the digital-analog hybrid storage and computing chip can also meet the model training requirements. The digital-analog hybrid storage and computing chip outputs the above final result to an external device, which judges the final result. If it meets the requirements, the neural network training is qualified. If it does not meet the requirements, it is necessary to use the controller and programming circuit in the digital-analog hybrid storage and computing chip to adjust the threshold voltage of each programmable semiconductor device to achieve reverse adjustment of the neural network parameters. After that, the training data is input into the network for forward propagation, and then reverse adjustment is performed. This is repeated to complete the model training process.

[0157] From the above analysis, it can be seen that the digital-analog hybrid storage and computing integrated chip provided by the embodiment of the present invention is not only suitable for the application of trained mature neural network models, but also suitable for the training process of neural network models, and has good applicability.

[0158] On the other hand, an embodiment of the present invention provides a computing device for a neural network, which uses a digital-analog hybrid storage and computing integrated chip and multiple flash memory processing arrays to realize the calculation of multiple layers of neurons in the neural network. Among them, one flash memory processing array can be used to realize the calculation of one layer of neurons, or multiple flash memory processing arrays can be used to realize the calculation of one layer of neurons (wherein each flash memory processing array realizes the calculation of part of the neurons in the layer of neurons), or one flash memory processing array can be used to realize the calculation of multiple layers of neurons (a part of the flash memory processing array realizes the calculation of one layer of neurons, and multiple parts realize the calculation of multiple layers of neurons), and the flash memory processing array stores the calculation results of the neurons in the corresponding layer in the on-chip memory, and the flash memory processing array corresponding to the neurons in the next layer realizes the calculation of the neurons in the next layer by reading the calculation results. By adopting the above method, the data between the neurons in each layer of the neural network is transferred through the on-chip memory instead of being directly cascaded, which can realize flexible adjustment of the neural network structure (including network size, number of network layers and connection order, etc.). In addition, since the calculation results of each flash memory processing array are transferred downward through the on-chip memory, there is no need to match the inputs of each flash memory processing array, so that the computing device is not only suitable for relatively simple network structures such as full connection, but also for deep learning neural networks with a large amount of data to be processed, such as convolutional neural networks commonly used in image processing and speech processing. The digital-analog hybrid storage and computing chip provided by the present invention can be suitable for neural networks with any number of layers, and only the number of flash memory processing arrays needs to be increased accordingly. It is more flexible in application and has a fast computing speed.

[0159] Of course, those skilled in the art will understand that Figures 8 to 11 The examples used are mainly to facilitate those skilled in the art to understand the solutions of the present invention. They are intended to reflect the principle of implementing neural network operations using the digital-analog hybrid storage and computing integrated chip provided by the embodiment of the present invention, and are not intended to limit the types and structures of neural network operations that can be implemented by the present invention. The digital-analog hybrid storage and computing integrated chip provided by the embodiment of the present invention can be suitable for a variety of neural network applications and training scenarios, including: convolutional neural networks, temporal recursive neural networks, BP neural networks, etc.

[0160] The embodiment of the present invention further provides an electronic device, including the above-mentioned digital-analog hybrid storage and computing integrated chip. Figure 12 As shown, it includes: a communication interface 8m, a communication bus 9m and a digital-analog hybrid storage and computing chip 1.

[0161] The communication interface 8m is used to interact with external devices, and the communication bus 9m is used to transmit signals received by the communication interface 8m to the digital-analog hybrid storage and computing chip 1, and transmit the results obtained by the digital-analog hybrid storage and computing chip 1 to the communication interface 8m. The digital-analog hybrid storage and computing chip 1 is used to process the received signals and output the calculation results.

[0162] Among them, the electronic device includes a smart phone, a tablet computer, a smart wearable device, a car navigator, etc. The electronic device may have a communication module (i.e., a communication unit) that can communicate with a remote server to realize data transmission with the server. The server may include a server on the side of the task scheduling center, and other implementation scenarios may also include a server on an intermediate platform, such as a server on a third-party server platform that has a communication link with the task scheduling center server. The server may include a single computer device, or a server cluster consisting of multiple servers, or a server structure of a distributed device.

[0163] The server and the electronic device may communicate using any suitable network protocol, including network protocols that have not yet been developed on the date of filing this application. The network protocols may include, for example, TCP / IP, UDP / IP, HTTP, HTTPS, etc. Of course, the network protocols may also include, for example, RPC (Remote Procedure Call Protocol) and REST (Representational State Transfer) protocols used on top of the above protocols.

[0164] The controller in the present application can take the form of, for example, a microprocessor or processor and a computer-readable medium storing a computer-readable program code (such as software or firmware) that can be executed by the (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. Those skilled in the art will also know that, in addition to implementing the controller in a purely computer-readable program code manner, the controller can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers to achieve the same function. Therefore, such a controller can be considered as a hardware component, and the devices included therein for implementing various functions can also be considered as structures within the hardware component.

[0165] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0166] Although the present application has been described with reference to the embodiments, those skilled in the art will appreciate that there are many modifications and variations to the present application without departing from the spirit of the present application. It is intended that the appended claims include these modifications and variations without departing from the spirit of the present application.

[0167] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0168] Specific embodiments are used in the present invention to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A digital-analog hybrid storage and computing chip, characterized in that: include: a plurality of flash memory processing arrays and an on-chip memory connected to the plurality of flash memory processing arrays; Each of the flash memory processing arrays reads data in the on-chip memory, performs calculations on the data, obtains calculation results, and transmits the calculation results to the on-chip memory; The on-chip memory stores the operation results and input data of the digital-analog hybrid storage and computing chip; The operation result includes a first operation result of a first flash memory processing array among the multiple flash memory processing arrays, and data read and processed by a second flash memory processing array among the multiple flash memory processing arrays includes the first operation result.

2. The digital-analog hybrid storage and computing integrated chip according to claim 1, characterized in that: Also includes: a writing circuit, connected between the flash memory processing array and the on-chip memory, for writing the operation result into the on-chip memory; A reading circuit is connected between the flash memory processing array and the on-chip memory, and is used for reading the data and transmitting the data to the flash memory processing array.

3. The digital-analog hybrid storage and computing integrated chip according to claim 2, characterized in that: Also includes: an ADC connected between the flash memory processing array and the write circuit, for converting the operation result into a digital signal and transmitting the digital signal to the write circuit; The DAC is connected between the flash memory processing array and the reading circuit, and is used for converting the read data into an analog signal and transmitting the analog signal to the flash memory processing array.

4. The digital-analog hybrid storage and computing integrated chip according to claim 1, characterized in that: The on-chip memory includes: SRAM, DRAM, and FLASH.

5. The digital-analog hybrid storage and computing integrated chip according to claim 2, characterized in that: Each of the flash memory processing arrays includes a plurality of programmable semiconductor devices arranged in an array; The sources of all programmable semiconductor devices in each column are connected to the same analog voltage input terminal, and multiple columns of programmable semiconductor devices are correspondingly connected to multiple analog voltage input terminals for receiving the data; The drains of all programmable semiconductor devices in each column are connected to the same analog current output terminal, and multiple columns of programmable semiconductor devices are correspondingly connected to multiple analog current output terminals for outputting the calculation result; The gates of all programmable semiconductor devices in each row are connected to the same bias voltage input terminal, and multiple rows of programmable semiconductor devices are correspondingly connected to multiple bias voltage input terminals; Wherein, the threshold voltage of each programmable semiconductor device is adjustable.

6. The digital-analog hybrid storage and computing integrated chip according to claim 2, characterized in that: Each of the flash memory processing arrays includes a plurality of programmable semiconductor devices arranged in an array; The gates of all programmable semiconductor devices in each row are connected to the same analog voltage input terminal, and multiple rows of programmable semiconductor devices are correspondingly connected to multiple analog voltage input terminals for receiving the data; The drains of all programmable semiconductor devices in each column are connected to the same first terminal, and multiple columns of programmable semiconductor devices are correspondingly connected to multiple first terminals; The sources of all programmable semiconductor devices in each column are connected to the same second terminal, and multiple columns of programmable semiconductor devices are connected to multiple second terminals. The threshold voltage of each programmable semiconductor device is adjustable; wherein, The first end is a bias voltage input end; the second end is an analog current output end, used to output the operation result; Alternatively, the first end is an analog current output end for outputting the operation result; and the second end is a bias voltage input end.

7. The digital-analog hybrid storage and computing chip according to any one of claims 5 or 6, characterized in that: Also includes: The programming circuit is connected to the source, gate and / or substrate of each programmable semiconductor device in the flash memory processing array and is used to adjust the threshold voltage of the programmable semiconductor device.

8. The digital-analog hybrid storage and computing integrated chip according to claim 7, characterized in that: The programming circuit includes: a voltage generating circuit and a voltage control circuit, the voltage generating circuit is used to generate a programming voltage or an erasing voltage, and the voltage control circuit is used to load the programming voltage to the source of the selected programmable semiconductor device, or to load the erasing voltage to the gate or substrate of the selected programmable semiconductor device to regulate the threshold voltage of the programmable semiconductor device.

9. The digital-analog hybrid storage and computing integrated chip according to claim 8, characterized in that: Also includes: A controller is connected to each of the flash memory processing arrays, the write circuit, the read circuit, and the programming circuit, and is used to control the working state of each of the flash memory processing arrays, the threshold voltage of each programmable semiconductor device in the flash memory processing array, the write address of the write circuit, and the read address of the read circuit.

10. The digital-analog hybrid storage and computing integrated chip according to claim 9, characterized in that: The programmable semiconductor device adopts a floating gate transistor.

11. A computing device for a neural network, wherein the neural network comprises multiple layers of neurons, each layer of neurons performing corresponding operations based on the output results of the neurons in the previous layer, characterized in that: The computing device includes the digital-analog hybrid storage and computing chip as claimed in any one of claims 1 to 10, In the digital-analog hybrid storage and computing chip, each of the flash memory processing arrays is used to implement operations on some neurons in the neural network and store the operation results in the on-chip memory.

Images