Three-level power conversion circuit and voltage clamping method

Abstract

The present invention discloses a three-level power conversion circuit and a voltage clamping method, wherein the three-level power conversion circuit comprises a Boost boost circuit, wherein the Boost boost circuit comprises an inductor L1, a diode D3, a diode D4, a switch tube Q1, a switch tube Q2, and a flying capacitor Cf, and further comprises a voltage clamping circuit connected in parallel at both ends of the diode D4, wherein the voltage clamping circuit comprises a capacitor C2 and a switch S1, wherein the capacitor C2 and the switch S1 are connected in series. The present invention can charge the flying capacitor Cf in a Boost circuit without input, thereby reducing the voltage stress of the diode D4; and the capacitance value of the capacitor C2 in the voltage clamping circuit can be adjusted according to the capacitance value of the flying capacitor Cf, the capacitance value of the input capacitor C1, and the voltage stress allowed by the selected diode D4, which is very flexible.

Description

Technical Field

[0001] The invention relates to a three-level power conversion circuit and a voltage clamping method, belonging to the technical field of new energy grid-connected power generation. Background Art

[0002] Solar photovoltaic grid-connected power generation system is one of the important means to effectively utilize new energy. As a sustainable, efficient and pollution-free green energy, solar grid-connected power generation is gaining more and more attention. As governments of various countries pay more attention to and encourage the use of new energy, this power generation method is becoming more and more common in practical applications.

[0003] Photovoltaic inverter is an important part of solar photovoltaic grid-connected power generation system, and usually photovoltaic inverter consists of two parts: DC / DC and DC / AC. DC / DC can not only stabilize the downstream bus voltage, but also improve the working range of inverter input voltage and improve the maximum power point tracking efficiency, thereby increasing the power generation of photovoltaic inverter. Therefore, DC / DC plays a vital role in the performance and efficiency of photovoltaic inverter.

[0004] The boost circuit is simple to control and is widely used in the DC / DC side of photovoltaic inverters. For low-voltage systems, two-level boost can meet the withstand voltage requirements. However, when the input voltage of the boost circuit is high, the voltage stress of a single switch tube and a diode in the boost circuit is limited. Therefore, two switches are connected in series and two diodes are connected in series, which naturally evolves into a three-level boost circuit. At present, the three-level boost circuit mainly includes a symmetrical boost three-level and a flying capacitor three-level. Among them, the flying capacitor three-level can directly realize the common negative pole (or common positive pole) of the input and output of multiple boosts when multiple boosts work in parallel, and the output ends are connected in parallel (generally referred to as bus voltage in the photovoltaic field). The alternating conduction of the two switches can realize current doubling, and there is no problem of large common-mode current to ground in the symmetrical boost three-level. Therefore, in the photovoltaic field, this feature makes the flying capacitor three-level boost more advantageous than the symmetrical boost three-level boost in reducing system cost and improving efficiency.

[0005] However, in actual use, when multiple flying capacitor boost circuits work in parallel, because the power-on time of the multiple boost circuits is different, or one of the boost circuits is not connected to the battery panel at all, the boost circuit that is powered on first will establish the bus voltage, and the boost circuit that is powered on later or not connected to the battery panel, at this time, its input terminal voltage and flying capacitor voltage are basically zero, such as Figure 1As shown, at this time, the diode D4 in the circuit will bear the entire bus voltage, and there is a risk of overvoltage breakdown and damage, which returns to the problem faced by the two-level circuit. The diode has limited voltage resistance, which is not conducive to selection and violates the original intention of connecting two diodes in series.

[0006] In order to solve the above problem, that is, when multiple flying capacitor Boost circuits are connected in parallel, the boost diode D4 in the boost circuit powered on later bears the entire bus voltage, the prior art generally adopts three solutions:

[0007] One is to add another diode in series with D4 to jointly bear the entire bus voltage. Although the additional series diode can solve the above problem, when Boost is working normally, the additional series diode will also have the same large current as diode D4, so the loss increases, the cost increases, and the Boost efficiency decreases;

[0008] The second is to cut off the loop formed by the diode D4 before power-on, so that the anode end of the diode D4 is in a high-resistance state, which can also solve the above problem. However, the device used to cut off the loop, whether it is a mechanical switch, a semiconductor switch, or a diode, is similar to the problem of method 1. When Boost is working normally, it needs to be closed, and the switches connected in series will also flow a large current, which will increase the loss, increase the cost, and reduce the Boost efficiency.

[0009] The third method is to take half of the bus voltage, connect it to the anode of diode D4 with a diode or switch, and use half of the bus potential to clamp the anode of diode D4, which can also solve the problem. However, when the half-bus voltage is seriously uneven and the voltage difference is too large, the withstand voltage risk of diode D4 will increase significantly. When Boost is working normally, when the lower tube Q2 is turned on, the added diode, Cf, Q2 and half of the bus voltage form a low-impedance current loop, with a very large peak current, affecting the reliability of the system. Summary of the invention

[0010] The technical problem to be solved by the present invention is: how to avoid the risk of overvoltage breakdown and damage to the diode when the Boost circuit is powered on or off later.

[0011] In order to solve the above technical problems, the technical solution of the present invention is to provide a three-level power conversion circuit, including a Boost boost circuit, the Boost boost circuit includes an inductor L1, a diode D3, a diode D4, a switch tube Q1, a switch tube Q2, and a flying capacitor Cf, one end of the inductor L1 is connected to one end of the input end, the other end of the inductor L1 is connected to one end of the diode D3, the other end of the diode D3 is connected to one end of the diode D4, the other end of the diode D4 is connected to one end of the output bus voltage, and the other end of the inductor L1 is connected to one end of the input end. The switching device is connected to one end of the switching tube Q1, the other end of the switching tube Q1 is connected to one end of the switching tube Q2, the other end of the switching tube Q2 is respectively connected to the other end of the input end and the other end of the output bus voltage, the common end between the switching tube Q1 and the switching tube Q2 is connected to one end of the flying capacitor Cf, the other end of the flying capacitor Cf is connected to the common end between the diode D3 and the diode D4, and is characterized in that it also includes a voltage clamping circuit connected in parallel at both ends of the diode D4, the voltage clamping circuit includes a capacitor C2 and a switch S1, and the capacitor C2 and the switch S1 are connected in series.

[0012] Preferably, one end of the inductor L1 is connected to the positive electrode of the input end, the other end of the inductor L1 is respectively connected to the collector of the switch tube Q1 and the anode of the diode D3, the cathode of the diode D3 is connected to the anode of the diode D4, the emitter of the switch tube Q1 is connected to the collector of the switch tube Q2, the two ends of the flying capacitor Cf are respectively connected to the emitter of the switch tube Q1 and the anode of the diode D4, the cathode of the diode D4 is connected to the output positive bus voltage, and the emitter of the switch tube Q2 is respectively connected to the negative electrode of the input end and the output negative bus voltage; one end of the capacitor C2 is connected to the common end of the flying capacitor Cf and the diode D4, the other end of the capacitor C2 is connected to one end of the switch S1, and the other end of the switch S1 is connected to the output positive bus voltage.

[0013] Preferably, the collector of the switching tube Q1 is respectively connected to the positive electrode of the input end and the output positive bus voltage, one end of the inductor L1 is connected to the negative electrode of the input end, the other end of the inductor L1 is respectively connected to the emitter of the switching tube Q2 and the cathode of the diode D3, the cathode of the diode D4 is connected to the anode of the diode D3, the emitter of the switching tube Q1 is connected to the collector of the switching tube Q2, the two ends of the flying capacitor Cf are respectively connected to the emitter of the switching tube Q1 and the anode of the diode D4, and the anode of the diode D4 is connected to the output negative bus voltage; one end of the capacitor C2 is respectively connected to the common end of the flying capacitor Cf and the diode D4, the other end of the capacitor C2 is connected to one end of the switch S1, and the other end of the switch S1 is connected to the output negative bus voltage.

[0014] Preferably, an input capacitor C1 is connected in parallel at both ends of the input terminal, and an output capacitor C3 is connected in parallel at both ends of the output bus voltage.

[0015] Preferably, the switch tube Q1 is anti-parallel connected to the diode D1, and the switch tube Q2 is anti-parallel connected to the diode D2.

[0016] Preferably, the switch S1 is a relay or a semiconductor switch tube based on electromagnetic principle.

[0017] Preferably, the semiconductor switch tube is a combination of one or more of a triode, an insulated gate bipolar transistor IGBT, and a field effect switch MOSFET.

[0018] Preferably, the voltage clamping circuit further comprises a current limiting resistor R1 connected in series with the capacitor C2 and the switch S1.

[0019] A voltage clamping method for a three-level power conversion circuit, characterized in that it comprises the following steps:

[0020] Close switch S1; when the Boost circuit is powered on or off, capacitor C2 clamps the voltage of diode D4, and the output bus provides a current loop through capacitor C2 to charge the flying capacitor Cf and input capacitor C1;

[0021] When the Boost circuit operates normally, the switch S1 is turned off and the current loop flows through the diode D4.

[0022] The present invention utilizes the principle that capacitor voltage cannot change suddenly and the principle of capacitor series voltage division, adds a capacitor in parallel to both ends of the diode D4, and can charge the flying capacitor Cf and input capacitor C1 of other Boost boost circuits while the Boost boost circuit powered on first establishes the bus voltage. In this way, when the bus voltage gradually increases, although other Boost boost circuits are not powered on, the flying capacitor Cf and input capacitor C1 of the circuits where they are located will also be charged as the common bus voltage increases, thereby indirectly raising the potential of the anode of the diode D4 and reducing the voltage stress of the diode D4 in the boost boost circuit powered on later. In order not to affect normal operation, a switch S1 is connected in series in the added capacitor loop to disconnect the diode loop when the Boost circuit is working normally.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] When there is no power at the input end of a certain Boost circuit or it is powered on later, and the bus voltage is rising because other Boost circuits have power, the voltage clamping circuit of the present invention can charge the flying capacitor Cf in the Boost circuit without input, thereby reducing the voltage stress of the diode D4; and the capacitance value of the capacitor C2 in the voltage clamping circuit can be adjusted according to the capacitance value of the flying capacitor Cf, the capacitance value of the input capacitor C1, and the allowable voltage stress of the selected diode D4, which is very flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of a three-level power conversion circuit of the present invention;

[0026] Figure 2 A schematic diagram of a three-level power conversion circuit of the present invention (a current-limiting resistor R1 is connected in series in the branch where the switch S1 is located);

[0027] Figure 3 A diagram of a three-level power conversion circuit and a voltage clamping method of the present invention;

[0028] Figure 4 A three-level power conversion circuit and a voltage clamping method diagram of the present invention (a current limiting resistor R1 is connected in series to the branch where the switch S1 is located);

[0029] Figure 5 It is a schematic diagram of the circuit of the present invention when the Boost circuit is powered on or off;

[0030] Figure 6 It is a schematic diagram of the circuit of the present invention when the Boost circuit works normally;

[0031] Figure 7 It is a schematic diagram of an equivalent circuit of the circuit of the present invention when the Boost circuit works normally. DETAILED DESCRIPTION

[0032] In order to make the present invention more clearly understood, preferred embodiments are described in detail below with reference to the accompanying drawings.

[0033] Example 1

[0034] like Figure 1As shown, a three-level power conversion circuit of the present invention includes an inductor L1, a diode D3 and a diode D4 connected in series, a switch tube Q1 and a switch tube Q2 connected in series, a flying capacitor Cf and a voltage clamping circuit, the switch tube Q1 is anti-parallel connected to the diode D1, and the switch tube Q2 is anti-parallel connected to the diode D2. One end of the inductor L1 is connected to the positive electrode of the input end, the other end of the inductor L1 is respectively connected to the collector of the switch tube Q1 and the anode of the diode D3, the cathode of the diode D3 is connected to the anode of the diode D4, the emitter of the switch tube Q1 is connected to the collector of the switch tube Q2, the two ends of the flying capacitor Cf are respectively connected to the emitter of the switch tube Q1 and the anode of the diode D4, the cathode of the diode D4 is connected to the output positive bus voltage, and the emitter of the switch tube Q2 is respectively connected to the negative electrode of the input end and the output negative bus voltage; the voltage clamping circuit includes a capacitor C2 and a switch S1, one end of the capacitor C2 is connected to the common end of the flying capacitor Cf and the diode D4, the other end of the capacitor C2 is connected to one end of the switch S1, and the other end of the switch S1 is connected to the output positive bus voltage. The two ends of the input end are connected in parallel with the input capacitor C1, and the two ends of the output bus voltage are connected in parallel with the output capacitor C3. The switch S1 can be a relay based on the electromagnetic principle, etc., or a semiconductor switch tube, such as a triode, an insulated gate bipolar transistor IGBT, a field effect switch MOSFET, etc., or a combination of multiple switches.

[0035] When there is no power at the input end of a certain Boost circuit or it is powered on later, and the bus voltage is rising because other Boost circuits have power, the voltage clamping circuit can charge the flying capacitor Cf in the Boost circuit without input, thereby reducing the voltage stress of the diode D4.

[0036] The switch S1 is in a closed state before the Boost main circuit works (i.e., it is closed by default when no power is turned on), and automatically switches to an open state after the main circuit works. At this time, both the forward current and the reverse current are blocked.

[0037] A voltage clamping method for a three-level power conversion circuit of the present invention comprises the following steps:

[0038] Close switch S1; when the Boost circuit is powered on or off, capacitor C2 clamps the voltage of diode D4, and the output bus provides a current loop through capacitor C2 to charge the flying capacitor Cf and input capacitor C1;

[0039] When the Boost circuit operates normally, the switch S1 is turned off and the current loop flows through the diode D4.

[0040] When the system is operating normally, the control unit sends a command to disconnect switch S1; when the system fails or is in standby mode, the control unit sends a command to close switch S1; the control unit controls the shutdown of Q1\Q2 according to the proportional change of the input / output voltage, and does not determine whether to turn off Q2 by detecting the voltage across the floating capacitor.

[0041] like Figure 5 As shown, when the Boost circuit where PV is located is powered on later or not powered on, the voltage of the input capacitor C1 and the flying capacitor Cf is basically 0, and the switch S1 is closed by default, that is, the on state. At this time, if other Boost circuits are powered on first, such as one or more of PV2, PV3...PVn, their common output bus voltage Vbus will rise. At this time, the added capacitor C2 can not only clamp the voltage of the diode D4 to ensure that D4 will not withstand the entire BUS voltage and break down due to overvoltage, but the output bus can also provide a current loop through the capacitor C2 to charge the flying capacitor Cf and the input capacitor C1. The charging loop is shown in the dotted line part.

[0042] like Figure 6 As shown, when Boost is working normally, switch S1 is disconnected, and the current loop flows through diode D4, and does not flow through capacitor C2 and switch S1, which does not affect the normal boost of the Boost circuit at all, and does not reduce the boost efficiency of the Boost circuit.

[0043] The flying capacitor Cf in the present invention is charged automatically, and the control unit cuts off the switch S1 when it determines that the voltage of the busbar and the flying capacitor Cf meets the normal working requirements.

[0044] The calculation method for the capacitance value of capacitor C2 is as follows:

[0045] When there is no power input and the bus voltage rises, because the switch S1 is closed by default, a charging loop will be formed for the flying capacitor Cf. In this process, it can be considered that the voltage of the diode D4 is equal to the voltage across the capacitor C2, the voltage of the diode D3 is equal to the voltage across the capacitor Cf, the voltage of the switch tube Q2 is equal to the voltage across the input capacitor C1, and the switch tube Q1 and the inductor L1 can be equivalent to a short circuit. After the capacitor is charged, its equivalent circuit diagram can be simplified as follows Figure 7 As shown. According to the capacitors connected in series, the charges are equal, then:

[0046] Vbus*C=Vd4*C2;

[0047] According to the reciprocal of the total capacitance value of the series circuit is equal to the sum of the reciprocals of the capacitance values ​​of each capacitor in the series circuit, we have:

[0048] 1 / C=1 / C1+1 / Cf+1 / C2;

[0049] Where C is the total capacitance of the capacitors in series, the series capacitors are C1, C2 and Cf, Vd4 is the voltage of the diode D4, and the maximum value can be the allowable withstand voltage of D4, and Vbus is the input voltage of other Boost when it is powered on, and the value is the highest input voltage allowed by the system.

[0050] The capacitance of C2 can be calculated by the above two formulas. The capacitance of capacitor C2 can be adjusted according to the capacitance of flying capacitor Cf, the capacitance of input capacitor C1, and the voltage stress allowed by the selected diode D4, which is very flexible.

[0051] For example, the withstand voltage of diode D4 is 1200V, so 1000V is taken for calculation. The bus voltage is the highest voltage of the system, 1500V. The capacitance of flying capacitor Cf is 20uF, and the input capacitance is 10uF. Substituting the known data into the above formula, we can get the capacitance of C2 to be about 3.333uF. In practice, we can take a capacitance close to the calculated value, such as 3.3uF, and select a capacitor with a withstand voltage of about 1100V.

[0052] Example 2

[0053] like Figure 3 As shown, it is a circuit diagram of the present invention when a common positive electrode is input, the diode D3 and the diode D4 are connected in reverse series, the collector of the switch tube Q1 is respectively connected to the positive electrode of the input end and the output positive bus voltage, one end of the inductor L1 is connected to the negative electrode of the input end, the other end of the inductor L1 is respectively connected to the emitter of the switch tube Q2 and the cathode of the diode D3, the cathode of the diode D4 is connected to the anode of the diode D3, the emitter of the switch tube Q1 is connected to the collector of the switch tube Q2, the two ends of the flying capacitor Cf are respectively connected to the emitter of the switch tube Q1 and the anode of the diode D4, and the anode of the diode D4 is connected to the output negative bus voltage; one end of the capacitor C2 is respectively connected to the common end of the flying capacitor Cf and the diode D4, the other end of the capacitor C2 is connected to one end of the switch S1, and the other end of the switch S1 is connected to the output negative bus voltage.

[0054] The rest is the same as Example 1.

[0055] Example 3

[0056] like Figure 2 As shown, in this embodiment, the voltage clamping circuit further includes a current limiting resistor R1 connected in series with the capacitor C2 and the switch S1, so as to limit the current generated when the switch S1 is closed instantly, and prevent the switch S1 from being damaged due to the large current.

[0057] The rest is the same as Example 1.

[0058] Example 4

[0059] like Figure 4As shown, in this embodiment, the voltage clamping circuit further includes a current limiting resistor R1 connected in series with the capacitor C2 and the switch S1, so as to limit the current generated when the switch S1 is closed instantly, and prevent the switch S1 from being damaged due to the large current.

[0060] The rest is the same as Example 2.

Claims

1. A three-level power conversion circuit, comprising a Boost boost circuit, the Boost boost circuit comprising an inductor L1, a diode D3, a diode D4, a switch tube Q1, a switch tube Q2, and a flying capacitor Cf, one end of the inductor L1 is connected to one end of the input end, the other end of the inductor L1 is connected to one end of the diode D3, the other end of the diode D3 is connected to one end of the diode D4, the other end of the diode D4 is connected to one end of the output bus voltage, the other end of the inductor L1 is connected to one end of the switch tube Q1, the other end of the switch tube Q1 is connected to one end of the switch tube Q2, the other end of the switch tube Q2 is respectively connected to the other end of the input end and the other end of the output bus voltage, the common end between the switch tube Q1 and the switch tube Q2 is connected to one end of the flying capacitor Cf, the other end of the flying capacitor Cf is connected to the common end between the diode D3 and the diode D4, characterized in that It also includes a voltage clamping circuit connected in parallel to both ends of the diode D4, the voltage clamping circuit includes a capacitor C2 and a switch S1, and the capacitor C2 and the switch S1 are connected in series; The calculation method for the capacitance value of capacitor C2 is as follows: When there is no power input and the bus voltage rises, because the switch S1 is closed by default, a charging loop will be formed for the flying capacitor Cf. In this process, the voltage of the diode D4 is equal to the voltage across the capacitor C2, the voltage of the diode D3 is equal to the voltage across the capacitor Cf, the voltage of the switch tube Q2 is equal to the voltage across the input capacitor C1, and the switch tube Q1 and the inductor L1 are equivalent to a short circuit; according to the series connection of capacitors, the charge is equal, then: Vbus*C=Vd4*C2; According to the reciprocal of the total capacitance value of the series circuit is equal to the sum of the reciprocals of the capacitance values ​​of each capacitor in the series circuit, we have: 1 / C=1 / C1+1 / Cf+1 / C2; Where C is the total capacitance of the capacitors in series, the series capacitors are C1, C2 and Cf, Vd4 is the voltage of the diode D4, and the maximum value is the allowable withstand voltage of D4, and Vbus is the input voltage of other Boost when it is powered on, and the value is the highest input voltage allowed by the system.

2. A three-level power conversion circuit as claimed in claim 1, characterized in that: One end of the inductor L1 is connected to the positive electrode of the input end, the other end of the inductor L1 is respectively connected to the collector of the switch tube Q1 and the anode of the diode D3, the cathode of the diode D3 is connected to the anode of the diode D4, the emitter of the switch tube Q1 is connected to the collector of the switch tube Q2, the two ends of the flying capacitor Cf are respectively connected to the emitter of the switch tube Q1 and the anode of the diode D4, the cathode of the diode D4 is connected to the output positive bus voltage, and the emitter of the switch tube Q2 is respectively connected to the negative electrode of the input end and the output negative bus voltage; one end of the capacitor C2 is connected to the common end of the flying capacitor Cf and the diode D4, the other end of the capacitor C2 is connected to one end of the switch S1, and the other end of the switch S1 is connected to the output positive bus voltage.

3. A three-level power conversion circuit as claimed in claim 1, characterized in that: The collector of the switch tube Q1 is respectively connected to the positive electrode of the input end and the output positive bus voltage, one end of the inductor L1 is connected to the negative electrode of the input end, the other end of the inductor L1 is respectively connected to the emitter of the switch tube Q2 and the cathode of the diode D3, the cathode of the diode D4 is connected to the anode of the diode D3, the emitter of the switch tube Q1 is connected to the collector of the switch tube Q2, the two ends of the flying capacitor Cf are respectively connected to the emitter of the switch tube Q1 and the anode of the diode D4, and the anode of the diode D4 is connected to the output negative bus voltage; one end of the capacitor C2 is respectively connected to the common end of the flying capacitor Cf and the diode D4, the other end of the capacitor C2 is connected to one end of the switch S1, and the other end of the switch S1 is connected to the output negative bus voltage.

4. A three-level power conversion circuit as claimed in claim 1, 2 or 3, characterized in that: The two ends of the input terminal are connected in parallel with an input capacitor C1, and the two ends of the output bus voltage are connected in parallel with an output capacitor C3.

5. A three-level power conversion circuit as claimed in claim 1, 2 or 3, characterized in that: The switch tube Q1 is anti-parallel connected to the diode D1, and the switch tube Q2 is anti-parallel connected to the diode D2.

6. A three-level power conversion circuit as claimed in claim 1, 2 or 3, characterized in that: The switch S1 is a relay or a semiconductor switch tube based on the electromagnetic principle.

7. A three-level power conversion circuit as claimed in claim 6, characterized in that: The semiconductor switch tube is one or more combinations of a triode, an insulated gate bipolar transistor IGBT, and a field effect switch MOSFET.

8. A three-level power conversion circuit as claimed in claim 1, 2 or 3, characterized in that: The voltage clamping circuit further includes a current limiting resistor R1 connected in series with the capacitor C2 and the switch S1.

9. A voltage clamping method using the three-level power conversion circuit according to any one of claims 1 to 3, characterized in that: The following steps are involved: Close switch S1; when the Boost circuit is powered on or off, capacitor C2 clamps the voltage of diode D4, and the output bus provides a current loop through capacitor C2 to charge the flying capacitor Cf and input capacitor C1; When the Boost circuit operates normally, the switch S1 is turned off and the current loop flows through the diode D4.

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