Semiconductor Devices

Abstract

The present disclosure provides a semiconductor device, which includes: a substrate, an n-type layer, a plurality of grooves, a p-type region, a p+-type region, an n+-type region, a gate electrode, a source electrode, and a drain electrode. The semiconductor device may include a plurality of unit cells. A unit cell in the plurality of unit cells may include: a contact portion, in which the source electrode contacts the n+-type region; a first branch portion, which is arranged above the contact portion on a plane; and a second branch portion, which is arranged below the contact portion on a plane, wherein the plurality of grooves are spaced apart from each other and arranged in a strip shape on a plane.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2018-0157503 filed on December 7, 2018, in the Korean Intellectual Property Office, which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device including silicon carbide (SiC). Background Art

[0004] Power semiconductor devices need to have low on-resistance or low saturation voltage to allow very large current to flow and reduce power loss in the on state. In addition, it is basically necessary to be able to withstand the reverse high voltage applied to the PN junction at both ends of the power semiconductor device in the off state or at the time of switch disconnection, that is, high breakdown voltage characteristics.

[0005] The concentration and thickness of the epitaxial layer or drift region of the raw material forming the power semiconductor device are determined according to the rated voltage required by the power system. According to Poisson's equation, since the power semiconductor device requires a high breakdown voltage, an epitaxial layer or drift region with a lower concentration and a thicker thickness is required, but this leads to an increase in on-resistance and a decrease in forward current density.

[0006] Research continues to increase the forward current density without adjusting the concentration and thickness of the epitaxial layer or drift region of the power semiconductor device.

[0007] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore the above information may contain information that does not form the prior art that is already known to a person skilled in the art. Summary of the invention

[0008] The present disclosure relates to a silicon carbide semiconductor device capable of increasing forward current density.

[0009] A semiconductor device according to an exemplary embodiment of the present disclosure includes: a substrate, an n-type layer, a plurality of grooves, a p-type region, a p+-type region, an n+-type region, a gate electrode, a source electrode, and a drain electrode. The semiconductor device includes a plurality of unit cells, wherein a unit cell in the plurality of unit cells includes: a contact portion in which a source electrode contacts the n+-type region; a first branch portion disposed above the contact portion on a plane; and a second branch portion disposed below the contact portion on a plane, wherein a plurality of grooves are spaced apart from each other and disposed in a stripe shape on a plane, wherein each of the plurality of grooves includes a protruding portion protruding to the left and right on a plane, and wherein the first branch portion and the second branch portion include protruding portions, respectively.

[0010] The p+ type region may be provided in the center of the unit cell in a plane, and the n+ type region may surround the p+ type region in the contact portion in a plane.

[0011] The source electrode may be in contact with the p + type region in the contact portion.

[0012] The protrusion portion included in the first branch portion and the protrusion portion included in the second branch portion may protrude from grooves adjacent to each other on a plane.

[0013] Among the plurality of unit cells, the p + -type regions of the unit cells adjacent to each other on the left and right in a plane may not face each other.

[0014] The first branch portion and the second branch portion may include a plurality of protrusion portions, respectively.

[0015] Among the plurality of unit cells, p + -type regions of unit cells adjacent to each other on the left and right in a plane may face each other.

[0016] An n-type layer may be disposed on the first surface of the substrate, a plurality of trenches may be disposed on the n-type layer, a p-type region may be disposed on the n-type layer and adjacent to sides of the trenches, an n+ type region may be disposed on the p-type region and adjacent to sides of the trenches, and a p+ type region may be disposed on the p-type region and adjacent to sides of the n+ type region.

[0017] The semiconductor device according to the exemplary embodiment of the present disclosure may further include a gate insulating layer disposed within the plurality of trenches, and the gate electrode may be disposed on the gate insulating layer.

[0018] The semiconductor device according to the exemplary embodiment of the present disclosure may further include an insulating layer disposed on the gate electrode, and the source electrode may be disposed on the insulating layer, the n+ region, and the p+ type region.

[0019] The drain electrode may be disposed on the second surface of the substrate.

[0020] The substrate may be an n+ type silicon carbide substrate.

[0021] The protruding portions protruding to the left and right on the plane may be provided on the same straight line in each groove.

[0022] A protrusion protruding to the left and right on a plane may be periodically provided in each groove.

[0023] According to an exemplary embodiment of the present disclosure, since the branch portion of the unit cell includes the protruding portion of the groove, the length of the size of the groove within the unit cell may be increased.

[0024] Therefore, the channel length of the semiconductor device can be increased. Therefore, the channel density of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1A and Figure 1B is a layout diagram schematically showing an example of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0026] Figure 2 is schematically shown along Figure 1A and Figure 1B A cross-sectional view of the example taken along line II-II in FIG.

[0027] Figure 3 is schematically shown along Figure 1A and Figure 1B A cross-sectional view of the example taken along line III-III in FIG.

[0028] Figure 4 It is schematically shown Figure 1A and Figure 1B Layout diagram of an example of a unit cell U of a semiconductor device.

[0029] Figure 5 is a diagram schematically showing a layout of a general semiconductor device.

[0030] Figures 6 to 8 are layout diagrams each schematically showing an example of a semiconductor device according to another exemplary embodiment of the present disclosure.

[0031] The following reference numerals are used in the drawings:

[0032] 100: substrate 200: n-type layer

[0033] 250: Groove 251: Protrusion

[0034] 300: p-type region 400: n+ type region

[0035] 500: p+ type region 600: gate insulating layer

[0036] 700: Gate electrode 800: Insulating layer

[0037] 910: Source electrode 920: Drain electrode

[0038] U: Unit cell CT: Contact part

[0039] BR1: First branch part BR2: Second branch part DETAILED DESCRIPTION

[0040] Hereinafter, the exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways without departing from the idea or scope of the present disclosure. On the contrary, the exemplary embodiments introduced herein are provided to make the disclosed content thorough and complete and to fully convey the idea of ​​the present disclosure to those skilled in the art.

[0041] In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. It will be understood that when a layer is referred to as being 'on' another layer or substrate, it can be directly on the other layer or substrate, or a third layer interposed therebetween may also be present.

[0042] Figure 1A and Figure 1B is a layout diagram schematically showing an example of a semiconductor device according to an exemplary embodiment of the present disclosure. Figure 2 is schematically shown along Figure 1A and Figure 1B A cross-sectional view of the example taken along line II-II in FIG. Figure 3 is schematically shown along Figure 1A and Figure 1B A cross-sectional view of the example taken along line III-III in FIG.

[0043] Reference Figures 1A to 3 , the semiconductor device according to the present exemplary embodiment includes a substrate 100 , an n-type layer 200 , a plurality of trenches 250 , a p-type region 300 , an n+ type region 400 , a p+ type region 500 , a gate electrode 700 , a source electrode 910 , and a drain electrode 920 .

[0044] Figure 1A is a view showing an example of a layout of a semiconductor device in which the source electrode 910 is omitted, Figure 1B 800 and 801 are views showing an example of a layout of a semiconductor device in which a portion of the insulating layer 800 and a portion of the gate electrode 700 are omitted.

[0045] The plurality of trenches 250 are spaced apart from each other and are disposed in a planar stripe shape, and the gate electrode 700 is disposed within the trench 250. Here, since the gate electrode 700 is disposed within the trench 250, the trench 250 may be defined as a gate trench.

[0046] Each groove 250 includes a plurality of protruding portions 251 protruding left and right on a plane. Therefore, the width of the portion where the protruding portion 251 is located in each groove 250 is wider than the width of the other portions. Here, the plurality of protruding portions 251 protruding left and right on a plane are periodically arranged in each groove 250.

[0047] In each groove 250, the protruding portion 251 protruding left and right on the plane is arranged on the same straight line on the plane, and the protruding portions 251 of the grooves 250 arranged adjacent to each other on the plane do not face each other. That is, in the grooves 250 adjacent to each other, the protruding portions 251 protrude in a zigzag shape on the plane.

[0048] The semiconductor device according to the present exemplary embodiment includes a plurality of unit cells U. Each unit cell U is a planar quadrilateral and is repeatedly arranged. Each unit cell U includes a p+ type region 500, and the p+ type region 500 is arranged in the center of each unit cell U on a plane. In each unit cell U, the n+ type region 400 surrounds the p+ type region 500. In the unit cells U adjacent to each other on the left and right on a plane, the p+ type region 500 does not face. Each unit cell U includes a protruding portion 251 of a groove 250. In the present exemplary embodiment, each unit cell U includes a protruding portion 251 of a groove 250 respectively arranged above and below the p+ type region 500 on a plane. Here, the protruding portion 251 of the groove 250 is respectively arranged one above and below the p+ type region 500 on a plane, and the protruding portions 251 of the groove 250 respectively arranged above and below the p+ type region 500 on a plane protrude from the grooves 250 adjacent to each other.

[0049] In each unit cell U, the p + type region 500 and the n + type region 400 are in contact with the source electrode 910 .

[0050] The insulating layer 800 covers the n+ type region 400 and the gate insulating layer 600 and the gate electrode 700 disposed in the trench 250 except for the p+ type region 500 and a portion of the n+ type region 400 disposed around the p+ type region 500 in a plane.

[0051] Next, a detailed structure of the semiconductor device according to the present exemplary embodiment is described.

[0052] The n-type layer 200 is disposed on the first surface of the substrate 100, and the trench 250 is disposed in the n-type layer 200. The substrate 100 may be an n+ type silicon carbide substrate.

[0053] The p-type region 300 is disposed on the n-type layer 200 and adjacent to the side of the trench 250. The n+ type region 400 is disposed on the p-type region 300 and adjacent to the side of the trench 250. The p+ type region 500 is disposed on the p-type region 300 and adjacent to the side of the n+ type region 400.

[0054] The gate insulating layer 600 is disposed in the trench 250 and on a portion of the n+ type region 400. The gate electrode 700 is disposed on the gate insulating layer 600. The gate electrode 700 may include metal or polysilicon. The gate electrode 700 is disposed to fill the trench 250.

[0055] The insulating layer 800 is disposed on the gate electrode 700 . The insulating layer 800 covers the side surfaces of the gate electrode 700 .

[0056] The source electrode 910 is disposed on the insulating layer 800, the n+ type region 400 and the p+ type region 500. The source electrode 910 contacts the p+ type region 500 and the n+ type region 400. The drain electrode 920 is disposed on the second surface of the substrate 100. The source electrode 910 and the drain electrode 920 may include an ohmic metal. Here, the second surface of the substrate 100 is disposed on a side opposite to the first surface of the n+ type silicon carbide substrate 100.

[0057] The channel of the semiconductor device according to the present exemplary embodiment is formed in the p-type region 300 disposed adjacent to the side of the trench 250. Each unit cell U of the semiconductor device according to the present exemplary embodiment includes a protruding portion 251 of the trench 250 disposed above and below the p+ type region 500 on a plane, so that the length of the channel of the semiconductor device can be increased. Therefore, the channel density of the semiconductor device can be improved.

[0058] Next, refer to Figure 4 A unit cell U of a semiconductor device according to an exemplary embodiment of the present disclosure is described.

[0059] Figure 4 It is schematically shown Figure 1A and Figure 1B Layout diagram of an example of a unit cell U of a semiconductor device. Figure 4 is based on Figure 1A and Figure 1B 1 is an enlarged view of a unit cell U of a semiconductor device, and as shown in FIG. 1 , a portion of a gate electrode 700, a source electrode 910, and a portion of an insulating layer 800 are omitted.

[0060] Reference Figure 4 , the unit cell U is quadrilateral in a plane. The unit cell U includes a p+ type region 500, and the p+ type region 500 is disposed in a central portion of each unit cell U in a plane. In the unit cell U, the n+ type region 400 surrounds the p+ type region 500. The unit cell U includes a protruding portion 251 of a groove 250. In the present exemplary embodiment, the unit cell U includes protruding portions 251 of the groove 250 disposed above and below the p+ type region 500 in a plane, respectively. That is, in the present exemplary embodiment, the unit cell U includes protruding portions 251 of two grooves 250.

[0061] The unit cell U includes a contact portion CT, a first branch portion BR1, and a second branch portion BR2. The contact portion CT includes a p+ type region 500 and an n+ type region 400. The p+ type region 500 and the n+ type region 400 in the contact portion CT are in contact with the source electrode 910. The first branch portion BR1 is disposed above the contact portion CT on a plane, and the second branch portion BR2 is disposed below the contact portion CT on a plane. The first branch portion BR1 and the second branch portion BR2 each include a protruding portion 251 of a groove 250.

[0062] As described above, the channel of the semiconductor device according to the present exemplary embodiment is formed in the p-type region 300 disposed adjacent to the side of the trench 250, and since the first branch portion BR1 and the second branch portion BR2 of the unit cell U respectively include the protruding portion 251 of the trench 250, the length of the channel of the semiconductor device can be increased. Therefore, the channel density of the semiconductor device can be improved.

[0063] Next, refer to Figure 5 A channel density of a general semiconductor device and a channel density of a semiconductor device according to an exemplary embodiment of the present disclosure are compared and described.

[0064] Generally, the channel density of a semiconductor device is defined as the length of a channel per area of ​​a unit cell on a plane.

[0065] Figure 5 is a diagram schematically showing a layout of a general semiconductor device.

[0066] Reference Figure 5, the general semiconductor device is a trench gate MOSFET, and the n+ type region 400 and the trench 250 are arranged in a strip shape on a plane. The gate insulating layer 600 and the gate electrode 700 are arranged in the trench 250. The channel of the semiconductor device is arranged on the side of the gate trench 250. The general semiconductor device includes a unit cell U, and the unit cell U includes a p+ type region 500 arranged in the central part on a plane. In the unit cells U adjacent to each other on the left and right on the plane, the p+ type regions 500 do not face each other.

[0067] When compared with general semiconductor devices (according to Figure 5 1 ), if the area of ​​the unit cell U is the same, in the unit cell U of the semiconductor device according to the present exemplary embodiment, the first branch portion BR1 and the second branch portion BR2 respectively include the protruding portion 251 of the trench 250, so the length of the channel of the semiconductor device can be increased (see Figure 4 ). That is, it can be confirmed that the length of the channel of the semiconductor device according to the present exemplary embodiment is longer than the length of the channel of a general semiconductor device.

[0068] In a trench gate MOSFET, the channel density is proportional to the forward current density. That is, an increase in the channel density means an increase in the forward current density. Therefore, compared with a general semiconductor device, in the case of the semiconductor device according to this exemplary embodiment, since the channel density increases and the current density increases, the area of ​​the semiconductor device for obtaining the same amount of current can be reduced. Therefore, the production cost of the semiconductor device can be reduced and the yield can be increased.

[0069] On the other hand, the layout of the semiconductor device according to the present exemplary embodiment may be various structures. Figures 6 to 8 Describe this.

[0070] Figures 6 to 8 are layout diagrams each schematically showing an example of a semiconductor device according to another exemplary embodiment of the present disclosure.

[0071] Figures 6 to 8 It is shown as Figure 1B A diagram showing an example of a layout of a semiconductor device in which a portion of the insulating layer 800 and a portion of the gate electrode 700 are omitted.

[0072] Reference Figure 6 , except for the arrangement of only each unit cell, the semiconductor device according to the present exemplary embodiment is different from the semiconductor device according to Figure 1A and Figure 1B The remaining structures of the semiconductor device are the same. The description of the same structures is omitted.

[0073] The semiconductor device according to the present exemplary embodiment includes a plurality of unit cells U, the unit cell U is a quadrilateral on a plane, and the p + type region 500 is provided at the center of the unit cell U on a plane.

[0074] According to Figure 1A and Figure 1B Unlike the semiconductor device of FIG. 1 , in the semiconductor device according to the present exemplary embodiment, in the unit cells U adjacent to each other left and right on a plane, the p + type regions 500 are arranged to face each other.

[0075] Reference Figure 7 , except for the structure of the unit cell U, the semiconductor device according to the present exemplary embodiment is different from the semiconductor device according to Figure 1A and Figure 1B The remaining structures of the semiconductor device are the same. The description of the same structures is omitted.

[0076] The semiconductor device according to the present exemplary embodiment includes a plurality of unit cells U, the unit cell U is a quadrilateral on a plane, and the p + type region 500 is provided at the center of the unit cell U on a plane.

[0077] In the semiconductor device according to the present exemplary embodiment, the unit cell U includes the protruding portions 251 of the trench 250 respectively disposed above and below the p+ type region 500 on a plane, and Figure 1A and Figure 1B Unlike the semiconductor device of FIG. 1 , the two protruding portions 251 of the trench 250 are respectively arranged above and below the p + -type region 500 in the plane.

[0078] Reference Figure 8 , except for the arrangement of each unit cell and the structure of the unit cell U, the semiconductor device according to the present exemplary embodiment is different from the semiconductor device according to the Figure 1A and Figure 1B The remaining structures of the semiconductor devices are the same. The description of the same structures is omitted.

[0079] The semiconductor device according to the present exemplary embodiment includes a plurality of unit cells U, the unit cell U is a quadrilateral on a plane, and the p + type region 500 is provided at the center of the unit cell U on a plane.

[0080] According to Figure 1A and Figure 1B Unlike the semiconductor device of FIG. 1 , in the semiconductor device according to the present exemplary embodiment, in the unit cells U adjacent to each other left and right on a plane, the p + type regions 500 are arranged to face each other.

[0081] Furthermore, in the semiconductor device according to the present exemplary embodiment, the unit cell U includes the protruding portions 251 of the trench 250 respectively disposed above and below the p+ type region 500 on a plane, and Figure 1A and Figure 1B Unlike the semiconductor device of FIG. 1 , the two protruding portions 251 of the trench 250 are respectively arranged above and below the p + -type region 500 in the plane.

[0082] While the invention has been described in conjunction with what are presently considered to be practical exemplary embodiments, it will be understood that the invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: a substrate, an n-type layer, a plurality of trenches, a p-type region, a p+ type region, an n+ type region, a gate electrode, a source electrode, and a drain electrode, The semiconductor device includes a plurality of unit cells, and a unit cell in the plurality of unit cells includes: a contact portion in which the source electrode contacts the n+ type region; A first branch portion disposed above the contact portion on a plane; and A second branch portion is disposed below the contact portion on the plane, The plurality of grooves are spaced apart from each other and are arranged in a stripe shape on a plane, Each of the plurality of grooves includes a protruding portion protruding leftward and rightward on a plane, and The first branch portion and the second branch portion include a plurality of the protruding portions, respectively.

2. The semiconductor device according to claim 1, wherein The p+ type region is disposed in the center of the unit cell in a plane, and The n+ type region surrounds the p+ type region in the contact portion in a plane.

3. The semiconductor device according to claim 2, wherein: The source electrode is in contact with the p + -type region in the contact portion.

4. The semiconductor device according to claim 3, wherein: The protruding portion included in the first branch portion and the protruding portion included in the second branch portion protrude from grooves adjacent to each other on a plane.

5. The semiconductor device according to claim 4, wherein: Among the plurality of unit cells, p + -type regions of unit cells adjacent to each other in the horizontal direction in a plane do not face each other.

6. The semiconductor device according to claim 4, wherein: Among the plurality of unit cells, p + -type regions of unit cells adjacent to each other in left and right on a plane face each other.

7. The semiconductor device according to claim 1, wherein The n-type layer is disposed on the first surface of the substrate, The plurality of trenches are disposed on the n-type layer, The p-type region is disposed on the n-type layer and adjacent to a side surface of the trench, The n+ type region is disposed on the p type region and adjacent to a side surface of the trench, and The p+ type region is disposed on the p type region and is adjacent to a side surface of the n+ type region.

8. The semiconductor device according to claim 7, further comprising: A gate insulating layer is disposed in the plurality of trenches, and the gate electrode is disposed on the gate insulating layer.

9. The semiconductor device according to claim 8, further comprising: The insulating layer is disposed on the gate electrode, and the source electrode is disposed on the insulating layer, the n+ region and the p+ region.

10. The semiconductor device according to claim 9, wherein The drain electrode is disposed on the second surface of the substrate.

11. The semiconductor device according to claim 1, wherein The substrate is an n+ type silicon carbide substrate.

12. The semiconductor device according to claim 1, wherein The protruding portions protruding to the left and right on the plane are arranged on the same straight line in each groove.

13. The semiconductor device according to claim 12, wherein: The protruding portions protruding to the left and right on the plane are periodically provided in each groove.

14. A semiconductor device comprising: a substrate having an upper surface and a lower surface; An n-type layer covering the upper surface of the substrate; a plurality of trenches extending into the n-type layer toward the substrate; a p-type region covering the n-type layer; a p+ type region, adjacent to the p type region in the lateral direction; An n+ type region is disposed in the p-type region, the p+ type region being separated from the n+ type region by a trench; a gate electrode disposed on and within the plurality of trenches; A source electrode covering the n+ region and the gate electrode; as well as a drain electrode adjacent to a lower surface of the substrate, The semiconductor device includes a plurality of unit cells, each unit cell includes a contact portion electrically connecting the source electrode and the n+ type region, a first branch portion and a second branch portion, the first branch portion and the second branch portion being laterally spaced apart from the contact portion, The plurality of grooves are spaced apart from each other and arranged in a stripe shape, each groove having a first adjacent groove and a second adjacent groove, Each of the plurality of grooves includes a plurality of protruding portions including a first protruding portion protruding toward the first adjacent groove and a second protruding portion protruding toward the second adjacent groove, and The first branch portion of each unit cell includes a plurality of the first protrusion portions, and the second branch portion of each unit cell includes a plurality of the second protrusion portions.

15. The semiconductor device according to claim 14, wherein: The p+ type region is arranged in the center of the unit cell in a plane, and The n+ type region surrounds the p+ type region in the contact portion in a plane.

16. The semiconductor device according to claim 14, wherein The plurality of protruding portions include a third protruding portion protruding toward the first adjacent groove and a fourth protruding portion protruding toward the second adjacent groove, and The first branch portion of each unit cell further includes the third protrusion portion, and the second branch portion of each unit cell further includes the fourth protrusion portion.

17. The semiconductor device according to claim 14, wherein: The substrate includes an n+ type silicon carbide substrate.

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