Semiconductor packaging

Abstract

A semiconductor package comprises: a redistribution substrate having a first surface and a second surface opposite to each other, and comprising an insulating member, a plurality of redistribution layers and redistribution vias, wherein the plurality of redistribution layers are located at different horizontal levels in the insulating member, and the redistribution vias have a shape that narrows from the second surface toward the first surface in a first direction; a plurality of under ball metal (UBM) layers, each comprising an under ball metal pad and an under ball metal via, wherein the under ball metal pad is located on the first surface of the redistribution substrate, and the under ball metal vias have a shape that narrows in a second direction opposite to the first direction; and at least one semiconductor chip, which is located on the second surface of the redistribution substrate and has a plurality of contact pads, wherein the plurality of contact pads are electrically connected to the redistribution layers of the plurality of redistribution layers that are adjacent to the second surface.

Description

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0164403 filed in the Korean Intellectual Property Office on December 18, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present inventive concept relates to a semiconductor package. More particularly, the present inventive concept relates to a semiconductor package including a through hole having a tapered shape. Background Art

[0004] A semiconductor package may be the result when a semiconductor chip (eg, an integrated circuit) is implemented in a form suitable for use in an electronic product. With the development of the electronics industry in recent years, semiconductor packages have been developed in various ways for reducing size, weight, and manufacturing cost.

[0005] A wafer level packaging (WLP) process may be provided as a method of manufacturing a semiconductor package. As semiconductor chips become more highly integrated, the size of semiconductor chips is gradually decreasing. However, as semiconductor chips become smaller, it becomes difficult to attach a required number of solder balls, and handling and testing of the solder balls becomes difficult.

[0006] In addition, there may be a problem in that the number of boards to be mounted depends on the size of the semiconductor chip. To solve this problem, a fan-out panel level package including a redistribution layer (RDL) technology may be used. Summary of the invention

[0007] Aspects of the inventive concept may provide a semiconductor package with high reliability by reducing fluctuations caused in a redistribution substrate having a redistribution layer.

[0008] According to certain exemplary embodiments, the present disclosure relates to a semiconductor package, the semiconductor package comprising: a redistribution substrate having a first surface and a second surface disposed opposite to each other, and comprising an insulating member, a plurality of redistribution layers, and redistribution vias, the plurality of redistribution layers being disposed at different horizontal levels in the insulating member, the redistribution vias connecting the redistribution layers disposed at adjacent horizontal levels and having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of under bump metallurgy (UBM) layers, each of the plurality of UBM layers comprising an under bump metal pad and an under bump metal via, the under bump metal pad being disposed on the first surface of the redistribution substrate, the under bump metal via being connected to a redistribution layer adjacent to the first surface among the plurality of redistribution layers and to the under bump metal pad, and the under bump metal via having a shape narrowing in a second direction opposite to the first direction; and at least one semiconductor chip disposed on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer adjacent to the second surface among the plurality of redistribution layers.

[0009] According to certain exemplary embodiments, the present disclosure relates to a semiconductor package, the semiconductor package comprising: a redistribution substrate having a first surface and a second surface disposed opposite to each other, and comprising a plurality of insulating layers and a plurality of redistribution layers disposed between the plurality of insulating layers, wherein the plurality of redistribution layers include a first redistribution layer adjacent to the first surface and at least one second redistribution layer disposed between the first redistribution layer and the second surface, each second redistribution layer having a redistribution via connected to the first redistribution layer or an adjacent second redistribution layer among the at least one second redistribution layer; a plurality of under ball metal (UBM) layers disposed on the first surface of the redistribution substrate, each of the UBM layers having an UBM via connected to the first redistribution layer; at least one semiconductor chip disposed on the second surface of the redistribution substrate and having a contact pad electrically connected to the at least one second redistribution layer; and a molding portion disposed on the second surface of the redistribution substrate and covering the at least one semiconductor chip, wherein the redistribution via has a shape narrowing from the second surface toward the first surface in a first direction, and the UBM via has a shape narrowing in a second direction opposite to the first direction.

[0010] According to certain exemplary embodiments, the present disclosure relates to a semiconductor package, the semiconductor package comprising: a redistribution substrate having a first surface and a second surface disposed opposite to each other, and comprising an insulating member and a plurality of redistribution layers disposed at different horizontal levels in the insulating member; an under ball metallization (UBM) layer comprising an under ball metal pad and an under ball metal via, the under ball metal pad being disposed on the first surface of the redistribution substrate, the under ball metal via electrically connecting the under ball metal pad and the plurality of redistribution layers and having a shape that becomes narrower in a direction from the first surface toward the second surface; and At least one semiconductor chip is disposed on the second surface of the redistribution substrate and has a contact pad, which is electrically connected to the plurality of redistribution layers, wherein the plurality of redistribution layers include: a first redistribution layer, which is disposed on a horizontal level adjacent to the first surface in the insulating member and is composed of a planar conductive pattern, and a plurality of second redistribution layers, which are disposed on different horizontal levels in the insulating member, each of the plurality of second redistribution layers having a redistribution through-hole, which is connected to the first redistribution layer or an adjacent second redistribution layer among the plurality of second redistribution layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of the present disclosure will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment.

[0013] Figure 2 It is shown Figure 1 An enlarged cross-sectional view of portion "A" of a semiconductor package is shown.

[0014] Figures 3 to 10 are cross-sectional views illustrating main processes of a method of manufacturing a semiconductor package according to an exemplary embodiment.

[0015] Fig.11 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment.

[0016] Fig.12 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment.

[0017] Fig.13 yes Fig.12 A plan view of a semiconductor package is shown.

[0018] Fig.14 is a block diagram illustrating a configuration of a semiconductor package according to an exemplary embodiment.

[0019] [Explanation of Symbols]

[0020] 1: First direction

[0021] 2: Second direction

[0022] 100, 100', 100", 1000: Semiconductor packaging

[0023] 110, 110': Insulating components

[0024] 111: Insulation layer / first insulation layer

[0025] 112: Insulation layer / second insulation layer

[0026] 113: Insulation layer / third insulation layer

[0027] 115: Insulation layer / base insulation layer

[0028] 120, 120': Redistribution structure

[0029] 121: Redistribution layer / first redistribution layer

[0030] 122: Redistribution layer / Second redistribution layer

[0031] 122a, 122b: second redistribution layer

[0032] 122V: Redistribution vias

[0033] 125: Bonding pad

[0034] 125V: Through hole part / UBM through hole

[0035] 130, 130', 130": Redistribution of the base

[0036] 130A: First surface

[0037] 130B: Second surface

[0038] 140: Under ball metal (UBM) layer

[0039] 140P: UBM pad

[0040] 140V: UBM through hole

[0041] 150: Semiconductor chips

[0042] 150A: semiconductor chip / first semiconductor chip

[0043] 150B: semiconductor chip / second semiconductor chip

[0044] 150P: Contact pad

[0045] 150T: Upper surface

[0046] 161: Bottom filling resin

[0047] 165: Molded part

[0048] 170: Passivation layer

[0049] 180: External connector

[0050] 191: Thermal conductive material layer

[0051] 195: Heat sink

[0052] 210: First Carrier

[0053] 220: Second carrier

[0054] 1010: Microprocessor

[0055] 1020: Memory

[0056] 1030: Interface

[0057] 1040: Graphics Processor

[0058] 1050: Function block

[0059] A: Partial

[0060] B: Connecting bump

[0061] d1a, d2a, Da: lower width

[0062] d1b, d2b, Db: upper width

[0063] H: Open

[0064] h1: first hole

[0065] h2: Second hole

[0066] t, T: thickness DETAILED DESCRIPTION

[0067] Hereinafter, various embodiments of the inventive concept will be explained with reference to the accompanying drawings.

[0068] Figure 1 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment, and Figure 2 It is shown Figure 1 An enlarged cross-sectional view of portion "A" of a semiconductor package is shown.

[0069] Reference Figure 1According to an exemplary embodiment, the semiconductor package 100 may be a semiconductor package in the form of a fan-outwafer level package (FOWLP). The semiconductor package 100 may include a redistribution substrate 130 having a first surface 130A and a second surface 130B disposed opposite to each other and away from each other. The semiconductor package 100 may also include an under ball metal (UBM) layer 140 and a semiconductor chip 150, the under ball metal (UBM) layer 140 being disposed on the first surface 130A of the redistribution substrate 130, and the semiconductor chip 150 being disposed on the second surface 130B of the redistribution substrate 130.

[0070] The semiconductor chip 150 may include a semiconductor substrate having an active surface on which various discrete devices are formed and an inactive surface opposite to the active surface. The semiconductor substrate may be a single semiconductor (e.g., silicon (Si) and germanium (Ge)) or a compound semiconductor (e.g., SiC (silicon carbide), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP)) or may have a silicon on insulator (SOI) structure. For example, the semiconductor substrate constituting the semiconductor chip 150 may include a buried oxide (BOX). The various discrete devices may include various microelectronic devices, such as metal-oxide-semiconductor field effect transistors (MOSFET) (such as complementary metal-insulator-semiconductor (CMOS) transistors), system large scale integration (LSI), image sensors (such as CMOS imaging sensors (CIS)), microelectromechanical systems (MEMS), active devices, passive devices, etc.

[0071] The semiconductor chip 150 may include a plurality of contact pads 150P electrically connected to discrete devices and disposed on an active surface.

[0072] The semiconductor chip 150 may be a memory chip or a logic chip. For example, the memory chip may be a volatile memory chip (e.g., a dynamic random access memory (DRAM) or a static random access memory (SRAM)) or a non-volatile memory chip (e.g., a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). In addition, the logic chip may be, for example, a microprocessor, an analog device, or a digital signal processor.

[0073] The redistribution substrate 130 may be used as an intermediate layer to package the semiconductor chip 150 so as to mount the semiconductor chip 150 on a main board. Figure 1 As shown, the redistribution substrate 130 may include an insulating member 110 and a redistribution structure 120, and the redistribution structure 120 is disposed at different horizontal levels in the insulating member 110. The insulating member 110 may include a plurality of insulating layers 111, 112, and 115, and the redistribution structure 120 may include a plurality of redistribution layers 121 and 122, and the plurality of redistribution layers 121 and 122 are disposed on boundary surfaces of the plurality of insulating layers 111, 112, and 115, respectively.

[0074] Boundary surfaces of the plurality of insulating layers 111, 112, and 115 may define formation positions of the redistribution layers 121 and 122, but according to some embodiments (e.g., when the plurality of insulating layers 111, 112, and 115 are formed of the same material), the boundary surfaces of the plurality of insulating layers 111, 112, and 115 may not be directly visually observed in the final structure. A portion of the plurality of redistribution layers 121 and 122 may include redistribution vias 122V that connect the redistribution layers 121 and 122 disposed on adjacent horizontal levels.

[0075] In some embodiments, the plurality of insulating layers 111, 112, and 115 may be made of a resin (e.g., epoxy resin or polyimide). For example, the plurality of insulating layers 111, 112, and 115 may be formed of a photosensitive insulating material. The redistribution layers 121 and 122 and the redistribution vias 122V may include, for example, copper, nickel, stainless steel, or a copper alloy (e.g., beryllium copper).

[0076] Specifically, refer to Figure 2 , the structure of the redistribution substrate 130 used in this embodiment will be described in detail. Figure 2 It is shown Figure 1 An enlarged cross-sectional view of portion "A" of a semiconductor package is shown.

[0077] Reference Figure 2 , the plurality of redistribution layers 121 and 122 may include a first redistribution layer 121 and a second redistribution layer 122, the first redistribution layer 121 being disposed between the base insulating layer 115 and the first insulating layer 111, and the second redistribution layer 122 being disposed between the first insulating layer 111 and the second insulating layer 112. For example, the first redistribution layer 121 may be disposed on the base insulating layer 115 and covered by the first insulating layer 111, and the second redistribution layer 122 may be disposed on the first insulating layer 111 and covered by the second insulating layer 112. The first redistribution layer 121 may constitute a planar conductive pattern without having a through-hole structure for interlayer connection. Meanwhile, the second redistribution layer 122 may have a redistribution through-hole 122V, which passes through the first insulating layer 111 and is connected to the first redistribution layer 121. For example, the redistribution through-hole 122V may electrically connect the second redistribution layer 122 to the first redistribution layer 121.

[0078] As described above, first redistribution layer 121 disposed at a horizontal level adjacent to first surface 130A in insulating component 110 may constitute a planar conductor pattern, and second redistribution layer 122 disposed at a different horizontal level in insulating component 110 may have redistribution vias 122V for connecting between adjacent horizontal levels.

[0079] The UBM layer 140 may partially pass through the insulating member 110 and may be connected to the first redistribution layer 121. Figure 2 As shown, the UBM layer 140 may include a UBM pad 140P and a UBM via 140V, the UBM pad 140P being disposed on the first surface 130A of the redistribution substrate 130, and the UBM via 140V passing through the base insulating layer 115 and connected to the first redistribution layer 121 and the UBM pad 140P. For example, the upper surface of the UBM via 140V may be coplanar with the upper surface of the base insulating layer 115, and the lower surface of the UBM via 140V may be at a higher vertical level than the lower surface of the base insulating layer. In addition, the upper surface of the UBM pad 140P may be adjacent to the lower surface of the base insulating layer 115, and the lower surface of the UBM pad 140P may be at a lower vertical level than the lower surface of the base insulating layer 115.

[0080] In this embodiment, the redistribution via 122V and the UBM via 140V may have shapes tapered in opposite directions to each other.

[0081] Redistribution via 122V may have a shape that narrows in a first direction 1 from second surface 130B toward first surface 130A. In some embodiments, when viewed in cross section, a side surface of redistribution via 122V extending in the first direction 1 may be a planar surface. Redistribution via 122V may have a lower width d1a narrower than an upper width d1b. Meanwhile, UBM via 140V may have a shape that narrows in a second direction 2 opposite to the first direction 1. In some embodiments, when viewed in cross section, a side surface of UBM via 140V extending in the second direction 2 may be a planar surface. UBM via 140V may have a lower width Da wider than an upper width Db. The thickness T of UBM layer 140 may be greater than the thickness t of redistribution layer 121 or 122. For example, the thickness T of UBM layer 140 may be about 10 μm or greater. The thickness T of the UBM layer 140 may be a vertical distance between a vertical level coplanar with an upper surface of the UBM via 140V and a vertical level coplanar with a lower surface of the UBM pad 140P.

[0082] In this embodiment, the second redistribution layer 122 may be shown as a single layer, but in another embodiment, the second redistribution layer 122 may be included in multiple layers (see Fig.12 and Fig.13 ).

[0083] like Figure 2 As shown, the UBM pad 140P may have a portion extending along the surface of the insulating member 110 located on the first surface 130A of the redistribution substrate 130. For example, the upper surface of the UBM pad 140P may face the lower surface of the insulating member 110 and contact the lower surface of the redistribution layer 121. As described above, the UBM pad 140P used in this embodiment may be a non-solder mask defined (NSMD) type that is not defined by the base insulating layer 115, and board-level reliability under thermal shock may be ensured.

[0084] In addition, the redistribution substrate 130 may include a plurality of bonding pads 125 disposed on the second surface 130B. The plurality of bonding pads 125 may partially penetrate the insulating member 110, respectively, and may have a through-hole portion 125V connected to a second redistribution layer 122 adjacent to the second surface 130B among the plurality of redistribution layers. The through-hole portion 125V of the bonding pad 125 may have a shape that narrows in a first direction 1 from the second surface 130B toward the first surface 130A in a manner similar to the redistribution through-hole 122V. The UBM through-hole 125V may have a lower width d2a that is narrower than the upper width d2b. In some embodiments, when viewed in cross-section, the side surface of the UBM through-hole 125V extending in the first direction 1 may be a planar surface.

[0085] For example, the bonding pads may include copper, nickel, stainless steel, or a copper alloy (eg, beryllium copper) in a similar manner as the redistribution layers 121 and 122 and the redistribution vias 122V.

[0086] The semiconductor chip 150 may be mounted on the second surface 130B of the redistribution substrate 130. The contact pads 150P of the semiconductor chip 150 may be connected to the bonding pads 125 using connection bumps B (e.g., solder), respectively. The semiconductor chip 150 may be electrically connected to the redistribution structure 120. The semiconductor package 100 may further include an underfill resin 161 disposed between the active surface of the semiconductor chip 150 and the second surface 130B of the redistribution substrate 130. The underfill resin 161 may be formed to surround the side surfaces of the connection bumps B. For example, the underfill resin 161 may include an epoxy resin.

[0087] A molding portion 165 covering the semiconductor chip 150 may be formed on the second surface 130B of the redistribution substrate 130. The upper surface 150T of the semiconductor chip 150 may be exposed through the upper surface of the molding portion 165, and heat dissipation may be promoted through the exposed upper surface of the semiconductor chip 150. The upper surface of the molding portion 165 may be ground to expose the upper surface 150T of the semiconductor chip 150. The upper surface 150T of the semiconductor chip 150 may be substantially coplanar with the upper surface of the molding portion 165. For example, the molding portion 165 may be formed of a hydrocarbon ring compound containing a filler. The filler may be, for example, SiO 2 In some embodiments, the molded portion 165 may be formed of Ajinomoto Build-up Film (ABF).

[0088] External connectors 180 may be attached to the UBM layer of the redistribution substrate 130. External connectors 180 may be, for example, solder balls or bumps. External connectors 180 may electrically connect semiconductor package 100 with an external device (eg, a motherboard).

[0089] Therefore, the formation direction of the redistribution via 122V may have a direction opposite to that of the UBM via 140V. After the build-up process of the redistribution layer, a relatively thick UBM layer 140 may be finally formed by using an additional carrier introduction transfer process in the build-up process of the redistribution substrate 130 .

[0090] This modification of the process sequence can greatly reduce the fluctuation problem. Specifically, after performing a build-up process of a redistribution layer having a relatively thin thickness using a first carrier, a UBM layer having a relatively thick thickness can be formed after a transfer process of transferring to a second carrier. Therefore, the fluctuation problem can be greatly reduced.

[0091] Figures 3 to 10 are cross-sectional views illustrating main processes of a method of manufacturing a semiconductor package according to an exemplary embodiment.

[0092] Reference Figure 3 , a first redistribution layer 121 may be disposed on the first carrier 210 , and a first insulating layer 111 may be formed on the first carrier 210 to cover the first redistribution layer 121 .

[0093] The first carrier 210 may be provided as a substrate for constructing a redistribution structure. As described above, the first redistribution layer 121 may include a planar conductor pattern without an interlayer via structure. The first redistribution layer 121 may include, for example, copper, nickel, stainless steel, or a copper alloy (e.g., beryllium copper). The first insulating layer 111 may include a resin (e.g., an epoxy resin or a polyimide resin), and may be a resin without a filler. For example, the first insulating layer 111 may be formed of a photosensitive insulating material.

[0094] Next, refer to Figure 4 , a first hole h1 for interlayer connection may be formed in the first insulating layer 111 .

[0095] When the first insulating layer 111 is a photosensitive insulating material, a first hole h1 having a small size can be formed using a fine pitch of a photolithography process. For example, since the exposed area gradually decreases in the thickness direction of the first insulating layer 111, the first hole h1 may have a shape that becomes narrower as its horizontal cross-sectional area decreases. Thus, the interlayer via (e.g., redistribution via, UBM via) defined by the first hole h1 may have a tapered shape that gradually narrows in the direction to be formed. In another embodiment, the first hole h1 may be formed by a laser drilling process using an ultraviolet (UV) laser or an excimer laser. The hole formed by the laser drilling process may also have a shape that narrows in the downward direction.

[0096] Reference Figure 5, a second redistribution layer 122 connected to the first redistribution layer 121 may be formed on the first insulating layer 111 .

[0097] This operation may be performed by a plating process. Specifically, the second redistribution layer 122 may be formed by forming a seed layer along the surface of the first insulating layer 111 on which the first holes h1 are formed, and then by a plating process (e.g., a copper plating process) using a mask pattern. For example, the second redistribution layer may be formed by an immersion plating process, an electroless plating process, an electroplating process, or a combination thereof. The second redistribution layer 122 may be formed by removing the mask pattern to remove the plated portion of the undesired area using an ashing or stripping process, and then after removing the mask pattern, removing the exposed portion of the seed layer by using a chemical etching process.

[0098] Since the second redistribution layer 122 and the redistribution through-hole 122V obtained by this process are formed by the same plating process as described above, the second redistribution layer 122 can have a structure continuously integrated with the redistribution through-hole 122V. As used herein, "continuously integrated structure" refers to a structure to be continuously integrated that does not have a discontinuous boundary surface (e.g., a grain boundary), wherein two components are not formed by different processes and simply contact (discontinuous), but are formed by the same process from the same material. For example, the continuously integrated structure may be a homogeneous monolithic structure.

[0099] In this embodiment, the second redistribution layer 122 may be referred to as a continuously integrated structure because the second redistribution layer 122 is formed through the same plating process together with the redistribution via 122V. Meanwhile, the first redistribution layer 121 and the redistribution via 122V may not be referred to as a continuously integrated structure because they are formed through different processes even when they are connected to each other.

[0100] Reference Figure 6 After forming the second insulating layer 112 , a bonding pad 125 connected to the second redistribution layer 122 may be formed on the second insulating layer 112 .

[0101] Specifically, this operation may include a first operation of forming the second insulating layer 112 having the second hole h2 and a second operation of forming the bonding pad 125 having the through hole portion 125V connected to the second redistribution layer 122 through the second hole h2. The first operation may refer to Figure 3 and Figure 4 The process, and the second operation can refer to Figure 5 The process.

[0102] Specifically, the second hole h2 may also have a shape whose horizontal cross-sectional area narrows downwardly in a manner similar to the first hole h1. Therefore, the via portion 125V of the bonding pad 125 defined by the second hole h2 may have a shape narrowing downwardly in a manner similar to the redistribution via 122V.

[0103] Reference Figure 7 , can be used in the reallocation structure ( Figure 6 The semiconductor chip 150 is mounted on the final structure shown in FIG. 1 to form a molding portion 165 for protecting the semiconductor chip 150 .

[0104] The contact pads 150P of the semiconductor chip 150 may be connected to the bonding pads 125, respectively, using connection bumps B (e.g., solder). As described above, the semiconductor chip 150 may be electrically connected to the redistribution structure 120. An underfill resin 161 may be formed between the active surface of the semiconductor chip 150 and the upper surface of the redistribution structure to surround the side surfaces of the connection bumps B. For example, the underfill resin 161 may include epoxy resin.

[0105] The molding portion 165 may be formed to cover the semiconductor chip 150, and the upper surface of the molding portion 165 may be ground to expose the upper surface 150T of the semiconductor chip 150. Figure 7 , the dotted lines represent the portions of each of the semiconductor chip 150 and the molding portion 165 to be removed by the grinding process. The upper surface 150T of the semiconductor chip 150 may be exposed by the grinding process to improve the heat dissipation effect and reduce the thickness of the semiconductor package at the same time. The upper surface 150T of the semiconductor chip 150 may be substantially coplanar with the upper surface of the molding portion 165. For example, the molding portion 165 may be formed of an Ajinomoto laminated film (ABF).

[0106] Next, refer to Figure 8 , after the redistribution structure is transferred to the second carrier 220 , the first carrier 210 may be removed, and a base insulating layer 115 may be formed on the removed surface.

[0107] The base insulating layer 115 may include a resin (eg, epoxy resin or polyimide resin). For example, the base insulating layer 115 may be formed of the same material as the first insulating layer 111 and the second insulating layer 112. In some embodiments, the base insulating layer 115 may be a photosensitive insulating material.

[0108] Reference Fig. 9, openings may be formed in base insulating layer 115 in which a portion of first redistribution layer 121 is exposed, and a plurality of UBM layers 140 may be formed to be connected to first redistribution layer 121. For example, openings may be formed in base insulating layer 115 to expose portions of the upper surface of first redistribution layer 121, and a plurality of UBM layers 140 may be formed to extend into the openings.

[0109] The UBM layer 140 may include a UBM pad 140P disposed on the base insulating layer 115 and a UBM via 140V connected to the first redistribution layer 121. The UBM layer 140 may be formed using a plating process in a similar manner to the second redistribution layer 122 and the bonding pad 125. Thus, the UBM pad 140P and the UBM via 140V may form a continuously integrated structure. For example, the UBM layer 140 may be a homogeneous monolithic structure.

[0110] In a manner different from the operation of forming the redistribution structure 120, the UBM layer 140 may be formed in a state of being transferred (vertically inverted) to the second carrier 220, so that the UBM via 140V may have a shape that is narrowed in a direction opposite to the narrowing direction of the redistribution via 122V. Figure 2 , UBM via 140V may have a lower width Da wider than an upper width Db. The thickness of UBM layer 140 may be greater than the thickness of first redistribution layer 121 or second redistribution layer 122 , and may be, for example, about 10 μm or greater.

[0111] Next, refer to Fig.10 , an external connector 180 may be formed on the UBM layer 140. The external connector 180 may be, for example, a solder ball or a bump. The external connector 180 may electrically connect the semiconductor package 100 with an external device.

[0112] The above process can be changed into various forms. For example, after forming the UBM layer 140 (in Fig. 9 After the operation shown in the figure) an operation of mounting a semiconductor chip is performed (see Figure 7 ). The redistribution structure may be shown as two horizontal levels of redistribution layers, and the second redistribution layer with redistribution vias may be shown as a single horizontal level, but the second redistribution layer may be introduced into multiple redistribution layers as needed. In this case, when forming the bonding pad ( Figure 6 ) operation, the operation of forming the second redistribution layer ( Figures 3 to 5 ) is repeated many times.

[0113] Fig.11 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment.

[0114] Reference Fig.11 The semiconductor package 100' according to this exemplary embodiment may be understood as having Figure 1 and Figure 2 The structure is similar to the embodiment shown in the figure, except that a redistribution substrate 130' having a different configuration is provided and a passivation layer 170 is further added. Therefore, unless otherwise specifically stated, Figure 1 and Figure 2 The description of the illustrated embodiment is combined with the description of this embodiment.

[0115] The redistribution substrate 130' used in this embodiment may include a redistribution structure 120' of three horizontal levels. The insulating member 110' may include a base insulating layer 115 and a first insulating layer 111, a second insulating layer 112, and a third insulating layer 113, and may also include a first redistribution layer 121 and two second redistribution layers 122a and 122b, which are located on respective boundary surfaces of the insulating layers 115, 111, 112, and 113.

[0116] In a different manner from the previous embodiments, the redistribution substrate 130' may not include bonding pads (eg, Figure 1 Specifically, the connection structure between the semiconductor chip 150 and the redistribution structure 120' can be made by forming an opening H on the insulating layer (third insulating layer 113) adjacent to the second surface 130B of the redistribution substrate 130', and directly connecting the contact pad 150P of the semiconductor chip 150 with the portion of the second redistribution layer 122b exposed by the opening H by using the connecting bump B.

[0117] The semiconductor package 100' may further include a passivation layer 170 disposed on the first surface 130A of the redistribution substrate 130'. The passivation layer 170 may expose at least a portion of the UBM layer 140, and an external connector 180 may be formed at the open UBM layer 140. In some embodiments, the insulating layers 115, 111, 112, and 113 and the passivation layer 170 may be formed of the same material. For example, the insulating layers 115, 111, 112, and 113 and the passivation layer 170 may include a photosensitive insulating material. In some embodiments, the passivation layer 170 may include an insulating material different from the insulating member 110'. For example, the insulating layers 115, 111, 112, and 113 may include a photosensitive insulating material, and the passivation layer 170 may be formed of a hydrocarbon ring compound containing a filler. For example, the passivation layer 170 may include ABF.

[0118] Also in this embodiment, in a similar manner to the previous embodiment, by introducing the UBM layer 140 in the latter half of the build-up process of the redistribution substrate 130 ′, the fluctuation problem due to the thickness of the UBM layer 140 can be greatly reduced to improve the reliability of the semiconductor package.

[0119] Fig.12 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment, and Fig.13 yes Fig.12 A plan view of a semiconductor package is shown.

[0120] Reference Fig.12 and Fig.13 The semiconductor package 100 according to this embodiment can be understood as having Figure 1 and Figure 2 The structure is similar to the embodiment shown in FIG. 1 , except that it includes a plurality of semiconductor chips 150A and 150B and a heat sink 195. Therefore, unless otherwise specifically stated, Figure 1 and Figure 2 The description of the illustrated embodiment is combined with the description of this embodiment.

[0121] The redistribution substrate used in this embodiment may include three horizontal levels of redistribution substrate 130", which is similar to Fig.11 A redistributive substrate 130 ′ is shown and may include a passivation layer 170 disposed on a first surface of the redistributive substrate.

[0122] In this embodiment, the first semiconductor chip 150A and the second semiconductor chip 150B can be mounted on the second surface 130B of the redistribution substrate 130". The contact pads of the first semiconductor chip and the second semiconductor chip can be connected to the bonding pads respectively through connecting bumps. A molding portion 165 can be formed to cover a portion or all of the first semiconductor chip 150A and the second semiconductor chip 150B. The molding portion 165 may include, for example, an epoxy molding compound. In a manner similar to the previous embodiment, the molding portion 165 may be coplanar with the upper surfaces of the first semiconductor chip 150A and the second semiconductor chip 150B.

[0123] The semiconductor package 100" according to this embodiment may also include a thermally conductive material layer 191 and a heat sink 195 sequentially arranged on the upper surfaces of the first semiconductor chip 150A and the second semiconductor chip 150B. The thermally conductive material layer 191 may be disposed between the heat sink 195 and the first and second semiconductor chips 150A, 150B and the molding portion 165. The thermally conductive material layer 191 may help to smoothly discharge the heat generated from the first and second semiconductor chips 150A, 150B to the heat sink 195. The thermally conductive material layer 191 may be made of a thermal interface material (TIM). For example, the thermally conductive material layer 191 may be formed of an insulating material, or may be formed of a material including an insulating material and capable of maintaining electrical insulation. The thermally conductive material layer 191 may include, for example, epoxy resin. Specific examples of the thermally conductive material layer 191 may include mineral oil, grease, gap filler putty, phase change gel, phase change material pad, or epoxy resin filled with particles.

[0124] The heat dissipation plate 195 may be disposed on the thermally conductive material layer 191. The heat dissipation plate 195 may be, for example, a heat sink, a heat spreader, a heat pipe, or a liquid cooled cold plate.

[0125] Fig.14 is a block diagram illustrating a configuration of a semiconductor package according to an exemplary embodiment.

[0126] Reference Fig.14 , the semiconductor package 1000 may include a microprocessor 1010, a memory 1020, an interface 1030, a graphics processor (GPU) 1040, a functional block 1050, and a bus 1060 connected therebetween. The semiconductor package 1000 may include both the microprocessor 1010 and the graphics processor 1040, or may include only one of them.

[0127] The microprocessor 1010 may include a core and an L2 cache. For example, the microprocessor 1010 may include multiple cores. Each core in the multiple cores may have the same or different performance. In addition, the cores of the multiple cores may be activated at the same time, or may be activated at different times from each other.

[0128] The memory 1020 may store results of processing performed in the functional block 1050 under the control of the microprocessor 1010, etc. The interface 1030 may exchange information and signals with external devices. The graphics processor 1040 may perform a graphics function. For example, the graphics processor 1040 may perform video encoding and decoding or process three-dimensional (3D) graphics. The functional block 1050 may perform various functions. For example, when the semiconductor package 1000 is an application processor (AP) used in a mobile device, a part of the functional block 1050 may perform a communication function. Here, the semiconductor package 1000 may include Figure 1 , Fig.11 and Fig.12 One or more of the semiconductor packages 100, 100' and 100" described in.

[0129] According to an exemplary embodiment, by introducing the UBM layer in the latter half of the build-up process of the redistribution substrate, the fluctuation problem due to the thickness of the UBM layer 140 can be greatly reduced to enhance the reliability of the semiconductor package. In some embodiments, the UBM layer can be formed in a non-solder mask defined (NSMD) form in which the pad portion does not contact the outer insulating layer.

[0130] Various and advantageous advantages and effects of the inventive concept may not be limited to the above description and may be more easily understood in the course of describing specific embodiments of the inventive concept.

[0131] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor package, comprising: A redistribution substrate having a first surface and a second surface arranged opposite to each other, and comprising an insulating member, a plurality of redistribution layers, and a redistribution through hole, wherein the plurality of redistribution layers are arranged at different horizontal levels in the insulating member, and the redistribution through hole connects the redistribution layers arranged at adjacent horizontal levels and has a shape that narrows from the second surface toward the first surface in a first direction; a plurality of UBM layers, each of the plurality of UBM layers comprising an UBM pad and an UBM via, the UBM pad being disposed on the first surface of the redistribution substrate, the UBM via being connected to a redistribution layer adjacent to the first surface among the plurality of redistribution layers and connected to the UBM pad, and the UBM via having a shape narrowed in a second direction opposite to the first direction, wherein the redistribution layer adjacent to the first surface is a planar conductive pattern; as well as at least one semiconductor chip disposed on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer of the plurality of redistribution layers adjacent to the second surface, The thickness of each of the plurality of UBM layers is greater than the thickness of the redistribution layer adjacent to the first surface, and the thickness of each of the plurality of UBM layers is 10 μm or greater.

2. The semiconductor package according to claim 1, wherein the redistribution substrate further comprises a plurality of bonding pads disposed on the second surface, each of the plurality of bonding pads being connected to a corresponding one of the plurality of contact pads, Each of the plurality of bonding pads has a via portion partially passing through the insulating member and connected to the redistribution layer adjacent to the second surface among the plurality of redistribution layers. 3 . The semiconductor package according to claim 2 , wherein the through hole portion has a shape narrowed in the first direction. 4 . The semiconductor package according to claim 1 , wherein the insulating member has a plurality of holes to expose portions of the redistribution layer adjacent to the second surface, and the plurality of contact pads are respectively connected to the redistribution layer adjacent to the second surface via the plurality of holes. The semiconductor package according to claim 1 , wherein the insulating member comprises a photosensitive insulating material. 6 . The semiconductor package of claim 1 , wherein the under ball metal pad has a portion extending along a surface of the insulating member located on the first surface of the redistribution substrate.

7. The semiconductor package according to claim 1, further comprising: a passivation layer disposed on the first surface of the redistribution substrate and exposing at least a portion of the plurality of UBM layers; as well as A plurality of external connectors are respectively disposed on the plurality of under-ball metal layers. The semiconductor package according to claim 7 , wherein the passivation layer comprises a photosensitive insulating material. 9 . The semiconductor package according to claim 7 , wherein the passivation layer comprises an insulating material different from a material of the insulating member.

10. The semiconductor package according to claim 1, further comprising: A molding portion is disposed on the second surface of the redistribution substrate and covers the at least one semiconductor chip.

11. A semiconductor package, comprising: A redistribution substrate having a first surface and a second surface disposed opposite to each other, and comprising a plurality of insulating layers and a plurality of redistribution layers disposed between the plurality of insulating layers, wherein the plurality of redistribution layers include a first redistribution layer adjacent to the first surface and at least one second redistribution layer disposed between the first redistribution layer and the second surface, each second redistribution layer having a redistribution through hole connected to the first redistribution layer or an adjacent second redistribution layer among the at least one second redistribution layer; a plurality of UBM layers disposed on the first surface of the redistribution substrate, each of the UBM layers having an UBM via connected to the first redistribution layer, wherein the first redistribution layer is a planar conductive pattern; at least one semiconductor chip disposed on the second surface of the redistribution substrate and having contact pads electrically connected to the at least one second redistribution layer; as well as a molding portion disposed on the second surface of the redistribution substrate and covering the at least one semiconductor chip, wherein the redistribution via has a shape that narrows from the second surface toward the first surface in a first direction, and the under ball metal via has a shape that narrows in a second direction opposite to the first direction, The thickness of each of the plurality of UBM layers is greater than the thickness of the first redistribution layer, and the thickness of each of the plurality of UBM layers is 10 μm or greater. 12 . The semiconductor package according to claim 11 , wherein the second RDL has a structure continuously integrated with the RVB, and the UBM layer has a structure continuously integrated with the UBM via.

13. The semiconductor package according to claim 11, further comprising: A passivation layer is disposed on the first surface of the redistribution substrate and exposes at least a portion of the UBM layer. 14 . The semiconductor package according to claim 13 , wherein each of the plurality of insulating layers and the passivation layer comprises a photosensitive insulating material. 15 . The semiconductor package according to claim 11 , wherein an upper surface of the at least one semiconductor chip is coplanar with an upper surface of the molding portion.

16. The semiconductor package according to claim 15, further comprising: The heat dissipation plate is disposed on the upper surface of the at least one semiconductor chip and the upper surface of the molding part. 17 . The semiconductor package according to claim 11 , wherein the at least one semiconductor chip comprises a plurality of semiconductor chips.

18. A semiconductor package, comprising: A redistribution substrate having a first surface and a second surface disposed opposite to each other, and comprising an insulating member and a plurality of redistribution layers disposed at different horizontal levels in the insulating member; an under ball metal layer, comprising an under ball metal pad and an under ball metal via, wherein the under ball metal pad is disposed on the first surface of the redistribution substrate, and the under ball metal via electrically connects the under ball metal pad and the plurality of redistribution layers and has a shape that becomes narrower in a direction from the first surface toward the second surface; as well as at least one semiconductor chip disposed on the second surface of the redistribution substrate and having contact pads electrically connected to the plurality of redistribution layers, The plurality of redistribution layers include: a first redistribution layer disposed at a horizontal level adjacent to the first surface in the insulating member and composed of a planar conductive pattern, and a plurality of second redistribution layers disposed at different horizontal levels in the insulating member, each of the plurality of second redistribution layers having a redistribution through-hole connected to the first redistribution layer or an adjacent second redistribution layer in the plurality of second redistribution layers, The thickness of each of the plurality of UBM layers is greater than the thickness of the first redistribution layer, and the thickness of each of the plurality of UBM layers is 10 μm or greater. 19 . The semiconductor package according to claim 18 , wherein the UBM layer has a structure continuously integrated with the UBM via. 20 . The semiconductor package according to claim 18 , wherein the redistribution via has a shape that becomes narrower in a direction from the second surface toward the first surface. 21 . The semiconductor package of claim 18 , wherein the second redistribution layer has a structure continuously integrated with the redistribution via, and the first redistribution layer does not include a via having a continuously integrated structure.

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