Power enhanced stack chip scale package solution with integrated die attach film

Abstract

An apparatus comprising: a die stack comprising at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die being over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.

Description

BACKGROUND

[0001] In current packaging architectures, power bond pads are located at the edge of the silicon die, which increases the wire bond density. Additionally, power pads compete for space with signal pads along the edge of the die. Power distribution requires traces from the power pads located at the edge of the die to points within the die, which increases the trace density. BRIEF DESCRIPTION OF DRAWINGS

[0002] Embodiments of the present disclosure can be more fully understood from the following detailed description and the accompanying drawings, in which:

[0003] Figure 1A A cross-sectional view of a partially completed tile die stack assembly with a dual layer die attach film (DLDAF) layer between two dies is shown.

[0004] Figure 1B A plan view of a tile die stack according to some embodiments of the present disclosure is shown, showing bond pads distributed on the upper die surface away from the die edge. Figure 1A

[0005] Figure 2A A cross-sectional view of an exemplary tile die stack assembly with spacer dies on top according to some embodiments of the present disclosure is shown, with a DLDAF layer between adjacent dies.

[0006] Figure 2B A cross-sectional view of an exemplary straight up die stack assembly according to some embodiments of the present disclosure is shown, with a DLDAF layer between adjacent dies.

[0007] Figure 3A A cross-sectional view of a portion of a DLDAF according to some embodiments of the present disclosure is shown.

[0008] Figure 3B A cross-sectional view of a portion of a three layer die attach film (TLDAF) according to some embodiments of the present disclosure is shown.

[0009] Figure 3C A plan view of a die with power pads distributed on top of the die surface and covered by a section of DLDAF according to some embodiments of the present disclosure is shown.

[0010] Figure 4 A cross-sectional view of an exemplary tile die stack with a three layer die attach film (TLDAF) between adjacent dual side dies according to some embodiments of the present disclosure is shown.

[0011] ​Figure 5 A flowchart showing a process flow for assembling a die stack with DLDAF is shown in accordance with some embodiments of the disclosure.

[0012] Figures 6A-6F A cross-sectional view of an exemplary method of assembling a tile die stack is shown in accordance with some embodiments.

[0013] Figure 7 A package of a stacked chip scale package (SCSP) with a DLDAF or TLDAF including connecting multiple dies in a vertical die stack as part of a system on a chip (SoC) package in a computing device implementation is shown in accordance with some embodiments of the disclosure. DETAILED DESCRIPTION

[0014] A stacked chip scale package (SCSP) architecture is described that employs a dual layer conductive die attach film (DAF) having at least one conductive adhesion layer integrated with a non-conductive adhesion layer for attaching dies in a vertical stack. In some embodiments, an insulating layer is sandwiched between the two conductive adhesion layers, forming a three layer conductive DAF. In some embodiments of some SCSP implementations, the dies in the stack carry bond pads on the top side. Accordingly, the dual layer conductive DAF is interposed between adjacent dies in a vertical die stack. The conductive layer adheres to the top side of the underlying die and forms contact with bond pads and terminals present on the top side. The insulating layer adheres to the bottom side of the overlying die where there are no bond pads or terminals. In some embodiments, power bond pads and / or terminals are located along the top side of the die at a location between the bond edge and the back edge.

[0015] In conventional die architectures, power bond pads are all located at the bond edge along with signal bond pads. A distributed power terminal layout can provide enhanced power delivery to the integrated circuit carried by the die. Power bond pads located at the edge are typically connected by internal trace metallization to the integrated circuit carried on or within the die. The architecture of embodiments provides greater flexibility for the design of the integrated circuit carried on or within the die. In accordance with some embodiments, power delivery to the integrated circuit is supplied by an external coupling, which eliminates the dependency on internal trace routing extending from the edge of the die.

[0016] The conductive layers of dual-layer and triple-layer DAFs provide sheet conductors that electrically couple one or more of the distributed power bonding pads and / or terminals together. In some embodiments, one or more relay bonding pads are located on the top surface, close to the bonding edge of the die, and in some embodiments, one or more relay bonding pads are connected to lead bonding pads via short internal traces. According to embodiments, relay bonding pads are externally coupled to the distributed power terminals via the conductive layers of the dual-layer DAF. In some embodiments, relay pads are coupled to a single lead bonding pad on the die edge via short internal traces. Thus, power is delivered from the relay pads to the power terminal pads through the conductive layers. The conductive layers of the dual-layer DAF electrically couple multiple power terminals on the die to a single lead bonding pad via intervening relay pads. Therefore, the lead bonding density at the die edge and the required number of bonding pads at the die's bonding edge can be significantly reduced. According to some embodiments, the conductive layers of the dual-sided DAF are sheet conductors that couple to one or more power terminals on the die surface covered by the DAF. In some embodiments, the conductive layer of the DAF has a lower sheet resistance than the power trace metallization, thereby providing a low-resistance current path from the relay pad through the conductive layer to one or more power terminals. The low sheet resistance of the conductive layer of the dual-sided DAF allows for lower Ig. 2 R power loss, which enables less localized heat generation and smaller IR drop.

[0017] In some embodiments, the DAF is a three-layer film having an inner insulating layer sandwiched between first and second outer conductive layers. The insulating layer isolates the first and second outer conductive layers, which form separate conductive adhesive sheets. In some embodiments, the die stack assembly includes a double-sided die having integrated circuits on both sides of the die. In this embodiment, the three-layer DAF is inserted between upper and lower adjacent dies in a vertical stack, with the first conductive layer adhered to the top side of the lower die and the bottom side of the upper die.

[0018] Numerous details are set forth in the following description to provide a more thorough explanation of embodiments of the present disclosure. However, it will be apparent to those skilled in the art that embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known structures and apparatuses are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present disclosure.

[0019] It should be noted that in the corresponding figures of the embodiments, signals are represented by lines. Some lines may be thicker to represent signal paths with more components, and / or have arrows at one or more ends to indicate the main direction of information flow. Such indications are not intended to be limiting. Rather, these lines may be used in conjunction with one or more exemplary embodiments to facilitate a more intuitive understanding of the circuit or logic unit. As specified by design requirements or preferences, any representative signal may practically include one or more signals that can travel in either direction and can be implemented using any suitable type of signaling scheme.

[0020] "Joint pad" is a term referring to an electrically bonded pad associated with a test point or external electrical connection of an integrated circuit. Related industry terms are "joint pad" and "bump". A "solder bump" or "bump" is a solder ball bonded to a joint pad for further assembly of the die into a package using surface mount technology, or for wire bonding.

[0021] The associated term is "terminal," which means a contact for receiving power or other electrical signals. For the purposes of this disclosure, "terminal" indicates a signal or power slot and a signal or power input point coupled to an integrated circuit. A terminal may be a bonding pad for wire bonding or solder bump attachment.

[0022] Throughout this specification and in the claims, the term “connection” means a direct connection, such as an electrical, mechanical, or magnetic connection between connected objects without any intermediary device. The term “coupled” means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between connected objects, or an indirect connection via one or more passive or active intermediary devices. The terms “circuit” or “module” can refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term “signal” can refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of “a” and “described” include plural references. The meaning of “in” includes both “in” and “on”.

[0023] The vertical orientation is in the z-direction, and it should be understood that the terms "top," "bottom," "above," and "below" refer to relative positions in the z-axis in their usual sense. However, it should be understood that embodiments are not necessarily limited to the orientations or configurations shown in the figures.

[0024] The terms “basically,” “near,” “roughly,” “near,” and “approximately” generally refer to within + / - 10% of the target value (unless explicitly specified). Unless otherwise specified, the use of ordinal adjectives such as “first,” “second,” and “third” to describe common objects merely indicates that different instances of similar objects are being referred to, and is not intended to imply that the objects described must be in a given order, sequence, or any other manner in time or space.

[0025] For the purposes of this disclosure, the phrases “A and / or B” and “A or B” mean (A), (B) or (A and B). For the purposes of this disclosure, the phrases “A, B and / or C” mean (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).

[0026] Views labeled "Section," "Outline," and "Planar" correspond to orthogonal planes in the Cartesian coordinate system. Thus, section and outline views are taken in the xz plane, and planar views are taken in the xy plane. Typically, the outline view in the xz plane is a section view. Axes are used to label the figures to indicate the orientation of the views.

[0027] Figure 1A A cross-sectional view in the xz plane is shown of a tile die stack assembly 100 with a double-layer die attachment membrane between two dies. This cross-section is along... Figure 1B It is cut by the cutting line A-A' in the middle.

[0028] Dies 101a and 101b are vertically stacked in a tile-like configuration with their edges offset in the x-axis. In some embodiments, dies 101a and 101b comprise a semiconductor body from which an integrated device is fabricated. In some embodiments, dies 101a and 101b comprise silicon or other Group IV elements such as germanium. In other embodiments, dies 101a and 101b comprise III-V compounds such as InAs, GaAs, InP, GaP, GaN, etc. For clarity, two dies 101 are shown in the die stack 100. However, the die stack 100 may have any number of dies in the stack. Dies 101a and 101b are bonded to each other, wherein a double-layer conductive die attachment film (DLDAF) 102 is disposed between dies 101a and 101b. In some embodiments, the DLDAF 102 comprises a non-conductive adhesive layer 103 over a conductive adhesive layer 104. Dies 101a and 101b include one or more power terminal pads 105 and relay pads 106 distributed on the top surface 107. According to some embodiments, the relay pad 106 is internally connected to the wire bonding pad 108 via a trace 109.

[0029] A conductive adhesive layer 104 of the DLDAF 102 is disposed on the top surface 107 of dies 101a and 101b (only die 101a is shown covered), thereby covering the power terminal pad 105 and the relay pad 106 (shown for die 101b, but the same description applies to die 101a). According to some embodiments, the conductive adhesive layer 104 adheres to the top surface 107 and conformally adheres to the power terminal pad 105 and the relay pad 106. In some embodiments, the conductive adhesive layer 104 is a sheet conductor and electrically couples the power terminal pad 105 to the relay pad 106. The relay pad 106 is electrically connected to a wire bonding pad 108, to which power can be supplied from leads originating from a substrate (not shown) and bonded to the wire bonding pad 108. In some embodiments, power is distributed to the power terminal pad 105 via the conductive adhesive layer 104.

[0030] In some embodiments, the bottom surfaces 107 of dies 101a and 101b do not have metallization in the form of contact pads for external electrical coupling and are not electrically active. For die attachment, a non-conductive adhesive layer 103 of DLDAF 102 is disposed beneath the bottom surfaces 110 of dies 101a and 101b. In some embodiments, the non-conductive adhesive layer 103 is a carrier or support layer for the conductive adhesive layer 104 and adheres to the inactive bottom surfaces 110 of dies 101a and 101b to complete the attachment of adjacent dies 101a and 101b. Although not active, the bottom surfaces 110 may exhibit conductivity and must be isolated from the metallization on the adjacent dies below by an insulating film. The non-conductive adhesive layer 103 serves this function.

[0031] Figure 1B Some embodiments according to this disclosure are shown. Figure 1A A plan view of the tile die stack 100, showing the bonding pads distributed on the upper die surface away from the die edge.

[0032] exist Figure 1B In this die 101b, multiple power terminal pads 105 are distributed on the top surface 107. In some embodiments, the power terminal pads 105 are distributed between the bonding edge 111 and the read edge 112. Wire bonding pads 108 are located near the bonding edge 111. In some embodiments, relay pads 106 are adjacent to wire bonding pads 108 and positioned between the wire bonding pads 108 and the power terminal pads 105. Figure 1B The dashed line in the diagram indicates the connection trace that connects relay pad 106 to wire bonding pad 108. Figure 1A(109 in the text). In some embodiments, the connection trace is embedded below the top surface 107. In the die stack 100, die 101a is below die 101b. Dies 101a and 101b are separated by an intermediate layer of DPDAF ( Figure 1A (102) is separated, which is in Figure 1B Not shown. In some embodiments, a die stack 100 is disposed on a packaging substrate 113, on which bonding fingers 114 are disposed near the bonding edges 111 of dies 101a and 101b. In some embodiments, the packaging substrate 113 comprises phenolic plastic, epoxy resin, or a polymer film. In some embodiments, power terminal pads 105 and relay pads 106 are equivalently disposed on die 101a.

[0033] The power terminal pad 105, relay pad 106, and wire bonding pad 108 may comprise materials such as, but not limited to, copper, copper alloys, aluminum and aluminum alloys, nickel, and polysilicon. In some embodiments, the power terminal pad 105 may be a single pad disposed on the top surface 107. In some embodiments, the power terminal pad 105 may be multiple pads disposed on the top surface 107, such as... Figure 1B As shown. Figure 1B As shown, there may be one or more relay pads 106. In some embodiments, the power terminal pad 105 is part of one or more integrated circuits incorporated on the die (100a and 100b). As an example, the power terminal pad 105 is coupled to V DD Power rail. In some embodiments, relay pad 106 is disposed near the bonding edge 111. In some embodiments, relay pad 106 is electrically coupled to one or more lead bonding pads 108.

[0034] Advantageously, the conductive adhesive layer 104 of the DPDAF 102 provides an external low-resistance path coupling the power terminal pad 105 to the relay pad 106, thereby eliminating the need for power traces on the coupling lead bonding pad 108 and the power terminal pad 105. The reduction or elimination of power traces allows for more signal routing options and increases signal trace density. In some embodiments, the conductive adhesive layer 104 has a thickness ranging from 1 to 50 micrometers and a width extending to a maximum die width. Due to the larger cross-sectional area of ​​the conductive adhesive layer 104, the sheet resistance can be significantly lower than that of conventional metal traces, allowing for significantly greater current distribution to the power terminal pad 105. The DPDAF 102 enables the design of integrated circuits with one or more distributed power terminals. As a result, the requirement for long and potentially higher-resistance power traces is reduced, allowing for the inclusion of higher-density power-consuming devices, such as transistors and resistors, in the integrated circuit.

[0035] Figure 2AA cross-sectional view of an exemplary tile die stack assembly 200a having a spacer die on top according to some embodiments of the present disclosure is shown, wherein a double die attachment film (DLDAF) layer is provided between adjacent dies.

[0036] Figure 2A An example of a complete die stack assembly 200 employing a tile-stacked construction is shown. In the tile stack, the edges 112 of dies 101a, 101b, and 101c (including spacer die 201) are offset. The spacer die 201 caps the die stack 200 of dies 101a, 101b, and 101c, which, according to some embodiments, are active dies. In some embodiments, the spacer die 201 is disposed above the top active die 101c and provides a cap for the non-conductive adhesive layer 103 of the topmost DLDAF layer 102c. Leads 202 are bonded at a first end to lead bonding pads 108 on dies 101a, 101b, and 101c. Leads 202 are bonded at a second end to bonding fingers 114 disposed on a package substrate 113. In some embodiments, leads 202 provide a power connection from power distribution metallization coupled to the bonding fingers 114 on the package substrate 113.

[0037] In some embodiments, as described above, the bonding pad 108 is coupled to the relay pad 106 via a trace 109. Figure 2A In the illustrated embodiment, power is delivered from a power pin on the package substrate 113 to a relay pad 106 via lead 202. The tiled stack configuration of the die stack 200a exposes bonding pads 108 for accessing wire bonds. Figure 2A In the illustrated embodiment, the die stack 200a includes three dies 101a, 101b and 101c. However, the number of dies in the die stack 200a is not limited, and the die stack 200a may include any number of dies.

[0038] Figure 2B A cross-sectional view is shown of an exemplary straight-up die stack 200b assembly having a double-sided die attachment membrane layer between adjacent dies according to some embodiments of the present disclosure.

[0039] exist Figure 2B In this example, an example of a straight-up die stack 200b having dies 101a, 101b, and 101c and spacer die 201 is arranged with edges 112 aligned. The straight-up die stack architecture reduces the xy package footprint, facilitating further miniaturization of computing and analog devices. Leads 202 are bonded to wire bond pads 108, which are embedded within the conductive adhesive layer 104 of the DLDAF 102. Figure 2AThus, in some embodiments, there is a spacer die 201 to cap the die stack 200b and cover the topmost DLDAF 102c with a non-conductive adhesive layer 103.

[0040] In some embodiments, the leads 202 are all bonded to bonding pads 108 at a first end and to bonding fingers 114 on the package substrate 113 at a second end. In other embodiments, the leads 202 are bonded to lead bonding pads 108 on adjacent or non-adjacent dies 101a-101c within the die stack 200b.

[0041] Figure 3A A cross-sectional view of a portion of a double-layer die attachment membrane 102 according to some embodiments of the present disclosure is shown.

[0042] exist Figure 3A A portion of DLDAF 102 is shown in the image. According to some embodiments, conductive adhesive layer 104 and non-conductive adhesive layer 103 are adjacent layers and comprise a polymer matrix impregnated with an adhesive compound. In some embodiments, conductive adhesive layer 104 comprises conductive particles of graphite, gold, and silver. In some embodiments, DLDAF 102 comprises a partially cured thermosetting polymer resin that is cured into a solid die attachment layer after the die stack is assembled to permanently secure the die stack in a rigid configuration.

[0043] Figure 3B A cross-sectional view of a portion of a three-layer core attachment membrane 300 according to some embodiments of the present disclosure is shown.

[0044] exist Figure 3B In this embodiment, the three-layer die-attachment film (TLDAF) 300 includes a non-conductive layer 103 sandwiched between two conductive adhesive layers 104. In some embodiments, the conductive adhesive layers 104 are substantially identical and include conductive particles, such as, but not limited to, graphite, gold, and silver. Similar to... Figure 3A The DLDAF102 and TLDAF 300 in the embodiment include a polymer matrix. In some embodiments, TLDAF 300 includes a thermoplastic polymer resin that cures upon heating. As shown below, TLDAF 300 can be used for dies having power terminal pads on both the top and bottom surfaces, wherein the conductive adhesive layer can contact the active surfaces of upper and lower adjacent dies in the stack.

[0045] Figure 3C A plan view of a die 310 covered by a section of a double-layer die attachment film (DLDAF) according to some embodiments of the present disclosure is shown, illustrating an exemplary current distribution through the conductive adhesive layer 104.

[0046] exist Figure 3CThe diagram shows a conductive adhesive layer 104 (of DLDAF 102 or TLDAF 300) with power pad terminals (e.g., Figure 1B 105 in the middle) and relay pads (e.g., Figure 1B The metallization coverage of 106) in the middle. Figure 3C In this process, the conductive adhesive layer 104 is partially transparent to show a similar appearance to... Figure 1B The lower power terminal pad 105 and relay pad 106 are shown in the configuration. An example of the current distribution from the relay pad to the power terminal is as current being conducted through the conductive adhesive layer 104. A dashed curve along the top surface 107 of the die 101 illustrates an exemplary current distribution from the relay pad 106 to the power terminal pad 105. This current distribution shows that current can diffuse from a single relay pad 106 to multiple power terminal pads 105. In some embodiments, multiple relay pads 106 simultaneously supply power to the power terminal pads 105, thereby allowing a symmetrical current distribution pattern to occur through the conductive adhesive layer 104, such as... Figure 3C As shown in the diagram. In this way, heat distribution can also be balanced on the top surface 107 of the die, thereby preventing hot spots on the die.

[0047] Figure 4 A cross-sectional view is shown of an exemplary tile die stack 400 having a three-layer die attachment membrane between adjacent double-sided dies according to some embodiments of the present disclosure.

[0048] exist Figure 4 In this embodiment, the die stack 400 includes dual-sided dies 401, each having power terminal pads 105 and relay pads 106 disposed on both sides. In this embodiment, a three-layer die attachment film (TLDAF) 300 is disposed between dies 401a, 401b, and 401c, contacting the power terminal pads 105 and relay pads 106 on both sides of die 401. A spacer die 201 caps the die stack 400. Below the spacer die 201 is a double-layer die attachment film (DLDAF) 102 between the spacer die 201 and die 401a. Similarly, the DLDAF 102 is inserted between the die stack 400 and the package substrate 113, wherein a non-conductive layer 103 bonds the die stack 400 to the package substrate 113 while coupling the power terminal pads 105 and relay pads 106 on the bottom side of die 401c.

[0049] In some embodiments, all power terminal pads 105 disposed on one side of dies 401a-401c are coupled to each other via a conductive adhesive layer 104 and are therefore at substantially the same potential. In some embodiments, portions of the power terminal pads 105 are coupled via separate portions of a double die attachment film. As an example, in some embodiments, one portion of the power terminal pad 105 is coupled to a positive voltage rail on substrate 113. Another portion of the power terminal pad 105 is coupled to a ground rail on substrate 113. In some embodiments, the power terminal pads 105 on the top surface 107 are coupled to either a positive or negative voltage rail on substrate 113, and the power terminals 105 on the bottom surfaces 110 of dies 401a, 401b, and 401c are coupled to a ground rail on substrate 113.

[0050] Figure 5 Flowchart 500 is shown, which describes a process flow for assembling a die stack with DLDAF according to some embodiments of the present disclosure.

[0051] exist Figure 5 The diagram illustrates several steps for assembling a die stack including a DLDAF (102) or a TLDAF (300). At operation 501, the uniform die is received and transferred to a front-end process (FOL) package assembly. In some embodiments, the die has power terminal pads and relay pads on one side. In other embodiments, the die has power terminal pads and relay pads on both sides.

[0052] At operation 502, die stack formation begins with substrate preparation. The substrate on which the die stack is to be assembled undergoes a pre-baking step. In some embodiments, a polymer film is used as the substrate. In other embodiments, an epoxy resin material is used as the substrate. In some embodiments, the pre-baking step is used to cure the substrate material.

[0053] At operation 503, the die stack is assembled. In some embodiments, the stack is assembled using a tile-like construction. In some embodiments, the stack is assembled using a straight-up construction. Die attachment is performed using DLDAF for single-sided dies or TLDAF for double-sided dies. In some embodiments, the DLDAF or TLDAF is partially cured to remain malleable, thereby maintaining a degree of tack for adhesion to the die surface. Die attachment can be facilitated using pick-and-place techniques. However, other die stack assembly methods can be used to construct the die stack. In some embodiments, the bottom die of the stack is a single-sided die and is attached to the substrate using a standard (non-conductive monolayer) DAF. The bottom side of the single-sided die is inactive and not metallized. A conventional die attachment film can be used to anchor the first die to the substrate.

[0054] In some embodiments, the bottom die of the stack is a double-sided die. In some embodiments, the bottom die is metallized. In some embodiments, power terminal pads and relay pads are distributed on the bottom surface of the die. In some embodiments, DLDAF attaches the die to a substrate, wherein a conductive adhesive layer of DLDAF is attached to the bottom side of the die. A non-conductive adhesive layer of DLDAF is attached to the substrate.

[0055] Returning to operation 503, dies are added to the stack as follows: DLDAF or TLDAF die attachment films are alternately and continuously disposed onto the topmost die, and then the die is placed onto the die attachment films. In some embodiments, the DLDAF or TLDAF layer is attached to the top surface of the bottommost die of the stack. The choice of DLDAF or TLDAF depends on the stack architecture. In some embodiments, the die stack consists entirely of single-sided dies. In some embodiments, the die stack consists entirely of double-sided dies. In some embodiments, the die stack consists of some single-sided dies and some double-sided dies.

[0056] A single-sided die is placed on a grown die stack with its bottom side (which is an inactive surface without metallization) exposed above the metallized surface of the adjacent die, either on one or both sides. In some embodiments, the bottom side of the single-sided die comprises a semiconductor material and is conductive. In some embodiments, the die stack is assembled by first placing a layer of DLDAF on top of the top die of the die stack with its conductive adhesive layer facing down, and then placing the single-sided die on the non-conductive adhesive layer of the DLDAF layer.

[0057] Bilateral dies are placed on the grown die stack so that their bottom sides (which are the metallized die surfaces) are exposed above the metallized die surfaces of the adjacent dies below in the vertical stack. In some embodiments, the die stack is assembled by first placing a TLDAF layer on the top die, and then placing the bilateral dies on the grown stack.

[0058] At the end of the assembly process, according to some embodiments, a spacer die is placed above the topmost active die in the die stack. In some embodiments, a layer of DLDAF with a conductive adhesive layer on the bottom side is placed above the top surface of the topmost die in the die stack. The conductive adhesive layer covers and adheres to the top surface metallization (e.g., power terminal pads and relay pads). A non-conductive adhesive layer adheres to the spacer die above. At this point, the die stack assembly is complete.

[0059] Now for reference Figure 5Operation 504 involves curing the die attachment film (e.g., DLDAF and / or TLDAF) at a high temperature for final curing. In some embodiments, the curing step is performed at 60°C–70°C. In other embodiments, the curing step is performed at 75°C–80°C (time). During curing, the die attachment film hardens to form a rigid layer, thereby bonding the dies in the die stack to a specific configuration (tile or straight-up).

[0060] At operation 505, wire bonding is performed, wherein wires are bonded to wire bonding pads on the bonding edge of the die in the die stack (e.g., Figure 1A The 108 is a junction finger disposed on the packaging substrate. In some embodiments, the die stack is constructed as a tile structure, and wire bonding is performed after operation 504 (curing the die attachment film). In some embodiments, the die stack is constructed as a straight-up structure. In some embodiments, wire bonding is performed after each die is attached to the grown straight-up die stack. Wire bonding can be performed using standard wire bonding methods.

[0061] Figures 6A-6F A cross-sectional view is shown of an exemplary method for assembling a tile core stack 200a according to some embodiments.

[0062] exist Figure 6A In this process, the assembly of the die stack 200a begins with attaching die 101a to substrate 113. In some embodiments, die 101a is a single-sided die, as shown in the figure. In some embodiments, in process flow 500 ( Figure 5 In operation 502, substrate 113 is prepared. Die 101a is attached to substrate 113 by any number of suitable methods. In some embodiments, die 101 is attached using a die attachment film. In some embodiments, the die attachment film is a standard single-layer insulating adhesive film. In some embodiments, die 101a is a double-sided die attached to substrate 113 by a layer of DLDAF.

[0063] exist Figure 6B In this process, the first layer of DLDAF 102a is attached to the die 101a using an upward-facing non-conductive layer 103. Because the stack is constructed as tiles, DLDAF 102a is offset relative to the die 101a in the x-axis. A conductive adhesive layer 104 covers the power terminal pads 105 and relay pads 106. Figure 6C In this process, the second die 101b is attached to the DLDAF 102a. Attachment can be accomplished using a pick-and-place technique. According to some embodiments, die 101b is attached to a non-conductive adhesive layer 103 with its edges aligned. In some embodiments, the die stack 200a is assembled as a straight-up die stack, for example... Figure 2BAs shown, edge 112 is aligned.

[0064] exist Figure 6D In the middle, Figure 6B and Figure 6C The illustrated operations are repeated twice, each time resulting in the structure shown in the figure. In some embodiments, dies 101b and 101c are added alternately and sequentially with DPDAF layers 102b and 102c, and offset in the x-axis. The non-conductive adhesive layer 103 of DPDAF layer 102c is exposed. Figure 6E In some embodiments, spacer dies 201 are attached to the DPDAF layer 102c to cap the die stack 200a. Spacer dies 210 are attached to a non-conductive adhesive layer 103 of the DPDAF layer 102c. In some embodiments, spacer dies 201 are omitted. In some embodiments, a curing operation (not shown) may be performed after the die stack assembly to cure the DPDAF, thereby obtaining a rigid die stack.

[0065] exist Figure 6F In this process, after assembling the die stack 200a, leads 202 are bonded to bonding pads 108. Lead bonding can be performed after any number of curing steps using various techniques. In some embodiments, on substrate 113, leads are ball-bonded to die bonding pads (108) and stitch-bonded to bonding fingers (114). In some embodiments, leads are bonded to each die during the construction of the die stack 200a.

[0066] Figure 7 The illustration shows a portion of a system-on-a-chip (SoC) package in an embodiment of computing device 700 according to some embodiments of the present disclosure, having an SCSP package having a DLDAF or TLDAF connecting multiple dies in a vertical die stack.

[0067] Figure 7 A block diagram illustrating an embodiment of a mobile device that can use a flat surface interface connector is shown. In some embodiments, computing device 700 represents a mobile computing device, such as a tablet device, a mobile phone or smartphone, a wirelessly capable e-reader, or other wireless mobile device. It should be understood that specific components are shown generally, and not all components of such a device are shown in computing device 700.

[0068] In some embodiments, computing device 700 includes a first processor 710. Various embodiments of this disclosure may also include a network interface, such as a wireless interface, within 770, thereby enabling the system embodiments to be integrated into wireless devices such as cellular phones or personal digital assistants.

[0069] In one embodiment, processor 710 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing device. Processing operations performed by processor 710 include executing an operating platform or operating system, and executing application and / or device functions on the operating platform or operating system. Processing operations include operations related to I / O (input / output) with human users or other devices, operations related to power management, and / or operations related to connecting computing device 700 to another device. Processing operations may also include operations related to radio I / O and / or display I / O.

[0070] In one embodiment, computing device 700 includes an audio subsystem 720, which represents hardware components (e.g., audio hardware and audio circuitry) and software components (e.g., drivers, codecs) associated with providing audio functionality to the computing device. Audio functionality may include speaker and / or headphone outputs, and microphone inputs. Devices for such functionality may be integrated into or connected to computing device 700. In one embodiment, a user interacts with computing device 700 by providing audio commands received and processed by processor 710.

[0071] Display subsystem 730 represents hardware components (e.g., display devices) and software components (e.g., drivers) that provide visual and / or tactile displays for user interaction with computing device 700. Display subsystem 730 includes display interface 732, which includes a specific screen or hardware device for providing a display to the user. In one embodiment, display interface 732 includes logic that performs at least some display-related processing independently of processor 710. In one embodiment, display subsystem 730 includes a touchscreen (or touchpad) device that provides input and output to the user.

[0072] I / O controller 740 represents hardware devices and software components related to user interaction. I / O controller 740 is operable to manage hardware that is part of audio subsystem 720 and / or display subsystem 730. Furthermore, I / O controller 740 illustrates connection points for attached devices that connect to computing device 700, enabling user interaction with the system. For example, devices that can be attached to computing device 700 may include microphone devices, speakers or stereo systems, video systems or other display devices, keyboards or keypad devices, or other application-specific I / O devices such as card readers or other devices.

[0073] As described above, the I / O controller 740 can interact with the audio subsystem 720 and / or the display subsystem 730. For example, input via a microphone or other audio device can provide input or commands to one or more applications or functions of the computing device 700. Furthermore, audio output can be provided as an alternative to or supplement to display output. In another example, if the display subsystem 730 includes a touchscreen, the display device also acts as an input device, which can be managed at least partially by the I / O controller 740. Additional buttons or switches may also be present on the computing device 700 to provide I / O functions managed by the I / O controller 740.

[0074] In one embodiment, the I / O controller 740 manages devices such as accelerometers, cameras, light sensors, or other environmental sensors, or other hardware that may be included in the computing device 700. Inputs may be part of direct user interaction, as well as providing environmental inputs to the system to affect its operation (e.g., filtering noise, adjusting the display for brightness detection, applying a flash to a camera, or other features).

[0075] In one embodiment, computing device 700 includes power management 750, which manages battery power usage, battery charging, and features related to power-saving operation. Memory subsystem 760 includes memory means for storing information in computing device 700. The memory may include non-volatile (its state does not change if power to the memory means is interrupted) and / or volatile (its state is uncertain if power to the memory means is interrupted) memory means. Memory subsystem 760 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to performing applications and functions of computing device 700.

[0076] Elements in the various embodiments are also provided as machine-readable media (e.g., memory 760) for storing computer-executable instructions. Machine-readable media (e.g., memory 760) may include, but are not limited to, flash memory, optical disc, CD-ROM, DVD-ROM, RAM, EPROM, EEPROM, magnetic or optical cards, phase-change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of this disclosure can be downloaded as a computer program (e.g., BIOS) that can be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a communication link (e.g., a modem or network connection) through data signals.

[0077] The connection via network interface 770 includes hardware devices (e.g., wireless and / or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable computing device 700 to communicate with external devices. Computing device 700 can be a standalone device, such as other computing devices, wireless access points or base stations, and peripherals or other devices such as headsets, printers, etc.

[0078] Network interface 770 may include various different types of connections. For general purposes, computing device 700 is illustrated as having cellular connection 772 and wireless connection 774. Cellular connection 772 generally refers to a cellular network connection provided by a wireless operator, such as via GSM (Global System for Mobile Communications) or its variants or derivatives, CDMA (Code Division Multiple Access) or its variants or derivatives, TDM (Time Division Multiplexing) or its variants or derivatives, or other cellular service standards. Wireless connection (or wireless interface) 774 refers to a non-cellular wireless connection and may include personal area networks (e.g., Bluetooth, NFC, etc.), local area networks (e.g., Wi-Fi), and / or wide area networks (e.g., WiMax) or other wireless communications.

[0079] Peripheral connection 780 includes hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to form the peripheral connection. It should be understood that computing device 700 can be either a peripheral device leading to other computing devices (“to” 782) or has peripheral devices connected to it (“from” 784). Computing device 700 typically has a “dock” connector for connecting to other computing devices for managing (e.g., downloading and / or uploading, modifying, synchronizing) content on computing device 700. Furthermore, the dock connector can allow computing device 700 to connect to specific peripheral devices, allowing computing device 700 to control content, for example, output to audio / video or other systems.

[0080] In addition to proprietary docking connectors or other proprietary connection hardware, computing device 700 can form peripheral connections 780 via general-purpose or standards-based connectors. General-purpose types may include Universal Serial Bus (USB) connectors (which may include any of several different hardware interfaces), display ports including Mini DisplayPort (MDP), High Definition Multimedia Interface (HDMI), FireWire, or other types.

[0081] In this specification, references to "embodiment," "one embodiment," "some embodiments," or "other embodiments" indicate that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least some embodiments, but not necessarily in all embodiments. The appearance of "embodiment," "one embodiment," or "some embodiments" in various places does not necessarily refer to the same embodiment. If the specification indicates that a component, feature, structure, or characteristic "may," "may," or "can" be included, it does not require that particular component, feature, structure, or characteristic be included. If the specification or claims refer to an element "a," it does not mean that there is only one element. If the specification or claims refer to an "additional" element, it does not exclude the existence of more than one additional element.

[0082] Furthermore, specific features, structures, functions, or characteristics can be combined in one or more embodiments in any suitable manner. For example, a first embodiment can be combined with a second embodiment, provided that the specific features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0083] Although this disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of such embodiments will be apparent to those skilled in the art in light of the foregoing description. The embodiments of this disclosure are intended to cover all such alternatives, modifications, and variations falling within the broad scope of the appended claims.

[0084] Furthermore, for the sake of simplicity of illustration and discussion, well-known power / ground connections to integrated circuit (IC) chips and other components may be shown or omitted in the presented figures to avoid obscuring the present disclosure. Additionally, arrangements may be shown in block diagram form to avoid obscuring the present disclosure, and it is also considered that the specific details of embodiments with respect to such block diagram arrangements are highly dependent on the platform on which the present disclosure is to be implemented (i.e., such specific details should be within the knowledge of those skilled in the art). While specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present disclosure, it will be apparent to those skilled in the art that the present disclosure can be practiced without these specific details or with variations thereof. Therefore, the description is to be regarded as exemplary rather than restrictive.

[0085] The following examples relate to other embodiments. Details from the examples may be used anywhere in one or more embodiments. All optional features of the device described herein may also be implemented with respect to a method or process.

[0086] Example 1 is an apparatus comprising: a die stack including at least one die pair having a first die above a second die, both the first die and the second die having a first surface and a second surface, the second surface of the first die being above the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair, wherein the adhesive film includes an insulating layer and a conductive layer, the insulating layer being adhered to the second surface of the first die and the conductive layer being adhered to the first surface of the second die.

[0087] Example 2 includes all the features of Example 1, wherein one or more electrical contact pads are on the first surface of the first die and the first surface of the second die, and wherein at least a portion of the one or more electrical contact pads is electrically coupled through a conductive layer of the adhesive film.

[0088] Example 3 includes all the features of Example 2, wherein one or more contact pads on the first surface of the first die and the first surface of the second die include at least one power terminal and at least one edge bonding pad.

[0089] Example 4 includes all the features of Example 3, wherein the distance between at least one power terminal and at least one edge bonding pad of the first die is within a range of one-third of the length of the first die and the length of the first die.

[0090] Example 5 includes all the features of Example 3, wherein the distance between at least one power terminal and at least one edge bonding pad of the second die is within one-third of the length of the second die and the length of the second die.

[0091] Example 6 includes all the features of Example 3, wherein one or more contact pads on the first surface of the first die and the first surface of the second die include at least one relay contact coupled to at least one edge-joining pad by a metal interconnect, and at least one power terminal is coupled to at least one relay contact via a conductive adhesive layer.

[0092] Example 7 includes all the features of Example 1, wherein the adhesive film includes an insulating layer between a first conductive adhesive layer and a second conductive adhesive layer.

[0093] Example 8 includes all the features of Example 7, wherein a first conductive adhesive layer is adhered to a second surface of a first die, and a second conductive adhesive layer is adhered to a first surface of a second die.

[0094] Example 9 includes all the features of Example 8, wherein one or more contact pads are on a second surface of a first die and a first surface of a second die, and wherein at least a portion of one or more contact pads on the second surface of the first die is electrically coupled by a first conductive adhesive layer, and at least a portion of one or more contact pads on the first surface of the second die is electrically coupled by a second conductive adhesive layer.

[0095] Example 10 includes all the features of Example 9, wherein one or more contact pads on the second surface of the first die include at least one power terminal.

[0096] Example 11 includes all the features of Example 9, wherein one or more contact pads on the first surface of the second die include at least one power terminal.

[0097] Example 12 includes all the features of Example 10 or 11, wherein one or more contact pads include at least one relay contact coupled to an edge-joining pad by a metal interconnect, and at least one power terminal is coupled to at least one relay contact via a conductive adhesive layer.

[0098] Example 13 includes all the features of Example 10 or 11, wherein the distance between at least one power terminal of the first die and the engagement edge is within a range of one-third of the length of the first die and the length of the first die.

[0099] Example 14 includes all the features of Example 10 or 11, wherein the distance between at least one power terminal and the engagement edge of the second die is within one-third of the length of the second die and the length of the second die.

[0100] Example 15 includes all the features of Example 1, wherein the adhesive film is a laminate comprising an insulating layer and at least one conductive layer.

[0101] Example 16 includes all the features of any of Examples 1 to 15, wherein one or more edges of the first die and the second die are offset laterally.

[0102] Example 17 includes all the features of any of Examples 1 to 15, wherein the edges of the first die and the second die are aligned.

[0103] Example 18 includes all the features of any of Examples 1 to 15, wherein the die stack body includes a spacer die above the first die of at least one die pair.

[0104] Example 19 is a system comprising: a memory, a processor coupled to the memory, and a device comprising: at least one die pair having a first die above a second die, both the first and second dies having a first surface and a second surface, the second surface of the first die being above the first surface of the second die; and an adhesive film between the first and second dies of the at least one die pair, wherein the adhesive film comprises an insulating layer adhered to the second surface of the first die and a conductive layer adhered to the first surface of the second die.

[0105] Example 20 includes all the features of Example 19, wherein one or more electrical contact pads are on the first surface of a first die and the first surface of a second die, and wherein at least a portion of one or more electrical contact pads is electrically coupled through a conductive layer of an adhesive film.

[0106] Example 21 includes all the features of Example 20, wherein one or more contact pads on the first surface of the first die and the first surface of the second die include at least one power terminal and at least one edge bonding pad.

[0107] Example 22 includes all the features of Example 21, wherein the distance between at least one power terminal of the first die and the edge of the bonding pad is within a range of one-third of the length of the first die and the length of the first die.

[0108] Example 23 includes all the features of Example 21, wherein the distance between at least one power terminal of the second die and the edge of the bonding pad is within one-third of the length of the second die and the length of the second die.

[0109] Example 24 includes all the features of any of Examples 20 to 23, wherein one or more contact pads on the first surface of the first die and the first surface of the second die include at least one relay contact coupled to at least one edge-joining pad by an interconnect, and at least one power terminal is coupled to at least one relay contact via a conductive adhesive layer.

[0110] Example 25 is a method comprising: receiving a first die having a first surface and a second surface; attaching a first adhesive film having an insulating layer and a conductive layer to the first die, wherein the conductive layer is attached to the first surface of the first die; receiving a second die having a first surface and a second surface; attaching a second adhesive film having an insulating layer and a conductive layer to the second die, wherein the conductive layer is attached to the first surface of the second die; and attaching the second surface of the second die to the insulating layer of the first adhesive film attached to the first die.

[0111] Example 26 includes all the features of Example 25, and further includes: receiving a spacer die having a first surface and a second surface, attaching the spacer die to an insulating layer of a second adhesive film, and curing the first adhesive film and the second adhesive film.

[0112] Example 27 includes all the features of Example 25 or 26, wherein receiving the first die includes receiving a first die attached to the substrate.

[0113] Example 28 includes all the features of Example 25, wherein receiving a first die having a first surface and a second surface includes receiving a first die having one or more power terminals disposed on the first surface.

[0114] Example 29 includes all the features of Example 28, wherein attaching a first film having an insulating layer and a conductive layer to a first die includes adhering the conductive layer of the first adhesive film to one or more power terminals disposed on a first surface of the first die.

[0115] Example 30 includes all the features of Example 25, wherein receiving a second die having a first surface and a second surface includes receiving a second die having one or more power terminals disposed on the first surface.

[0116] Example 31 includes all the features of Example 30, wherein a second adhesive film having an insulating layer is attached to one or more power terminals disposed on a first surface of the second die.

[0117] An abstract is provided to allow the reader to determine the nature and substance of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are incorporated herein by reference, wherein each claim represents a separate embodiment.

Claims

1. An IC package, comprising: A die stack comprising at least one die pair having a first die above a second die, the first die and the second die both having a first surface opposite to and parallel to a second surface, the second surface of the first die being above the first surface of the second die; A film comprising an adhesive material, wherein the film is disposed between the first and second dies of the at least one die pair; and One or more first electrical contact pads on the first surface of the second die, the one or more first electrical contact pads including at least one power terminal and at least one edge bonding pad, The membrane comprises an insulating layer and a conductive layer. The insulating layer is adhered to the second surface of the first die, and the conductive layer is directly adhered to the first surface of the second die. In this embodiment, at least a portion of the one or more first electrical contact pads are electrically coupled through the conductive layer of the film.

2. The IC package of claim 1, comprising one or more first electrical contact pads on the first surface of the first die, wherein, At least a portion of the one or more first electrical contact pads are electrically coupled through the conductive layer of the film.

3. The IC package according to claim 2, wherein, The one or more first electrical contact pads on the first surface of the first die include at least one power terminal and at least one edge bonding pad.

4. The IC package according to claim 3, wherein, The at least one power terminal and the at least one edge bonding pad of the first die are separated by a first distance, wherein the first distance is within the range of one-third of the length of the first die to the length of the first die.

5. The IC package according to claim 3, wherein, The at least one power terminal and the at least one edge bonding pad of the second die are separated by a second distance, wherein the second distance is within the range of one-third of the length of the second die to the length of the second die.

6. The IC package according to claim 3, wherein, The one or more first electrical contact pads on the first surface of the first die and the first surface of the second die include at least one relay contact coupled to the at least one edge bonding pad by a metal interconnect, and the at least one power terminal is coupled to the at least one relay contact through the conductive adhesive layer.

7. The IC package according to claim 1, wherein, The insulating layer is located between the first conductive adhesive layer and the second conductive adhesive layer.

8. The IC package according to claim 7, wherein, The first conductive adhesive layer adheres to the second surface of the first die, and the second conductive adhesive layer adheres to the first surface of the second die.

9. The IC package of claim 8, comprising one or more second electrical contacts on the second surface of the first die and on the first surface of the second die, wherein, At least a portion of the one or more second electrical contact pads on the second surface of the first die is electrically coupled by the first conductive adhesive layer, and at least a portion of the one or more second electrical contact pads on the first surface of the second die is electrically coupled by the second conductive adhesive layer.

10. The IC package according to claim 9, wherein, The one or more second electrical contact pads on the second surface of the first die include at least one power terminal.

11. The IC package according to claim 9, wherein, The one or more second electrical contact pads on the first surface of the second die include at least one power terminal.

12. The IC package according to any one of claim 10 or 11, wherein, The one or more second electrical contact pads include at least one relay contact coupled to the edge bonding pad by a metal interconnect, and the at least one power terminal is coupled to the at least one relay contact through the conductive adhesive layer.

13. The IC package according to any one of claim 10 or 11, wherein, The distance between the at least one power terminal and the engagement edge of the first die is within the range of one-third of the length of the first die and the length of the first die.

14. The IC package according to any one of claim 10 or 11, wherein, The distance between the at least one power terminal and the engagement edge of the second die is within the range of one-third of the length of the second die and the length of the second die.

15. The IC package according to any one of claims 1 to 11, wherein, One or more edges of the first die and the second die are offset laterally.

16. The IC package according to any one of claims 1 to 11, wherein, The edges of the first die and the second die are aligned.

17. The IC package according to any one of claims 1 to 11, wherein, The die stack includes a spacer die above the first die of the at least one die pair.

18. A system comprising: Package, including: A die stack comprising at least one die pair having a processor on top of a memory, the processor and the memory both having a first surface opposite to and parallel to a second surface, the second surface of the processor being on top of the first surface of the memory; A film comprising an adhesive material, wherein the film is situated between the processor and the memory of the at least one die pair; and One or more electrical contact pads on the first surface of the memory, the one or more first electrical contact pads including at least one power terminal and at least one edge bonding pad, The film includes an insulating layer and a conductive layer, the insulating layer being adhered to the second surface of the processor, and the conductive layer being directly adhered to the first surface of the memory, wherein at least a portion of the one or more electrical contact pads is electrically coupled through the conductive layer of the film; and A wireless interface is communicatively coupled to the package, the wireless interface being used to allow the processor to communicate with another device.

19. The system according to claim 18, wherein, One or more electrical contact pads are on the first surface of the processor, and wherein at least a portion of the one or more electrical contact pads are electrically coupled through the conductive layer of the film.

20. A method for manufacturing an IC package, comprising: A first die having a first surface and a second surface is received, wherein the first die has one or more first electrical contact pads disposed on the first surface, the one or more first electrical contact pads including at least one power terminal and at least one edge bonding pad; A first film having an insulating layer and a conductive layer is attached to the first die, wherein the conductive layer is attached to the first surface of the first die, and wherein at least a portion of the one or more first electrical contact pads are electrically coupled through the conductive layer. Receive a second die having a first surface and a second surface; A second film having an insulating layer and a conductive layer is attached to the second die, wherein the conductive layer is attached to the first surface of the second die; and The second surface of the second die is attached to the insulating layer of the first membrane attached to the first die.

21. The method for manufacturing an IC package according to claim 20, further comprising: Receive a spacer die having a first surface and a second surface; The spacer core is attached to the insulating layer of the second membrane; as well as The first membrane and the second membrane are solidified.

22. The method for manufacturing an IC package according to claim 20, wherein, Receiving the second die includes receiving a second die having one or more power terminals disposed on the first surface.

23. The method for manufacturing an IC package according to claim 22, wherein, Attaching the second membrane includes adhering the conductive layer of the second membrane to one or more power terminals disposed on the first surface of the second die.

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