Semiconductor device and method of making chip scale package

Abstract

A semiconductor device and a method of making a chip scale package. The semiconductor device has a semiconductor wafer. A trench is formed through the active surface of the semiconductor wafer between the first semiconductor die and the second semiconductor die. An encapsulant is deposited in the trench. A back surface of the semiconductor wafer opposite the active surface is back-ground using a coarse grinder to expose the encapsulant. The back surface of the semiconductor wafer is back-ground using a fine grinder. A fine grinder removes approximately 20 [mu] m thicknesses from the semiconductor wafer. Back-end fabrication is performed on the wafer after depositing the encapsulant and before back face grinding using the coarse grinder.

Description

Technical Field

[0001] This invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods for fabricating chip-scale packages. Background Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and creating visual images for television displays. Semiconductor devices are found in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0003] Semiconductor device manufacturers are constantly striving to create smaller semiconductor devices to meet the needs of both electronics manufacturers and consumers. At the same time, device manufacturers are demanding increasingly complex semiconductor devices. Chip-scale packaging (CSM) has a remarkably small structural size, making the final package almost no larger than the packaged semiconductor die. However, as chips become thinner and smaller, CSM methods and structures require technological advancements to keep pace.

[0004] Semiconductor devices are typically manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional electrical circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, create the voltage and current relationships necessary for the electrical circuit to function.

[0005] Back-end manufacturing refers to the process of cutting or isolating finished wafers into individual semiconductor dies and packaging these dies for structural support, electrical interconnection, and environmental isolation. Figure 1a A semiconductor wafer 100 is shown, having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials for structural support. A plurality of semiconductor dies 104 are formed on the wafer 100, separated by non-active, inter-die wafer regions or saw tracks 106. The saw tracks 106 provide dicing areas to individualize the semiconductor wafer 100 into individual bridging dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0006] Figure 1bA cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back surface or passive surface 108 and an active surface 110, which includes analog or digital circuitry implemented as formed on or within the die and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), memory, power devices, or other signal processing circuitry. The semiconductor die 104 may also include IPDs, such as inductors, capacitors, and resistors, for RF signal processing.

[0007] A conductive layer 112 is formed on the active surface 110 using a suitable metal deposition process. The conductive layer 112 functions as contact pads electrically connected to circuitry on the active surface 110. In other embodiments, Figures 1a-1c The wafer 100 has been fabricated via front-end development but not via back-end development. Therefore, the wafer will have already been doped to form different regions of transistors and other active components, but when... Figure 1c When the wafer is monomerized, no conductive layer may be formed on the wafer.

[0008] exist Figure 1c In this process, a saw blade or laser cutting tool 118 is used to monomerize the semiconductor wafer 100 into individual semiconductor dies 104 through the saw path 106. The individual semiconductor dies 104 can be inspected and electrically tested to identify known good dies (KGD) or known good cells (KGU) after monomerization.

[0009] Figures 1d-1j The illustration shows a common method for chip-level packaging of semiconductor die 104 in the prior art. Figure 1d This illustrates how, after monomerization, individual semiconductor dies 104 are flipped and individually mounted onto a back-side polished tape or other carrier 120. The semiconductor die 104 is placed on the carrier 120 with the active surface 110 oriented toward the carrier. A sealant 130 is deposited on... Figure 1e On top of the semiconductor die. Sealant 130 is completely deposited on and covers the back surface 108 of each semiconductor die 104. The combination of sealant 130 and semiconductor die 104 is referred to as reconstructed wafer 132 because, in a sense, wafer 100 has been reconstructed into wafer 132, wherein sealant 130 connects the semiconductor die to the saw groove 106 instead of the original wafer material.

[0010] With the sealant 130 deposited, the carrier 120 is removed and back-end fabrication occurs on the reconstructed wafer 132. Figure 1f In the back-end fabrication, a stacked interconnect structure 140 has been formed on the active surface 110 of the semiconductor die 104. The interconnect structure 140 includes one or more insulating layers 142 interleaved with one or more conductive layers 144. The conductive layers 144 are formed and patterned to physically and electrically connect to contact pads 112, or to provide ohmic contacts to doped semiconductor regions, and then fan out electrical signals to solder bumps 146. Solder bumps 146 are formed on the contact pads or UBMs of the top conductive layer 144.

[0011] After the back-end manufacturing is completed, an important chip-level packaging step is to thin and reconstruct the wafer 132 for final packaging. Figure 1g The illustration shows a polishing machine 150 for removing the top portion of sealant 130 downwards to the back surface 108 of a semiconductor die 104, where line 152 is positioned. In some cases, such as Figure 1h As shown, grinding of line 152 is sufficient for forming a package. In other cases, grinding continues to remove portions of both the sealant 130 and the semiconductor die 104 down to, for example, line 156. Figure 1i As shown in the image.

[0012] Reconstructing chip 132 in Figure 1j The semiconductor die 104 is monolithically isolated to separate each semiconductor die 104 into its own chip-scale package 160. Current requirements are driving increasingly thinner packages, thus necessitating thinning of the back surface of the semiconductor die 104 more towards the active surface 110. However, back-grinding such thin dies presents significant problems. A coarse grinder 150 is typically used to quickly remove the sealant 130. Unfortunately, the coarse grinder 150 can create scratches and damage the semiconductor die 104. Using a fine grinder 150, which is less likely to scratch and damage the semiconductor die 104, slows manufacturing output to a point where the solution cannot be sustained. Therefore, there is a need for improved chip-scale packaging methods and structures. Attached Figure Description

[0013] Figures 1a-1j The illustration shows how to form a chip-level package in the prior art; Figures 2a-2l The diagram illustrates an improved method for forming a chip-scale package; and Figure 3a and Figure 3b The illustration shows an electronic device with chip-level packaging. Detailed Implementation

[0014] In the following description, the invention is described in one or more embodiments with reference to the figures, wherein similar reference numerals denote the same or similar elements. While the invention is described with respect to the best mode for carrying out its objectives, those skilled in the art will appreciate that it is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and the figures. Features shown in the figures are not necessarily drawn to scale. Elements assigned the same reference numerals in the figures have similar functions and descriptions to each other. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word, and therefore can refer to both a single semiconductor device and multiple semiconductor devices.

[0015] Figures 2a-2l This demonstrates the use of an improved process to form a chip-level package. Figure 2a Another cross-section of the semiconductor wafer 100 is shown, wherein the active surface 110 is oriented upwards or otherwise available for processing. As described above, the semiconductor wafer 100 may have only undergone front-end fabrication, such as doping of different active regions, without any conductive layer formed on the active surface 110. In this case, Figure 2a The contact pads 112 illustrated herein will actually be, or represent, areas of semiconductor material in which ohmic contacts will be made by conductive layers during back-end manufacturing. Except for the absence of a conductive layer on the active surface 110, wafers 100 in this state typically have only a single passivation layer formed on the active surface for protection, for example, by thermal oxidation, after front-end manufacturing is complete. In other embodiments, in Figure 2a Prior to the stage illustrated in the figure, some conductive and insulating layers have been built on the semiconductor wafer 100, and metal contact pads 112 are exposed at the active surface 110. Figure 2a It shows Figure 1b Some wasted space 180 around the outer side of the chip 100 (not shown in the figure).

[0016] exist Figure 2b In this process, a saw blade 202 or other suitable tool is used to form a trench 200 in the saw path 106 into the active surface 110 of the semiconductor wafer 100. The trench 200 is formed around each side of the semiconductor die 104, including in a space 180 around the outer side of the wafer 100. Figure 2cA plan view is shown in which each semiconductor die 104 is surrounded by a trench 200. In one embodiment, the trench 200 is formed to a depth from the active surface 110 into the wafer 100 that exceeds the desired final wafer thickness by 20 micrometers (μm) or approximately 20 μm after back-side grinding. In one example, the wafer 100 has a thickness of 750 μm, which is the thickness measured perpendicularly from the back surface 108 to the active surface 110, and the desired final thickness of the semiconductor die 104 after back-side grinding is 70 μm. In this example, the trench 200 is formed to a depth of 90 μm measured perpendicularly from the active surface 110 to the bottom of the trench. The +20 μm design rule can be applied to any desired final thickness and any starting wafer thickness.

[0017] exist Figure 2d In this process, wafer 100 is laminated onto thermal release tape 210 or other similar removable support structure and positioned within mold 212. Mold 212 includes a bottom chase 212a and a top chase 212b. As indicated by arrow 222, sealant 220 or other molding compound is inserted into the opening to fill trench 200. Release tape 210 is directly attached to active surface 110 such that sealant 220 fills only trench 200 without extending onto or above active surface 110.

[0018] In some embodiments, sealant 220 is deposited to fill trench 200 using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or another suitable applicator. Sealant 220 may be a liquid or granular polymer composite, such as an epoxy resin, epoxy acrylate, or polymer with or without added filler. In another embodiment, sealant 220 is a laminated die sheet or film with or without filler. Sealant 220 is non-conductive, provides structural support, and environmentally protects semiconductor die 104 from external components and contaminants. Sealant 220 may also be any material and is generally formed using any of the methods discussed below for insulating layers.

[0019] exist Figure 2e In this process, wafer 100 is removed from mold 212 and oriented with active surface 110 facing upwards or otherwise available for back-end processing. The heat release layer 210 has been removed via a suitable release mechanism.

[0020] exist Figure 2f In the process, backend processing is performed to create stacked interconnect structure 240. The interconnect structure 240, referred to as a stacked interconnect structure, refers to the method of forming an interconnect structure by continuously building insulating and conductive layers on the semiconductor wafer 100 until the desired signal routing is achieved.

[0021] The formation of interconnect structure 240 begins with the formation of an insulating layer 242a on wafer 100 and sealant 220. Insulating layer 242a comprises one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide (PI), photosensitive polyimide (PSPI), benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. Insulating layer 242a can be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), printing, lamination, spin coating, spraying, sintering, or thermal oxidation.

[0022] Any insulating layer, passivation layer, dielectric layer, or sealant mentioned above or below can be formed using any material or method described for insulating layer 242a. An opening is formed from the front-end fabrication through insulating layer 242a and any passivation layer on active surface 110 to expose the ohmic contacts or contact pads 112 of semiconductor die 104. The opening can be formed by chemical etching, photolithography, mechanical drilling, laser drilling, or any other suitable means. In some embodiments, a conductive layer is first formed on wafer 100, and then insulating layer 242a is formed. Where wafer 100 already has a passivation layer formed on active surface 110 for protection after front-end fabrication, said passivation layer can be used as a first insulating layer for the stacked interconnect structure 240.

[0023] A conductive layer 244a is formed on an insulating layer 242a and is physically and electrically coupled to contact pads 112 or active surfaces 110 through openings in the insulating layer. The conductive layer 244a includes conductive traces fan-out or fan-in from the semiconductor die 104, and contact pads optionally at both ends of the traces for connection to contacts in the underlying layer and for subsequent formation of the overlying conductive structure. The conductive layer 244a is formed using PVD, CVD, electroplating, electroless plating, sputtering, or other suitable metal deposition processes. The conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. Any conductive layer described above or below can be formed using the same materials and methods described for the conductive layer 244a.

[0024] Additional conductive layers 244 and insulating layers 242 are interleaved on wafer 100 as needed to achieve desired electrical signal routing. In the illustrated embodiment, two conductive layers 244a and 244b are formed for signal routing, wherein two insulating layers 242a and 242b are formed to support the conductive layers, respectively. Each successive conductive layer 244 is formed through an opening in the underlying insulating layer 242 to be vertically electrically connected via a stacked interconnect structure 240. Any suitable number of insulating and conductive layers can be used to achieve the desired signal routing.

[0025] After the desired number of conductive layers 244 and insulating layers 242 have been constructed, contact pads or under-bump metallization (UBM) pads are optionally formed on the top conductive layer 244. The UBM pads are optionally formed from multiple conductive layers including a wetting layer, a barrier layer, and an adhesion layer. A passivation or solder mask layer 246 is optionally formed over the top contact pads or UBM layer. The passivation layer 246 is generally formed from a material using the method described above for the insulating layer. Openings are formed in the passivation layer 246 to expose the contact pads or UBM pads for subsequent electrical interconnection. The UBM pads may have a flat top surface as illustrated, or they may be conformally formed in the openings of the passivation layer 246 or the top insulating layer 242.

[0026] In some embodiments, after formation and before forming the next successive layer, each insulating layer 242 and conductive layer 244 is etched to completely remove over the trench 200, sealant 220, and serration 106. Removing the layers between the semiconductor dies 104 during individual layer formation reduces manufacturing cost and complexity compared to monomerizing the interconnect structure 240 with the wafer 100 at a later step. The interconnect structure 240 will not be formed over the serration, so the final monomerization step will only need to cut through the sealant 220.

[0027] Conductive bump material is deposited on the top conductive layer 244 or overlying UBM using evaporation, electrolytic plating, electroless plating, droplet coating, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, with optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer 244b using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed to form balls or bumps 250 by heating the material above its melting point. The bumps 250 can also be compression bonded or thermocompressed bonded to the conductive layer 244b. The bumps 250 represent a type of interconnect structure that can be formed. The interconnect structure can also utilize bonded wiring, conductive paste, columnar bumps, microbumps, or other electrical interconnects. Figure 2f Any suitable combination of backend processing steps performed in the middle.

[0028] After completing the desired back-end processing steps, the chip 100 is flipped and mounted onto... Figure 2g On the back surface 252 of the back surface polishing tape. Solder bumps 250 are oriented toward and optionally embedded in the back surface polishing tape 252. A coarse polisher or rough polisher 260 is used on the back surface 108 to reduce the thickness of the wafer 100 by removing semiconductor material from the back surface. The coarse polisher 260 is used to thin the wafer 100 down to line 262, which is flush with or coplanar with the bottom surface of the trench 200.

[0029] The coarse grinding mill 260 thins the wafer 100 until the sealant 220 is exposed, as... Figure 2h As shown in the diagram. In some embodiments, sealant 220 is used as an etch stop layer. The sealant 220 and the back surface of the semiconductor die 104 are now coplanar at line 262. In one embodiment, the remainder of the wafer 100 within the saw path 106 is completely removed, which physically separates the semiconductor die 104 from being connected by semiconductor material. If the interconnect structure 240 is formed to extend across the saw path 106, the semiconductor die 104 remains connected by the sealant 220 and the interconnect structure 240. In other embodiments, the coarse polisher 260 leaves a thin layer of semiconductor material on the sealant 220, for example, 5-10 μm of the semiconductor wafer 100 remains on the sealant 220 after the coarse polisher 260 completes.

[0030] In either case, the coarse polisher 260 does not thin the wafer 100 all the way to the final thickness of the die 104. Stopping the coarse polisher 260 just before reaching the final thickness of the semiconductor die 104 reduces damage to the die caused by the coarse polisher. Any deep scratches caused by the coarse polisher 260 will then be removed.

[0031] Figure 2i A fine polisher 270 is shown for further thinning wafer 100 from line 262 to line 272. Line 272 represents the final desired thickness of semiconductor die 104. The fine polisher 270 is referred to as fine because it has a smaller grain size than the coarse polisher 260 for processing the back surface of wafer 100. In one embodiment, the fine polisher 270 uses a fine mesh wheel and a gentler or lower polishing speed than the coarse polisher 260. A lower polishing speed means that the rotational speed of the fine polisher 270 is lower than that of the coarse polisher 270 during polishing.

[0032] Compared to the thickness reduction achieved using the coarse polisher 260, the fine polisher 270 is only used to reduce the thickness of the wafer 100 by 20 μm, approximately 20 μm, or another relatively small thickness. In some embodiments, the thickness reduction achieved by the fine polisher 270 is considered relatively small when it is less than 5% of the thickness reduction achieved by the coarse polisher 260 or less than 50 μm. In the example above, with an initial thickness of 750 μm and a desired final thickness of 70 μm for the wafer 100, the coarse polisher 260 would reduce the wafer thickness by 660 μm. The fine polisher 270 would reduce the wafer thickness by 20 μm, approximately 3% of the thickness reduction achieved by the coarse polisher.

[0033] Figure 2j This illustrates the final thickness of wafer 100 thinned to semiconductor die 104, for example, 70 μm, where sealant 220 and die 104 have coplanar back surfaces at line 272. Figure 2k In this process, a saw blade or laser cutting tool 276 is used to monomerize the wafer 100 into individual chip-scale packages 280 separating the semiconductor die 104. A thin layer of sealant 220 is optionally left on the side surface of the semiconductor die 104. In other embodiments, the sealant 220 is completely removed from the side surface of the semiconductor die 104, and optionally, some sacrificial regions of the semiconductor die 104 are also removed. In some embodiments, with or without complete removal of the sealant 220, an additional insulating back-side protective layer is formed over the back surface of the semiconductor die 104 opposite the interconnect structure 240. The back-side protective layer may be formed prior to monomerization and generally uses the methods and materials described above for the insulating layer or sealant.

[0034] Figure 2l The completed chip-scale package 280 is shown. Because a fine grinder 270 is used instead of a coarse grinder 260 to grind the semiconductor die 104 down to its final thickness, the semiconductor die 104 is less likely to be damaged or fail. The use of a faster and cheaper grinder saves time and money by significantly reducing the use of the coarse grinder 260. Using the coarse grinder 260 only on the semiconductor wafer 100 and not on the additional sealant deposited between the semiconductor dies reduces wear on the coarse grinder and improves grinding speed. Completing the grinding with the fine grinder 270 prevents damage to the final die 104 caused by the coarse grinder 260. Reducing the thickness by only 20 μm using the fine grinder 270 reduces wheel wear, thus lowering the manufacturing cost per wafer.

[0035] Figure 3a and Figure 3b The illustration shows the integration of the aforementioned semiconductor package (e.g., chip-scale package 280) into a larger electronic device 300. Figure 3aThe illustration shows a partial cross-section of a chip-scale package 280 mounted on a printed circuit board (PCB) or other substrate 302, which is part of an electronic device 300. Solder bumps 250 are reflowed onto the conductive layer 304 of the PCB 302 to physically attach and electrically connect the chip-scale package 280 to the PCB. In other embodiments, thermal compression or another suitable attachment and connection method is used. In some embodiments, an adhesive or underfill layer is used between the chip-scale package 280 and the PCB 302. A semiconductor die 104 is electrically coupled to the conductive layer 304 via interconnect structure 240.

[0036] Figure 3b The illustration shows an electronic device 300 having a chip carrier substrate or PCB 302, having multiple semiconductor packages disposed on the surface of the PCB 302, including a chip-scale package 280. Depending on the application, the electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages.

[0037] Electronic device 300 can be a standalone system using semiconductor packaging to perform one or more electrical functions. Alternatively, electronic device 300 can be a sub-component of a larger system. For example, electronic device 300 can be part of a tablet, cellular phone, digital camera, communication system, or other electronic device. Alternatively, electronic device 300 can be a graphics card, network interface card, or other signal processing card that can be plugged into a computer. Semiconductor packages can include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electrical components. Miniaturization and weight reduction are crucial for product market acceptance. The distance between semiconductor devices can be reduced to achieve higher density. PCB 302 can have more irregular shapes to easily fit into more ergonomic and smaller device housings.

[0038] exist Figure 3b In this PCB 302, a general substrate is provided for the structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 304 are formed on the surface or within the layers of the PCB 302 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition processes. The signal traces 304 provide electrical communication between each of the semiconductor packages, mounted components, and other external system components. The traces 304 also provide power and ground connections to each of the semiconductor packages.

[0039] In some embodiments, the semiconductor device has two packaging levels. The first-level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second-level packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only a first-level package, where the die is directly mechanically and electrically mounted to the PCB.

[0040] For illustrative purposes, several types of first-level packages are shown on PCB 302, including a bonding wiring package 346 and a flip chip 348. Additionally, several types of second-level packages are shown disposed on PCB 302, including a ball grid array (BGA) 350, a bump chip carrier (BCC) 352, a ground grid array (LGA) 356, a multi-chip module (MCM) or SIP module 358, a quad flat package (QFN) 360, a quad flat package 362, and an embedded chip-level ball grid array (eWLB) 364. In one embodiment, eWLB 364 is a fan-out chip-level package (Fo-WLP) or a fan-in chip-level package (Fi-WLP).

[0041] Depending on system requirements, any combination of semiconductor packages configured with first-level and second-level packaging styles, along with any combination of other electrical components, can be connected to PCB 302. In some embodiments, electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnect packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-fabricated components into electronic devices and systems. Because semiconductor packages encompass complex functionality, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less prone to failure and less expensive to manufacture, reducing costs throughout the supply chain.

[0042] Although one or more embodiments of the invention have been illustrated in detail, those skilled in the art will appreciate that modifications and adaptations can be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method of fabricating a semiconductor device, comprising: providing a semiconductor wafer; forming a trench through an active surface of the semiconductor wafer between a first semiconductor die and a second semiconductor die; depositing an encapsulant in the trench; backgrinding a back surface of the semiconductor wafer opposite the active surface using a coarse grinder to expose the encapsulant; and backgrinding the back surface of the semiconductor wafer using a fine grinder.

2. The method of claim 1, wherein the fine grinder removes approximately 20 μιη of thickness from the semiconductor wafer.

3. The method of claim 1, further comprising performing back-end fabrication on the wafer after depositing the encapsulant and before backgrinding using the coarse grinder.

4. The method of claim 3, further comprising singulating the semiconductor wafer through the encapsulant after backgrinding using the fine grinder.

5. The method of claim 3, wherein performing back-end fabrication comprises forming a build-up interconnect structure over the active surface.

6. The method of claim 5, further comprising forming a solder bump over the build-up interconnect structure.

7. A method of fabricating a semiconductor device, comprising: providing a semiconductor wafer; forming a trench through an active surface of the semiconductor wafer; depositing an encapsulant in the trench; backgrinding a back surface of the semiconductor wafer opposite the active surface using a coarse grinder to expose the encapsulant; and backgrinding the back surface of the semiconductor wafer using a fine grinder.

8. The method of claim 7, wherein the fine grinder removes approximately 20 μιη of thickness from the semiconductor wafer.

9. The method of claim 8, wherein the coarse grinder removes more than 400 μιη of thickness from the semiconductor wafer.

10. The method of claim 9, further comprising performing back-end fabrication on the wafer after depositing the encapsulant and before backgrinding using the coarse grinder.

11. A method of fabricating a semiconductor device, comprising: providing a semiconductor wafer; backgrinding a surface of the semiconductor wafer using a coarse grinder; and backgrinding the surface of the semiconductor wafer using a fine grinder after using the coarse grinder.

12. The method of claim 11, wherein the fine grinder removes approximately 20 μιη of thickness from the semiconductor wafer.

13. The method of claim 12, wherein the coarse grinder removes more than 400 μιη of thickness from the semiconductor wafer.

14. The method of claim 11, further comprising performing back-end fabrication on the wafer before backgrinding using the coarse grinder.

15. The method of claim 14, wherein performing back-end fabrication comprises forming a build-up interconnect structure over the surface.

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