Low power consumption power management circuit

Abstract

The present invention discloses a low-power power management circuit, comprising: a reference circuit, a comparator, a clock generation circuit, a power acquisition sensor, a switch circuit, and a charged module; wherein one end of the reference circuit and one end of the power acquisition sensor are respectively connected to one end of the comparator, the other end of the comparator is connected to one end of the clock generation circuit, the other end of the clock generation circuit is connected to the control end of the switch circuit, one end of the power acquisition sensor is also connected to one end of the switch circuit, and the other end of the switch circuit is connected to the charged module. Compared with the prior art, the present invention reduces the power consumption of the power management circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of power management circuits, and in particular to a low-power consumption power management circuit. Background Art

[0002] In the field working environment, it is usually necessary to collect weak charges and charge related circuit modules to ensure that the circuit can work stably for a long time. The power management circuit has extremely stringent requirements on the union, and its working current needs to be below tens of nanoamperes. The power consumption of the traditional power management circuit structure is difficult to meet the requirements. Summary of the invention

[0003] The main purpose of the present invention is to provide a low-power power management circuit, aiming to reduce the power consumption of the power management circuit.

[0004] To achieve the above object, the present invention provides a low-power power management circuit, including: a reference circuit, a comparator, a clock generation circuit, a power acquisition sensor, a switch circuit, and a charged module;

[0005] Among them, one end of the reference circuit and one end of the power collection sensor are respectively connected to one end of the comparator, the other end of the comparator is connected to one end of the clock generating circuit, the other end of the clock generating circuit is connected to the control end of the switch circuit, one end of the power collection sensor is also connected to one end of the switch circuit, and the other end of the switch circuit is connected to the charged module.

[0006] A further technical solution of the present invention is that the power acquisition sensor is used to acquire and accumulate charge signals, and the comparator is used to compare the voltage of the power acquisition sensor and the voltage of the reference circuit;

[0007] When the voltage of the power acquisition sensor exceeds the signal of the first reference voltage, the comparator turns on the clock generating circuit and controls the switch circuit to close, so that the charge on the power acquisition sensor charges the charged module;

[0008] After the switch is closed, the charge of the power acquisition sensor decreases. When the comparator detects a signal that the voltage of the power acquisition sensor is lower than the second reference voltage, the switch circuit is disconnected and the charge of the power acquisition sensor continues to accumulate. If the voltage detected by the comparator is still higher than the second reference voltage and the clock signal of the clock generating circuit becomes a low level, the switch circuit is still disconnected.

[0009] A further technical solution of the present invention is that the reference circuit comprises: a PMOS tube M1, a PMOS tube M2, an NMOS tube M3, an NMOS tube M4, a resistor R3, a resistor R1, a resistor R5, a triode P1, a triode P2, a PMOS tube M6, a PMOS tube M9, an NMOS tube M5, an NMOS tube M8, a triode P3, a PMOS tube M0 and a resistor R2;

[0010] Wherein, the PMOS tube M1 and the PMOS tube M2 form a current mirror, the source electrodes of the PMOS tube M1 and the PMOS tube M2 are connected to the power supply, the gate electrodes of the PMOS tube M1 and the PMOS tube M2 are connected to the drain electrode of the PMOS tube M2, the drain electrode of the PMOS tube M2 is connected to the source electrode of the PMOS tube M4, the drain electrode of the PMOS tube M1 is connected to the source electrode of the NMOS tube M3, the drain electrode of the NMOS tube M4 is respectively connected to one end of the resistor R5 and one end of the resistor R1, the drain electrode of the NMOS tube M3 is respectively connected to one end of the resistor R3 and the emitter electrode of the triode P1, and the other end of the resistor R1 is connected to the emitter electrode of the triode P2; the base electrode and the collector electrode of the triode P1 and the triode P2 are short-circuited and connected to the ground wire, and the other end of the resistor R3 and the other end of the resistor R5 are connected to the ground wire;

[0011] The base electrode and base level of the transistor P3 are short-circuited and connected to the ground line, the emitter of the transistor P3 is connected to the source of the NMOS tube M5, the gate and drain of the NMOS tube M5 are short-circuited and connected to the drain of the PMOS M6, the source of the PMOS M6 is connected to the power supply, and the gate of the PMOS M6 is respectively connected to the gates of the PMOS tube M1 and the PMOS tube M2; the drain of the NMOS tube M5 is respectively connected to the gates of the PMOS tube M9 and the NMOS tube M8; the sources of the PMOS tube M9 and the NMOS tube M8 are respectively connected to the power supply and the ground line, and the drains of the PMOS tube M9 and the NMOS tube M8 are connected;

[0012] The gate of the PMOS tube M0 is connected to the gates of the PMOS tubes M1 and M2, the source of the PMOS tube M0 is connected to the power supply, the drain of the PMOS tube M0 is connected to one end of the resistor R2 and one end of the comparator, and the other end of the resistor R2 is connected to the ground line.

[0013] A further technical solution of the present invention is that the clock generating circuit comprises: inverter I1, inverter I2, inverter I11, inverter I12, inverter I5, inverter I6, inverter I7, inverter I8;

[0014] Among them, the inverter I1, the inverter I2, the inverter I11, and the inverter I12 form an oscillation loop, the output end of the inverter I1 is respectively connected to the input end of the inverter I2, the input end of the inverter I6, and the output end of the inverter I5, the output end of the inverter I2 is respectively connected to the output end of I7, the input end of the inverter I11, and the input end of the inverter I8, the output end of the inverter I11 is respectively connected to the input end of the inverter I12, the input end of the inverter I5, and the output end of the inverter I6, and the output end of the inverter I12 is respectively connected to the input end of the inverter I1, the input end of the inverter I7, and the output end of the inverter I8.

[0015] The beneficial effect of the low-power power management circuit of the present invention is that, compared with the prior art, the present invention can meet the demand for low power consumption, not only stops external charging when the voltage is lower than the reference voltage, but also adds a clock generation circuit, uses the duty cycle of the clock signal to control the external charging time, thereby ensuring that the charge of the power acquisition circuit can be gradually accumulated without being quickly released. The reference circuit, the clock generation circuit and the low-impedance switch circuit in the present invention all adopt a low-power design, which can ensure that the leakage charge is much smaller than the accumulated charge of the power acquisition sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a circuit structure diagram of a first embodiment of a low-power power management circuit of the present invention;

[0017] Figure 2 It is a schematic diagram of source startup and clock signals in a preferred embodiment of a low-power power management circuit of the present invention;

[0018] Figure 3 It is a circuit structure diagram of the second embodiment of the low-power power management circuit of the present invention.

[0019] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0020] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0021] Please refer to Figure 1 , Figure 1 It is a circuit structure diagram of the first embodiment of the low-power power management circuit of the present invention.

[0022] like Figure 1 As shown, in this embodiment, the low-power power management circuit includes: a reference circuit, a comparator, a clock generation circuit, a power acquisition sensor, a switch circuit, and a charged module.

[0023] Among them, one end of the reference circuit and one end of the power collection sensor are respectively connected to one end of the comparator, the other end of the comparator is connected to one end of the clock generating circuit, the other end of the clock generating circuit is connected to the control end of the switching circuit, one end of the power collection sensor is also connected to one end of the switching circuit, and the other end of the switching circuit is connected to the charged module.

[0024] The power acquisition sensor is used to acquire and accumulate charge signals, and the comparator is used to compare the voltage of the power acquisition sensor and the voltage of the reference circuit.

[0025] When the voltage of the power acquisition sensor exceeds the signal of the first reference voltage, the comparator turns on the clock generation circuit and controls the switch circuit to close, so that the charge on the power acquisition sensor charges the charged module.

[0026] After the switch circuit is closed, the charge of the power collection sensor decreases. When the comparator detects that the voltage of the power collection sensor is lower than the signal of the second reference voltage, the switch circuit is disconnected and the charge of the power collection sensor continues to accumulate. If the voltage detected by the comparator is still higher than the second reference voltage and the clock signal of the clock generating circuit becomes a low level, the switch circuit is still disconnected.

[0027] Please refer to Figure 2 , Figure 2 It is a schematic diagram of source startup and clock signals in a preferred embodiment of a low-power power management circuit of the present invention.

[0028] In this embodiment, the power acquisition sensor acquires and accumulates weak charge signals, and the comparator compares the voltage of the power acquisition sensor with the voltage of the reference circuit. When the voltage of the power acquisition sensor exceeds the signal of the reference voltage 1, the comparator turns on the clock generation circuit to generate a clock signal with a certain duty cycle, which controls the switch circuit to close, so that the charge on the power acquisition sensor charges the charged module; after the switch is turned on, the charge of the power acquisition sensor drops rapidly, and when the comparator detects that its voltage is lower than the reference voltage 2, the switch is disconnected, and the charge of the power acquisition sensor continues to accumulate. If the voltage detected by the comparator is still higher than the reference voltage 2, and the clock signal of the clock generation circuit becomes a low level, the switch circuit is still disconnected, thereby ensuring that the charge of the power acquisition sensor continues to accumulate.

[0029] It can be understood that in this embodiment, during the power-on process of the power acquisition sensor voltage, when the voltage value reaches the value of reference voltage 1, the clock generation circuit works, the switch circuit is closed, and external charging is performed. If the power acquisition sensor voltage is lower than reference voltage 2, the switch circuit is disconnected, the clock signal is set to a low level, external charging is stopped, and the power acquisition sensor voltage rises slowly. If the power acquisition sensor voltage is always higher than reference voltage 2 during external charging, due to the frequency relationship of the clock signal, after the high level period ends, the switch circuit will still be disconnected, thereby ensuring that the power acquisition sensor voltage rises slowly again.

[0030] For further information, please refer to Figure 3 , Figure 3 It is a circuit structure diagram of the second embodiment of the low-power power management circuit of the present invention.

[0031] like Figure 3 As shown, in this embodiment, the reference circuit includes: PMOS tube M1, PMOS tube M2, NMOS tube M3, NMOS tube M4, resistor R3, resistor R1, resistor R5, transistor P1, transistor P2, PMOS tube M6, PMOS tube M9, NMOS tube M5, NMOS tube M8, transistor P3, PMOS tube M0 and resistor R2.

[0032] Among them, the PMOS tube M1 and the PMOS tube M2 form a current mirror, the source electrodes of the PMOS tube M1 and the PMOS tube M2 are connected to the power supply, the gate electrodes of the PMOS tube M1 and the PMOS tube M2 are connected to the drain electrode of the PMOS tube M2, the drain electrode of the PMOS tube M2 is connected to the source electrode of the PMOS tube M4, the drain electrode of the PMOS tube M1 is connected to the source electrode of the NMOS tube M3, the drain electrode of the NMOS tube M4 is respectively connected to one end of the resistor R5 and one end of the resistor R1, the drain electrode of the NMOS tube M3 is respectively connected to one end of the resistor R3 and the emitter electrode of the triode P1, and the other end of the resistor R1 is connected to the emitter electrode of the triode P2; the base electrode and the collector electrode of the triode P1 and the triode P2 are short-circuited and connected to the ground wire, and the other end of the resistor R3 and the other end of the resistor R5 are connected to the ground wire.

[0033] The base electrode and base stage of the transistor P3 are short-circuited and connected to the ground line, the emitter of the transistor P3 is connected to the source of the NMOS tube M5, the gate and drain of the NMOS tube M5 are short-circuited and connected to the drain of the PMOS M6, the source of the PMOS M6 is connected to the power supply, and the gate of the PMOS M6 is respectively connected to the gates of the PMOS tube M1 and the PMOS tube M2; the drain of the NMOS tube M5 is respectively connected to the gates of the PMOS tube M9 and the NMOS tube M8; the sources of the PMOS tube M9 and the NMOS tube M8 are respectively connected to the power supply and the ground line, and the drains of the PMOS tube M9 and the NMOS tube M8 are connected.

[0034] The gate of the PMOS tube M0 is connected to the gates of the PMOS tubes M1 and M2, the source of the PMOS tube M0 is connected to the power supply, the drain of the PMOS tube M0 is connected to one end of the resistor R2 and one end of the comparator, and the other end of the resistor R2 is connected to the ground line.

[0035] This embodiment adopts the reference circuit to solve the technical problem in the prior art that a certain current needs to be consumed due to the stability and bandwidth requirements of the operational amplifier itself and the low power consumption requirement cannot be met, thereby reducing the current consumption of the power management circuit.

[0036] Furthermore, in this embodiment, the clock generating circuit includes: inverter I1, inverter I2, inverter I11, inverter I12, inverter I5, inverter I6, inverter I7, inverter I8;

[0037] Among them, inverter I1, inverter I2, inverter I11, and inverter I12 form an oscillation loop, the output end of inverter I1 is respectively connected to the input end of inverter I2, the input end of inverter I6, and the output end of inverter I5, the output end of inverter I2 is respectively connected to the output end of I7, the input end of inverter I11, and the input end of inverter I8, the output end of inverter I11 is respectively connected to the input end of inverter I12, the input end of inverter I5, and the output end of inverter I6, and the output end of inverter I12 is respectively connected to the input end of inverter I1, the input end of inverter I7, and the output end of inverter I8.

[0038] It is understandable that, in other embodiments, the clock generating circuit may also adopt a cascade structure to realize different periodic signals, and may even adopt more cascade modes to realize a clock signal with a longer period.

[0039] This embodiment adopts the clock generating circuit, which reduces the power consumption of the clock generating circuit compared to the prior art and meets the power consumption requirement of the power management circuit.

[0040] The beneficial effect of the low-power power management circuit of the present invention is that, compared with the prior art, the present invention can meet the demand for low power consumption, not only stops external charging when the voltage is lower than the reference voltage, but also adds a clock generation circuit, uses the duty cycle of the clock signal to control the external charging time, thereby ensuring that the charge of the power acquisition circuit can be gradually accumulated without being quickly released. The reference circuit, the clock generation circuit and the low-impedance switch circuit in the present invention all adopt a low-power design, which can ensure that the leakage charge is much smaller than the accumulated charge of the power acquisition sensor.

[0041] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A low-power power management circuit, characterized in that: include: Reference circuit, comparator, clock generation circuit, power acquisition sensor, switch circuit, and charged module; Wherein, one end of the reference circuit and one end of the power collection sensor are respectively connected to one end of the comparator, the other end of the comparator is connected to one end of the clock generating circuit, the other end of the clock generating circuit is connected to the control end of the switch circuit, one end of the power collection sensor is also connected to one end of the switch circuit, and the other end of the switch circuit is connected to the charged module; The power acquisition sensor is used to acquire and accumulate charge signals, and the comparator is used to compare the voltage of the power acquisition sensor and the voltage of the reference circuit; When the voltage of the power acquisition sensor exceeds the signal of the first reference voltage, the comparator turns on the clock generating circuit and controls the switch circuit to close, so that the charge on the power acquisition sensor charges the charged module; After the switch circuit is closed, the charge of the power acquisition sensor decreases. When the comparator detects that the voltage of the power acquisition sensor is lower than the second reference voltage, the switch circuit is disconnected, and the charge of the power acquisition sensor continues to accumulate. If the voltage detected by the comparator is still higher than the second reference voltage, and the clock signal of the clock generating circuit becomes a low level, the switch circuit is still disconnected; The reference circuit includes: a PMOS tube M1, a PMOS tube M2, an NMOS tube M3, an NMOS tube M4, a resistor R3, a resistor R1, a resistor R5, a triode P1, a triode P2, a PMOS tube M6, a PMOS tube M9, an NMOS tube M5, an NMOS tube M8, a triode P3, a PMOS tube M0 and a resistor R2; Wherein, the PMOS tube M1 and the PMOS tube M2 form a current mirror, the source electrodes of the PMOS tube M1 and the PMOS tube M2 are connected to the power supply, the gate electrodes of the PMOS tube M1 and the PMOS tube M2 are connected to the drain electrode of the PMOS tube M2, the drain electrode of the PMOS tube M2 is connected to the source electrode of the PMOS tube M4, the drain electrode of the PMOS tube M1 is connected to the source electrode of the NMOS tube M3, the drain electrode of the NMOS tube M4 is respectively connected to one end of the resistor R5 and one end of the resistor R1, the drain electrode of the NMOS tube M3 is respectively connected to one end of the resistor R3 and the emitter electrode of the transistor P1, and the other end of the resistor R1 is connected to the emitter electrode of the transistor P2; the base electrode and the collector electrode of the transistor P1 and the transistor P2 are short-circuited and connected to the ground wire, and the other end of the resistor R3 and the other end of the resistor R5 are connected to the ground wire; The collector and base of transistor P3 are short-circuited and connected to the ground line, the emitter of transistor P3 is connected to the source of NMOS tube M5, the gate and drain of NMOS tube M5 are short-circuited and connected to the drain of PMOS M6, the source of PMOS M6 is connected to the power supply, and the gate of PMOS M6 is respectively connected to the gates of PMOS tube M1 and PMOS tube M2; the drain of NMOS tube M5 is respectively connected to the gates of PMOS tube M9 and NMOS tube M8; the sources of PMOS tube M9 and NMOS tube M8 are respectively connected to the power supply and the ground line, and the drains of PMOS tube M9 and NMOS tube M8 are connected; The gate of the PMOS tube M0 is connected to the gates of the PMOS tube M1 and the PMOS tube M2, the source of the PMOS tube M0 is connected to the power supply, the drain of the PMOS tube M0 is connected to one end of the resistor R2 and one end of the comparator, and the other end of the resistor R2 is connected to the ground line; The clock generating circuit includes: inverter I1, inverter I2, inverter I11, inverter I12, inverter I5, inverter I6, inverter I7, inverter I8; Among them, the inverter I1, the inverter I2, the inverter I11, and the inverter I12 form an oscillation loop, the output end of the inverter I1 is respectively connected to the input end of the inverter I2, the input end of the inverter I6, and the output end of the inverter I5, the output end of the inverter I2 is respectively connected to the output end of I7, the input end of the inverter I11, and the input end of the inverter I8, the output end of the inverter I11 is respectively connected to the input end of the inverter I12, the input end of the inverter I5, and the output end of the inverter I6, and the output end of the inverter I12 is respectively connected to the input end of the inverter I1, the input end of the inverter I7, and the output end of the inverter I8.

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