Packaging structure, semiconductor device and packaging method

Abstract

The present invention discloses a packaging structure, a semiconductor device and a packaging method. The packaging structure comprises: a chip unit, comprising a substrate and a client layer located on the surface of the substrate, wherein the surface of the client layer facing away from the substrate is defined as a first surface, and the surface of the substrate facing away from the client layer is defined as a second surface, wherein a welding pad is formed in the client layer; a welding protrusion is formed on the second surface of the chip unit; a metal wiring layer is electrically connected between the welding pad and the welding protrusion; an insulating layer is formed between the metal wiring layer and the chip unit, wherein the insulating layer comprises a silicon dioxide layer and a SiO2 layer formed in sequence on the surface of the chip unit. 3 N 4 The insulating layer of the packaging structure of the present invention is made of SiO 2 +Si 3 N 4 + Epoxy resin three-layer structure, through this structure, not only can the moisture isolation effect be greatly improved, but also its own stress resistance strength is greatly improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and specifically relates to a packaging structure, a semiconductor device and a packaging method, which are particularly suitable for TSV (through silicon via) packaging of Low-k (low dielectric loss constant) chips of 40nm and below. Background Art

[0002] Wafer Level Chip Size Packaging (WLCSP) technology is a technology that packages and tests the entire wafer and then cuts it into individual finished chips. The size of the packaged chip is the same as the bare die. Wafer Level Chip Packaging technology subverts the traditional packaging model such as Ceramic Leadless Chip Carrier and Organic Leadless Chip Carrier, and conforms to the market demand for increasingly light, small, short, thin and low-priced microelectronic products. The chip packaged by wafer level chip packaging technology has achieved a high degree of miniaturization, and the chip cost is significantly reduced as the chip size decreases and the wafer size increases. Wafer level chip packaging technology is a technology that can integrate IC design, wafer manufacturing, packaging and testing into one, and is currently a hot topic and development trend in the packaging field.

[0003] In existing TSV packaging, organic materials such as SiO2 or epoxy resin are often used as insulating layers. However, organic materials have a high coefficient of thermal expansion (CTE), which can significantly stress the chip and its bonding pads, potentially causing cracks in the bonding pads themselves or fractures in nearby client layers. Summary of the Invention

[0004] An embodiment of the present invention provides a packaging structure, a semiconductor device, and a packaging method for solving the problem in the prior art of cracking of the solder pad itself or fracture of the adjacent client layer due to the large CTE of the insulating layer, including:

[0005] A packaging structure, comprising:

[0006] The chip unit includes a substrate and a client layer located on a surface of the substrate, wherein a surface of the client layer facing away from the substrate is defined as a first surface, a surface of the substrate facing away from the client layer is defined as a second surface, and a bonding pad is formed in the client layer;

[0007] a welding protrusion formed on the second surface of the chip unit;

[0008] a metal wiring layer electrically connected between the solder pad and the solder bump;

[0009] An insulating layer is formed between the metal wiring layer and the chip unit, and the insulating layer includes a silicon dioxide layer and a Si3N4 layer sequentially formed on the surface of the chip unit.

[0010] In one embodiment, the silicon dioxide layer is connected to the bonding pad, and / or

[0011] The Si3N4 layer is connected to the welding pad.

[0012] In one embodiment, the insulating layer further includes an epoxy resin layer formed between the Si 3 N 4 layer and the metal wiring layer.

[0013] In one embodiment, the method further comprises a through hole penetrating the substrate, wherein the through hole exposes the solder pad;

[0014] The insulating layer extends over the second surface of the chip unit and the sidewall of the through hole.

[0015] In one embodiment, a solder resist layer is further included, which is formed at least on the surface of the metal wiring layer. The solder resist layer has an opening that exposes a portion of the metal wiring layer. The solder bump fills the opening and is exposed outside the surface of the solder resist layer.

[0016] In one embodiment, the first surface of the chip unit has a functional structure, and the packaging structure further includes:

[0017] a substrate covering the first surface of the chip unit;

[0018] The supporting structure is located between the substrate and the chip unit, and the functional structure is located in a cavity surrounded by the supporting structure and the first surface of the chip unit.

[0019] A semiconductor device comprises the packaging structure.

[0020] In one embodiment, the semiconductor device is at least selected from OLED, LED, optical fingerprint sensor, or image sensor.

[0021] A packaging method, comprising:

[0022] Providing a wafer, the wafer comprising a plurality of chip units arranged in an array;

[0023] forming a through hole at a position corresponding to the solder pad;

[0024] An insulating layer is formed on the second surface of the chip unit and the sidewall of the through hole, wherein the insulating layer includes a silicon dioxide layer, a Si3N4 layer and an epoxy resin layer formed in sequence;

[0025] Making a metal wiring layer on the surface of the insulating layer;

[0026] The wafer is divided by a cutting process to form a packaging structure of multiple chip units.

[0027] In one embodiment, the through hole is formed by using a TSV process.

[0028] Compared with the prior art, the insulating layer of the packaging structure of the present invention adopts a three-layer structure of SiO2+Si3N4+epoxy resin. Through this structure, not only the moisture isolation effect can be greatly improved, but also the stress resistance strength itself is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 is a cross-sectional view of the packaging structure in embodiment 1 of the present application;

[0031] Figures 2 to 8 It is a schematic diagram of the intermediate structure formed by the packaging structure in embodiment 1 of the present application. DETAILED DESCRIPTION

[0032] As mentioned in the background, existing packaging structures are prone to fractures in the pads themselves or in the adjacent client layers. This is primarily due to the fact that in TSV (Through Silicon Via) packaging, organic materials such as SiO2 or epoxy resin serve as insulating layers, covering the sidewalls of the vias and connecting to the pads. Due to the high CTE (coefficient of thermal expansion) of these organic materials, they can easily pull on the pads, causing fractures.

[0033] In response to the problems of the existing technology, the main innovation of the embodiments of the present invention is that the insulating layer adopts a three-layer structure of SiO2+Si3N4+epoxy resin. Through this structure, the moisture isolation effect can be greatly improved, and the stress resistance strength itself is also greatly improved. Therefore, it has a significant effect in resisting structural stress and reducing stress at the welding pad.

[0034] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] This embodiment provides a packaging structure, referring to Figure 1 The package structure 10 includes a chip unit 11 . The chip unit 11 has a first surface 111 and a second surface 112 opposite to each other.

[0036] The chip unit 11 may be a fingerprint sensor chip, an image sensor chip, a photodiode chip, or a micro-electromechanical chip.

[0037] The chip unit 11 includes a functional structure 113 , a substrate 114 , a client layer 115 and a bonding pad 116 .

[0038] The substrate 114 is made of silicon, germanium, GaAs, InP, GaN, etc., preferably silicon.

[0039] The client layer 115 covers one side of the first surface 111 of the substrate 114 . An opening (not shown) is defined in the client layer 115 , and the bonding pad 116 is correspondingly disposed in the opening.

[0040] There can be a plurality of pads 117 , which are discretely arranged around the periphery of the functional structure 113 and serve as input terminals or output terminals for connecting the internal circuit of the chip unit with the external circuit.

[0041] The functional structure 113 is disposed on the surface of the client layer 115 . When the chip unit is a fingerprint sensor chip or an image sensor chip, the functional structure 113 is a photosensitive area. When the chip unit is an OLED or LED chip, the functional structure 113 is a light-emitting area.

[0042] The chip unit 11 is provided with a through hole 117 penetrating the substrate 114. The through hole 117 is passed through the upper and lower surfaces to achieve electrical interconnection between the first surface 111 and the second surface 112, thereby facilitating 3D packaging.

[0043] In a preferred embodiment, the through hole 117 is arranged as a whole inclined. More preferably, Figure 1 The side wall has a step portion (not shown) that connects the two inclined side walls up and down.

[0044] The second surface 112 of the chip unit 11 and the surface of the through hole 117 are formed with an insulating layer 12 .

[0045] The insulating layer 12 includes a Si 3 N 4 layer 122 . However, the Si 3 N 4 material itself is relatively hard. If it is directly deposited on the surface of the chip unit 11 , it is prone to breakage under the action of external force.

[0046] To overcome the problem of Si3N4 being hard, a buffer layer is provided between the Si3N4 layer 122 and the chip unit 11. The buffer layer is preferably a silicon dioxide layer 121. Since Si3N4 has excellent moisture isolation capability, it can reduce stress caused by moisture absorption by SiO2.

[0047] Further, to solve the stress problem, the insulating layer 12 further includes an epoxy resin layer 123 formed on the surface of the silicon dioxide layer 121. The insulating layer adopts a three-layer structure of SiO2 + Si3N4 + epoxy resin. According to the relationship of the coefficient of thermal expansion, SiO2 < Si3N4 < epoxy resin, and the three materials offset each other to a certain extent, and there will be no sudden change to cause the epoxy resin to break.

[0048] Among the silicon dioxide layer 121, the Si3N4 layer 122, and the epoxy resin layer 123, at least one layer needs to extend to the surface of the solder pad 116. In a preferred embodiment, both the silicon dioxide layer 121 and the Si3N4 layer 122 extend along the inner wall of the through hole 117 to the surface of the solder pad 116.

[0049] The position and area of the epoxy resin layer 123 laid can be set according to the need to solve the stress.

[0050] In one embodiment, the epoxy resin layer 123 is only formed on the horizontal surface of the second surface 112 of the chip unit 11, and there is no contact between it and the solder pad 116.

[0051] In another embodiment, the epoxy resin layer 123 can also extend along the inner wall surface of the through hole 117, and its end can be in contact with the solder pad 116.

[0052] A metal wiring layer 13 is formed on the surface of the insulating layer 12, and one end of the metal wiring layer 13 is electrically connected to the solder pad 116.

[0053] The surface of the metal wiring layer 13 is further covered with a solder resist layer 14. The solder resist layer 14 has an opening (not labeled) exposing a part of the metal wiring layer 13, and a welding bump 15 is filled in the opening, and the welding bump 15 is exposed outside the surface of the solder resist layer 14.

[0054] In one embodiment, the material of the solder resist layer 14 is epoxy resin.

[0055] The package structure 10 further includes a substrate 16, and the substrate 16 is located on one side of the first surface 111 of the chip unit 11.

[0056] In one embodiment, the substrate 16 is used as a protection plate, and its material can be selected from glass, Si, etc.

[0057] A support structure 17 is provided between the substrate 16 and the chip unit 11, and the functional structure 113 is located in the cavity surrounded by the support structure 18 and the first surface of the chip unit 11.

[0058] Correspondingly, the embodiment of the present invention provides a packaging method for forming the Figure 1 package structure as shown. Please refer to Figures 2 to 8, is a schematic diagram of an intermediate structure formed during the packaging process of the packaging method according to an embodiment of the present invention.

[0059] First, refer to Figure 2 and 3 , providing a wafer 200 to be packaged, wherein, Figure 2 is a schematic diagram of the top view of the wafer 200 to be packaged, Figure 3 for Figure 2 Cross-sectional view along A-A1.

[0060] The wafer 200 to be packaged includes a plurality of chip units 11 , and gaps are reserved between the chip units 11 as dicing lane areas 210 .

[0061] In this embodiment, the multiple chip units 11 on the wafer 200 to be packaged are arranged in an array, and the cutting line area 210 is located between adjacent chip units 11. The wafer 200 to be packaged is subsequently cut along the cutting line area 210 to form multiple chip packaging structures including chip units 11.

[0062] It should be noted that, in the subsequent steps of the packaging method of the embodiment of the present invention, for the sake of simplicity and clarity, only Figure 2 The cross-sectional view along the AA direction of the wafer 200 to be packaged is taken as an example for description, and similar process steps are performed in other areas.

[0063] Next, refer to Figure 4 A substrate 16 is provided, the substrate 16 includes a first surface 16a and a second surface 16b opposite to the first surface 16a, and a plurality of support structures 17 are formed on the first surface 16a of the substrate 16. The cavity enclosed by the support structure 17 and the first surface 16a of the substrate 16 corresponds to the functional structure 113.

[0064] In this embodiment, substrate 16 covers first surface 16a of functional structure 113 during subsequent processing, protecting functional structure 113. Because light must pass through substrate 16 to reach functional structure 113, substrate 16 is made of a light-transmitting material with high light transmittance. Both surfaces 15a and 15b of substrate 16 are flat and smooth, preventing scattering or diffuse reflection of incident light.

[0065] Specifically, the material of substrate 16 can be inorganic glass, organic glass, or other light-transmitting materials with a specific strength. In this embodiment, the thickness of substrate 16 is 300μm to 500μm, for example, 400μm. If the thickness of substrate 16 is too large, the thickness of the final chip packaging structure will be too large, which will not meet the requirements of thin and light electronic products. If the thickness of substrate 16 is too small, the strength of substrate 16 will be low, it will be easily damaged, and it will not provide sufficient protection for the subsequent covered sensing area.

[0066] In some embodiments, the support structure 17 is formed by depositing a support structure material layer on the first surface 16a of the substrate 16 and then etching it. Specifically, a support structure material layer (not shown) is first formed to cover the first surface 16a of the substrate 16. The support structure material layer is then patterned, and a portion of the support structure material layer is removed to form the support structure 17. The position of the cavity enclosed by the support structure 17 and the first surface 16a of the substrate 16 on the substrate 16 corresponds to the position of the functional structure 113 on the wafer 200 to be packaged. This allows the functional structure 113 to be located within the cavity enclosed by the support structure 17 and the first surface 16a of the substrate 16 after a subsequent bonding process.

[0067] In some embodiments, the material of the support structure material layer is a wet film or dry film photoresist, which is formed by spraying, spin coating, or pasting. The support structure material layer is exposed and developed for patterning to form the support structure 17 .

[0068] In some embodiments, the support structure material layer may also be an insulating dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride, which is formed by a deposition process and subsequently patterned by photolithography and etching processes to form the support structure 17 .

[0069] In some other embodiments, the support structure 17 may also be formed by etching the substrate 16. Specifically, a patterned photoresist layer may be formed on the substrate 16, and then the substrate 16 may be etched using the patterned photoresist layer as a mask to form the support structure 17 within the substrate 16. The support structure 17 is a raised portion on the first surface 16a of the substrate 16.

[0070] Next, refer to Figure 5 The first surface 16a of the substrate 16 is aligned with and combined with the surface of the wafer 200 to be packaged, so that the support structure 17 and the surface of the wafer 200 to be packaged form a cavity (not shown), and the functional structure 113 is located in the cavity.

[0071] In this embodiment, the substrate 16 and the wafer 200 to be packaged are combined by an adhesive layer (not shown). For example, an adhesive layer can be formed on the top surface of the support structure 17 of the first surface 16a of the substrate 16 and / or on the surface of the wafer 200 to be packaged by spraying, spin coating or gluing, and then the first surface 16a of the substrate 16 and the surface of the wafer 200 to be packaged are pressed relative to each other and combined by the adhesive layer. The adhesive layer can achieve both bonding and insulating and sealing functions. The adhesive layer can be a polymer adhesive material, such as a polymer material such as silicone, epoxy resin, benzocyclobutene, etc.

[0072] In this embodiment, after the first surface 16a of the substrate 16 is relatively combined with the surface of the wafer 200 to be packaged, the support structure 17 and the surface of the wafer 200 to be packaged form a cavity. The position of the cavity corresponds to the position of the functional structure 113, and the area of ​​the cavity is slightly larger than the area of ​​the functional structure 113, so that the functional structure 113 can be located in the cavity. In this embodiment, after the substrate 16 and the wafer 200 to be packaged are combined, the pads 116 on the wafer 200 to be packaged are covered by the support structure 17 on the substrate 16. The substrate 16 can play a role in protecting the wafer 200 to be packaged in subsequent processes.

[0073] Next, refer to Figure 6-8 , the wafer 200 to be packaged is packaged.

[0074] (1) Thinning the wafer 200 to be packaged to facilitate subsequent etching of through holes. The thinning of the wafer 200 to be packaged can be performed by mechanical grinding, chemical mechanical grinding, etc.

[0075] (2) Figure 6 , the wafer to be packaged 200 is etched to form a through hole 117, which exposes the welding pad 116; then, an insulating layer 12 is formed on the second surface 112 of the wafer to be packaged 200 and on the sidewall of the through hole 117, and the insulating layer 12 exposes the welding pad 116 at the bottom of the through hole. The insulating layer 12 can provide electrical insulation for the second surface 112 of the wafer to be packaged 200, and can also provide electrical insulation for the substrate of the wafer to be packaged 200 exposed by the through hole. The insulating layer 12 includes a silicon dioxide layer 121, a Si3N4 layer 122 and an epoxy resin layer 123 which are stacked in sequence.

[0076] The three-layer insulation structure has a good moisture isolation effect and has a very high advantage in resisting structural stress and reducing stress at the pad.

[0077] (3) Figure 7 A metal wiring layer 13 connected to the pad 116 is formed on the surface of the insulating layer 12. The metal wiring layer 13 leads the pad 116 to the second surface 112 of the wafer 200 to be packaged, and then connects to the external circuit. The metal wiring layer 13 is formed by depositing a metal film and etching the metal film.

[0078] (4) Figure 8 A solder resist layer 14 having openings (not shown) is formed on the surface of the metal wiring layer 13 and the surface of the insulating layer 213 , wherein the openings expose a portion of the surface of the metal wiring layer 13 . The material of the solder resist layer 14 is an insulating dielectric material such as silicon oxide and silicon nitride, and is used to protect the metal wiring layer 13 .

[0079] (5) Then, a solder bump 15 is formed on the surface of the solder resist layer 14. The solder bump 15 fills the opening. The solder bump 15 can be a connection structure such as a solder ball or a metal column, and the material can be a metal material such as copper, aluminum, gold, tin or lead.

[0080] (6) After the wafer 200 to be packaged is packaged, the chip package structure obtained by subsequent cutting can be connected to the external circuit through the welding bump 15. After the functional structure 113 of the chip unit converts the optical signal into an electrical signal, the electrical signal can be transmitted to the external circuit for processing through the welding pad 116, the metal wiring layer 13 and the welding bump 15 in sequence.

[0081] (7) Cut the wafer 200 to be packaged and the substrate 16 along the cutting path area of ​​the wafer 200 to be packaged to form a plurality of Figure 1 The package structure shown.

[0082] Cutting can be done by using a slicing knife or laser cutting, and slicing knife cutting can be done by using a metal knife or a resin knife.

[0083] The various aspects, embodiments, features and examples of the present invention should be considered as illustrative in all respects and are not intended to limit the present invention, the scope of which is defined solely by the claims. Other embodiments, modifications and uses will be apparent to those skilled in the art without departing from the spirit and scope of the invention as claimed.

[0084] The use of headings and sections in this application is not meant to limit the invention; each section may apply to any aspect, embodiment, or feature of the invention.

[0085] Throughout this application, where a composition is described as having, containing, or comprising particular components, or where a process is described as having, containing, or comprising particular process steps, it is contemplated that the compositions taught by the present invention also consist essentially of, or consist of, the recited components, and that the processes taught by the present invention also consist essentially of, or consist of, the recited process steps.

[0086] In this application, where an element or component is referred to as being included in and / or selected from a list of recited elements or components, it should be understood that the element or component may be any one of the recited elements or components and may be selected from a group consisting of two or more of the recited elements or components. Furthermore, it should be understood that the elements and / or features of the compositions, apparatuses, or methods described herein may be combined in various ways, whether explicitly or implicitly stated herein, without departing from the spirit and scope of the present teachings.

[0087] Unless specifically stated otherwise, use of the terms "include," "includes," "including," "have," "has," or "having" should generally be construed as open ended and non-limiting.

[0088] Unless specifically stated otherwise, the use of the singular herein includes the plural (and vice versa). Furthermore, unless the context clearly dictates otherwise, the singular forms "a," "an," and "the" include the plural. Additionally, where the term "about" is used before a quantitative value, the present teachings also include the specific quantitative value itself unless specifically stated otherwise.

[0089] Should be understood that, the order of each step or the order in which specific action is performed is not very important, as long as the present invention teachings remain operable.In addition, two or more steps or actions can be performed simultaneously.

[0090] It should be understood that the figures and descriptions of the present invention have been simplified to illustrate elements relevant to a clear understanding of the present invention, while other elements have been eliminated for clarity. However, those skilled in the art will recognize that these and other elements may be desirable. However, since such elements are well known in the art and since they do not promote a better understanding of the present invention, a discussion of such elements is not provided herein. It should be understood that the figures are presented for illustrative purposes and are not intended to be construction diagrams. Omitted details and modifications or alternative embodiments are within the scope of those skilled in the art.

[0091] It will be appreciated that in certain aspects of the present invention, a single component may be replaced by multiple components and multiple components may be replaced by a single component to provide an element or structure or to perform one or more given functions. Except where such substitution would not operate to practice a specific embodiment of the present invention, such substitution is considered within the scope of the present invention.

[0092] Although the present invention has been described with reference to illustrative embodiments, it will be understood by those skilled in the art that various other changes, omissions, and / or additions may be made and that substantial equivalents may be substituted for the elements of the embodiments without departing from the spirit and scope of the present invention. Additionally, many modifications may be made to adapt specific circumstances or materials to the teachings of the present invention without departing from the scope of the present invention. Therefore, it is not intended herein to limit the present invention to the disclosed specific embodiments for carrying out the present invention, but rather to include all embodiments within the scope of the appended claims. Furthermore, unless specifically stated, any use of the terms first, second, etc. does not indicate any order or importance, but rather uses the terms first, second, etc. to distinguish one element from another.

Claims

1. A packaging structure, characterized in that: include: The chip unit comprises a substrate and a client layer located on the surface of the substrate, wherein the surface of the client layer facing away from the substrate is defined as a first surface, the surface of the substrate facing away from the client layer is defined as a second surface, and a pad is formed in the client layer; A welding protrusion is formed on the second surface of the chip unit; A metal wiring layer electrically connected between the bonding pad and the bonding protrusion; An insulating layer, formed between the metal wiring layer and the chip unit, the insulating layer comprising a silicon dioxide layer, a Si3N4 layer and an epoxy resin layer sequentially formed on the surface of the chip unit; It also includes a through hole penetrating the substrate, wherein the through hole exposes the pad, and the insulating layer extends to the second surface of the chip unit and the side wall of the through hole.

2. The packaging structure according to claim 1, characterized in that: The silicon dioxide layer is connected to the pad, and / or The Si3N4 layer is connected to the welding pad.

3. The packaging structure according to claim 1, characterized in that: It also includes a solder resist layer, which is formed at least on the surface of the metal wiring layer. The solder resist layer has an opening that exposes a portion of the metal wiring layer. The solder protrusion fills the opening and is exposed outside the surface of the solder resist layer.

4. The packaging structure according to claim 1, characterized in that: The first surface of the chip unit has a functional structure, and the packaging structure further includes: A substrate covering the first surface of the chip unit; The support structure is located between the substrate and the chip unit, and the functional structure is located in a cavity surrounded by the support structure and the first surface of the chip unit.

5. A semiconductor device, comprising the packaging structure according to any one of claims 1 to 4.

6. The semiconductor device according to claim 5, characterized in that The semiconductor device is at least selected from OLED, LED, optical fingerprint sensor, or image sensor.

7. A packaging method for the packaging structure according to any one of claims 1 to 4, characterized in that: include: Providing a wafer, the wafer comprising a plurality of chip units arranged in an array; Forming a through hole at a position corresponding to the welding pad; An insulating layer is formed on the second surface of the chip unit and the side wall of the through hole, wherein the insulating layer includes a silicon dioxide layer, a Si3N4 layer and an epoxy resin layer formed in sequence; Making a metal wiring layer on the surface of the insulating layer; The wafer is divided by a cutting process to form a packaging structure of multiple chip units.

8. The packaging method of the packaging structure according to claim 7, characterized in that: The through hole is formed by TSV process.

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