Selective Growth of SiO2 on Dielectric Surfaces in the Presence of Copper

Abstract

Methods and apparatus are provided for selectively depositing silicon oxide on a dielectric surface relative to a metal-containing surface such as copper. The method comprises exposing a substrate having a dielectric surface and a copper surface to a copper blocking agent (e.g., an alkylthiol) to selectively adsorb the copper surface, exposing the substrate to a silicon-containing precursor to deposit silicon oxide, exposing the substrate to a weak oxidizer gas and igniting a plasma to convert the adsorbed silicon-containing precursor to form silicon oxide, and then exposing the substrate to a reducing agent to reduce any oxidized copper exposed to the weak oxidizer gas.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Patent Application No. 15 / 821,590, filed November 22, 2017, entitled “SELECTIVE GROWTH OF SIO2 ONDIELECTRIC SURFACES IN THE PRESENCE OF COPPER,” which is incorporated herein by reference in its entirety and for all purposes. Background Art

[0003] The manufacture of semiconductor devices includes the manufacture of microprocessors, logic and memory devices. Such devices can be manufactured using a variety of techniques, including self-aligned patterning, such as double or quad patterning, gap filling processes and other techniques. Some processes involve forming structures comprising silicon oxide and metal (e.g., copper). Conventional techniques for forming such structures may be limited. Summary of the Invention

[0004] Methods and apparatus for processing semiconductor substrates are provided herein. One aspect relates to a method for selectively depositing silicon oxide on a dielectric material relative to copper on the substrate, the method comprising: (a) providing the substrate comprising the dielectric material and an exposed copper metal surface; (b) prior to depositing the silicon oxide, exposing the substrate to a copper sealant to selectively adsorb the copper sealant onto the exposed copper metal surface; (c) exposing the substrate to a silicon-containing precursor to adsorb the silicon-containing precursor onto the dielectric material; (d) exposing the substrate to an oxidizing plasma generated in an environment comprising a weak oxidant to convert the adsorbed silicon-containing precursor into silicon oxide; and (e) exposing the substrate to a reducing agent to reduce the exposed copper metal surface.

[0005] In some embodiments, the copper sealant comprises sulfur.

[0006] In some embodiments, the copper blocking agent is an alkylthiol. For example, in some embodiments, the copper blocking agent is either ethanethiol or butanethiol.

[0007] In various embodiments, the copper sealant has the chemical formula SH(CH2) n CH3 alkylthiol, wherein n is an integer between 2 and 12, inclusive. In some embodiments, the copper sealant is a compound having the formula SH(CH2) nIn some embodiments, the copper sealant has the chemical formula SH(CH2)2CH3. In some embodiments, the copper sealant has the chemical formula SH(CH2)8CH3. In some embodiments, the copper sealant has the chemical formula SH(CH2)8CH3. 12 CH3.

[0008] In some embodiments, the silicon-containing precursor is an aminosilane. For example, the silicon-containing precursor can be any one of N-(diethylaminosilyl)-N-ethylethylamine, bis(diethylamino)silane (BDEAS), diisopropylaminosilane (DiPAS), diisobutylaminosilane (DiBAS), bis(tert-butylamino)silane (BTBAS), and tris(dimethylamino)silane (TDMAS).

[0009] In some embodiments, the weak oxidizing agent is any one of carbon dioxide, nitrous oxide, ozone, plasma thereof, and water. In some embodiments, the reducing agent is any one of hydrogen gas, hydrogen plasma, hydrazine gas, hydrazine plasma, ammonia gas, ammonia plasma, alcohol, and aldehyde. In some embodiments, the dielectric material is any one of silicon dioxide, aluminum oxide, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0010] In various embodiments, the silicon oxide is deposited at a temperature between about 70°C and about 200°C.

[0011] The method may further include introducing a second reducing agent to reduce the exposed copper metal surface before exposing the substrate to the copper sealant. The second reducing agent may be any one of hydrogen gas, hydrogen plasma, hydrazine gas, hydrazine plasma, ammonia gas, ammonia plasma, alcohol, and aldehyde.

[0012] The method may also include repeating operations (b)-(e) in two or more cycles. In some embodiments, (c) is self-limiting. In various embodiments, the copper sealant is preferably adsorbed onto the exposed copper metal surface to prevent subsequent deposition of silicon oxide on the exposed copper metal surface.

[0013] Another aspect relates to a method for selectively depositing silicon oxide on a dielectric material relative to a metal-containing surface on a substrate, the method comprising: (a) providing the substrate comprising the dielectric material and an exposed metal-containing surface; (b) exposing the substrate to a metal capping agent to selectively adsorb the metal capping agent onto the exposed metal-containing surface prior to depositing the silicon oxide; (c) exposing the substrate to a silicon-containing precursor to adsorb the silicon-containing precursor onto the dielectric material; (d) exposing the substrate to an oxidizing plasma generated in an environment comprising a weak oxidizing agent to convert the adsorbed silicon-containing precursor into silicon oxide; and (e) exposing the substrate to a reducing agent to reduce the exposed metal-containing surface.

[0014] In various embodiments, the exposed metal-containing surface comprises copper. In some embodiments, the exposed metal-containing surface comprises ruthenium.

[0015] In some embodiments, the exposed metal-containing surface comprises any of copper metal, copper oxide, ruthenium metal, and ruthenium oxide.

[0016] In some embodiments, the metal blocking agent is an alkylthiol. For example, in some embodiments, the metal blocking agent is either ethanethiol or butanethiol.

[0017] In various embodiments, the metal blocking agent is a metal blocking agent having the chemical formula SH(CH2) n Alkylthiols of CH3, wherein n is an integer between 2 and 12, inclusive.

[0018] In some embodiments, the silicon-containing precursor is an aminosilane. For example, the silicon-containing precursor can be any one of N-(diethylaminosilyl)-N-ethylethylamine, bis(diethylamino)silane (BDEAS), diisopropylaminosilane (DiPAS), diisobutylaminosilane (DiBAS), bis(tert-butylamino)silane (BTBAS), and tris(dimethylamino)silane (TDMAS).

[0019] In some embodiments, the weak oxidizing agent is any one of carbon dioxide, nitrous oxide, ozone, plasma thereof, and water. In some embodiments, the reducing agent is any one of hydrogen gas, hydrogen plasma, hydrazine gas, hydrazine plasma, ammonia gas, ammonia plasma, alcohol, and aldehyde. In some embodiments, the dielectric material is any one of silicon dioxide, aluminum oxide, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0020] In various embodiments, the silicon oxide is deposited at a temperature between about 70°C and about 200°C.

[0021] The method may further include introducing a second reducing agent to reduce the exposed metal-containing surface before exposing the substrate to the metal blocking agent. The second reducing agent may be any one of hydrogen gas, hydrogen plasma, hydrazine gas, hydrazine plasma, ammonia gas, ammonia plasma, alcohol and aldehyde.

[0022] The method may also include repeating operations (b)-(e) in two or more cycles. In some embodiments, (c) is self-limiting. In various embodiments, the metal blocking agent is preferably adsorbed onto the exposed metal-containing surface to prevent subsequent deposition of silicon oxide on the exposed metal-containing surface.

[0023] Another aspect relates to an apparatus for processing a semiconductor substrate, the apparatus comprising: at least one processing chamber including a susceptor for holding a semiconductor substrate; at least one outlet for coupling to a vacuum; a plasma generator; one or more process gas inlets coupled to one or more gas sources; and a controller for controlling operations in the apparatus, the controller comprising machine-readable instructions for: exposing the semiconductor substrate to a copper sealant to selectively adsorb onto exposed copper metal surfaces prior to depositing silicon oxide; exposing the substrate to a silicon-containing precursor to adsorb the silicon-containing precursor onto a dielectric material on the semiconductor substrate; exposing the substrate to an oxidizing plasma generated in an environment containing a weak oxidizing agent to convert the adsorbed silicon-containing precursor to deposit silicon oxide; and exposing the substrate to a reducing agent to reduce the exposed copper metal surfaces.

[0024] Another aspect relates to an apparatus for processing a semiconductor substrate, the apparatus comprising: at least one processing chamber including a susceptor for holding a semiconductor substrate; at least one outlet for coupling to a vacuum; a plasma generator; one or more process gas inlets coupled to one or more gas sources; and a controller for controlling operations in the apparatus, the controller comprising machine-readable instructions for: exposing the semiconductor substrate to a metal capping agent to selectively adsorb onto exposed metal-containing surfaces prior to depositing silicon oxide; exposing the substrate to a silicon-containing precursor to adsorb the silicon-containing precursor onto the dielectric material; exposing the substrate to an oxidizing plasma generated in an environment containing a weak oxidizing agent to convert the adsorbed silicon-containing precursor to deposit silicon oxide; and exposing the substrate to a reducing agent to reduce the exposed metal-containing surfaces.

[0025] These and other aspects are further described below in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1A-1E is a schematic diagram of a substrate undergoing a process for depositing metal in a via.

[0027] Figures 2A-2F is a schematic diagram of a substrate undergoing a process for forming perfectly aligned vias using selective dielectric deposition on a dielectric.

[0028] Figure 3 is a process flow diagram depicting operations for performing methods according to certain disclosed embodiments.

[0029] Figures 4A-4E is a schematic diagram of an example of a mechanism for selectively depositing dielectric material according to certain disclosed embodiments.

[0030] Figure 5 is a timing diagram illustrating an example of a loop in a method according to certain disclosed embodiments.

[0031] Figure 6 is a schematic diagram of an exemplary processing chamber for performing the disclosed embodiments.

[0032] Figure 7 is a schematic diagram of an exemplary processing tool for performing the disclosed embodiments.

[0033] Figure 8A 、 8B , 9A, 9B, 9C and 9D show the experimental results of the film thickness deposited on silicon oxide and copper surfaces. DETAILED DESCRIPTION

[0034] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other cases, well-known processing operations are not described in detail to avoid unnecessarily obscuring the disclosed embodiments. Although the disclosed embodiments will be described in conjunction with specific embodiments, it should be understood that they are not intended to limit the disclosed embodiments.

[0035] Semiconductor manufacturing processes typically involve depositing and etching various materials in a patterned scheme to form a specific type of semiconductor device. For example, a patterned scheme can be used to manufacture static random access memory (SRAM) cells. However, as devices shrink, the error margins of the process become smaller and smaller, especially for manufacturing metal interconnects between metal trenches above and below the metal interconnects. In addition, although various patterning and / or extreme ultraviolet lithography techniques can be used to manufacture small devices with low critical dimensions, these techniques are not yet capable of manufacturing dense circuits from the 10nm technology node to the 5-7nm technology node. Therefore, as a result, in conventional techniques, alignment differences of a few nanometers become a challenge when one layer is misaligned with the previous layer.

[0036] exist Figures 1A-1EAn example is provided in . These figures depict a conventional process for forming vias on interconnects, which results in so-called “unlanded vias,” where the material deposited in the via is misaligned with the previous interconnect layer due to misalignment in the mask formation process prior to depositing metal in the via.

[0037] Figure 1A The substrate 101 having metal lines 103a and 103b and an etch stop layer 105a deposited on the substrate 101 having the metal lines 103a and 103b are shown. The etch stop layer 105a may be a silicon nitride layer. Figure 1B middle, Figure 1A The etch stop layer 105a is patterned to form a patterned etch stop layer 105b. This etching process exposes the surface of the metal line 103a, but continues to mask the metal line 103b. Figure 1C In the embodiment, a dielectric material 107a such as silicon oxide is deposited on a substrate 101 having metal lines 103a and a patterned etch stop layer 105b. Figure 1D In the conventional etching technique Figure 1C The dielectric material 107a is removed to form an etched dielectric layer 107b containing a via 109. To form the via 109, conventional techniques involve forming a mask on a substrate, patterning the mask using an etching technique such as photolithography, and etching the dielectric material into the pattern of the mask. However, since the wafer transfer and alignment process and the etching process may not always accurately align the mask on the metal line 103a, the via 109 may be formed as shown in FIG. Figure 1D The metal line 103a is shown as misaligned. This misalignment may not be a problem in larger critical dimension features and for the manufacture of larger devices. However, in cases where the distance between the two metal lines 103a and 103b is on the nanometer scale, the misalignment of the via 109 can also cause the via 109 to be aligned too close to the adjacent metal line 103b, which may cause short circuits or other device problems. In addition, it is difficult to obtain a vertical profile in the via 109 using conventional processing.

[0038] exist Figure 1E In the embodiment of the present invention, via 109 is filled with metal to connect to metal line 103a. However, due to the misalignment of via 109, the metal deposited in via 109 can penetrate into substrate material 101, resulting in the formation of so-called "tooth" or "tiger tooth" defects 111. The blanket deposition at tooth 111 can cause device problems. For example, this misalignment can cause the via metal to short, resulting in high resistance and poor time-dependent dielectric breakdown (TDDB) lifetime.

[0039] It is desirable to form fully aligned through-holes. Figures 2A-2F An example is provided in . Figure 2AIn FIG, dielectric substrate 201 includes copper vias 203a and 203b. Figure 2B In the embodiment, dielectric material 213 is selectively deposited on the surface of dielectric 201 relative to the exposed copper surfaces of copper vias 203a and 203b. Such dielectric material 213 may have an etch contrast with ultra low k (ULK) dielectric. Figure 2C In FIG. 1 , a blanket ULK dielectric material 211 is deposited on the substrate including the dielectric material 213 and the copper vias 203a and 203b. Figure 2D In the embodiment, the blanket ULK dielectric material 211 is etched to form the through hole 215. Figure 2E In the embodiment, the blanket ULK dielectric material is further etched to form an etched ULK dielectric material 231. Since the selectively deposited dielectric material 213 has an etch selectivity to the ULK dielectric material 231, the through hole 235 is completely self-aligned. Figure 2F In , copper is filled into the vias to form a dual damascene structure.

[0040] For example, one possible patterning scheme may involve a dual damascene structure planarized by CMP to expose the metal in the via, followed by selective deposition of a dielectric material on the dielectric material relative to the metal in the via, wherein the dielectric has an etch contrast with an ultra-low-k (ULK) dielectric layer, followed by forming a blanket ULK dielectric material on the substrate, followed by a via etch and a line trench etch, wherein the etch contrast provides self-alignment, followed by a dual damascene metal fill.

[0041] However, conventional techniques for selectively depositing silicon oxide relative to copper materials on dielectric materials are limited. For example, although silicon oxide can be deposited using a chlorine-containing precursor by thermal reaction, chlorine may also etch the copper surface. In addition, if a plasma-based reaction is performed using a plasma generated using oxygen (O2) gas, the strong oxidizing plasma of oxygen will oxidize the exposed copper surface. Therefore, it is necessary to selectively deposit dielectrics relative to copper on dielectric materials to achieve the manufacture of fully aligned through-holes. Although there are techniques for depositing metal oxides (such as aluminum oxide, hafnium oxide, and zirconium oxide) using water as a reactant, these techniques may be selective to dielectrics with high dielectric constants. However, such techniques are not suitable for selectively depositing silicon oxide.

[0042] Methods are provided herein for selectively depositing dielectric materials on dielectric materials relative to copper, copper oxide, ruthenium, and / or ruthenium oxide. For example, the disclosed embodiments may involve depositing silicon oxide (e.g., SiO2) on silicon oxide (SiO2), aluminum oxide (Al2O3), silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. A non-limiting example of silicon oxycarbide is a material having the chemical formula SiO x C ySilicon oxycarbide, wherein 2x+4y=4 (x and y do not have to be integers). A non-limiting example of silicon carbonitride is a silicon oxycarbide having the chemical formula SiC a N b A non-limiting example of silicon oxycarbonitride is a silicon oxycarbonitride having the formula SiO i C j N k Silicon oxycarbon nitride, where 2i+4j+3k=4.

[0043] Certain disclosed embodiments involve exploiting the reactivity difference between hydroxyl terminated silicon oxide and reduced copper to enable selective deposition by using exposure to a copper blocking agent (e.g., thiol) that preferentially adsorbs onto the reduced copper surface and prevents subsequent deposition on the copper surface. Certain disclosed embodiments may be particularly suitable for selectively depositing dielectrics on dielectrics relative to copper surfaces, for example, in conjunction with the above Figures 2A-2F The patterning scheme described forms fully aligned through-holes.

[0044] The techniques described herein involve thermal atomic layer deposition (ALD) and / or plasma enhanced atomic layer deposition (PEALD).That is, in various embodiments, a reaction between a silicon-containing precursor and an oxidant is performed to form silicon oxide.

[0045] ALD is a technique for depositing thin layers of material using sequential, self-limiting reactions. Generally, an ALD cycle involves the delivery and adsorption of at least one reactant onto the substrate surface, followed by reaction of the adsorbed reactant with one or more reactants to form a portion of the film layer. For example, a silicon oxide deposition cycle may include the following: (i) delivery / adsorption of a silicon-containing precursor, (ii) purging the silicon-containing precursor from the chamber, (iii) delivery of an oxygen-containing reactant or oxygen-containing gas, and (iv) purging the chamber of the oxygen-containing reactant.

[0046] Unlike chemical vapor deposition (CVD) techniques, the ALD process uses surface-mediated deposition reactions to deposit films layer by layer. In one example of an ALD process, a substrate surface containing a population of surface active sites is exposed to a first precursor, such as a silicon-containing precursor, that is dosed into a chamber containing the substrate in a vapor phase distribution. Molecules of the first precursor are adsorbed on the substrate surface, comprising chemically adsorbed species and / or physically adsorbed molecules of the first precursor. It should be understood that when a compound is adsorbed onto the substrate surface as described herein, the adsorption layer may comprise the compound and derivatives of the compound. For example, an adsorption layer of a silicon-containing precursor may comprise a silicon-containing precursor and derivatives of the silicon-containing precursor. After the first precursor is dosed, the chamber is then evacuated to remove most or all of the remaining first precursor in the vapor phase, so that primarily or only the adsorbed species remain. In some implementations, the chamber may not be completely evacuated. For example, the chamber may be evacuated to a point where the local pressure of the first precursor in the vapor phase is sufficiently low to slow the reaction. A second reactant (e.g., an oxygen-containing reactant) is introduced into the chamber so that some of these molecules react with the first precursor adsorbed on the surface. In some processes, the second reactant reacts immediately with the adsorbed first precursor. The chamber can then be evacuated again to remove unbound second reactant molecules. As described above, in some embodiments, the chamber may not be completely evacuated. Additional ALD cycles may be used to build film thickness.

[0047] In certain embodiments, the dose of the ALD first precursor partially saturates the surface of the substrate. In some embodiments, the dosing phase of the ALD cycle is terminated before the precursor is contacted with the substrate to uniformly saturate the surface. Typically, the precursor flow is shut off or diverted at this point, and only the purge gas flow is maintained. By operating in this subsaturated regime, the ALD process reduces cycle time and improves throughput. However, because precursor adsorption is not saturation-limited, the adsorbed precursor concentration varies slightly across the substrate surface. An example of an ALD process operating in a subsaturated regime is provided in U.S. patent application Ser. No. 14 / 061,587, filed Oct. 23, 2013 (now U.S. Patent No. 9,355,839), entitled “SUB-SATURATED ATOMIC LAYER DEPOSITION AND CONFORMAL FILM DEPOSITION,” which is incorporated herein by reference in its entirety.

[0048] As described above, in some implementations, the ALD method includes plasma activation. As described herein, the ALD method and apparatus described herein can be a conformal film deposition (CFD) method, which is generally described in U.S. patent application Ser. No. 13 / 084,399, filed on April 11, 2011, entitled “PLASMA ACTIVATED CONFORMAL FILM DEPOSITION” (now U.S. Patent No. 8,728,956), and U.S. patent application Ser. No. 13 / 084,305, filed on April 11, 2011, entitled “SILICON NITRIDE FILMS AND METHODS,” which are incorporated herein by reference in their entirety.

[0049] Figure 3 A process flow diagram is provided that describes operations in a method performed according to certain disclosed embodiments. The embodiments described herein can be performed at a temperature between about 70° C. and about 200° C., for example, at a temperature between about 100° C. and about 150° C. In operation 301, a substrate having an exposed copper surface and an exposed dielectric surface is provided. The substrate can be a silicon wafer, such as a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer, including a wafer having one or more layers of material (e.g., a dielectric material, a conductive material, or a semiconductive material) deposited thereon. Non-limiting examples of bottom layers include dielectric layers and conductive layers, such as silicon oxide, silicon nitride, silicon carbide, metal oxides, metal nitrides, metal carbides, and metal layers.

[0050] In various embodiments, the substrate includes a dielectric material and metal-filled vias (e.g., interconnects). In various embodiments, the dielectric material can be a silicon-containing material, such as silicon oxide. In various embodiments, the dielectric material can be a ULK dielectric. In some embodiments, the dielectric material can be a semiconductor material rather than a dielectric material. In various embodiments, the dielectric layer comprises hydroxyl-terminated silicon oxide.

[0051] In various embodiments, the vias are filled with copper. In some embodiments, the vias are filled with copper oxide, ruthenium, and / or ruthenium oxide. In some embodiments, exposure to a reducing agent (e.g., hydrogen or hydrazine) is used to reduce the copper in preparation for service in subsequent operations.

[0052] Figure 4A is a schematic diagram of an exemplary substrate having an exposed silicon oxide surface 401 and an exposed copper surface 403 .

[0053] In operation 303, the substrate is exposed to a copper sealant to selectively react with the exposed copper surface. In various embodiments, the copper sealant is a thiol. In some embodiments, the copper sealant is an alkylthiol having the following structure:

[0054]

[0055] wherein n is an integer between 2 and 12, inclusive, or between 2 and 6, inclusive. For example, in some embodiments, n may be 8. In some embodiments, n may be 12. Exemplary thiols include alkyl thiols, such as ethanethiol and butanethiol, as depicted below:

[0056]

[0057] The copper blocking agent is selected to react with copper and copper oxide surfaces, but not with dielectric surfaces (e.g., hydroxyl-terminated silicon oxide surfaces). For example, a thiol contains a sulfur atom that can react with copper on a copper surface that has been previously reduced with a reducing agent. Since some copper surfaces have a native oxide on the surface that forms copper oxide, the selected thiol contains a sulfur atom that reacts with copper oxide to form water and a thiolate.

[0058] The blocked copper surface is both non-volatile and sterically crowded. In some embodiments, methanethiol is not used because it may not be bulky enough to prevent oxidation of the copper surface. In some embodiments, octanethiol may not be used because they contain long tails that are bulky enough to prevent oxidation of the copper surface, but cannot be densely packed to adsorb onto the majority of exposed copper surfaces. In various embodiments, the alkyl chain is a carbon chain having only hydrogen atoms and no other non-hydrogen substituents.

[0059] Figure 4B is a schematic diagram of an exemplary substrate having an exposed silicon oxide surface 401 that does not react with butanethiol as a copper blocking agent, but Figure 4A The exposed copper surface 403 reacts with butanethiol to form a closed surface 405 .

[0060] return Figure 3In operation 305, the chamber containing the substrate may optionally be purged to remove excess copper sealant that does not react with the exposed copper. Purging the chamber may involve flowing a purge gas or purge gas, which may be a carrier gas used for other operations, or may be a different gas. In some embodiments, purging may involve evacuating the chamber. Exemplary purge gases include argon, nitrogen, hydrogen, and helium. In some embodiments, operation 305 may include one or more evacuation sub-stages for evacuating the process chamber. Alternatively, it should be understood that operation 305 may be omitted in some embodiments. Operation 305 may have any suitable duration, such as a duration between about 0 seconds and about 60 seconds, for example, a duration of about 0.01 seconds. In some embodiments, increasing the flow rate of one or more purge gases may reduce the duration of operation 305. For example, the purge gas flow rate may be adjusted based on various reactant thermodynamic properties and / or the geometric properties of the process chamber and / or process chamber conduit to change the duration of operation 305. In one non-limiting example, the duration of the sweep phase can be adjusted by adjusting the sweep gas flow rate. This can reduce the deposition cycle time, thereby increasing substrate throughput. After sweeping, the copper sealant remains adsorbed on the copper surface.

[0061] In operation 307, the substrate is exposed to a silicon-containing precursor. In various embodiments, the silicon-containing precursor is an aminosilane. Aminosilanes contain at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogens, and carbon. Examples of aminosilanes are mono-, di-, tri-, and tetra-aminosilanes (H3Si(NH2), H2Si(NH2)2, HSi(NH2)3, and Si(NH2)4, respectively), as well as substituted mono-, di-, tri-, and tetra-aminosilanes, such as tert-butylaminosilane, methylaminosilane, tert-butylsilylamine, bis(tert-butylamino)silane (SiH2(NHC(CH3)3)2(BTBAS), tert-butylsilylcarbamate, SiH(CH3)-(N(CH3)2)2, SiHCl-(N(CH3)2)2, (Si(CH3)2NH)3), and the like. Another example of an aminosilane is trimethylsilylamine (N(SiH3)).

[0062] In some embodiments, the silicon-containing precursor is an alkylaminosilane having the following general structure:

[0063]

[0064] wherein at least one of R1, R2, R3, and R4 comprises a primary or secondary amino group. In some embodiments, one to three of the substituents R1, R2, R3, and R4 are hydrogen atoms. For example, in some embodiments, the silicon-containing precursor is SAM24 (N-(diethylaminosilyl)-N-ethylethylamine) having the following structure:

[0065]

[0066] The silicon-containing precursor is an aminosilane. Exemplary silicon-containing precursors include bis(diethylamino)silane (BDEAS), diisopropylaminosilane (DiPAS), diisobutylaminosilane (DiBAS), bis(tert-butylamino)silane (BTBAS), and tris(dimethylamino)silane (TDMAS). The silicon-containing precursor forms a silicamide on the surface of the substrate, such as Figure 4C 407. In some embodiments, some hydroxyl terminated groups 405 may remain on the surface during operation 307. Note that the silicon-containing precursor does not adsorb onto the copper surface in view of the blocked copper surface 409.

[0067] Operation 307 can be part of an atomic layer deposition (ALD) cycle. As described above, typically an ALD cycle is a minimum set of operations for performing a surface deposition reaction. In some embodiments, the result of one cycle is the generation of at least a portion of a silicon oxide film layer on the substrate surface. The cycle may include certain auxiliary operations, such as cleaning one of the reactants or byproducts and / or processing the deposited portion of the film. Typically, one cycle comprises an example of a unique sequence of operations. As described above, typically, one cycle is a minimum set of operations for performing a surface deposition reaction. The result of one cycle is the generation of at least a portion of a film layer, such as a portion of a silicon nitride film layer, on the substrate surface.

[0068] During operation 307, the substrate is exposed to a silicon-containing precursor such that the silicon-containing precursor is adsorbed onto the surface of the substrate to form an adsorbed layer. In some embodiments, the aminosilane precursor adsorbs onto the surface of the substrate in a self-limiting manner such that once the active sites are occupied by the aminosilane precursor, little or no additional aminosilane precursor will be adsorbed on the substrate surface. For example, the aminosilane precursor may be adsorbed onto about 60% of the substrate surface. In various embodiments, as the aminosilane precursor flows into the chamber, the aminosilane precursor adsorbs onto the active sites on the substrate surface, thereby forming a thin layer of the aminosilane precursor on the surface. In various embodiments, the layer may be less than a monolayer and may have a thickness between about 100 nm and about 100 nm. peace treaty The methods provided herein can be performed at a temperature of about 70°C to about 200°C, for example, at a temperature between about 100°C and about 150°C.

[0069] return Figure 3 In operation 309 , the chamber containing the substrate may optionally be purged using any one or more of the techniques described above with respect to operation 305 .

[0070] In operation 311, the substrate is exposed to a mild oxidizing plasma. The mild oxidizing plasma is generated using a weak oxidizing agent defined as limiting oxidation of the bulk copper to less than a surface oxidation depth. An oxidizing agent is used. Exemplary mild oxidizing agents include carbon dioxide, nitrous oxide, ozone, and water. In addition to water, any one or more of these oxidizing agents can be used in the generated plasma. In some embodiments, water vapor is used instead of an oxidizing plasma. A mild oxidizing plasma is used to prevent oxidation on the copper surface. Thus, the oxidizing agent can be selected so that it does not react with copper but reacts with the silicon-containing precursor adsorbed on the dielectric surface. Figure 4D An example of a substrate after exposure to a carbon dioxide plasma is shown, so that hydroxyl-terminated silicon groups 411 remain on the surface, thereby building up a thickness of silicon oxide. During oxidation, the blocking agent can react with the oxide to form various gases 413, such as water, carbon dioxide, sulfur dioxide, and sulfur trioxide. Such gases are mild oxidants and therefore do not necessarily oxidize the copper surface. However, as Figure 4D As shown, some copper may be oxidized or a hydroxyl terminated copper surface may be formed. In some embodiments, some copper blocking agent may remain on the surface.

[0071] return Figure 3 In operation 313, the chamber containing the substrate is optionally purged to remove excess byproducts, such as gases formed by the reaction of the mild oxidizing plasma with the capping agent and the reaction of the mild oxidizing plasma with the silicon-containing precursor adsorbed on the substrate surface. The purge may be performed using any one or more of the techniques described above with respect to operation 305.

[0072] In operation 315, the substrate is exposed to a reducing agent to reduce the copper surface. The reducing agent can be hydrogen, hydrogen plasma, hydrazine gas, hydrazine plasma, ammonia, ammonia plasma, an alcohol in gaseous form, or an aldehyde in gaseous form. Exemplary alcohols include ethanol and isopropyl alcohol. An exemplary aldehyde that can be used is formaldehyde. In some embodiments, plasma is used instead of gas to improve the reduction efficiency. In some embodiments, during operation 315, a plasma is ignited to form a plasma based on one of hydrogen, hydrazine, or ammonia. For example, in some embodiments, operation 315 involves exposing the substrate to a hydrogen plasma to reduce the copper surface. The reducing agent allows the copper surface to reduce the amount of oxidation on the copper surface, so that the subsequently deposited dielectric material can be selectively deposited on the dielectric surface rather than on the copper surface. The reducing agent is selected so that the deposited silicon oxide material is not affected by the reducing agent.

[0073] In some embodiments, operation 315 is performed before operation 303. In some embodiments, operation 315 is performed before operation 303 and after operation 311. In various embodiments, the reducing agents used before and after are different. In some embodiments, the reducing agents are the same.

[0074] Figure 4E An exemplary substrate is shown whereby, after exposure to a reducing agent, silicon oxide 411 remains on the surface and some thiols 415 are replenished on the surface and from Figure 4D Some of the oxidized copper is reduced to leave a copper surface.

[0075] return Figure 3 In operation 317, the chamber is optionally purged to remove excess byproducts generated by exposing the substrate to the reducing agent in operation 315. In various embodiments, these byproducts include products formed by reacting the reducing agent with copper oxide, such as water.

[0076] In operation 319, determine whether silicon oxide is deposited to the desired thickness. If so, the deposition process ends. If not, deposition can be resumed by repeating operations 303-317 in a loop. In various embodiments, operations 303 and 315 are performed in each cycle. In some embodiments, either or both of operations 303 and 315 are performed every other cycle. However, it may be appropriate to perform both operations 303 and 315 in each cycle to continue to close the copper surface during the deposition of silicon oxide to prevent oxidation of the copper surface and to allow selective deposition of silicon oxide. In some embodiments, each cycle may involve repeating the same operation using the same chemicals and process conditions. In some embodiments, each cycle may involve repeating the operation using different chemicals. For example, the reducing agent used in one cycle may be different from the reducing agent used in another cycle.

[0077] Figure 5 Provides a timing diagram of various operations performed according to certain disclosed embodiments. Figure 5 The process 500 depicted in FIG. 5 includes only two deposition cycles 599A and 599B, ​​but it should be understood that in certain disclosed embodiments, more than two deposition cycles (and in some cases, only one deposition cycle) may be performed.

[0078] Figure 5Stages in an exemplary deposition process 500 are shown for various process parameters, such as argon flow as a carrier gas and / or sweep gas, thiol flow, silicon-containing precursor flow, oxygen-containing plasma exposure, and reducing agent flow. Although this example depicts an oxygen-containing plasma as a deposition technique, in some embodiments, thermal deposition can be performed using an oxygen-containing gas. The lines indicate when flows are turned on and off and when the plasma is turned on and off. Various disclosed embodiments depend on process parameters, including but not limited to the flow rates of inert and reactant materials, the flow rates of argon, thiol, silicon-containing precursor, and reducing agent gases, plasma conditions, substrate temperature, and chamber pressure.

[0079] Deposition cycle 599A includes a copper sealant exposure phase 503A, a silicon-containing precursor exposure phase 507A, a sweep phase 509A, an oxidizing plasma exposure phase 511A, a sweep phase 513A, and a reducing agent exposure phase 515A. The copper sealant exposure phase 503A may correspond to Figure 3 During the copper sealant exposure phase 503A, the argon flow can be turned on to introduce the copper sealant into the chamber, and the thiol flow can be turned on while the silicon-containing precursor flow, the oxygen-containing plasma, and the reducing agent flow are turned off. Although not specified in this example, it should be understood that the thiol can be any suitable thiol, such as the thiol described above with respect to Figure 3 After the copper sealant exposure phase 503A, the silicon-containing precursor exposure phase 507A is performed. Note that in this example, no Figure 3 However, it should be understood that in various embodiments, operation 305 may be performed between the copper sealant exposure phase 503A and the silicon-containing precursor exposure phase 507A. The silicon-containing precursor exposure phase 507A may correspond to Figure 3 During the silicon-containing precursor exposure phase 507A, the argon flow may be maintained to assist in the delivery of the silicon-containing precursor, while the thiol flow is turned off, the silicon-containing precursor flow is turned on, the oxygen-containing plasma flow is turned off, and the reducing agent flow is turned off. In the sweep phase 509A, all gas flows and plasma are turned off except for the argon flow (which serves as a sweep gas). The sweep phase 509A may correspond to Figure 3 Operation 309. In the oxidation plasma exposure phase 511A, the argon flow may continue to be on, the thiol flow may be off, the silicon-containing precursor flow may be off, the oxygen-containing plasma may be on, and the reducing agent flow may be off. In various embodiments, the oxygen-containing plasma is as described above with respect to Figure 3 Any weak oxidant ignited by the plasma as described in operation 311. The oxidizing plasma exposure phase 511A may correspond to Figure 3In operation 311 of FIG. 5 , the argon gas flow is turned on to act as a sweep gas, while the mercaptan gas flow is turned off, the silicon-containing precursor gas flow is turned off, the oxygen-containing plasma is turned off, and the reducing agent gas flow is turned off. The sweep phase 513A may correspond to Figure 3 Operation 313. In the reducing agent exposure phase 515A, argon gas flow can be used as a carrier gas to assist in the delivery of the reducing agent, the thiol gas flow is turned off, the silicon-containing precursor gas flow is turned off, the oxygen-containing plasma is turned off, and the reducing agent gas flow is turned on. Although the examples described herein relate to thermal reactions of reducing agent exposure, it should be understood that in some embodiments, the reducing agent gas flow is turned on while the plasma is ignited during this exposure phase. The reducing agent exposure phase 515A may correspond to Figure 3 315. In this example, no sweep operation is performed after the reducing agent exposure phase 515A, but it should be understood that in some embodiments, a sweep operation can be performed. In this example, it is determined that the silicon oxide has not been deposited to the desired thickness, so these operations are repeated in deposition cycle 599B. Deposition cycle 599B includes: a copper sealant exposure phase 503B, in which argon gas flow and thiol flow are turned on, while silicon-containing gas flow, oxygen-containing plasma, and reducing agent gas flow are turned off; a silicon-containing precursor exposure phase 507B, in which only argon gas and silicon-containing gas flow are turned on, while thiol gas flow, oxygen-containing plasma, and reducing agent gas flow are turned off; a sweep phase 509B, in which only argon gas flows as a sweep gas; an oxidizing plasma exposure phase 511B, in which only argon gas and oxygen-containing plasma are turned on, while thiol gas flow, silicon-containing precursor gas flow, and reducing agent gas flow are turned off; a sweep phase 513B, in which argon gas flows as a sweep gas; and a reducing agent exposure phase 515B, in which only argon gas and reducing agent gas flow are turned on, while silicon-containing precursor gas flow, thiol gas flow, and oxygen-containing plasma are turned off.

[0080] In various embodiments, after the silicon oxide is deposited to a sufficient thickness, the copper surface can be reduced by a reducing agent, and any remaining thiols on the copper surface can be removed by rinsing with acetic acid.

[0081] equipment

[0082] Figure 6 A schematic diagram of one embodiment of an atomic layer deposition (ALD) processing station 600 having a processing chamber body 602 for maintaining a low pressure environment is depicted. Multiple ALD processing stations 600 can be included in a common low pressure processing tool environment. For example, Figure 7 One embodiment of a multi-station processing tool 700 is depicted. In some embodiments, one or more hardware parameters of the ALD processing station 600 (including those discussed in detail below) can be programmatically adjusted by one or more computer controllers 650.

[0083] The ALD processing station 600 is in fluid communication with a reactant delivery system 601a for delivering process gases to a distribution showerhead 606. The reactant delivery system 601a includes a mixing vessel 604 for blending and / or regulating process gases, such as an aminosilane precursor gas, or a mild oxidant gas (e.g., carbon dioxide), or a reducing agent (e.g., hydrogen) gas, delivered to the showerhead 606. One or more mixing vessel inlet valves 620 can control the introduction of process gases into the mixing vessel 604. A mild oxidizing plasma and / or a reducing agent plasma can also be delivered to the showerhead 606 or can be generated in the ALD processing station 600.

[0084] For example, Figure 6 Embodiments include a vaporization point 603 for vaporizing liquid reactants to be supplied to the mixing container 604. In some embodiments, the vaporization point 603 can be a heated evaporator. The saturated reactant vapors produced from such an evaporator will condense in the downstream delivery pipe. Incompatible gases exposed to the condensed reactants will produce small particles. These small particles may block the pipes, hinder valve operation, contaminate the substrate, etc. Some methods for dealing with these problems involve cleaning and / or emptying the delivery pipes to remove residual reactants. However, cleaning the delivery pipes will increase the processing station cycle time and reduce the processing station throughput. Therefore, in some embodiments, the delivery pipes downstream of the vaporization point 603 can be heat traced. In some examples, the mixing container 604 can also be heat traced. In a non-limiting example, the pipes downstream of the vaporization point 603 have an increased temperature distribution, extending from about 100°C to about 150°C at the mixing container 604.

[0085] In some embodiments, the liquid precursor or liquid reactant can be vaporized at the liquid injector. For example, the liquid injector can eject a pulse of liquid reactant into the carrier gas flow upstream of the mixing vessel. In one embodiment, the liquid injector can vaporize the reactant by flashing the liquid from a higher pressure to a lower pressure. In another example, the liquid injector can atomize the liquid into dispersed droplets that are then vaporized in a heated delivery pipe. Smaller droplets can vaporize faster than larger droplets, thereby reducing the delay between liquid injection and completion of vaporization. Faster vaporization can reduce the length of the pipeline downstream of the vaporization point 603. In one embodiment, the liquid injector can be loaded directly into the mixing vessel 604. In another embodiment, the liquid injector can be loaded directly into the spray head 606.

[0086] In some embodiments, a liquid flow controller (LFC) can be set upstream of the vaporization point 603 to control the mass flow of the liquid for vaporization and delivery to the processing station 600. For example, the LFC can include a thermal mass flow meter (MFM) located downstream of the LFC. The plunger valve of the LFC can then be adjusted in response to a feedback control signal provided by a proportional integral differential (PID) controller that is electrically communicated with the MFM. However, it can take one second or more to use feedback control to stabilize the liquid flow. This can extend the time of dosing the liquid reactant. Therefore, in some embodiments, the LFC can dynamically switch between a feedback control mode and a direct control mode. In some embodiments, this can be performed by disabling the sensing conduit and PID controller of the LFC.

[0087] Showerhead 606 distributes process gas toward substrate 612. Figure 6 In the illustrated embodiment, substrate 612 is positioned below showerhead 606 and is shown resting on pedestal 608. Showerhead 606 can have any suitable shape and can have any suitable number and arrangement of ports to distribute process gases to substrate 612.

[0088] In some embodiments, the pedestal 608 can be raised or lowered to expose the substrate 612 to the volume between the substrate 612 and the showerhead 606. It will be appreciated that in some embodiments, the pedestal height can be programmatically adjusted via a suitable computer controller 650.

[0089] In another embodiment, in which the plasma is ignited, adjusting the height of the pedestal 608 can allow the plasma density to be varied during the plasma activation cycle of the process. At the end of the processing phase, the pedestal 608 can be lowered to allow the substrate 612 to be removed from the pedestal 608 during another substrate transfer phase.

[0090] In some implementations, the susceptor 608 can be temperature controlled via a heater 610. In some implementations, the susceptor 608 can be heated to a temperature between about 70°C and about 200°C, or between about 100°C and about 120°C.

[0091] Additionally, in some embodiments, pressure control for the processing station 600 may be provided by a butterfly valve 618. Figure 6 In the embodiment shown in FIG, butterfly valve 618 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of process station 600 can also be adjusted by varying the flow rate of one or more gases introduced into process station 600.

[0092] In some embodiments, the position of the showerhead 606 can be adjusted relative to the pedestal 608 to change the volume between the substrate 612 and the showerhead 606. Furthermore, it should be understood that the vertical position of the pedestal 608 and / or showerhead 606 can be changed by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 608 can include a rotation axis for rotating the orientation of the substrate 612. It should be understood that in some embodiments, one or more of these exemplary adjustments can be performed programmatically by one or more appropriate computer controllers 650.

[0093] In some embodiments in which plasma can be used as described above, the showerhead 606 and the base 608 are electrically connected to a radio frequency (RF) power source 614 and a matching network 616 to provide power to the plasma. In some embodiments, the energy of the plasma can be controlled by controlling one or more of the pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing of the processing station. For example, the RF power source 614 and the matching network 616 can be operated at any suitable power to form a plasma having a composition of desired free radical species. An example of a suitable power is about 150W to about 6000W. Plasma can be used during the treatment of the silicon nitride surface before selectively depositing silicon oxide on silicon oxide relative to silicon nitride. The RF power source 614 can provide RF power of any appropriate frequency. In some embodiments, the RF power source 614 can be configured to control a high frequency RF power source and a low frequency RF power source independently of each other. Exemplary low frequency RF frequencies can include, but are not limited to, frequencies between 0kHz and 500kHz. Exemplary high frequency RF frequencies may include, but are not limited to, frequencies between 1.8 MHz and 2.45 GHz, or frequencies greater than about 13.56 MHz, or greater than 27 MHz, or greater than 40 MHz, or greater than 60 MHz. It will be appreciated that any suitable parameter may be adjusted discretely or continuously to provide plasma energy for surface reactions.

[0094] In some embodiments, the plasma can be monitored in situ by one or more plasma monitors. In one case, the plasma power can be monitored by one or more voltage and current sensors (e.g., VI probes). In another case, the plasma density and / or the concentration of the process gas can be measured by one or more optical emission spectroscopy sensors (OES). In some embodiments, one or more plasma parameters can be adjusted programmatically based on the measurement results from such in situ plasma monitors. For example, an OES sensor can be used in a feedback loop to provide programmatic control of the plasma power. It should be understood that in some embodiments, other monitors can be used to monitor the plasma and other process characteristics. Such monitors can include, but are not limited to, infrared (IR) monitors, acoustic monitors, and pressure sensors.

[0095] In some embodiments, instructions for the controller 650 may be provided via input / output control (IOC) sequencing instructions. In one example, instructions for setting conditions for a process stage may be included in a corresponding recipe stage of a process recipe. In some cases, the process recipe stages may be arranged in sequence so that all instructions for a process stage are executed simultaneously with that process stage. In some embodiments, instructions for setting one or more reactor parameters may be included in a recipe stage. For example, a first recipe stage may include instructions for setting the flow rate of a copper sealant gas or a metal sealant gas, instructions for setting the flow rate of a carrier gas (e.g., argon), instructions for igniting the plasma, and time delay instructions for the first recipe stage. A second recipe stage may include instructions for setting the flow rate of an inert gas and / or an aminosilane silicon precursor gas, instructions for setting the flow rate of a carrier gas (e.g., argon), and time delay instructions for the second recipe stage. A subsequent third recipe stage may include instructions for adjusting or stopping the flow rate of an inert gas and / or a reactant gas, instructions for adjusting the flow rate of a carrier gas or a purge gas, and time delay instructions for the third recipe stage. The fourth recipe stage may include instructions for adjusting the flow rate of the weak oxidizer gas, instructions for igniting the plasma, instructions for adjusting the flow rate of the carrier or purge gas, and time delay instructions for the fourth recipe stage. The following fifth recipe stage may include instructions for adjusting or stopping the flow rate of the inert gas and / or the reactant gas, and instructions for adjusting the flow rate of the carrier or purge gas, and time delay instructions for the fifth recipe stage. The sixth recipe stage may include instructions for adjusting the flow rate of the reducing agent gas, instructions for igniting the plasma, instructions for adjusting the flow rate of the carrier gas, and time delay instructions for the sixth recipe stage. It should be understood that within the scope of the presently disclosed embodiments, these recipe stages may be further subdivided and / or repeated in any appropriate manner. In some embodiments, the controller 650 may include the following instructions regarding Figure 7 Any features described for the system controller 750.

[0096] As described above, one or more processing stations may be included in a multi-station processing tool. Figure 7A schematic diagram of one embodiment of a multi-station processing tool 700 is shown having an inbound load lock 702 and an outbound load lock 704, either or both of which may include a remote plasma source. A robot 706 at atmospheric pressure is configured to move wafers from a cassette loaded via a wafer boat 708 into the inbound load lock 702 via an atmospheric port 710. The wafer is placed on a pedestal 712 in the inbound load lock 702 by the robot 706, the atmospheric port 710 is closed, and the load lock is evacuated. In addition, the wafer may also be heated in the inbound load lock 702, for example to remove moisture and adsorbed gases. Next, a chamber transfer port 716 to a processing chamber 714 is opened, and another robot (not shown) places the wafer into the reactor on a pedestal at the first station shown in the reactor for processing. Although in Figure 7 The embodiment depicted in FIG includes a load lock, but it should be understood that in some embodiments, wafers may be allowed to enter the processing station directly.

[0097] The depicted processing chamber 714 contains four processing stations. Figure 7 The stations are numbered 1 to 4 in the illustrated embodiment. Each station has a heated susceptor (shown as 718 for station 1) and a gas line inlet. It should be understood that in some embodiments, each processing station can have different or multiple uses. For example, in some embodiments, the processing station can be switchable between ALD and plasma-enhanced ALD processing modes. Additionally or alternatively, in some embodiments, the processing chamber 714 can include one or more matched pairs of ALD and plasma-enhanced ALD processing stations. Although the processing chamber 714 is depicted as including 4 stations, it should be understood that a processing chamber according to the present disclosure can have any suitable number of stations. For example, in some embodiments, the processing chamber can have 5 or more stations, while in other embodiments, the processing chamber can have 3 or fewer stations.

[0098] Figure 7 One embodiment of a wafer handling system 790 for transporting wafers within the processing chamber 714 is depicted. In some embodiments, the wafer handling system 790 can transport wafers between various processing stations and / or between a processing station and a load lock. It should be understood that any suitable wafer handling system can be employed. Non-limiting examples include a wafer turntable and a robot for handling wafers. Figure 7 Also depicted is one embodiment of a system controller 750 employed to control process conditions and hardware states of the processing tool 700. The system controller 750 may include one or more memory devices 756, one or more mass storage devices 754, and one or more processors 752. The processor 752 may include a CPU or computer, analog and / or digital input / output connections, a stepper motor controller board, etc.

[0099] In some embodiments, the system controller 750 controls all activities of the processing tool 700. The system controller 750 executes system control software 758 stored in the mass storage device 754, loaded into the memory device 756, and executed on the processor 752. Alternatively, the control logic can be hard-coded in the controller 750. Application-specific integrated circuits, programmable logic devices (e.g., field programmable gate arrays, or FPGAs), etc. can be used for these purposes. In the following discussion, whether "software" or "code" is used, functionally equivalent hard-coded logic can be used instead. The system control software 758 can include instructions for controlling timing, gas mixing, gas flow rates, chamber and / or station pressures, chamber and / or station temperatures, wafer temperature, target power level, RF power level, substrate pedestal, chuck and / or pedestal position, and other parameters of the specific process performed by the processing tool 700. The system control software 758 can be configured in any suitable manner. For example, various processing tool component subroutines or control objects can be written to control the operation of the processing tool components used to perform various processing tool processes. System control software 758 may be coded in any suitable computer-readable programming language.

[0100] In some embodiments, the system control software 758 may include input / output control (IOC) sequencing instructions for controlling the various parameters described above. In some embodiments, other computer software and / or programs associated with the system controller 750 and stored in the mass storage device 754 and / or the memory device 756 may be employed. Examples of programs or program segments used for this purpose include substrate positioning programs, process gas control programs, pressure control programs, heater control programs, and plasma control programs.

[0101] The substrate positioning program may include program code for processing tool components used to load a substrate onto the pedestal 718 and control the spacing between the substrate and other parts of the processing tool 700.

[0102] The process gas control program may include code for controlling gas composition (e.g., copper sealant gas or metal sealant gas, such as ethanethiol and butanethiol, aminosilane gas, and weak oxidant gas, reducing agent gas, carrier gas, and / or purge gas, as described herein) and flow rate and optionally code for flowing gas into one or more process stations prior to deposition to stabilize the pressure in the process station. The pressure control program may include code for controlling the pressure within the process station by adjusting, for example, a throttle valve in the exhaust system of the process station, gas flow into the process station, and the like.

[0103] The heater control program may include code for controlling the flow of current to a heating unit for heating the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas (such as helium) toward the substrate.

[0104] A plasma control program may include code for setting RF power levels applied to process electrodes within one or more process stations according to embodiments herein.

[0105] The pressure control program may include code for maintaining the pressure within the reaction chamber according to embodiments herein.

[0106] In some embodiments, there may be a user interface associated with the system controller 750. The user interface may include a display screen, graphical software displays of equipment and / or process conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0107] In some embodiments, the parameters regulated by the system controller 750 may relate to process conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma conditions (e.g., RF bias power level), etc. These parameters may be provided to the user in the form of a recipe, which may be entered using the user interface.

[0108] Signals for monitoring the process can be provided from various process tool sensors via analog and / or digital input connections of the system controller 750. Signals for controlling the process can be output via analog and / or digital output connections of the process tool 700. Non-limiting examples of process tool sensors that can be monitored include mass flow controllers, pressure sensors (e.g., manometers), thermocouples, and the like. Appropriately programmed feedback and control algorithms can be used with the data from these sensors to maintain process conditions.

[0109] The system controller 750 may provide program instructions for executing the above-described deposition process. The program instructions may control various process parameters, such as DC power level, RF bias power level, pressure, temperature, etc. The instructions may control these parameters to operate the in-situ deposition of film stacks according to various embodiments described herein.

[0110] The system controller 750 will typically include one or more memory devices and one or more processors configured to execute instructions so that the apparatus will perform the methods according to the disclosed embodiments. A machine-readable medium containing instructions for controlling processing operations according to the disclosed embodiments can be coupled to the system controller 750.

[0111] In some implementations, the system controller 750 is part of a system, which can be part of the examples described above. Such a system can include a semiconductor processing apparatus comprising one or more processing tools, one or more processing chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronics for controlling their operation before, during, and after processing semiconductor wafers or substrates. The electronics can be referred to as a "controller," which can control various elements or subcomponents of one or more systems. Depending on the processing requirements and / or the type of system, the system controller 750 can be programmed to control any of the processes disclosed herein, including controlling process gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer into and out of tools and other transfer tools, and / or load locks connected to or interfaced with a specific system.

[0112] In a broad sense, the system controller 750 can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that stores program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions may be instructions transmitted to the system controller 750 in the form of various separate settings (or program files) that define operating parameters for performing specific processes on or for a semiconductor wafer or system. In some embodiments, the operating parameters may be part of a recipe defined by a process engineer for completing one or more process steps during the preparation of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0113] In some implementations, the system controller 750 may be part of or coupled to a computer that is integrated with, coupled to, or connected to the system via a network, or a combination thereof. For example, the system controller 750 may be in the "cloud" or in all or part of a fab host system, thereby enabling remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of manufacturing operations, review the history of past manufacturing operations, examine trends or performance metrics across multiple manufacturing operations, change parameters of the current process, set processing steps to follow the current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system via a network, which may include a local network or the Internet. The remote computer may include a user interface that allows for the input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, the system controller 750 receives instructions in the form of data specifying parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool, such that the system controller 750 is configured to interface with or control that tool type. Thus, as described above, the system controller 750 can be distributed, for example, by including one or more discrete controllers that are connected together via a network and work toward a common goal (e.g., the processes and controls described herein). An example of a distributed controller for these purposes can be one or more integrated circuits on the chamber that communicate with one or more remote integrated circuits (e.g., at the platform level or as part of a remote computer) that are combined to control the processes within the chamber.

[0114] Exemplary systems may include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin cleaning chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, ALD chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the preparation and / or fabrication of semiconductor wafers.

[0115] As described above, depending on the process step or steps to be performed by the tool, the system controller 750 can communicate with one or more other tool circuits or modules, other tool components, combination tools, other tool interfaces, adjacent tools, adjacent tools, tools located throughout the factory, a host computer, another controller, or materials handling tools used in moving containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0116] Suitable apparatus for performing the methods disclosed herein are further discussed and described in U.S. patent application Ser. No. 13 / 084,399, filed on April 11, 2011, entitled “PLASMA ACTIVATED CONFORMAL FILM DEPOSITION” (now U.S. Patent No. 8,728,956); and U.S. patent application Ser. No. 13 / 084,305, filed on April 11, 2011, entitled “SILICON NITRIDE FILMS AND METHODS,” each of which is incorporated herein in its entirety.

[0117] The apparatus / processes described herein can be used in conjunction with photolithographic patterning tools or processes, e.g., for preparing or manufacturing semiconductor devices, displays, LEDs, photovoltaic panels, etc. Typically, though not necessarily, these tools / processes will be used or operated together in a common manufacturing facility. Photolithographic patterning of films typically includes some or all of the following operations, each of which utilizes multiple available tools: (1) applying photoresist to a workpiece (i.e., substrate) using a spin coating or spray coating tool; (2) curing the photoresist using a hot plate or oven or UV curing tool; (3) exposing the photoresist to visible light or ultraviolet light or x-rays using a tool such as a wafer stepper; (4) developing the resist to selectively remove the resist and thereby pattern it using a tool such as a wet bench; (5) transferring the resist pattern to an underlying film or workpiece using a dry or plasma assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.

[0118] experiment

[0119] Experiment 1

[0120] Experiments were conducted on a silicon oxide surface and on a copper surface alone to evaluate silicon oxide growth using SAM24 on both surfaces using cycles of silicon oxide deposition and reducing agent exposure. The silicon oxide surface was exposed to 35 cycles of the following: a 1 second dose of SAM24, a 16 second argon purge, a 10 second flow of weak oxidizers CO2 and argon, a 1 second pulse of CO2 and argon using a 50W plasma, a 16 second argon purge, a 30 second 50W plasma generated reducing agent hydrogen plasma and argon, and a 30 second argon purge. The experiments showed The results show that the hydrogen / argon plasma does not affect the deposition of silicon oxide, because the previous experiment was performed, which involved 25 cycles of deposition cycles, namely a 1 second dose of SAM24, a 16 second argon purge, a 10 second flow of weak oxidizer CO2 and argon, and a 1 second CO2 and argon pulse using a 50W plasma with a 16 second argon purge, which showed The copper surface was exposed to an argon / hydrogen plasma reduction for 30 cycles, followed by 30 cycles of the following deposition cycles: a 1 second dose of SAM24, a 16 second argon purge, a 10 second flow of weak oxidizer CO2 and argon, a 1 second CO2 and argon pulse using a 50W plasma, a 16 second argon purge, a 30 second 50W plasma generated reducing agent hydrogen plasma and argon, and a 30 second argon purge. The growth rate seen on the copper surface was / loop. Figure 8A and 8B The results depicted in Figure 8 (8A shows the entire cycle, while 8B shows a magnified cross-section of two cycles in particular) indicate that the hydrogen plasma reduced the copper oxide, but not sufficiently. The higher growth rate exhibited is likely due to the different adsorption / nucleation behaviors on copper and silicon oxide.

[0121] Experiment 2

[0122] Experiments were conducted on a silicon oxide surface and on a copper surface alone to evaluate the growth of silicon oxide on both surfaces using SAM 24 using cycles of thiol exposure, silicon oxide deposition, and reducing agent exposure.

[0123] Both the silicon oxide surface and the copper surface were pretreated with an argon / hydrogen plasma and then subjected to 100 cycles of the following deposition cycles:

[0124] (1) 2-second dose of butanethiol

[0125] (2) Use argon gas to purge for 10 seconds

[0126] (3) 1 second dose of SAM24

[0127] (4) Use argon gas to purge for 16 seconds

[0128] (5) Weak oxidant CO2 and argon flow for 10 seconds

[0129] (6) 1 second CO2 and argon pulses using 50W plasma

[0130] (7) Use argon gas to purge for 16 seconds

[0131] (8) Using 50W plasma to generate reducing agent hydrogen plasma and argon for 30 seconds

[0132] (9) Purge with argon for 30 seconds.

[0133] Figure 9A and 9B The oxide thickness is shown for all cycles and for a single cycle, respectively, with the reference numbers in the cycle corresponding to the reference numbers in the deposition cycle above. Figure 9C and 9D The thickness on the copper surface is shown for all cycles and two cycles, respectively, with the reference numbers in the cycles corresponding to the reference numbers in the above deposition cycles.

[0134] The experiments showed some loading effect on the silicon oxide surface during the initial cycles, but then the silicon oxide continued to grow at a linear and steady rate. Figure 9B In FIG. 901 , the effect of SAM 24 adsorption onto the substrate surface during the deposition cycle is shown. The measured thickness also shows that Figure 9D There is a clear inhibition of SAM-24 adsorption on copper during the 1 second dose of SAM-24 indicated in the circled portion 903. The results also show that growth on copper is arrested after the initial thiol loading.

[0135] Table 1 below summarizes the measured silicon oxide thicknesses on silicon oxide and copper surfaces, the silicon oxide actually deposited on each surface, and their relative selectivities.

[0136] Table 1. Silicon oxide growth on silicon oxide and copper surfaces

[0137]

[0138] in conclusion

[0139] Although the above embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways to implement the processes, systems, and apparatus of the embodiments of the present invention. Therefore, the embodiments of the present invention are to be considered as illustrative rather than restrictive, and the embodiments of the present invention should not be limited to the details set forth herein.

Claims

1. A method for depositing silicon oxide on a dielectric material selectively relative to copper on a substrate, the method comprising: (a) providing the substrate comprising the dielectric material and an exposed copper metal surface; (b) before depositing the silicon oxide, exposing the substrate to a copper sealant to selectively adsorb the copper sealant onto the exposed copper metal surface; (c) exposing the substrate to a silicon-containing precursor so that the silicon-containing precursor is adsorbed onto the dielectric material; (d) exposing the substrate to an oxidizing plasma generated in an environment containing a weak oxidant to convert the adsorbed silicon-containing precursor into silicon oxide; and (e) exposing the substrate to a reducing agent to reduce the exposed copper metal surface, The reducing agent is selected from the group consisting of hydrogen gas, hydrogen plasma, hydrazine gas, hydrazine plasma, ammonia gas, ammonia plasma, alcohol and aldehyde.

2. The method according to claim 1, wherein The copper sealer comprises sulfur.

3. The method according to claim 1, wherein The copper blocking agent is an alkylthiol.

4. The method according to claim 3, wherein: The copper sealant is selected from ethanethiol and butanethiol.

5. The method according to claim 1, wherein The copper sealant has the chemical formula SH(CH2) n Alkylthiols of CH3, wherein n is an integer between 2 and 12, inclusive.

6. The method of claim 1, further comprising introducing a second reducing agent to reduce the exposed copper metal surface before exposing the substrate to the copper sealant.

7. The method of claim 6, wherein the second reducing agent is selected from the group consisting of hydrogen gas, hydrogen plasma, hydrazine gas, hydrazine plasma, ammonia gas, ammonia plasma, alcohols, and aldehydes.

8. The method according to any one of claims 1 to 7, wherein the silicon-containing precursor is an aminosilane.

9. The method according to any one of claims 1 to 7, wherein the silicon-containing precursor is selected from the group consisting of N-(diethylaminosilyl)-N-ethylethylamine, bis(diethylamino)silane (BDEAS), diisopropylaminosilane (DiPAS), diisobutylaminosilane (DiBAS), bis(tert-butylamino)silane (BTBAS) and tris(dimethylamino)silane (TDMAS).

10. The method according to any one of claims 1 to 7, wherein The weak oxidant is selected from the group consisting of carbon dioxide, nitrous oxide, ozone, plasma thereof and water.

11. The method according to any one of claims 1 to 7, wherein The silicon oxide is deposited at a temperature between about 70°C and about 200°C.

12. The method according to any one of claims 1 to 7, wherein The dielectric material is selected from the group consisting of silicon dioxide, aluminum oxide, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

13. The method according to any one of claims 1 to 7, further comprising repeating operations (b) to (e) in two or more cycles.

14. The method according to any one of claims 1 to 7, wherein (c) is self-limiting.

15. The method of any one of claims 1 to 7, wherein the copper sealant preferentially adsorbs onto the exposed copper metal surface to prevent subsequent deposition of the silicon oxide on the exposed copper metal surface.

16. A method of selectively depositing silicon oxide on a dielectric material relative to a metal-containing surface on a substrate, the method comprising: (a) providing the substrate comprising the dielectric material and an exposed metal-containing surface; (b) prior to depositing the silicon oxide, exposing the substrate to a metal blocking agent to selectively adsorb the metal blocking agent onto the exposed metal-containing surface; (c) exposing the substrate to a silicon-containing precursor so that the silicon-containing precursor is adsorbed onto the dielectric material; (d) exposing the substrate to an oxidizing plasma generated in an environment containing a weak oxidant to convert the adsorbed silicon-containing precursor into silicon oxide; and (e) exposing the substrate to a reducing agent to reduce the exposed metal-containing surface, The reducing agent is selected from the group consisting of hydrogen gas, hydrogen plasma, hydrazine gas, hydrazine plasma, ammonia gas, ammonia plasma, alcohol and aldehyde.

17. The method according to claim 16, wherein The exposed metal-containing surface comprises copper.

18. The method according to claim 16, wherein The exposed metal-containing surface comprises a material selected from the group consisting of copper metal, copper oxide, ruthenium metal, and ruthenium oxide.

19. A method of selectively depositing silicon oxide on a dielectric material relative to a metal-containing surface on a substrate, the method comprising: (a) providing the substrate comprising the dielectric material and an exposed metal-containing surface; (b) prior to depositing the silicon oxide, exposing the substrate to a metal blocking agent to selectively adsorb the metal blocking agent onto the exposed metal-containing surface; (c) exposing the substrate to a silicon-containing precursor so that the silicon-containing precursor is adsorbed onto the dielectric material; (d) exposing the substrate to an oxidizing plasma generated in an environment containing a weak oxidant to convert the adsorbed silicon-containing precursor into silicon oxide; and (e) exposing the substrate to a reducing agent to reduce the exposed metal-containing surface, Wherein, the exposed metal-containing surface comprises ruthenium.

20. An apparatus for processing a semiconductor substrate, the apparatus comprising: at least one processing chamber comprising a susceptor for holding a semiconductor substrate; at least one outlet for coupling to a vacuum; plasma generator; one or more process gas inlets coupled to one or more gas sources; and A controller for controlling operations in the apparatus, comprising machine-readable instructions for: Prior to depositing silicon oxide, exposing the semiconductor substrate to a copper sealant to selectively adsorb onto exposed copper metal surfaces; exposing the substrate to a silicon-containing precursor to adsorb the silicon-containing precursor onto a dielectric material on the semiconductor substrate; exposing the substrate to an oxidizing plasma generated in an environment containing a weak oxidant to convert the adsorbed silicon-containing precursor to deposit silicon oxide; and exposing the substrate to a reducing agent to reduce the exposed copper metal surface, The reducing agent is selected from the group consisting of hydrogen gas, hydrogen plasma, hydrazine gas, hydrazine plasma, ammonia gas, ammonia plasma, alcohol and aldehyde.

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