Image sensor and method for manufacturing the same

Abstract

An image sensor and a method for manufacturing the same are provided, the image sensor comprising: a plurality of color filters spaced apart from each other on a semiconductor substrate; a protective layer covering side walls of the color filters and a top surface of the color filters; and a low-refractive pattern filling spaces between the color filters.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The entire contents of Korean Patent Application No. 10-2019-0000914, entitled “Image Sensor and Method of Fabricating the Same,” filed on January 3, 2019 in the Korean Intellectual Property Office are incorporated herein by reference. Technical Field

[0003] Embodiments relate to image sensors and methods of manufacturing the same. Background Art

[0004] Image sensors are semiconductor devices that convert optical images into electrical signals. Image sensors can be divided into charge coupled device (CCD) type and complementary metal oxide semiconductor (CMOS) type. CMOS type image sensors are abbreviated as CIS (CMOS image sensor). CIS has multiple pixels arranged in two dimensions. Each pixel includes a photodiode. Photodiodes are used to convert incident light into electrical signals. Summary of the invention

[0005] An embodiment may be implemented by providing an image sensor comprising: a plurality of color filters spaced apart from each other on a semiconductor substrate; a protective layer covering sidewalls and top surfaces of the color filters; and a low-refractive pattern filling spaces between the color filters.

[0006] An embodiment can be implemented by providing an image sensor, which includes: a semiconductor substrate having a plurality of unit pixel regions; a deep device isolation portion, which is located between the plurality of unit pixel regions; a photoelectric conversion portion, which is located in the semiconductor substrate of each of the unit pixel regions; a plurality of color filters, which are spaced apart from each other on the semiconductor substrate; a shading pattern, which is located on the semiconductor substrate and between the color filters, and the thickness of the shading pattern is less than the thickness of the color filters; a low refraction pattern, which fills the space between the color filters; and a protective layer, which is located between the low refraction pattern and the color filter and between the low refraction pattern and the shading pattern.

[0007] An embodiment can be implemented by providing an image sensor comprising: a plurality of filters spaced apart from each other on a semiconductor substrate; a low-refractive pattern filling a space between the filters; and a shading pattern located between the low-refractive pattern and the semiconductor substrate.

[0008] An embodiment may be implemented by providing a method for manufacturing an image sensor, the method comprising: forming a plurality of sacrificial patterns on a semiconductor substrate to define a plurality of color filter regions; forming a plurality of color filters in the plurality of color filter regions, respectively; and replacing the sacrificial patterns with low-refractive patterns. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 A cross-sectional view of an image sensor according to some example embodiments is illustrated.

[0011] Figure 2A and Figure 2B Shows Figure 1 Magnified view of section II.

[0012] Figures 3A to 3G Shown are some examples of manufacturing Figure 1 A cross-sectional view of various stages in the method of manufacturing an image sensor.

[0013] Figure 4 A cross-sectional view of an image sensor according to some example embodiments is illustrated.

[0014] Figure 5 A cross-sectional view of an image sensor according to some example embodiments is illustrated.

[0015] Figure 6 A cross-sectional view of an image sensor according to some example embodiments is illustrated. DETAILED DESCRIPTION

[0016] Figure 1 A cross-sectional view of an image sensor according to some example embodiments is illustrated. Figure 2A and Figure 2B Shows Figure 1 Magnified view of section II.

[0017] Reference Figure 1 , Figure 2A and Figure 2B, the image sensor 100 according to the present embodiment may include a semiconductor substrate 1. The semiconductor substrate 1 may be a single crystal silicon wafer or an epitaxial silicon layer. The semiconductor substrate 1 may be doped with impurities having a first conductivity type. In one embodiment, the first conductivity type may be a p-type and the impurity may be boron. The semiconductor substrate 1 may have a first surface 1a and a second surface 1b facing each other along a second direction D2.

[0018] The semiconductor substrate 1 may include a plurality of unit pixel regions UP. The semiconductor substrate 1 may be provided with a deep device isolation portion 13 that separates the unit pixel regions UP from each other along a first direction D1. The deep device isolation portion 13 may be located in a deep trench 7. The deep trench 7 may extend from the second surface 1b toward the first surface 1a. As the deep trench 7 approaches the first surface 1a from the second surface 1b (e.g., in the depth direction), the width of the deep trench 7 may decrease. The deep device isolation portion 13 may include a fixed charge layer 9 (conformally covering the sidewalls of the deep trench 7) and a buried dielectric layer 11 (filling, for example, the rest of the deep trench 7).

[0019] The fixed charge layer 9 may have a negative fixed charge. The fixed charge layer 9 may include a metal oxide or a metal fluoride, which may include, for example, hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y) or a lanthanide. For example, the fixed charge layer 9 may be a hafnium oxide layer or an aluminum oxide layer. Hole accumulation may occur around the fixed charge layer 9. Therefore, dark current and white spots may be effectively reduced. The buried dielectric layer 11 may be formed by a dielectric layer (e.g., a silicon oxide layer) having excellent step coverage. In one embodiment, the deep device isolation portion 13 may have a grid shape observed in a top view. The fixed charge layer 9 may extend onto the second surface 1b and contact the second surface 1b. The buried dielectric layer 11 may also extend onto the second surface 1b along the first direction D1.

[0020] In one embodiment, the photoelectric conversion portion PD may be located on each unit pixel region UP (defined by the deep device isolation portion 13) or in the semiconductor substrate 1 at each unit pixel region UP. The photoelectric conversion portion PD may be a region doped with an impurity having a second conductivity type opposite to the first conductivity type. For example, the photoelectric conversion portion PD may be doped with n-type arsenic or phosphorus. The photoelectric conversion portion PD and the semiconductor substrate 1 surrounding it may form a pn junction to constitute a photodiode.

[0021] In one embodiment, the semiconductor substrate 1 may include, for example, a transfer transistor, a reset transistor, a source follower transistor, and a selection transistor located on its first surface 1a, through which the charge generated from the photoelectric conversion part PD is transferred. In one embodiment, the first surface 1a of the semiconductor substrate 1 may be covered with an interlayer dielectric layer 5. The interlayer dielectric layer 5 may have a single-layer structure or a multi-layer structure, and the single-layer structure or the multi-layer structure includes one or more of a silicon oxide layer, a silicon oxynitride layer, and / or a silicon nitride layer. In one embodiment, a plurality of connection lines may be located in the interlayer dielectric layer 5.

[0022] The semiconductor substrate 1 may include a device isolation region 3, which is adjacent to (e.g., directly in contact with) the first surface 1a and overlaps with the deep device isolation portion 13 along the second direction D2. The device isolation region 3 may be doped with impurities having a first conductivity type. The concentration of the first conductivity type impurities doped in the device isolation region 3 may be greater than the concentration of the first conductivity type impurities doped in the semiconductor substrate 1.

[0023] The auxiliary dielectric layer 15 may be located on the buried dielectric layer 11 on the second surface 1b of the semiconductor substrate 1. The auxiliary dielectric layer 15 may include one or more of an anti-reflection layer or a planarization layer. The auxiliary dielectric layer 15 may include one or more of a silicon nitride layer or an organic dielectric layer.

[0024] The auxiliary dielectric layer 15 may include a first color filter CF1 and a second color filter CF2 alternately arranged along the first direction D1. The first color filter CF1 and the second color filter CF2 may have an island shape spaced apart from each other (e.g., completely spaced apart) so that the color filters CF1 and CF2 have an island shape in a top view. In a top view, the first color filter CF1 and the second color filter CF2 may be located between the low refractive patterns 25a arranged in a grid shape. The first color filter CF1 and the second color filter CF2 may include dyes or pigments having different colors from each other. The first color filter CF1 and the second color filter CF2 may filter light having a specific wavelength. The first color filter CF1 and the second color filter CF2 may also be referred to as optical filters. In one embodiment, the first color filter CF1 and the second color filter CF2 may be infrared filters.

[0025] The protective layer 23 may cover the sidewalls and top surface of the first color filter CF1 (e.g., the surface facing away from the semiconductor substrate 1) and the sidewalls and top surface of the second color filter CF2. The protective layer 23 may have a single-layer structure or a multi-layer structure. The protective layer 23 may include one or more of an aluminum oxide layer and a silicon oxycarbide layer (e.g., a single-layer aluminum oxide, a single-layer silicon oxycarbide, a multi-layer structure including an aluminum oxide layer, a multi-layer structure including a silicon oxycarbide layer, or a multi-layer structure including an aluminum oxide layer and a silicon oxycarbide layer).

[0026] like Figure 2B As shown, the portion of the protective layer 23 located on the sidewall of the first color filter CF1 and the sidewall of the second color filter CF2 may have a first thickness T1 along the first direction D1, and the portion of the protective layer 23 located on the top surface of the first color filter CF1 and the top surface of the second color filter CF2 may have a second thickness T2 along the second direction D2. The first thickness T1 may be equal to or greater than the second thickness T2. The protective layer 23 may have, for example, about to about In one embodiment, the first thickness T1 may be, for example, about to about The protective layer 23 may protect the first color filter CF1 and the second color filter CF2 from being damaged and from absorbing moisture. As a result, the reliability of the image sensor 100 may be improved.

[0027] The shading pattern 17a may be located on the auxiliary dielectric layer 15 and between the first color filter CF1 and the second color filter CF2. When in a top view, the shading pattern 17a may have a grid shape. In one embodiment, the shading pattern 17a may include, for example, titanium. The shading pattern 17a may have a third thickness T3 along the second direction D2. The sidewalls of the shading pattern 17a may be aligned with the sidewalls of the adjacent color filters in the first color filter CF1 and the second color filter CF2. The shading pattern 17a may help prevent bruise defects (e.g., an image is partially viewed as blue), which may achieve clear image quality.

[0028] The low refraction pattern 25a may fill the space between the first color filter CF1 and the second color filter CF2. The refractive index of the low refraction pattern 25a may be less than the refractive index of the first color filter CF1 and the refractive index of the second color filter CF2. The refractive index of the low refraction pattern 25a may be, for example, equal to or less than about 1.3. The low refraction pattern 25a may include an organic material. The low refraction pattern 25a may have a fourth thickness T4 along the second direction D2. The fourth thickness T4 may be greater than the third thickness T3. The protective layer 23 may be located between the low refraction pattern 25a and the first color filter CF1 and the second color filter CF2 and between the low refraction pattern 25a and the light shielding pattern 17a. The top surface of the low refraction pattern 25a may be coplanar with the top surface of the protective layer 23. The width of the low refraction pattern 25a along the first direction D1 may be less than the width of the light shielding pattern 17a along the first direction D1. The low refraction pattern 25a and the light shielding pattern 17a may overlap vertically with the deep device isolation portion 13.

[0029] The microlens ML may be located on the protective layer 23. The microlens ML may overlap with corresponding ones of the first and second color filters CF1 and CF2 along the second direction D2. The microlenses ML may each contact (eg, directly contact) the top surface of the protective layer 23 and the top surface of the low-refractive pattern 25a.

[0030] In the image sensor 100 according to the present embodiment, the refractive index of the low refraction pattern 25a may be smaller than the refractive index of the first color filter CF1 and the refractive index of the second color filter CF2. Therefore, when the first light L1 is incident on the edge of the first color filter CF1 and the edge of the second color filter CF2 adjacently, the first light L1 may be refracted from the surface of the low refraction pattern 25a and then may travel to the photoelectric conversion portion PD located on the relevant unit pixel area UP. In addition, the refractive index of the low refraction pattern 25a may be equal to or less than about 1.3, and when the second light L2 is incident on the top surface of the low refraction pattern 25a, the second light L2 may be refracted from the top surface of the low refraction pattern 25a and then may travel to the photoelectric conversion portion PD located on the relevant unit pixel area UP.

[0031] Therefore, the photoelectric conversion portion PD can receive an increased amount of light incident thereon, which can improve light receiving efficiency, and in turn can improve brightness efficiency. As a result, a signal-to-noise ratio (SNR) can be improved. The protective layer 23 can have a thickness equal to or less than about 100 nm between the low-refractive pattern 25a and the first and second color filters CF1 and CF2. The thickness is small, and thus the impact on the paths of the first light L1 and the second light L2 may be slight or no.

[0032] Figures 3A to 3G The manufacturing method according to some example embodiments is shown Figure 1 A cross-sectional view of each stage in the image sensor process.

[0033] Reference Figure 3A , a semiconductor substrate 1 having a first surface 1a and a second surface 1b facing each other may be prepared. An ion implantation process may be performed to form a device isolation region 3 adjacent to the first surface 1a in the semiconductor substrate 1. A photoelectric conversion portion PD may be formed in the semiconductor substrate 1. In one embodiment, a transistor may be formed on the semiconductor substrate 1. An interlayer dielectric layer 5 may be formed to cover the first surface 1a of the semiconductor substrate 1. In one embodiment, a multilayer connection line may be formed in the interlayer dielectric layer 5.

[0034] The semiconductor substrate 1 may be etched along the second direction D2 from the second surface 1b toward the first surface 1a to form a deep trench 7. A fixed charge layer 9 may be conformally formed on the entire second surface 1b to cover the sidewalls and bottom surface of the deep trench 7, and a buried dielectric layer 11 may be formed to fill, for example, the remaining portion of the deep trench 7. Therefore, a deep device isolation portion 13 including the fixed charge layer 9 and the buried dielectric layer 11 may be provided in the deep trench 7. An auxiliary dielectric layer 15 may be formed on the buried dielectric layer 11.

[0035] A light shielding layer 17 and a sacrificial layer 19 may be sequentially stacked on the auxiliary dielectric layer 15 along the second direction D2. In one embodiment, the light shielding layer 17 may be formed of, for example, titanium. The sacrificial layer 19 may be formed of, for example, one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, etc. using a deposition process (e.g., chemical vapor deposition, physical vapor deposition, etc.). The sacrificial layer 19 may be formed to have a thickness suitable for the optical characteristics of the first color filter CF1 and the optical characteristics of the second color filter CF2, which will be discussed below.

[0036] Reference Figure 3B , a mask pattern may be formed on the sacrificial layer 19. The mask pattern may include a photoresist pattern or any pattern whose material has an etching selectivity relative to the sacrificial layer 19. The mask pattern may be used as an etching mask for an anisotropic etching process, by which the sacrificial layer 19 and the light shielding layer 17 may be anisotropically etched in sequence to expose the auxiliary dielectric layer 15. The above processes may form a sacrificial pattern 19a that defines a color filter region CFR, and also form a light shielding pattern 17a located below the sacrificial pattern 19a. In one embodiment, the sacrificial pattern 19a and the light shielding pattern 17a may have a grid shape in a top view.

[0037] Reference Figure 3B and Figure 3C , the first color filter CF1 and the second color filter CF2 may be formed in the corresponding color filter region CFR. The first color filter CF1 and the second color filter CF2 may be formed by performing a photolithography process several times. For example, the photolithography process may include a coating process performed on a photoresist composition including a dye or a pigment, a soft baking process, an exposure process, a post-baking process, a developing process, etc.

[0038] Reference Figure 3D , the sacrificial pattern 19a may be removed to expose the space 21 between the first color filter CF1 and the second color filter CF2. When the sacrificial pattern 19a is formed of a silicon oxide layer, the sacrificial pattern 19a may be removed using an etchant including, for example, fluorine. The space 21 may expose the top surface of the light shielding pattern 17a and the sidewalls of the first color filter CF1 and the second color filter CF2.

[0039] Reference Figure 3E , the protective layer 23 can be conformally formed on the entire second surface 1b of the semiconductor substrate 1. Figure 2B As shown, the protective layer 23 may be formed to have a first thickness T1. The protective layer 23 may be formed as a single layer or multiple layers including, for example, one or more of an aluminum oxide layer or a silicon oxycarbide layer. The protective layer 23 may be formed by chemical vapor deposition or atomic layer deposition. The protective layer 23 may be deposited at a temperature below about 200°C to help prevent damage to the first color filter CF1 and the second color filter CF2, both of which include organic materials. For example, when the protective layer 23 is formed of an aluminum oxide layer, the protective layer 23 may be deposited at a temperature of about 100°C. When the protective layer 23 is formed of a silicon oxycarbide layer, the protective layer 23 may be deposited at a temperature of about 150°C.

[0040] Reference Figure 3E and Figure 3F , a low-refractive layer 25 may be formed on the protective layer 23 to fill the space 21. The low-refractive layer 25 may include an organic material. For example, the formation of the low-refractive layer 25 may include performing a step of spin coating a composition including an organic material and a solvent on the protective layer 23 and performing a step of removing the solvent by a soft baking process or a dry process.

[0041] Reference Figure 3G , a blanket etch-back process or a polishing process may be performed to remove the low refractive layer 25 from the top surfaces of the color filters CF1 and CF2 so that the protective layer 23 may be exposed and a low refractive pattern 25a may be formed between the first color filter CF1 and the second color filter CF2. The protective layer 23 located on the top surfaces of the first color filter CF1 and the second color filter CF2 may also be partially etched to have a low refractive pattern 25a. Figure 2B The second thickness T2 shown. In contrast, the protective layer 23 may not be etched between the color filters CF1 and CF2, and thus may maintain its initial first thickness T1. The second thickness T2 may be equal to or less than the first thickness T1. The protective layer 23 may help protect the first color filter CF1 and the second color filter CF2 from damage. Subsequently, as shown Figure 1 As shown, micro lenses ML may be formed on the protective layer 23 .

[0042] In the method of manufacturing an image sensor according to an embodiment, the sacrificial layer 19 can be formed of a silicon oxide layer or the like widely used in semiconductor manufacturing, so that an etchant for deposition thickness adjustment and anisotropic etching processes can be easily selected. Subsequently, the sacrificial pattern 19a having a grid shape can be formed to have a precise critical dimension, so that the first color filter CF1 and the second color filter CF2 can be formed at regular intervals. In addition, the sacrificial pattern 19a can have a desired thickness (or a determined thickness of the first color filter CF1 and the second color filter CF2), so that the first color filter CF1 and the second color filter CF2 can be formed to have a desired profile.

[0043] If the color filter is manufactured by forming a grid-shaped low-refractive pattern from a low-refractive layer instead of forming a sacrificial pattern from a silicon oxide layer, the material properties of the low-refractive layer may make it difficult to form a low-refractive layer with a desired thickness and also difficult to perform an anisotropic etching process. In this case, it is impossible to form a properly shaped color filter and to form a refractive pattern with an accurate critical dimension.

[0044] In the method of manufacturing an image sensor according to an embodiment, the sacrificial layer 19 and the light shielding layer 17 may be sequentially etched to form a sacrificial pattern 19a and a light shielding pattern 17a, and then the sacrificial pattern 19a may be replaced with a low-refractive pattern 25a, with the result that the low-refractive pattern 25a and the light shielding pattern 17a may simply overlap each other vertically without misalignment. For example, an image sensor capable of improving luminous efficiency and achieving clear image quality may be provided.

[0045] Figure 4 A cross-sectional view of an image sensor according to some example embodiments is illustrated.

[0046] Reference Figure 4 , the image sensor 101 according to the present embodiment may be, for example, an autofocus image sensor. In the image sensor 101, the deep device isolation portion 13 may separate the unit pixel regions UP from each other, and the sub-deep device isolation portion 13s may extend along the second direction D2 to divide each unit pixel region UP into a first sub-pixel region SP1 and a second sub-pixel region SP2 along the first direction D1. The first photoelectric conversion portion PD1 may be located in the semiconductor substrate 1 on or at the first sub-pixel region SP1. The second photoelectric conversion portion PD2 may be located in the semiconductor substrate 1 on or at the second sub-pixel region SP2.

[0047] The sub-deep device isolation portion 13s may be located between the first photoelectric conversion portion PD1 and the second photoelectric conversion portion PD2. The sub-deep device isolation portion 13s may overlap the center of one of the color filters CF1 and CF2.

[0048] Similar to the deep device isolation portion 13, the sub-deep device isolation portion 13s may include a fixed charge layer 9 and a buried dielectric layer 11. The semiconductor substrate 1 may include, for example, a first transfer gate electrode TG1 and a second transfer gate electrode TG2 spaced apart from each other in the first direction D1 directly on and below the first surface 1a thereof. The first transfer gate electrode TG1 may be located in the first sub-pixel region SP1, and the second transfer gate electrode TG2 may be located in the second sub-pixel region SP2. A floating diffusion region FD may be located in the semiconductor substrate 1 between the first transfer gate electrode TG1 and the second transfer gate electrode TG2. Other configurations may be the same as those described with reference to FIG. Figure 1 , Figure 2A and Figure 2B The constructions in question are the same or similar.

[0049] Figure 5 A cross-sectional view of an image sensor according to some example embodiments is illustrated.

[0050] Reference Figure 5 , the image sensor 102 according to the present embodiment may include a shallow device isolation portion 2 adjacent to the first surface 1a of the semiconductor substrate 1 (e.g., directly located on the first surface 1a of the semiconductor substrate 1). The shallow device isolation portion 2 may define an active area for a transistor on the first surface 1a. The shallow device isolation portion 2 may be formed by a shallow trench isolation (STI) process. The shallow device isolation portion 2 may have a single-layer structure or a multi-layer structure, and the single-layer structure or the multi-layer structure includes one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The deep trench 7 may penetrate the shallow device isolation portion 2 and the semiconductor substrate 1. The width of the deep trench 7 may decrease in a direction approaching the second surface 1b from the first surface 1a.

[0051] The deep device isolation portion 53 may be located in the deep trench 7. The deep device isolation portion 53 may include a polysilicon pattern 51 doped with impurities and a dielectric layer 55 surrounding the sidewalls of the polysilicon pattern 51. The deep device isolation portion 53 may contact the auxiliary dielectric layer 15. The thermal expansion coefficient of the polysilicon pattern 51 may be almost the same as that of the semiconductor substrate 1 made of single crystal silicon, which may help reduce the physical stress caused by the difference in the thermal expansion coefficient of the material. The polysilicon pattern 51 may be used as a common bias line. A negative voltage may be provided to the polysilicon pattern 51. For example, since holes that may exist on the surface of the deep trench 7 are maintained, dark current characteristics may be improved.

[0052] The auxiliary dielectric layer 15 may contact the second surface 1b of the semiconductor substrate 1, for example, may be directly located on the second surface 1b. The auxiliary dielectric layer 15 may include, for example, a fixed charge layer, an anti-reflection layer, and a planarization layer sequentially stacked along the second direction D2, and the fixed charge layer may contact the second surface 1b. The first surface 1a of the semiconductor substrate 1 may be covered (for example, completely covered) by the interlayer dielectric layer 5. The deep device isolation portion 53 may be spaced apart from the interlayer dielectric layer 5 and the shallow device isolation portion 2. The deep trench 7 may include an auxiliary buried dielectric layer 4 located between the deep device isolation portion 53 and the interlayer dielectric layer 5. The shallow device isolation portion 2 may surround the auxiliary buried dielectric layer 4 and may be shorter along the first direction D1. Other configurations may be similar to those described with reference to FIG. Figure 1 , Figure 2A and Figure 2B The constructions in question are the same or similar.

[0053] Figure 6 A cross-sectional view of an image sensor according to some example embodiments is illustrated.

[0054] Reference Figure 6 , the image sensor 103 according to the present embodiment may include a through electrode 57 located in the semiconductor substrate 1. The through electrode 57 may be insulated from the polysilicon pattern 51 of the deep device isolation portion 53. The through electrode 57 may be surrounded by a first via dielectric layer 59. The through electrode 57 and the first via dielectric layer 59 may be located in a through electrode hole 7h in the semiconductor substrate 1. The transfer gate electrode TG may be located on the first surface 1a of the semiconductor substrate 1.

[0055] The transfer gate electrode TG may extend along a portion of the first surface 1a of the semiconductor substrate 1 in a first direction D1, and may extend toward the second surface 1b of the semiconductor substrate 1 in a second direction D2. The first floating diffusion region FD1 may be located in the semiconductor substrate 1 adjacent to the transfer gate electrode TG. The semiconductor substrate 1 may include a second floating diffusion region FD2, which is spaced apart from the first floating diffusion region FD1 in the first direction D1 by a shallow device isolation portion 2 that does not surround the auxiliary buried dielectric layer 4. The first photoelectric conversion portion PD1 may be located in the semiconductor substrate 1 on or at each unit pixel region UP. The first photoelectric conversion portion PD1 may be a region doped with impurities having a second conductivity type.

[0056] The auxiliary dielectric layer 15 may be located on the second surface 1b of the semiconductor substrate 1. At each unit pixel region UP, one of the color filters CF1 and CF2 may be included on the auxiliary dielectric layer 15. The light shielding pattern 17a may be located on the auxiliary dielectric layer 15 between the first color filter CF1 and the second color filter CF2. The protective layer 23 may cover the top and sidewall of the first color filter CF1, the top and sidewall of the second color filter CF2, and the top surface of the light shielding pattern 17a. The low refractive pattern 25a may fill the space between the first color filter CF1 and the second color filter CF2.

[0057] The first dielectric layer 30 may be located on the protective layer 23 and the low-refractive pattern 25a. The first dielectric layer 30 may be a silicon oxide layer or a silicon nitride layer. At each unit pixel region UP, a pixel electrode 32 may be located on the first dielectric layer 30. The second dielectric layer 44 may be located between the pixel electrodes 32. The second dielectric layer 44 may be a silicon oxide layer or a silicon nitride layer. The second photoelectric conversion portion PD2 may be located on the pixel electrode 32. The common electrode 34 may be located on the second photoelectric conversion portion PD2. The passivation layer 36 may be located on the common electrode 34. The microlens ML may be located on the passivation layer 36.

[0058] The pixel electrode 32 and the common electrode 34 may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or an organic transparent conductive material. The second photoelectric conversion portion PD2 may be, for example, an organic photoelectric conversion layer. The second photoelectric conversion portion PD2 may include a p-type organic semiconductor material and an n-type organic semiconductor material, and the p-type organic semiconductor material and the n-type organic semiconductor material may form a pn junction. In one embodiment, the second photoelectric conversion portion PD2 may include quantum dots or chalcogenides.

[0059] The pixel electrode 32 may be electrically connected to the through electrode 57 through the via plug 40. The via plug 40 may include polysilicon doped with impurities, a metal nitride layer such as a titanium nitride layer, a metal material such as tungsten, titanium, and copper, or a transparent conductive material such as ITO. The via plug 40 may contact the through electrode 57 while penetrating the first dielectric layer 30, the low-refractive pattern 25a, the protective layer 23, the light shielding pattern 17a, and the auxiliary dielectric layer 15. The second via dielectric layer 42 may cover the sidewall of the via plug 40. The through electrode 57 may be electrically connected to the second floating diffusion region FD2 through the first connector 8a, the connecting line 8, and the second connector 8b. Other configurations may be the same as those described above with reference to FIG. Figure 5 The constructions in question are the same or similar.

[0060] According to one embodiment, the image sensor may include a low refraction pattern (located between color filters) that refracts light incident adjacent to the edge of the color filter and allows the light to travel to the relevant pixel. For example, the light receiving efficiency can be improved and the signal-to-noise ratio (SNR) can be improved.

[0061] Additionally, according to one embodiment, the image sensor may include a protection layer covering the top surface and sidewalls of the color filter, which helps prevent the color filter from absorbing moisture or being damaged during a manufacturing process, which may improve reliability.

[0062] Furthermore, an image sensor according to an embodiment may include a light shielding pattern to help prevent or block a blue spot defect, and thus clear image quality may be achieved.

[0063] According to one embodiment, a method of manufacturing an image sensor may use a sacrificial pattern by which a color filter region is limited or defined to prevent the color filter from having a bad profile and to accurately form the color filter having a desired size.

[0064] Furthermore, according to one embodiment, a method of manufacturing an image sensor may use a protective layer to help prevent damage to the color filters.

[0065] One or more embodiments may provide an image sensor having improved light emitting efficiency.

[0066] One or more embodiments may provide a method of manufacturing an image sensor that reduces process defects.

[0067] Although the corresponding top view and / or perspective view of some cross-sectional views may not be shown, the cross-sectional view of the device structure shown herein provides support for multiple device structures extending in two different directions as shown in the top view and / or in three different directions as shown in the perspective view. The two different directions may be orthogonal to each other or may not be orthogonal. The three different directions may include a third direction that may be orthogonal to the two different directions. Multiple device structures may be integrated in the same electronic device. For example, when a device structure (e.g., a memory cell structure or a transistor structure) is shown in a cross-sectional view, the electronic device may include multiple device structures (e.g., a memory cell structure or a transistor structure), as shown in a top view of the electronic device. Multiple device structures may be arranged in an array and / or a two-dimensional pattern.

[0068] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as would be apparent to one of ordinary skill in the art at the time of filing this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically noted. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. An image sensor, comprising: a plurality of color filters spaced apart from each other on a semiconductor substrate; a protective layer covering the sidewalls and top surface of the color filter; a low-refractive pattern filling a space between the color filters; a microlens located on the color filter; as well as a light shielding pattern, the light shielding pattern being located on the semiconductor substrate and between the color filters, wherein the microlens contacts the top surface of the protective layer and the top surface of the low-refractive pattern, Wherein, the top surface of the light shielding pattern is covered by the protective layer, Wherein, the protection layer is located between the low-refractive pattern and the light-shielding pattern.

2. The image sensor according to claim 1, wherein: A refractive index of the low-refractive pattern is lower than a refractive index of the color filter.

3. The image sensor according to claim 1, wherein: The protective layer includes one or more of an aluminum oxide layer and a silicon oxycarbide layer.

4. The image sensor according to claim 1, wherein: The thickness of the protective layer is to 5. The image sensor according to claim 1, wherein: A sidewall of the light shielding pattern is aligned with a sidewall of one of the color filters.

6. The image sensor according to claim 1, further comprising: A through electrode, wherein the through electrode is located in the semiconductor substrate; a pixel electrode, the pixel electrode being located on the protection layer and overlapping the low-refractive pattern; An organic photoelectric conversion layer, wherein the organic photoelectric conversion layer is located on the pixel electrode; as well as a via plug electrically connecting the pixel electrode to the through electrode, Wherein, the via plug penetrates the low-refractive pattern and the protective layer.

7. The image sensor according to claim 1, wherein: A top surface of the protection layer is coplanar with a top surface of the low-refractive pattern.

8. The image sensor according to claim 1, wherein: The portion of the protective layer located on the sidewall of the color filter has a first thickness, A portion of the protective layer located on the top surface of the color filter has a second thickness, and The first thickness is equal to or greater than the second thickness.

9. An image sensor, comprising: A semiconductor substrate having a plurality of unit pixel regions; A deep device isolation portion, wherein the deep device isolation portion is located between the unit pixel regions; a photoelectric conversion part, the photoelectric conversion part being located in the semiconductor substrate of each of the unit pixel regions; a plurality of color filters spaced apart from each other on the semiconductor substrate; a light shielding pattern located on the semiconductor substrate and between the plurality of color filters, wherein a thickness of the light shielding pattern is smaller than a thickness of each of the plurality of color filters; a low-refractive pattern filling a space between the color filters; as well as A protective layer is located between the low-refractive pattern and the opposing surface of the color filter and between the low-refractive pattern and the opposing surface of the light-shielding pattern.

10. The image sensor according to claim 9, wherein: The protection layer contacts a top surface of the color filter.

11. The image sensor according to claim 10, wherein: A top surface of the protection layer is coplanar with a top surface of the low-refractive pattern.

12. The image sensor according to claim 10, wherein: The portion of the protective layer located on the sidewall of the color filter has a first thickness, The portion of the protective layer located on the top surface of the color filter has a second thickness, and The first thickness is equal to or greater than the second thickness.

13. The image sensor according to claim 9, wherein: A sidewall of the light shielding pattern is aligned with a sidewall of one of the color filters.

14. An image sensor, comprising: a plurality of optical filters spaced apart from one another on a semiconductor substrate; a low-refractive pattern filling the space between the filters; a light shielding pattern, wherein the light shielding pattern is located between the low-refractive pattern and the semiconductor substrate; as well as A protective layer is located between the low-refractive pattern and the light-shielding pattern.

15. The image sensor according to claim 14, wherein: The thickness of the light shielding pattern is smaller than the thickness of the low-refractive pattern.

16. The image sensor according to claim 14, wherein: The protective layer is located between the low-refractive pattern and the optical filter, and the protective layer covers the top surface of the optical filter. The portion of the protective layer located on the side wall of the optical filter has a first thickness, The portion of the protective layer located on the top surface of the optical filter has a second thickness, and The first thickness is equal to or greater than the second thickness.

17. The image sensor according to claim 16, wherein: A top surface of the protection layer is coplanar with a top surface of the low-refractive pattern.

18. The image sensor according to claim 14, wherein: A side wall of the light shielding pattern is aligned with a side wall of one of the optical filters.

19. A method for manufacturing an image sensor, the method comprising: sequentially forming a light shielding layer and a sacrificial layer on a semiconductor substrate; sequentially patterning the sacrificial layer and the light shielding layer to form a sacrificial pattern and a light shielding pattern, wherein the sacrificial pattern defines a plurality of color filter regions; forming a plurality of color filters in the plurality of color filter regions respectively; removing the sacrificial pattern to expose spaces between the color filters; After removing the sacrificial pattern to expose the space between the color filters, forming a protection layer conformally covering the top surface and sidewalls of the color filters; filling spaces between the color filters by forming a low-refractive layer on the protective layer; as well as The low-refractive layer on the color filter is removed to form a low-refractive pattern in the space.

20. The method according to claim 19, wherein: Removing the low refractive layer on the color filter includes exposing the protective layer.

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