A chip packaging structure and packaging method thereof

Abstract

The present invention discloses a chip packaging structure and a packaging method thereof, belonging to the field of semiconductor packaging technology. A protective layer (200) is provided on the active surface of a chip body (100) and the upper surface of a chip electrode (101), wherein the protective layer (200) opens a protective layer opening (201) above the chip electrode (101), wherein a metal bump (300) is provided in the protective layer opening (201), and wherein the metal bump (300) is connected to the chip electrode (101) through the protective layer opening (201); an adhesion layer (601), a seed layer (602) and a back gold block (600) are provided in sequence on the back side of the chip body (100), wherein the adhesion layer (601) covers the back side of the chip body (100); a back gold block (600) is provided on the lower surface of the seed layer (602), and the covering layer (700) covers the exposed surface of the back gold block (600) and extends upward to the edges around the lower surface of the adhesion layer (601). The present invention can effectively overcome wafer warping and fragmentation, reduce the difficulty of dicing, and solve the problems of warping and fragmentation of packaged finished products.

Description

Technical Field

[0001] The present invention relates to a chip packaging structure and a packaging method thereof, belonging to the technical field of semiconductor chip packaging. Background Art

[0002] With the development of the semiconductor industry, the performance requirements for electronic products continue to increase. For power products such as MOSFETs, the chip thickness needs to be continuously reduced while the back metal (back metal) thickness needs to be increased to reduce resistance and improve product performance. Currently, the thinnest chip thickness for this type of product reaches 50 microns, and the back metal thickness reaches 50 microns. As product resistance continues to decrease, the chip thickness needs to be further reduced and the back metal thickness needs to be further increased.

[0003] Existing chip packaging structures such as Figure 1 As shown, the chip is provided with a protective layer and bumps, and a back-gold layer is provided on the back of the chip. The packaging method is: the protective layer is formed on the front of the wafer by photolithography, the bumps are formed by electroplating or chemical plating, the back of the wafer is polished and metal is evaporated and deposited, and then it is cut into individual chips.

[0004] As chip thickness continues to decrease and back-metal thickness continues to increase, existing packaging methods present the following problems: 1. Due to the wafer's thinness, the cutting force during dicing causes vibration. Furthermore, the thick back-metal can cause metal sticking to the knife and wire drawing when slicing directly through the thick back-metal. This can easily cause chip cracking, making dicing very difficult. 2. Back-metal often contains metals such as Cu that easily diffuse into the chip. Thick back-metal easily forms wires during dicing. Upon contact with the chip, the Cu-containing wires can diffuse into the chip, causing chip failure. The finished package also presents the following problems: 1. The thin chip and thick back-metal lead to warping due to the difference in thermal expansion coefficients between the chip and back-metal, resulting in cold solder joints during SMT (surface mount technology). 2. The mechanical strength of the finished package is directly related to chip thickness. As chip thickness decreases, the strength of the finished package decreases, making it more susceptible to breakage during subsequent use, leading to reliability issues. Summary of the Invention

[0005] The purpose of the present invention is to overcome the shortcomings of existing packaging technology and provide a chip packaging structure and packaging method that can reduce the difficulty of dicing, avoid back metal diffusion into the interior of the chip causing functional failure, and solve the problem of warping and fragmentation of the packaged product.

[0006] The object of the present invention is achieved like this:

[0007] The present invention provides a chip packaging structure, comprising a chip body having an active surface, wherein the active surface of the chip body is provided with a chip electrode, and a protective layer is provided on the active surface of the chip body and the upper surface of the chip electrode, wherein the protective layer has a protective layer opening above the chip electrode, a metal bump is provided in the protective layer opening, and the metal bump is connected to the chip electrode through the protective layer opening;

[0008] The back side of the chip body is provided with an adhesive layer, a seed layer and a back gold block in sequence, and the adhesive layer covers the back side of the chip body;

[0009] The cross section of the seed layer is smaller than the cross section of the chip body and / or the cross section of the adhesion layer, and the edges around the lower surface of the adhesion layer are exposed;

[0010] The lower surface of the seed layer is provided with a backing gold block, and the coverage area thereof is equal;

[0011] The invention also comprises a covering layer, which covers the exposed surface of the back gold block and extends upward to the edges around the lower surface of the adhesive layer.

[0012] Furthermore, the metal material of the metal bump includes but is not limited to Ti, Cu, Ni, Sn, and Au elements.

[0013] Furthermore, the material of the back gold block includes but is not limited to TiNiAg, TiNiAgNi, CrCu, CrCuCr, TiCu, TiCuTi, and TiCuNi.

[0014] The present invention also provides a packaging method for a chip packaging structure, the process steps of which are as follows:

[0015] Step 1: providing a wafer having scribe lines interlaced horizontally and vertically to divide the wafer into a plurality of chip units arranged in an array, wherein chip electrodes are provided on the active surfaces of the chip bodies of the chip units;

[0016] Step 2: selectively forming a protective layer on the surface of the wafer by photolithography, and opening the protective layer to expose the upper surface of the chip electrode;

[0017] Step 3: Form metal bumps in the openings of the protective layer by sputtering, photolithography, electroplating, desmearing, and etching to interconnect with the chip electrodes;

[0018] Step 4: Bond the carrier to the wafer using a bonding adhesive. The bonding method is usually to apply or press the bonding adhesive on the surface of the wafer and then bond it to the carrier under the action of pressure, temperature, and vacuum.

[0019] Step 5: Thinning the back of the chip body of the wafer by grinding, and changing the microscopic morphology of the chip body by chemical etching after grinding;

[0020] Step 6: Depositing an adhesion layer and a seed layer on the back of the wafer in sequence by sputtering;

[0021] Step 7: Form a photoresist layer on the wafer by photolithography, and form an array of photoresist layer openings, and then electroplating and depositing back gold blocks in the photoresist layer openings to form an array of back gold blocks with intervals;

[0022] Step 8: removing the photoresist with an organic solution, etching the seed layer with an acidic solution to form a metal opening while leaving the adhesion layer uncorroded;

[0023] Step 9: Cover the exposed surface of the back gold block with a coating layer by lamination, printing or encapsulation, and fill the metal opening;

[0024] Step 10: Separate the carrier from the wafer and remove the bonding glue by debonding.

[0025] Step 11: Dicing the wafer into chip packaging structures along the dicing lanes.

[0026] Furthermore, in step three, the metal bumps are formed by chemical plating, and the metal materials of the metal bumps include but are not limited to Ti, Cu, Ni, Sn, and Au elements.

[0027] Furthermore, in step four, the bonding adhesive material is a thermoplastic liquid material, or a film material that is sensitive to UV light.

[0028] Furthermore, in step six, the back gold block includes but is not limited to CrCu, TiCu, TiCu, TiCuNi, and TiCuNiAu.

[0029] Furthermore, in step six, the adhesion layer includes but is not limited to Cr, Ti, TiW, V, and NiV; the thickness of the adhesion layer is 0.01 to 3 microns; the seed layer includes but is not limited to Cu and Ni, and the thickness of the seed layer is 0.01 to 1 micron.

[0030] Furthermore, in step nine, the material of the coating layer is a thermosetting polymer material, including but not limited to epoxy resin and phenolic resin.

[0031] Furthermore, in step ten, debonding includes but is not limited to thermal debonding, chemical debonding, laser debonding or UV debonding.

[0032] Beneficial effects

[0033] 1. The present invention uses a composite wafer structure formed by a wafer, a back-gold block, and an encapsulation layer to increase the strength of the wafer during the packaging process and overcome the jitter problem caused by the cutting force during dicing. By setting the back-gold block interval, the problem of knife sticking when directly dicing through thick back-gold blocks is solved, reducing chip cracking caused by dicing and reducing the difficulty of dicing.

[0034] 2. The present invention forms a gap between the back-gold blocks to avoid metal wiredrawing caused by directly scratching the thick back-gold blocks, as well as the problem of chip failure caused by the diffusion of easily diffusible metals such as Cu in the back-gold material into the chip. At the same time, the process does not corrode the adhesion layer. The retained adhesion layer ensures a complete diffusion barrier layer between the seed layer and the back-gold and the chip body, effectively avoiding chip failure caused by the diffusion of metal atoms.

[0035] 3. The present invention increases the rigidity of the chip packaging structure product through the composite packaging structure formed by the chip, the back gold block and the encapsulation layer, overcomes the warping problem of the packaging product, and solves the SMT cold soldering problem; and through the composite packaging structure, improves the mechanical strength of the chip packaging product, overcomes the problem of fragmented packaging products, and improves reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a schematic diagram of the traditional chip packaging structure;

[0037] Figure 2 A packaging flow chart of the packaging structure of the chip of the present invention;

[0038] Figure 3 Schematic cross-sectional view of the chip packaging structure of the present invention; Figure 3 is a cross-sectional schematic diagram of an embodiment of a chip packaging structure of the present invention;

[0039] Figures 4A to 4N A schematic cross-sectional view of a packaging method for a chip packaging structure according to the present invention;

[0040] In the picture:

[0041] Wafer 10A

[0042] Chip body 100

[0043] Chip Electrode 101

[0044] Protective layer 200

[0045] Metal Bump 300

[0046] Bonding adhesive 400

[0047] Slide 500

[0048] Gold nugget 600

[0049] Adhesion layer 601

[0050] Seed layer 602

[0051] Coating layer 700

[0052] 900 dicing lanes. DETAILED DESCRIPTION

[0053] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0054] Reference Figure 1 The packaging process of a chip packaging structure of the present invention is as follows:

[0055] Executing step S101: providing a wafer;

[0056] Executing step S102: selectively forming a protective layer on the surface of the wafer by photolithography;

[0057] Executing step S103: manufacturing metal bumps by electroplating or chemical plating;

[0058] Executing step S104: bonding the carrier to the wafer by a bonding method;

[0059] Executing step S105: thinning the back side of the wafer by grinding;

[0060] Executing step S106: forming an adhesion layer and a seed layer on the back side of the wafer by sputtering;

[0061] Executing step S107: selectively forming a photoresist on the wafer by photolithography, and forming a back gold block array by electroplating;

[0062] Executing step S108: removing the photoresist, etching the seed layer, and leaving the adhesion layer unetched;

[0063] Executing step S109: coating the back gold block with a coating layer and filling the gaps between the back gold blocks by lamination, printing or encapsulation;

[0064] Executing step S110: separating the carrier from the wafer by a debonding method and removing the bonding glue;

[0065] Execute step S111: cut the wafer into single chip packaging structures by a dicing method.

[0066] Example

[0067] The present invention provides a chip packaging structure, such as Figure 3FIG2 is a schematic cross-sectional view of the chip package structure of the present invention. It includes a chip body 100 having an active surface, with a thickness of 25 to 150 microns. Chip electrodes 101 are provided on the active surface of the chip body 100, and a protective layer 200 is provided on the active surface of the chip and the upper surface of the chip electrodes 101. The protective layer 200 includes, but is not limited to, a passivation layer and an insulating layer. The protective layer 200 defines a protective layer opening 201 above the chip electrodes 101, and a metal bump 300 is provided within the protective layer opening 201. The metal bump 300 is made of a metal material containing Ti, Cu, Ni, Sn, and Au elements, and is typically 2 to 100 microns in height.

[0068] The metal bump 300 is connected to the chip electrode 101 through the protective layer opening 201. The cross-sectional shape of the metal bump 300 is designed according to actual needs, including but not limited to rectangular, circular, and elliptical shapes.

[0069] The back side of the chip body 100 is sequentially provided with an adhesion layer 601, a seed layer 602, and a back gold block 600. The adhesion layer 601 covers the back side of the chip body 100. The cross section of the seed layer 602 is smaller than the cross section of the chip body 100 and / or the cross section of the adhesion layer 601, and the edges of the bottom surface of the adhesion layer 601 are exposed.

[0070] The back gold block 600 is disposed on the lower surface of the seed layer 602 , and its coverage area is equal.

[0071] The material of the back gold block 600 is usually a multilayer material such as TiNiAg, TiNiAgNi, CrCu, CrCuCr, TiCu, TiCuTi, TiCuNi, etc.; the thickness of the back gold block 600 is usually 10-100 microns.

[0072] The covering layer 700 covers the exposed surface of the back gold block 600 and extends upward to the edges around the lower surface of the adhesive layer 601 to play a supporting and protective role.

[0073] The present invention provides a packaging method for a chip packaging structure. Figures 4A to 4N The schematic diagram of the chip packaging method is as follows:

[0074] Step 1: See Figure 4A and 4B , providing a wafer 10A, Figure 4A It is a schematic top view of a wafer; the wafer 10A is provided with horizontal and vertical interlaced scribing streets 900 to divide it into a plurality of chip units 10B arranged in an array, and the active surface of the chip body 100 of the chip unit 10B is provided with a chip electrode 101.

[0075] Step 2: See Figure 4CBy photolithography, a protection layer 200 is selectively formed on the surface of the wafer 10A, and an opening 201 is opened in the protection layer to expose the upper surface of the chip electrode 101.

[0076] Step 3: See Figure 4D A metal bump 300 is formed within the protective layer opening 201 through a sequential process of sputtering, photolithography, electroplating, debonding, and etching, interconnecting the chip electrode 101. The metal bump 300 can also be formed by chemical plating. The metal bump 300 is made of a metal material containing Ti, Cu, Ni, Sn, or Au, and typically has a height of 2 to 100 microns.

[0077] Step 4: See Figure 4E The carrier sheet 500 is bonded to the wafer 10A using bonding adhesive 400. The bonding method typically involves applying or pressing bonding adhesive 400 onto the surface of the wafer 10A, and then bonding the bonding adhesive 400 to the carrier sheet 500 under the influence of pressure, temperature, and vacuum. Preferably, the bonding adhesive 400 is a thermoplastic liquid material or a film material that is sensitive to UV light.

[0078] Step 5: See Figure 4F The backside of the chip body 100 of the wafer 10A is thinned by lapping, which can be either mechanical or chemical mechanical lapping. Typically, chemical etching is added after lapping to alter the microscopic morphology of the chip body 100, thereby enhancing the bonding strength between the subsequent backside gold block 600 and the chip body 100. The thickness of the chip body 100 after lapping is typically 25 to 150 microns.

[0079] Step 6: See Figure 4G Adhesion layer 601 and seed layer 602 are sequentially deposited on the back side of wafer 10A by sputtering. Adhesion layer 601 can be made of materials such as Cr, Ti, TiW, V, NiV, or a composite layer of one or two materials, with a thickness of 0.01 to 3 microns. Seed layer 602 can be made of materials such as Cu and Ni, with a thickness of 0.01 to 1 micron. Adhesion layer 601 not only bonds to chip body 100 but also prevents metal atoms or other metal particles from the seed layer 602 and back gold block 600 from diffusing into chip body 100.

[0080] Step 7: See Figure 4H and 4IA photoresist layer 603 is formed on the wafer by photolithography, and an array of photoresist openings 604 are formed in the layer. Then, back-gold blocks 600 are deposited in the photoresist openings 604 by electroplating. The back-gold blocks 600 are typically made of Cu, CuNi, CuNiAu, NiAu, or other materials, and have a thickness of 5 to 100 microns. Because the areas where the photoresist layer 603 remains cannot be electroplated, an array of back-gold blocks with intervals between them is formed.

[0081] Step 8: See Figure 4J The photoresist layer 603 is removed using an organic solution such as acetone or NMP, and the seed layer 602 is etched away using an acidic solution to form a metal opening while leaving the adhesion layer 601 uncorroded. The purpose of not corroding the adhesion layer 601 is to ensure a complete diffusion barrier between the seed layer 602 and the backing gold block 600 and the chip body 100.

[0082] Step 9: See Figure 4K The coating layer 700 is applied to the exposed surface of the backing gold block 600 by lamination, printing, or encapsulation, filling the metal opening. Preferably, the coating layer 700 is made of a thermosetting polymer such as epoxy resin, phenolic resin, silica gel, amino, or unsaturated resin. To improve heat dissipation, the coating layer can be a composite material containing powders or fibers such as metal, ceramic, silicon oxide, or graphene. The coating layer 700 has a thickness of 25 to 200 microns.

[0083] Step 10: See Figure 4L , the carrier 500 is separated from the wafer 10A and the bonding glue 400 is removed by a debonding method; the debonding can be thermal debonding, chemical debonding, laser debonding or UV debonding, etc.

[0084] Step 11: See Figure 4M and 4N By scribing, the wafer 10A is divided into single chip packaging structures along the scribing streets 900; scribing can be performed using a blade containing diamond or ceramic particles, or laser cutting can be used.

[0085] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A packaging method for a chip packaging structure, the process steps are as follows: Step 1: providing a wafer (10A), wherein the wafer (10A) is provided with scribe lines (900) interlaced in transverse and longitudinal directions to divide the wafer (10A) into a plurality of chip units (10B) arranged in an array, and the active surface of the chip body (100) of the chip unit (10B) is provided with a chip electrode (101); Step 2: selectively forming a protective layer (200) on the surface of the wafer (10A) by photolithography, and opening the protective layer (201) to expose the upper surface of the chip electrode (101); Step 3: forming a metal bump (300) in the protective layer opening (201) by sequentially using sputtering, photolithography, electroplating, degumming and etching methods to form an interconnection with the chip electrode (101); Step 4: Bonding the carrier (500) and the wafer (10A) together using a bonding adhesive (400). The bonding method is generally to apply or press the bonding adhesive (400) on the surface of the wafer (10A), and then bond the bonding adhesive (400) to the carrier (500) under the action of pressure, temperature, and vacuum. Step 5: Thinning the back side of the chip body (100) of the wafer (10A) by grinding, and changing the microscopic morphology of the chip body (100) by chemical etching after grinding; Step 6: Depositing an adhesion layer (601) and a seed layer (602) on the back side of the wafer (10A) in sequence by sputtering; Step 7: forming a photoresist layer (603) on the wafer by photolithography, and forming an array of photoresist layer openings (604); then electroplating and depositing back gold blocks (600) in the photoresist layer openings (604) to form an array of back gold blocks with intervals; Step eight, removing the photoresist layer (603) by an organic solution, etching the seed layer (602) by an acidic solution to form a metal opening, while retaining the adhesion layer (601) from being corroded, so as to ensure that there is a complete diffusion barrier layer between the seed layer (602) and the back gold block (600) and the chip body (100); Step nine: by lamination, printing or encapsulation, the coating layer (700) is coated on the exposed surface of the back gold block (600) and the seed layer (602), and the metal opening is filled; Step 10: Separate the carrier (500) from the wafer (10A) by a debonding method, and remove the bonding glue (400); Step 11: Using a scribing method, the wafer (10A) is scribed along scribing lanes (900) to form a chip packaging structure, wherein the coating layer (700) exposes the side surface of the adhesion layer (601).

2. The packaging method according to claim 1, wherein: In step three, the metal bump (300) is formed by a chemical plating method, and the metal material of the metal bump (300) includes but is not limited to Ti, Cu, Ni, Sn, and Au elements.

3. The packaging method according to claim 2, wherein: In step 4, the bonding adhesive (400) material is a thermoplastic liquid material, or a film material that is sensitive to UV light.

4. The packaging method according to claim 3, wherein: In step six, the back gold block (600) includes but is not limited to CrCu, TiCu, TiCu, TiCuNi, TiCuNiAu.

5. The packaging method according to claim 4, wherein: In step six, the adhesion layer (601) includes but is not limited to Cr, Ti, TiW, V, NiV; the thickness of the adhesion layer (601) is 0.01-3 microns; the seed layer (602) includes but is not limited to Cu and Ni, and the thickness of the seed layer (602) is 0.01-1 microns.

6. The packaging method according to claim 5, characterized in that: In step nine, the coating layer (700) is made of a thermosetting polymer material, including but not limited to epoxy resin and phenolic resin.

7. The packaging method according to claim 6, characterized in that: In step ten, debonding includes but is not limited to thermal debonding, chemical debonding, laser debonding or UV debonding.

8. A chip packaging structure, formed by the packaging method of the chip packaging structure according to claim 1, comprising a chip body (100) having an active surface, wherein the active surface of the chip body (100) is provided with a chip electrode (101), characterized in that: A protective layer (200) is provided on the active surface of the chip body (100) and the upper surface of the chip electrode (101); the protective layer (200) has a protective layer opening (201) above the chip electrode (101); a metal bump (300) is provided in the protective layer opening (201); and the metal bump (300) is connected to the chip electrode (101) through the protective layer opening (201); The back side of the chip body (100) is provided with an adhesion layer (601), a seed layer (602) and a back gold block (600) in sequence, and the adhesion layer (601) covers the back side of the chip body (100); The cross section of the seed layer (602) is smaller than the cross section of the chip body (100) and / or the cross section of the adhesion layer (601), and the edges around the lower surface of the adhesion layer (601) are exposed. The adhesion layer (601) is used to ensure that there is a complete diffusion barrier layer between the seed layer (602) and the back gold block (600) and the chip body (100); The lower surface of the seed layer (602) is provided with a back gold block (600), and the coverage area thereof is equal; The invention also includes a coating layer (700), which covers the exposed surface of the back gold block (600) and the seed layer (602) and extends upward to the edges around the lower surface of the adhesion layer (601). The coating layer (700) exposes the side of the adhesion layer (601).

9. The chip packaging structure according to claim 8, characterized in that: The metal material of the metal bump (300) includes but is not limited to Ti, Cu, Ni, Sn, and Au elements.

10. The chip packaging structure of claim 8, wherein: The material of the back gold block (600) includes but is not limited to TiNiAg, TiNiAgNi, CrCu, CrCuCr, TiCu, TiCuTi, and TiCuNi.

Images