A three-dimensional chip packaging structure and packaging method

Abstract

The present invention provides a three-dimensional chip packaging structure and packaging method, the packaging structure includes: a packaging substrate; a three-dimensional stacked chip assembly, including a first chip assembly and a second chip assembly, the size of the first chip assembly is larger than the size of the second chip assembly; a thermal bridge structure, formed on the first chip assembly, with a spacing between the first chip assembly and the second chip assembly; a heat dissipation cover assembly, formed on the packaging substrate, and thermally conductive between the thermal bridge structure, the first chip assembly and the heat dissipation cover assembly. The present invention introduces a thermal bridge structure to form a heat conduction path, which is beneficial to the heat dissipation of the three-dimensional stacked chip and greatly reduces the heat dissipation thermal resistance and temperature of the bottom chip. The design of the present invention can also reduce the temperature difference of the first chip, thereby greatly reducing thermal stress. The thermal bridge structure shares the pressure originally applied to the heat sink on the three-dimensional stacked chip, so that the packaging force is more uniform and the structure is more stable. The process of the present invention is simple and basically does not affect the existing packaging process flow and process.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a three-dimensional chip packaging structure and a packaging method. Background Art

[0002] In the structure of three-dimensional stacked chips, different types of chips are often stacked together. However, the heat of the chip is difficult to dissipate, resulting in the stacked chip failing due to too high a junction temperature, which limits the integration and performance improvement of the entire device. In addition, in the stacked chip, the upper chip is composed of multiple layers, each layer includes a micro-bump array interconnection form, and is filled with a bottom filling layer (underfill), resulting in a large thermal resistance from the bottom to the outside of the heat dissipation cover, thereby making the temperature of the bottom chip too high and unable to ensure normal operation. Some existing heat dissipation technologies have complex processes, and some technologies introduce plastic packaging materials to cause a large series thermal resistance, and the heat generation is difficult to fully dissipate, especially the bottom chip has a large thermal resistance to the outside, and the chip temperature is too high, which is easy to fail, limiting the integration and performance improvement of the entire device.

[0003] Therefore, it is necessary to provide a three-dimensional chip packaging structure and a packaging method to solve the above-mentioned problems in the prior art. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a three-dimensional chip packaging structure and packaging method, which are used to solve the problems of internal heat being difficult to dissipate and the bottom chip temperature being too high in the prior art.

[0005] To achieve the above objectives and other related objectives, the present invention provides a three-dimensional chip packaging structure, comprising:

[0006] Package substrate;

[0007] A three-dimensional stacked chip assembly is formed on the packaging substrate, wherein the three-dimensional stacked chip assembly includes a first chip assembly and a second chip assembly formed on the first chip assembly, and the size of the first chip assembly is larger than the size of the second chip assembly;

[0008] a thermal bridge structure formed on the first chip component, wherein a preset distance exists between the thermal bridge structure and the second chip component; and

[0009] A heat dissipation cover assembly is formed on the packaging substrate, the heat dissipation cover assembly surrounds the three-dimensional stacked chip assembly and the thermal bridge structure, and the thermal bridge structure, the first chip assembly and the heat dissipation cover assembly are thermally connected.

[0010] Optionally, the first chip component includes a central area and a peripheral area surrounding the central area, wherein the second chip component is disposed on the central area, and the thermal bridge structure is disposed on the peripheral area.

[0011] Optionally, the shape of the thermal bridge structure includes a ring shape.

[0012] Optionally, the preset distance between the thermal bridge structure and the second chip component is between 0.2-2 mm; and the width of the thermal bridge structure is between 1-5 mm.

[0013] Optionally, the thermal bridge structure is formed on the first chip component through a bottom die-bonding layer.

[0014] Optionally, the upper surface of the thermal bridge structure is not higher than the upper surface of the three-dimensional stacked chip assembly, and the height difference between the upper surface of the thermal bridge structure and the upper surface of the three-dimensional stacked chip assembly is less than 100 μm.

[0015] Optionally, a first thermal interface layer is provided between the thermal bridge structure and the heat dissipation cover assembly, and the first thermal interface layer is also located between the three-dimensional stacked chip assembly and the heat dissipation cover assembly.

[0016] Optionally, a second thermal interface layer is further formed on the heat dissipation cover assembly, and the second thermal interface layer is thermally connected to the heat dissipation cover plate.

[0017] Optionally, there is a first bump array between the first chip component and the second chip component, and the first bump array includes a plurality of first bump units; and / or, the second chip component includes at least two semiconductor chips stacked one above the other, and adjacent semiconductor chips are electrically connected through a second bump array, and the second bump array includes a plurality of second bump units.

[0018] Optionally, the height of the first bump unit is less than 30 μm, and the height of the second bump unit is less than 30 μm; the temperature and temperature difference on the first chip component are adjusted by at least one of the spacing, height, size between the first bump units and the spacing, height, size between the second bump units.

[0019] Optionally, a first space is formed between the thermal bridge structure and the second chip assembly, and a second space is formed between the thermal bridge structure and the heat dissipation cover assembly, wherein at least one first exhaust hole is provided in the thermal bridge structure, and the first exhaust hole connects the first space and the second space; and / or, at least one second exhaust hole is provided in the heat dissipation cover assembly, and the second exhaust hole connects the second space with the outside atmosphere.

[0020] Optionally, the first chip component is thermally connected to the heat dissipation cover component through the thermal bridge structure above and has a first thermal resistance, and the first chip component is thermally connected to the heat dissipation cover component through the second chip component above and has a second thermal resistance, wherein the specific thermal resistance value of the first thermal resistance is between 0.8-2.5 times the specific thermal resistance value of the second thermal resistance.

[0021] The present invention further provides a three-dimensional chip packaging method. The three-dimensional chip packaging structure provided by the present invention is preferably prepared by the three-dimensional chip packaging method provided by the present invention. Of course, other packaging methods can also be used. The packaging method includes:

[0022] Providing a packaging substrate;

[0023] Forming a three-dimensional stacked chip component on the packaging substrate, wherein the three-dimensional stacked chip component includes a first chip component and a second chip component formed on the first chip component, and the size of the first chip component is larger than the size of the second chip component;

[0024] Preparing a thermal bridge structure on the first chip component, with a preset distance between the thermal bridge structure and the second chip component; and

[0025] A heat dissipation cover assembly is formed on the packaging substrate, the heat dissipation cover assembly surrounds the three-dimensional stacked chip assembly and the thermal bridge structure, and the thermal bridge structure, the first chip assembly and the heat dissipation cover assembly are thermally connected.

[0026] Optionally, the first chip component includes a central area and a peripheral area surrounding the central area, wherein the second chip component is disposed on the central area, and the thermal bridge structure is disposed on the peripheral area.

[0027] Optionally, before forming the thermal bridge structure, the method includes the step of forming a bottom bonding layer at a position of the first chip component where the thermal bridge structure is to be formed, and the thermal bridge structure is formed on the bottom bonding layer.

[0028] Optionally, after forming the thermal bridge structure, the method includes forming a first thermal interface layer on the thermal bridge structure and the three-dimensional stacked chip assembly, and the heat dissipation cover assembly is formed on the first thermal interface layer.

[0029] Optionally, after forming the heat dissipation cover assembly, the step includes: forming a second thermal interface layer on the heat dissipation cover assembly, and the second thermal interface layer is thermally connected to the heat dissipation cover plate.

[0030] Optionally, there is a first bump array between the first chip component and the second chip component, and the first bump array includes a plurality of first bump units; and / or, the second chip component includes at least two semiconductor chips stacked one above the other, and adjacent semiconductor chips are electrically connected through a second bump array, and the second bump array includes a plurality of second bump units.

[0031] Optionally, the temperature and the temperature difference on the first chip component are adjusted by at least one of the spacing, height, and size between the first bump units and the spacing, height, and size between the second bump units.

[0032] Optionally, a first space is formed between the thermal bridge structure and the second chip assembly, and a second space is formed between the thermal bridge structure and the heat dissipation cover assembly, wherein at least one first exhaust hole is provided in the thermal bridge structure, and the first exhaust hole connects the first space and the second space; and / or, at least one second exhaust hole is provided in the heat dissipation cover assembly, and the second exhaust hole connects the second space with the outside atmosphere.

[0033] Optionally, the first chip component is thermally connected to the heat dissipation cover component through the thermal bridge structure above and has a first thermal resistance, and the first chip component is thermally connected to the heat dissipation cover component through the second chip component above and has a second thermal resistance, wherein the specific thermal resistance value of the first thermal resistance is between 0.8-2.5 times the specific thermal resistance value of the second thermal resistance.

[0034] As described above, the three-dimensional chip packaging structure and packaging method of the present invention, by introducing a thermal bridge structure, form a heat conduction path, which is beneficial to the heat dissipation of the three-dimensional stacked chip and greatly reduces the heat dissipation thermal resistance and temperature of the bottom chip. Through the design of the present invention, the temperature difference of the chip can be reduced, thereby greatly reducing thermal stress. The thermal bridge structure shares the pressure of the heat sink and the like originally applied to the three-dimensional stacked chip, so that the packaging force is more evenly distributed and the structure is more stable. The process of the present invention is simple and basically does not affect the existing packaging process flow and process (infrastructure). BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Shown is a flow chart of a three-dimensional chip packaging method according to an embodiment of the present invention.

[0036] Figure 2 Shown is a schematic structural diagram of a packaging substrate provided in a three-dimensional chip package in an embodiment of the present invention.

[0037] Figure 3 It is a schematic diagram showing the structure of a three-dimensional stacked chip assembly formed in a three-dimensional chip package in an embodiment of the present invention.

[0038] Figure 4 It is a schematic diagram showing the structure of forming a first dispensing layer in a three-dimensional chip package in an embodiment of the present invention.

[0039] Figure 5 Shown is a top view schematic diagram of forming a first dispensing layer in a three-dimensional chip package in an embodiment of the present invention.

[0040] Figure 6 It is a schematic diagram showing a structure of a thermal bridge structure formed in a three-dimensional chip package according to an embodiment of the present invention.

[0041] Figure 7 Shown is a top view schematic diagram of a thermal bridge structure formed in a three-dimensional chip package in an embodiment of the present invention.

[0042] Figure 8 It is a schematic diagram showing the structure of forming a second dispensing layer in a three-dimensional chip package in an embodiment of the present invention.

[0043] Fig. 9 It is a schematic diagram showing the structure of a heat dissipation cover assembly formed in a three-dimensional chip package according to an embodiment of the present invention.

[0044] Fig.10 It is a schematic diagram showing the formation of a second thermal interface layer and a heat sink in a three-dimensional chip package according to an embodiment of the present invention.

[0045] FIG. 11( a ) shows a side view and a top view of a temperature distribution contour diagram on a package structure without a thermal bridge structure, and FIG. 11( b ) shows a side view and a top view of a temperature distribution contour diagram on a package structure with a thermal bridge structure.

[0046] Figure 12(a) shows the maximum temperature distribution of different chips in a packaging structure with different pitches and sizes of the second bump units in a packaging structure without a thermal bridge structure, and Figure 12(b) shows the maximum temperature distribution of different chips in a packaging structure with different pitches and sizes of the second bump units in a packaging structure with a thermal bridge structure.

[0047] Fig.13 The graph shows the relationship between the temperature difference of the first chip assembly and the spacing and size of the second bump unit.

[0048] Fig.14 It is shown as a curve showing the change of the temperature difference of the first chip component with the ratio of the specific thermal resistance values ​​of the first thermal resistor to the second thermal resistor.

[0049] Component number description

[0050] 100 Package substrate

[0051] 101 Three-dimensional stacked chip assembly

[0052] 102 First Chip Assembly

[0053] 103 Second chip assembly

[0054] 103a Semiconductor chip

[0055] 104 first bump array

[0056] 104a first bump unit

[0057] 105 second bump array

[0058] 105a Second bump unit

[0059] 106 First dispensing layer

[0060] 107 Bottom die bonding layer

[0061] 108 Thermal bridge structure

[0062] 109 Second dispensing layer

[0063] 110 first thermal interface layer

[0064] 111 Heat sink cover assembly

[0065] 112 Adhesive layer

[0066] 113 Second thermal interface layer

[0067] 114 Heat sink

[0068] Steps S1 to S4 DETAILED DESCRIPTION

[0069] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0070] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0071] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0072] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0073] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0074] like Fig.10 Shown and referenced Figure 1-9 The present invention provides a three-dimensional chip packaging structure, which includes a packaging substrate 100, a three-dimensional stacked chip assembly 101, a thermal bridge structure 108, and a heat dissipation cover assembly 111, wherein:

[0075] The packaging substrate 100 may be a chip substrate commonly used in the art, including an organic substrate such as Bismaleimidetriazine, epoxy FR4 or an alumina ceramic substrate, but is not specifically limited thereto.

[0076] The three-dimensional stacked chip assembly 101 is assembled layer by layer on the packaging substrate 100. The three-dimensional stacked chip assembly 101 includes a first chip assembly 102 and a second chip assembly 103 formed on the first chip assembly 102, wherein the first chip assembly 102 may include a plurality of stacked semiconductor chips, such as 1, 2, or 5 chips, etc., which may be selected based on actual needs. In addition, the second chip assembly 103 may include a plurality of stacked semiconductor chips, such as 2, 8, 10 chips, etc., which may be selected based on actual needs. Fig.10As shown, in this example, the first chip assembly 102 includes one semiconductor chip, such as a microprocessor (CPU), and the second chip assembly 103 includes two semiconductor chips (such as memory chips) stacked one above the other.

[0077] In addition, the size of the first chip component 102 is larger than the size of the second chip component 103. Here, "larger" means that, from a top view, there is a part of the first chip component 102 that is not covered by the second chip component 103, that is, the first chip component 102 at the bottom has an exposed part, so that the subsequent preparation of the thermal bridge structure can be implemented. The size of the chip itself in the first chip component 102 can be larger than the size of the chip in the second chip component 103, or a chip of a larger size can be prepared. In an example, in the structure of a three-dimensional stacked chip, different types of chips are often stacked together. The chip at the bottom (the semiconductor chip in the first chip component 102), such as a microprocessor (CPU), is generally larger in size, and a memory chip (the second chip component 103) with a smaller three-dimensional size is stacked on the top. In addition, the memory chip generally has multiple layers, each layer includes a micro-bump array interconnection form, and is filled with a bottom filling layer (underfill), resulting in a large thermal resistance from the bottom to the external heat dissipation cover, which further causes the temperature of the first chip component 102 such as the CPU to be too high, and normal operation cannot be guaranteed. The above-mentioned heat dissipation problem can be alleviated by the solution of the present invention.

[0078] The thermal bridge structure 108 is formed on the first chip assembly 102, and there is a preset distance s between the thermal bridge structure 108 and the second chip assembly 103. That is, the second chip assembly 103 and the thermal bridge structure 108 are arranged on the first chip assembly 102 at intervals, and the thermal bridge structure 108 is arranged on the exposed part of the first chip assembly.

[0079] As an example, the first chip assembly 102 includes a central area and a peripheral area surrounding the central area, wherein the second chip assembly 103 is arranged on the central area, and optionally, the center of the first chip assembly 102 may coincide with the center of the second chip assembly 103, thereby facilitating the stability of the packaging structure. The thermal bridge structure 108 is arranged on the peripheral area and has the preset spacing s with the second chip assembly 103.

[0080] As an example, the preset spacing s is between 0.2-2 mm, and the preset spacing s can avoid the direct contact between the thermal bridge structure and the second chip causing additional thermal-mechanical stress. The preset spacing s can be 0.5 mm, 1 mm, or 1.5 mm. As an optional example, the width d of the thermal bridge structure 108 is between 1-5 mm, for example, it can be 1.2 mm or 1.3 mm. In another optional example, the upper surface of the thermal bridge structure 108 is lower than the upper surface of the three-dimensional stacked chip assembly 101, or the upper surfaces of the two are flush. Optionally, the height difference between the upper surface of the thermal bridge structure 108 and the upper surface of the three-dimensional stacked chip assembly 101 is less than 100 μm, for example, it can be 50 μm, 80 μm, etc. Among them, since the chip assembly needs to be carried out at a relatively high temperature, such as the bottom filling curing glue is generally filled at 80-100°C, the top TIM1 (i.e., organic thermal interface material, the first thermal interface layer) is also cured at around 80-150°C, such as Shin-Etsu 7772-4 high thermal conductivity silicone material, and the solder joints are generally connected and formed at 200-250°C. When the assembly is completed and cooled to room temperature, the substrate and heat dissipation cover components will bulge upwards, generally tens to 200-300 microns. By appropriately reducing the height of the thermal bridge structure, it can play the role of fitting the rigid heat dissipation cover, reduce the stress on the thermal bridge, and help maintain the integrity of the interface material. In addition, the thermal bridge is at the outer edge and has large deformation. If it is too thin, it will cause large shear deformation and a large pump-out effect, affecting the integrity and reliability of the interface material. In addition, the thermal resistance of the thermal bridge structure is less than the thermal resistance of the second chip assembly with the bump, which is conducive to maintaining the heat dissipation balance and the temperature difference of the large chip (the first chip assembly) through the height difference between the upper surface of the thermal bridge structure 108 and the upper surface of the three-dimensional stacked chip assembly 101. In addition, the heat dissipation balance and the small temperature difference of the large chip can be achieved by increasing the thickness of the first thermal interface layer. In one example, the upper surface of the thermal bridge structure 108 can be 10μm, 20μm, or 30μm lower than the upper surface of the three-dimensional stacked chip assembly 101. In one example, the height of the thermal bridge structure 108 is between 0.1-1mm, such as 0.2mm, 0.5mm, or 0.8mm. The material of the thermal bridge structure 108 can be a high thermal conductivity material, such as a semiconductor silicon wafer, a metal copper sheet, an aluminum sheet, stainless steel, a ceramic such as aluminum nitride (ALN), aluminum oxide, etc., but is not limited thereto. Of course, in other embodiments, the upper surface of the thermal bridge structure 108 can also be flush with the upper surface of the three-dimensional stacked chip assembly 101.

[0081] As an example, the shape of the thermal bridge structure 108 includes a ring shape, which is arranged around the second chip component 103, and can be a circular ring shape, a square ring shape, etc. In another example, the thermal bridge structure 108 is arranged in sections, that is, the thermal bridge structure 108 includes a plurality of thermal bridge units (not shown in the figure), each of which is arranged on the periphery of the second chip component 103. The segmented thermal bridge structure can arrange each of the thermal bridge units according to actual needs, which is conducive to effective heat dissipation. Optionally, each of the thermal bridge units forms a ring shape, which is arranged around the second chip component 103. The spacing between each of the thermal bridge units can be arranged according to actual needs. In one example, it is selected to be evenly spaced.

[0082] As an example, the thermal bridge structure 108 is formed on the first chip assembly 102 through a bottom bonding layer 107 . Optionally, the material of the bottom bonding layer 107 includes a thermally conductive gel or a thermosetting thermally conductive adhesive.

[0083] As an example, a first thermal interface layer (thermal interface material 1 or TIM 1) 110 is provided between the thermal bridge structure 108 and the heat dissipation cover assembly 111, which generally adopts a silicone thermal conductive material with good ductility, such as Shin-gao thermal conductive silicone 7772-4, and the thickness is generally 10-100um, which provides a heat conduction path and has good flexibility to avoid large thermal-mechanical stress between the heat dissipation cover and the chip. In one example, the process of the first thermal interface layer 110 can be: point mounting or X-shaped glue dispensing on the chip, annular glue dispensing on the thermal bridge, filling the interface gap after the heat dissipation cover is pressed, and then curing at a high temperature of 80-150°C. The first thermal interface layer 110 is also located between the three-dimensional stacked chip assembly 101 and the heat dissipation cover assembly 110, that is, after the second chip assembly 103 and the thermal bridge structure 108 are formed, the first thermal interface layer 110 is formed above the two, and the heat dissipation cover assembly 111 is formed on the first thermal interface layer 110. In this example, a heat dissipation path is formed between the first chip assembly 102, the bottom die-bonding layer 107, the thermal bridge structure 108, the first thermal interface layer 110 and the heat dissipation cover assembly 111 corresponding to each other. A heat dissipation path is formed between the first chip assembly 102, the second chip assembly 103, the first thermal interface layer 110 and the heat dissipation cover assembly 111 corresponding to each other.

[0084] The heat dissipation cover assembly 111 is formed on the packaging substrate 100. The heat dissipation cover assembly 111 surrounds the three-dimensional stacked chip assembly 101 and the thermal bridge structure 108. It is similar to a cap-shaped structure and is placed on the upper and side portions of the three-dimensional stacked chip assembly 101 and the thermal bridge structure 108. The thermal bridge structure 108, the first chip assembly 102 and the heat dissipation cover assembly 111 are thermally conductive. That is to say, the present invention introduces the thermal bridge structure 108 to form a heat conduction path between the first chip assembly 102, the thermal bridge structure 108 and the heat dissipation cover assembly 111, which is beneficial to the heat dissipation of the three-dimensional stacked chip assembly and the heat dissipation of the first chip assembly 102 through the thermal bridge structure 108, thereby greatly reducing the heat dissipation thermal resistance and temperature of the first chip assembly (such as the bottom large-size chip). In addition, the thermal bridge structure 108 can have a supporting effect, which is beneficial to reducing the use of packaging materials around the stacked chips in the packaging structure. Among them, the heat dissipation cover assembly 111 can be a heat dissipation cap, such as a metal heat dissipation cap, and the structure is as Fig.10 As shown, the material of the heat dissipation cover assembly 114 can be a copper cover, a thermally conductive ceramic, or a ceramic-metal composite material such as AL-SIC. In one example, the thermal conductivity of the heat dissipation cover assembly 111 is set to be higher than the thermal conductivity of the thermal bridge structure 108 .

[0085] As an example, the heat dissipation cover assembly 111 is formed on the packaging substrate 100 through an adhesive layer 112. The adhesive layer 112 can be an epoxy resin or an organic silicone adhesive, such as Dow Corning 1-4173 thermal conductive adhesive, which can be used for both the adhesive layer and the material of the die-bonding layer and TIM1. In addition, the heat dissipation cover assembly can be already prepared and directly bonded to the packaging substrate 100 during the packaging process.

[0086] As an example, a second thermal interface layer 113 is also formed on the heat dissipation cover assembly 110. The second thermal interface layer 113 is TIM2, that is, a second layer of thermal interface material, which is used to fill interface gaps, reduce interface thermal resistance, and improve thermal conductivity. Uncured thermal conductive silicone grease can be used for easy disassembly, and the thickness is generally 50-200um. Of course, thermal conductive adhesives such as 1-4173 can also be used. The second thermal interface layer 113 is thermally connected to the heat dissipation cover plate 111, and a thermal conductive path can be formed between the two.

[0087] As an example, a heat sink 114 and the like can also be formed on the second thermal interface layer 113. Of course, a heat sink can also be formed on the second thermal interface layer 113, which is further conducive to the dissipation of heat. In addition, the present invention provides a thermal bridge structure 108 to share the pressure of the heat sink and the like originally added to the second chip component, so that the package is evenly stressed and the structure is more stable. The heat sink is generally fixed to the component by buckling on all sides, and the heat sink pressure can be evenly dispersed through the thermal bridge structure, so that the force becomes uniform.

[0088] As an example, Fig.10 As shown, a first space c1 is formed between the thermal bridge structure 108 and the second chip component 103, and a second space c2 is formed between the thermal bridge structure 108 and the heat dissipation cover component 111, wherein, in an optional example, at least one first exhaust hole (not shown in the figure) is provided in the thermal bridge structure 108, and the first exhaust hole connects the first space c1 and the second space c2, and may be two or more first exhaust holes, and each of the first exhaust holes may be arranged in parallel and evenly spaced on the thermal bridge structure, and pass through the side wall of the thermal bridge structure on the left and right, and the size of the first exhaust hole may be 0.2-0.5mm, such as 0.3mm or 0.4mm; further optionally, at least one second exhaust hole (not shown in the figure) is provided in the heat dissipation cover component 111, and the second exhaust hole connects the second space c2 and the outside atmosphere, and may be two or more second exhaust holes, and each of the second exhaust holes may be arranged in parallel and evenly spaced on the thermal bridge structure, and pass through the side wall of the heat dissipation cover component on the left and right, and the size of the second exhaust hole may be 0.3-1mm, such as 0.6mm or 0.8mm. The first exhaust hole and the second exhaust hole can be used for releasing gas during the solidification of organic materials to reduce structural stress.

[0089] As an example, there is a first bump array 104 between the first chip assembly 102 and the second chip assembly 103, and the first bump array 104 includes a plurality of first bump units (bumps) 104a. The material of the first bump unit (bump) 104a can be SAC (tin-silver-copper alloy), which can be formed by screen printing or evaporation process. In addition, a first bottom filling layer (underfill) is formed between the first bump units 104a. The bottom filling layer is generally made of epoxy material and curing agent. The gap in the middle of the bump is finally filled by dispensing glue on one or more sides of the chip at a medium-high temperature such as 80°C and capillary flow. After a curing time of 10 minutes to 30 minutes, the main function is to match the deformation and stress caused by thermal expansion to improve reliability. The first bottom filling layer fills the gap between the upper and lower chips.

[0090] As an example, the second chip assembly 103 includes at least two semiconductor chips stacked one above the other, and the adjacent semiconductor chips are electrically connected via a second bump array 105. The second bump array 105 includes a plurality of second bump units 105a. The composition and other related descriptions of the second bump units 105a are consistent with those of the first bump units 104a, and reference may be made to the related descriptions of the first bump units 104a. In addition, a second bottom filling layer is formed between the second bump units 105a, and the second bottom filling layer fills the gap between the upper and lower chips.

[0091] As an example, when the first chip assembly 102 includes two or more semiconductor chips stacked one above the other, adjacent semiconductor chips are electrically connected via a third bump array (not shown in the figure), and the third bump array includes a plurality of third bump units.

[0092] In one example, the temperature and temperature difference of the first chip component 102 (bottom large-size chip) can be adjusted by at least one of the spacing, height, and size between the first bump units 104a and the spacing, height, and size between the second bump units 105a. At this time, in one example, the first bump unit 104a and the second bump unit 105a are arranged one by one up and down, and the arrangement and size of the two are equal. It can be considered that the two have the same adjustment on the temperature of the first chip component 102 (bottom large-size chip).

[0093] The temperature and temperature difference on the first chip assembly 102 are related to the size of the first bump unit 104a and the second bump unit 105a above it. The higher the height of the first bump unit 104a and the second bump unit 105a, the smaller the diameter, the greater the thermal resistance, and the greater the temperature and temperature difference on the first chip assembly 102; the larger the spacing between adjacent first bump units 104a, the smaller the temperature and temperature difference on the first chip assembly 102; the larger the spacing between adjacent second bump units 105a (that is, the sparser), the higher the temperature and temperature difference on the first chip assembly 102. In an example, the first bump unit 104a and the second bump unit 105a are arranged one by one up and down. Among them, the so-called bump height, size and spacing adjust the temperature and temperature difference, which actually provides an equivalent heat conduction path. The thermal resistance of the equivalent heat conduction path is proportional to the height, and inversely proportional to the geometric factor A / L of the bump when the height is constant. A is the effective cross-sectional area of ​​the bump, which is the bottom area for cylindrical bumps, and L is the height. If the thermal resistance on the bump side is small, the temperature in the middle of the large chip is low and is at the same level as the temperature on the edge. Otherwise, the temperature in the middle increases, further leading to larger temperature and temperature difference.

[0094] As an example, the height of the first bump unit is less than 30 μm, and may be 15 μm, 10 μm, 8 μm, etc., and the height of the second bump unit is less than 30 μm, and may be 15 μm, 10 μm, 8 μm, etc.

[0095] For the setting of the thermal bridge structure of the present invention, as shown in Figures 11(a) and (b), a temperature distribution profile diagram of a package structure with the thermal bridge structure and without the thermal bridge structure in an example is provided. Among them, Figure 11(a) shows the side view and top view of the temperature distribution profile diagram of the package structure without the thermal bridge structure, and Figure 11(b) shows the side view and top view of the temperature distribution profile diagram of the package structure with the thermal bridge structure. It can be seen from the figure that in the package structure without the thermal bridge structure, almost all the heat is transferred upward to the heat dissipation cover assembly and the radiator through the second chip assembly (such as a memory stack chip, memory stack, in this example, an 8-layer stacked chip structure), and the temperature of the bottom first chip assembly (such as the bottom logic chip) is as high as 207°C, the temperature is uneven, and it is easy to cause a large temperature gradient and thermal stress, and the high-temperature hot spots at the corners of the first chip assembly are more obvious. In the packaging structure arranged with a thermal bridge structure, part of the heat is transferred upward to the heat dissipation cover assembly and the radiator through the second chip assembly (such as a memory stack chip, memory stack, in this example, an 8-layer stacked chip structure), and part of the heat is transferred upward through the thermal bridge structure. The temperature of the bottom first chip assembly (such as the bottom logic chip) can be reduced to 97.3°C, the temperature is uniform, the temperature gradient and thermal stress are reduced, and the high temperature at the corners of the first chip assembly disappears.

[0096] As shown in FIG12, a distribution diagram of the highest temperature on different chips in a package structure with different pitches and sizes of second bump units (which can also be considered as first bump units) with and without a thermal bridge structure is provided in an example, wherein FIG12(a) shows the distribution of the highest temperature on different chips in a package structure with different pitches and sizes of second bump units in a package structure without a thermal bridge structure, and FIG12(b) shows the distribution of the highest temperature on different chips in a package structure with different pitches and sizes of second bump units in a package structure with a thermal bridge structure, wherein CuSpacer indicates that the material of the thermal bridge structure is copper. Wherein, Bump(50,30) indicates that the pitch between the second bump units is 50um, and the diameter and height of the second bump units are both 30um; Bump(50,30,10) indicates that the pitch between the second bump units is 50um, the diameter of the second bump unit is 30um, and the height of the second bump unit is 10um. Die represents a large chip (the first chip component), DRAM0-DRAM1 represents the first of the stacked chips (the second chip component) from bottom to top close to the first chip component, and so on. As can be seen from the figure, in the packaging structure with a thermal bridge structure, the maximum temperature of the chip is reduced. As shown in Bump (50, 30), the temperature of the bottom first chip component (such as the bottom logic chip) can be reduced to below 100°C.

[0097] In addition, if Fig.13 As shown, a comparison diagram of the relationship between the temperature gradient of the first chip component (such as CPU) and the spacing and size of the second bump unit in an example is provided. It can be seen that the higher the height of the second bump unit (from 10um to 60um), the greater the thermal resistance, resulting in a large temperature difference on the first chip component, causing greater thermal stress. Therefore, the actual height of the second bump unit is designed to be below 30um, which can significantly reduce the thermal resistance. In addition, a full array arrangement is adopted. The full array refers to an m*n array, that is, m rows and n columns, without locally missing bumps. If the middle bump is missing, for example, there are only bumps around, it cannot be a full array arrangement, resulting in large thermal resistance and high temperature at the missing part, affecting reliability and design performance.

[0098] As an example, the first chip component 102 is thermally connected to the heat dissipation cover component 111 through the thermal bridge structure 108 above and has a first thermal resistance (external thermal resistance), and the first chip component 102 is thermally connected to the heat dissipation cover component 111 through the second chip component 103 above and has a second thermal resistance (internal thermal resistance), wherein the specific thermal resistance value of the first thermal resistance is the thermal resistance per unit bottom surface area of ​​the thermal bridge (note that the specific thermal resistance and thermal resistance differ by an area, unit: Kcm 2 / W), which is between 0.8-2.5 times the resistance value of the second specific thermal resistance, and is preferably greater than 1.2 and less than 2. That is to say, a heat dissipation path is formed between the first chip component 102 corresponding to the bottom, the thermal bridge structure 108 and the heat dissipation cover component 111, and the path has a first thermal resistance. A heat dissipation path is formed between the first chip component 102 corresponding to the top and bottom, the second chip component 103 and the heat dissipation cover component 111, and the path has a second thermal resistance. The specific thermal resistance of the first thermal resistance is between 0.8-2.5 times the resistance value of the second thermal resistance, and is preferably greater than 1.2 and less than 2, and can be 1.2 times, 1.3 times, etc. The difference in thermal resistance on the two paths can be controlled by the thermal bridge structure. In one example, the first chip component, such as the CPU chip, generally has a higher temperature in the middle of the chip and a lower temperature around it. By adjusting the internal and external thermal resistances (the first thermal resistance and the second thermal resistance), the temperature difference of the first chip component can be reduced and the temperature rise can be improved. Fig.14 As shown, it is a curve diagram showing the temperature difference of a first chip component (such as a CPU) in an example as the ratio of the first thermal resistance to the second thermal resistance changes, wherein TIM1 in the figure is 0.263Kcm 2 / W(50,30,30) means that the specific thermal resistance of the first interface layer is 0.263, the spacing between the second bump units 105a is 50um, the diameter is 30um, the height is 10um, and R 2 Representing the curve fitting degree, the ratio of the first thermal resistance to the second thermal resistance can be selected between 0.8-2.5 times, preferably greater than 1.2 and less than 2.

[0099] like Figure 1 As shown, the present invention also provides a three-dimensional chip packaging method. The three-dimensional chip packaging structure provided by the present invention is preferably prepared by the three-dimensional chip packaging method provided by the present invention, and of course, it can also be packaged by other methods. The present invention adds a thermal bridge structure assembly step, the process is simple, and does not affect the existing packaging process and process.

[0100] In one example, if Figure 1 As shown, the packaging method includes:

[0101] First, if Figure 1 S1 and Figure 2 As shown, step S1 is performed to provide a packaging substrate 100;

[0102] Then, if Figure 1 S2 and Figure 3As shown, step S2 is performed to form a three-dimensional stacked chip component 101 on the packaging substrate 100, wherein the three-dimensional stacked chip component 101 includes a first chip component 102 and a second chip component 103 formed on the first chip component 102, and the size of the first chip component 102 is larger than the size of the second chip component 103;

[0103] Then, if Figure 1 S3 and Figure 4-7 As shown, step S3 is performed to prepare a thermal bridge structure 108 on the first chip component 101, and a preset distance is provided between the thermal bridge structure 108 and the second chip component 103; and

[0104] Finally, if Figure 1 S3 and Figure 8-10 As shown, step S4 is performed to form a heat dissipation cover assembly 111 on the packaging substrate 100, wherein the heat dissipation cover assembly 111 surrounds the three-dimensional stacked chip assembly 101 and the thermal bridge structure 108, and the thermal bridge structure 108, the first chip assembly 102 and the heat dissipation cover assembly 111 are thermally connected.

[0105] As an example, the first chip component 102 includes a central area and a peripheral area surrounding the central area, wherein the second chip component 103 is disposed on the central area, and the thermal bridge structure 108 is disposed on the peripheral area.

[0106] As an example, before forming the thermal bridge structure 108, the steps include: forming a bottom bonding layer 107 at the position of the first chip component 102 where the thermal bridge structure 108 is to be formed, and the thermal bridge structure 108 is formed on the bottom bonding layer. In the process of forming the bottom bonding layer 107, it can be as follows Figure 4 As shown, dispensing is first performed to form a first dispensing layer 106 , and then the bottom die-bonding layer 107 is formed based on the first dispensing layer 106 .

[0107] As an example, the formation of the thermal bridge structure 108 includes the following steps: forming a first thermal interface layer 110 on the thermal bridge structure 108 and the three-dimensional stacked chip assembly 101, and forming the heat dissipation cover assembly 111 on the first thermal interface layer 110. In the process of forming the first thermal interface layer 110, the following steps may be performed: Figure 8 As shown, dispensing is first performed to form a second dispensing layer 109 , and then the first thermal interface layer 110 is formed based on the second dispensing layer 109 .

[0108] As an example, the formation of the heat dissipation cover assembly 111 includes the following steps: forming a second thermal interface layer 113 on the heat dissipation cover assembly 111 , and thermally conducting between the second thermal interface layer 113 and the heat dissipation cover assembly 111 .

[0109] As an example, a first bump array 104 is provided between the first chip assembly 102 and the second chip assembly 103 , and the first bump array 104 includes a plurality of first bump units 104 a .

[0110] As an example, the second chip assembly includes at least two semiconductor chips stacked one above the other, and adjacent semiconductor chips are electrically connected via a second bump array 105 , and the second bump array includes a plurality of second bump units 105 a .

[0111] As an example, the temperature and the temperature difference on the first chip assembly 102 are adjusted by at least one of the spacing, height, and size between the first bump units 104 a and the spacing, height, and size between the second bump units 105 a .

[0112] As an example, Fig.10 As shown, a first space c1 is formed between the thermal bridge structure 108 and the second chip component 103, and a second space c2 is formed between the thermal bridge structure 108 and the heat dissipation cover component 111. In an optional example, at least one first exhaust hole (not shown in the figure) is provided in the thermal bridge structure 108, and the first exhaust hole connects the first space c1 and the second space c2. There may be two or more first exhaust holes, and each of the first exhaust holes may be arranged in parallel and evenly spaced on the thermal bridge structure, and penetrate the side wall of the thermal bridge structure from left to right. The first exhaust hole may be formed in the thermal bridge structure before packaging. The size of the first exhaust hole can be 0.2-0.5mm, such as 0.3mm or 0.4mm; further optionally, at least one second exhaust hole (not shown in the figure) is provided in the heat dissipation cover assembly 111, and the second exhaust hole connects the second space c2 and the outside atmosphere, and can be two or more second exhaust holes, and each of the second exhaust holes can be arranged in parallel and evenly spaced on the thermal bridge structure, and penetrate the side wall of the heat dissipation cover assembly from left to right, and the second exhaust hole can be formed in the heat dissipation cover assembly before packaging, and the size of the second exhaust hole can be 0.3-1mm, such as 0.6mm or 0.8mm. The first exhaust hole and the second exhaust hole can be used for degassing of organic materials during solidification to reduce structural stress.

[0113] As an example, the first chip component 102 is thermally connected to the heat dissipation cover component 111 through the thermal bridge structure 108 above and has a first thermal resistance, and the first chip component 102 is thermally connected to the heat dissipation cover component 111 through the second chip component 103 above and has a second thermal resistance, wherein the specific thermal resistance value of the first thermal resistance is between 0.8-2.5 times the specific thermal resistance value of the second thermal resistance, preferably greater than 1.2 and less than 2.

[0114] In summary, the three-dimensional chip packaging structure and packaging method of the present invention, by introducing a thermal bridge structure, form a heat conduction path, which is beneficial to the heat dissipation of the three-dimensional stacked chip and greatly reduces the heat dissipation thermal resistance and temperature of the bottom chip. Through the design of the present invention, the temperature difference of the chip can be reduced, thereby greatly reducing thermal stress. The thermal bridge structure shares the pressure of the heat sink and the like originally applied to the three-dimensional stacked chip, so that the packaging force is more evenly distributed and the structure is more stable. The process of the present invention is simple and basically does not affect the existing packaging process flow and process (infrastructure). Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0115] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A three-dimensional chip packaging structure, characterized in that: The packaging structure comprises: Package substrate; A three-dimensional stacked chip assembly is formed on the packaging substrate, wherein the three-dimensional stacked chip assembly includes a first chip assembly and a second chip assembly formed on the first chip assembly, and the size of the first chip assembly is larger than the size of the second chip assembly; a thermal bridge structure formed on the first chip component, wherein a preset distance exists between the thermal bridge structure and the second chip component; and A heat dissipation cover assembly is formed on the packaging substrate, the heat dissipation cover assembly surrounds the three-dimensional stacked chip assembly and the thermal bridge structure, and the thermal bridge structure, the first chip assembly and the heat dissipation cover assembly are thermally connected; The first chip assembly includes a central area and a peripheral area surrounding the central area, wherein the second chip assembly is arranged on the central area, and the thermal bridge structure is arranged on the peripheral area; A first thermal interface layer is disposed between the thermal bridge structure and the heat dissipation cover assembly, the first thermal interface layer is also located between the three-dimensional stacked chip assembly and the heat dissipation cover assembly, and / or a second thermal interface layer is also formed on the heat dissipation cover assembly, the second thermal interface layer is thermally conductive with the heat dissipation cover assembly; The first chip component is thermally connected to the heat dissipation cover component through the thermal bridge structure above and has a first thermal resistance, and the first chip component is thermally connected to the heat dissipation cover component through the second chip component above and has a second thermal resistance, wherein the specific thermal resistance value of the first thermal resistance is between 0.8-2.5 times the specific thermal resistance value of the second thermal resistance.

2. The three-dimensional chip packaging structure according to claim 1, characterized in that: The shape of the thermal bridge structure includes a ring; the preset spacing between the thermal bridge structure and the second chip component is between 0.2-2mm; the width of the thermal bridge structure is between 1-5mm; the thermal bridge structure is formed on the first chip component through a bottom solid crystal layer.

3. The three-dimensional chip packaging structure according to claim 1, characterized in that: The upper surface of the thermal bridge structure is not higher than the upper surface of the three-dimensional stacked chip assembly, and the height difference between the upper surface of the thermal bridge structure and the upper surface of the three-dimensional stacked chip assembly is less than 100 μm.

4. The three-dimensional chip packaging structure according to claim 1, characterized in that: There is a first bump array between the first chip component and the second chip component, and the first bump array includes a plurality of first bump units; and / or the second chip component includes at least two semiconductor chips stacked one above the other, and adjacent semiconductor chips are electrically connected via a second bump array, and the second bump array includes a plurality of second bump units.

5. The three-dimensional chip packaging structure according to claim 4, characterized in that: The height of the first bump unit is less than 30 μm, and the height of the second bump unit is less than 30 μm; the temperature and temperature difference on the first chip component are adjusted by at least one of the spacing, height, and size between the first bump units and the spacing, height, and size between the second bump units.

6. The three-dimensional chip packaging structure according to claim 1, characterized in that: A first space is formed between the thermal bridge structure and the second chip assembly, and a second space is formed between the thermal bridge structure and the heat dissipation cover assembly, wherein at least one first exhaust hole is provided in the thermal bridge structure, and the first exhaust hole connects the first space and the second space; and / or at least one second exhaust hole is provided in the heat dissipation cover assembly, and the second exhaust hole connects the second space with the outside atmosphere.

7. A three-dimensional chip packaging method, characterized in that: The packaging method comprises: Providing a packaging substrate; Forming a three-dimensional stacked chip component on the packaging substrate, wherein the three-dimensional stacked chip component includes a first chip component and a second chip component formed on the first chip component, and the size of the first chip component is larger than the size of the second chip component; Preparing a thermal bridge structure on the first chip component, with a preset distance between the thermal bridge structure and the second chip component; and A heat dissipation cover assembly is formed on the packaging substrate, wherein the heat dissipation cover assembly surrounds the three-dimensional stacked chip assembly and the thermal bridge structure, and the thermal bridge structure, the first chip assembly and the heat dissipation cover assembly are thermally connected; The first chip component is thermally connected to the heat dissipation cover component through the thermal bridge structure above and has a first thermal resistance, and the first chip component is thermally connected to the heat dissipation cover component through the second chip component above and has a second thermal resistance, wherein the specific thermal resistance value of the first thermal resistance is between 0.8-2.5 times the specific thermal resistance value of the second thermal resistance.

8. The three-dimensional chip packaging method according to claim 7, characterized in that: The first chip component includes a central area and a peripheral area surrounding the central area, wherein the second chip component is disposed on the central area, and the thermal bridge structure is disposed on the peripheral area.

9. The three-dimensional chip packaging method according to claim 7, characterized in that: Before forming the thermal bridge structure, the method includes the following steps: forming a bottom solid crystal layer at the position of the first chip component where the thermal bridge structure is to be formed, and the thermal bridge structure is formed on the bottom solid crystal layer.

10. The three-dimensional chip packaging method according to claim 7, characterized in that: After forming the thermal bridge structure, the steps include: forming a first thermal interface layer on the thermal bridge structure and the three-dimensional stacked chip assembly, and the heat dissipation cover assembly is formed on the first thermal interface layer; And / or, a second thermal interface layer is formed on the heat dissipation cover assembly, and the second thermal interface layer is thermally connected to the heat dissipation cover assembly.

11. The three-dimensional chip packaging method according to claim 7, characterized in that: There is a first bump array between the first chip component and the second chip component, and the first bump array includes a plurality of first bump units; and / or the second chip component includes at least two semiconductor chips stacked one above the other, and adjacent semiconductor chips are electrically connected via a second bump array, and the second bump array includes a plurality of second bump units.

12. The three-dimensional chip packaging method according to claim 11, characterized in that: The temperature and the temperature difference on the first chip component are adjusted by at least one of the spacing, height, and size between the first bump units and the spacing, height, and size between the second bump units.

13. The three-dimensional chip packaging method according to claim 7, characterized in that: A first space is formed between the thermal bridge structure and the second chip assembly, and a second space is formed between the thermal bridge structure and the heat dissipation cover assembly, wherein at least one first exhaust hole is provided in the thermal bridge structure, and the first exhaust hole connects the first space and the second space; and / or at least one second exhaust hole is provided in the heat dissipation cover assembly, and the second exhaust hole connects the second space with the outside atmosphere.

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