Wire, display device including the wire, and method for manufacturing the display device

Abstract

The present disclosure relates to a conductive line, a display device including the conductive line, and a method for manufacturing the display device. The conductive line for the display device may include: a first layer including aluminum or an aluminum alloy; a second layer arranged on the first layer, the second layer including titanium nitride; and a third layer arranged on the second layer, the third layer including titanium and having a multilayer structure including a plurality of stacked sublayers.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly to a conductive line for a display device, a display device including the conductive line, and a method of manufacturing the display device including the conductive line. Background Art

[0002] As display devices for visually representing various electrical signal information have been rapidly developed, various flat panel display devices having excellent characteristics such as thinness, lightness, and low power consumption have been used. Liquid crystal display devices and organic light emitting display devices among flat panel display devices are widely commercialized due to their advantages such as excellent resolution, image quality, etc. In particular, the organic light emitting display device has attracted attention due to its advantages such as wide viewing angle, high contrast, and high response speed.

[0003] Recently, the demand for display devices with high resolution has been increasing, and therefore, research has been conducted to improve pixel integration per unit area. In order to process image signals at high speed, wires with lower resistance are increasingly needed, and therefore, research has been conducted to use aluminum (Al) instead of molybdenum (Mo) and the like as materials for wires.

[0004] However, during high temperature processing, hillocks of aluminum (Al) may be generated in the conductive line including aluminum (Al). In order to prevent the generation of hillocks, a capping layer including titanium (Ti) or the like may be additionally formed on the conductive line. However, when the thickness of the capping layer increases, during the etching process of the conductive line, excessive residues may be generated from grains included in the capping layer. Summary of the invention

[0005] The embodiment provides a conductive line for a display device in which an excessive amount of residue is not generated, and a display device including the conductive line.

[0006] The embodiment provides a method of manufacturing a display device including a conductive line for preventing generation of an excessive amount of residue.

[0007] According to an embodiment, a conductive line for a display device may include: a first layer including aluminum (Al) or an aluminum alloy; a second layer disposed on the first layer, the second layer including a refractory metal nitride; and a third layer disposed on the second layer, the third layer including a refractory metal having a multilayer structure including a plurality of stacked sublayers, the third layer having an interface disposed between adjacent sublayers.

[0008] In one embodiment, the refractory metal nitride may include titanium nitride, and the refractory metal may include titanium.

[0009] In an embodiment, each of the first layer and the second layer may have a single-layer structure.

[0010] In an embodiment, the plurality of stacked sub-layers may include substantially the same material as each other.

[0011] In an embodiment, each sub-layer of the plurality of stacked sub-layers may include titanium.

[0012] In an embodiment, the plurality of stacked sub-layers may include materials different from each other.

[0013] In an embodiment, one sub-layer of the plurality of stacked sub-layers may include titanium, and another sub-layer of the plurality of stacked sub-layers may include titanium nitride or titanium oxide.

[0014] In one embodiment, the thicknesses of the plurality of stacked sub-layers may be substantially equal.

[0015] In one embodiment, the thickness of the third layer may be smaller than the thickness of the first layer.

[0016] In one embodiment, the thickness of the second layer may be smaller than the thickness of the first layer and the thickness of the third layer.

[0017] In one embodiment, the third layer may consist of two, three or four sub-layers.

[0018] A display device according to an embodiment may include: a substrate; a semiconductor layer disposed on the substrate; a first conductive line disposed on the semiconductor layer; and a second conductive line disposed on the first conductive line. The second conductive line may include: a first layer including aluminum (Al) or an aluminum alloy; a second layer disposed on the first layer, the second layer including a refractory metal nitride; and a third layer disposed on the second layer, the third layer including a refractory metal and having a multilayer structure including a plurality of stacked sublayers, the third layer having an interface disposed between adjacent sublayers.

[0019] In one embodiment, the first conductive line may include: a first layer including aluminum or an aluminum alloy; a second layer disposed on the first layer, the second layer including titanium nitride; and a third layer disposed on the second layer, the third layer including titanium and having a single-layer structure.

[0020] In an embodiment, a thickness of the third layer of the second conductive line may be greater than or substantially equal to a thickness of the third layer of the first conductive line.

[0021] In an embodiment, a thickness of each of the plurality of stacked sub-layers of the third layer of the second conductive line may be smaller than a thickness of the third layer of the first conductive line.

[0022] In an embodiment, an average size of grains included in the third layer of the second conductive line may be smaller than an average size of grains included in the third layer of the first conductive line.

[0023] In one embodiment, the display device may further include a third wire disposed on the second wire. The third wire may contact the semiconductor layer via a first contact hole exposing a portion of the semiconductor layer, and may contact the second wire via a second contact hole exposing a portion of the second wire.

[0024] In one embodiment, the depth of the first contact hole may be greater than the depth of the second contact hole.

[0025] In one embodiment, the display device may further include: a first electrode disposed on the second conductive line; an emission layer disposed on the first electrode; and a second electrode disposed on the emission layer.

[0026] The method of manufacturing a display device according to an embodiment may include: forming a semiconductor layer on a substrate; forming a first conductive line on the semiconductor layer; and forming a second conductive line on the first conductive line, the second conductive line including: a first layer including aluminum or an aluminum alloy, a second layer including a refractory metal nitride, and a third layer including a refractory metal. The third layer of the second conductive line may have a multilayer structure including a plurality of stacked sublayers, and the forming of the second conductive line may include forming a vacuum break between the sublayers formed by discontinuous deposition.

[0027] In one embodiment, the first conductive line may include a first layer including aluminum or an aluminum alloy, a second layer including titanium nitride, and a third layer including titanium. During the formation of the third layer of the first conductive line, the third layer of the first conductive line may be formed without vacuum interruption.

[0028] In an embodiment, a thickness of the third layer of the second conductive line may be greater than or substantially equal to a thickness of the third layer of the first conductive line.

[0029] In one embodiment, the method may further include: forming a first insulating layer covering the semiconductor layer before forming the first conductive line; forming a second insulating layer covering the first conductive line before forming the second conductive line; forming a third insulating layer covering the second conductive line; forming a first contact hole passing through the first insulating layer, the second insulating layer and the third insulating layer to expose a portion of the semiconductor layer, and forming a second contact hole passing through the third insulating layer to expose a portion of the second conductive line; and forming a third conductive line on the third insulating layer, the third conductive line filling the first contact hole and the second contact hole.

[0030] In one embodiment, the first contact hole and the second contact hole may be formed substantially simultaneously.

[0031] In one embodiment, the method may further include: forming a first electrode on the second conductive line; forming an emission layer on the first electrode; and forming a second electrode on the emission layer.

[0032] According to an embodiment of the present invention, the conductive line for a display device may include: a first layer including an aluminum (Al) alloy; a second layer disposed on the first layer, the second layer including titanium nitride (TiN x );And a third layer disposed on the second layer, the third layer includes titanium (Ti), the third layer has a multilayer structure including a plurality of stacked sublayers, and the third layer has an interface between adjacent sublayers.

[0033] According to an embodiment, a display device may include: a substrate; a switching transistor, including a first gate electrode, the first gate electrode including aluminum or an aluminum alloy, a refractory metal nitride and a refractory metal sequentially arranged on the substrate; a driving transistor, including a second gate electrode, the second gate electrode including aluminum or an aluminum alloy, a refractory metal nitride and a refractory metal sequentially arranged on the substrate; a light emitting diode having an electrode connected to the driving transistor and arranged on the substrate, wherein the refractory metal in the second gate electrode includes a plurality of stacked sublayers, and the plurality of stacked sublayers have interfaces arranged between adjacent sublayers.

[0034] In one embodiment, the refractory metal in the first gate electrode may have no interface.

[0035] In one embodiment, the refractory metal nitride may include titanium nitride, and the refractory metal may include titanium.

[0036] In an embodiment, each of the plurality of stacked sub-layers may have columnar grains, and the columnar grains have discontinuous portions at the interface.

[0037] In one embodiment, the plurality of stacked sub-layers of the refractory metal in the driving transistor may include a titanium layer and a titanium nitride layer or a titanium oxide layer disposed on the titanium layer.

[0038] In an embodiment, the plurality of stacked sub-layers of the refractory metal in the driving transistor may include a plurality of titanium layers stacked sequentially and the interface is between adjacent titanium layers.

[0039] In one embodiment, the display device may further include a capacitor connected between the source electrode and the gate electrode of the driving transistor. The capacitor may include a first electrode having the same structure as the first gate electrode and a second electrode having the same structure as the second gate electrode.

[0040] In one embodiment, an average size of grains included in the refractory metal in the driving transistor may be smaller than an average size of grains included in the refractory metal in the switching transistor.

[0041] In the conductive line for a display device and the display device including the conductive line according to the embodiment, the conductive line may include: a first layer including aluminum or an aluminum alloy, a second layer including titanium nitride, and a third layer including titanium, and the third layer may have the multilayer structure including the plurality of stacked sublayers. Therefore, a conductive line that does not generate an excessive amount of residue during the etching process can be provided.

[0042] In the method of manufacturing a display device including a conductive line according to an embodiment, a plurality of stacked sub-layers of a third layer of the conductive line may be formed by discontinuous deposition, and thus, generation of excessive residues during an etching process may be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0044] Figure 1 is a plan view showing a display device according to an embodiment.

[0045] Figure 2 It is shown Figure 1 A circuit diagram of an example of a pixel in FIG.

[0046] Figure 3 is a cross-sectional view showing a display device according to an embodiment.

[0047] Figure 4 It is shown Figure 3 A cross-sectional view of the first conductor in FIG.

[0048] Figure 5 It is shown Figure 3 A cross-sectional view of the second wire in FIG.

[0049] Fig. 6A and Figure 6B It is shown Figure 4 A diagram of a die in the third layer of the first conductor.

[0050] Fig. 7A , Figure 7B and Figure 7C It is shown Figure 5Figure 2. A diagram of a die in the third layer of the second conductor.

[0051] Figure 8 , Fig. 9 , Fig.10 , Fig.11 and Fig.12 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0052] Hereinafter, a conductive line, a display device, and a method of manufacturing the display device according to embodiments will be described in detail with reference to the accompanying drawings.

[0053] In the following, reference will be made to Figures 1 to 7C A conductive line for a display device and a display device including the conductive line according to an embodiment are described.

[0054] Figure 1 is a plan view showing a display device 100 according to an embodiment.

[0055] refer to Figure 1 , the display device 100 may include a substrate 110 and a plurality of pixels PX disposed on the substrate 110 .

[0056] The substrate 110 may include a display area DA and a peripheral area PA. The peripheral area PA may be located outside the display area DA. The peripheral area PA may be located at at least one side of the display area DA.

[0057] A plurality of gate lines GL and a plurality of data lines DL may be provided in the display area DA. The gate lines GL may extend in a first direction DR1 and may be arranged along a second direction DR2 crossing the first direction DR1. The data lines DL may extend in the second direction DR2 and may be arranged along the first direction DR1. The gate lines GL and the data lines DL may be connected to a gate driver and a data driver provided in the peripheral area PA, respectively, and may receive a gate signal and a data signal, respectively.

[0058] The pixels PX may be respectively disposed at intersections between the gate lines GL and the data lines DL, and each pixel PX may be connected to the corresponding gate line GL and the corresponding data line DL to receive a gate signal and a data signal. Each pixel PX may emit light in response to the gate signal and the data signal, and the light emitted from each pixel PX may display an image in the display area DA. The pixels PX may not be disposed in the peripheral area PA, and therefore, the peripheral area PA may be a non-display area.

[0059] Figure 2 It is shown Figure 1 2 is a circuit diagram of an example of a pixel PX in FIG.

[0060] refer to Figure 2 , the pixel PX may be electrically connected to the gate line GL, the data line DL, the first power source ELVDD and the second power source ELVSS. In one embodiment, the voltage level of the first power source ELVDD may be greater than the voltage level of the second power source ELVSS.

[0061] In one embodiment, the pixel PX may include a first transistor TR1 (switching transistor), a second transistor TR2 (driving transistor), a capacitor CAP, and an organic light emitting diode OLED. However, the present disclosure is not limited thereto, and in another embodiment, the pixel PX may include three or more transistors and / or two or more capacitors. In addition, in another embodiment, the elements of the pixel PX may be connected to Figure 2 The connections of the elements of the pixel PX shown are connected differently.

[0062] The first transistor TR1 may have a gate electrode connected to the gate line GL, a source electrode connected to the data line DL, and a drain electrode connected to the first node N1. The second transistor TR2 may have a gate electrode connected to the first node N1, a source electrode connected to the first power source ELVDD, and a drain electrode connected to the organic light emitting diode OLED. The capacitor CAP may have a first capacitor electrode connected to the first node N1 and a second capacitor electrode connected to the first power source ELVDD. The organic light emitting diode OLED may have an anode connected to the second transistor TR2 and a cathode connected to the second power source ELVSS.

[0063] When the first transistor TR1 is turned on by a gate signal received from the gate line GL, the first transistor TR1 may transmit a data signal received from the data line DL to the first node N1. The second transistor TR2 may supply a driving current to the organic light emitting diode OLED in response to a voltage between the first power source ELVDD stored in the capacitor CAP and the first node N1, and the organic light emitting diode OLED may emit light according to the driving current.

[0064] Figure 3 is a cross-sectional view showing a display device 100 according to an embodiment. For example, Figure 3 It can be shown Figure 2 The pixel PX in.

[0065] refer to Figure 3, the display device 100 may include a first transistor TR1, a second transistor TR2, a capacitor CAP, and an organic light emitting diode OLED disposed on a substrate 110. Sequentially stacked semiconductor layers 131 and 132, first conductive lines 151 and 153, second conductive lines 172 and 173, third conductive lines 191a, 191b, 192a, and 192b, a first electrode 220, an emission layer 240, and a second electrode 250 may be disposed on the substrate 110.

[0066] The substrate 110 may be an insulating substrate including glass, quartz, plastic, or the like.

[0067] The buffer layer 120 may be disposed on the substrate 110. The buffer layer 120 may block impurities such as oxygen, moisture, etc. from penetrating into the substrate 110. In addition, the buffer layer 120 may provide a planarized surface over the substrate 110. The buffer layer 120 may be an inorganic insulating layer including silicon nitride, silicon oxide, silicon oxynitride, etc. Alternatively, the buffer layer 120 may be omitted.

[0068] The semiconductor layers 131 and 132 may be disposed on the buffer layer 120. The semiconductor layers 131 and 132 may include a first semiconductor 131 and a second semiconductor 132 spaced apart from each other (for ease of understanding and clarity, the first semiconductor 131 and the second semiconductor 132 are represented by the same reference numerals as the corresponding semiconductor layers 131 and 132, respectively). The semiconductor layers 131 and 132 may be formed of amorphous silicon, polycrystalline silicon, or an oxide semiconductor, etc. Each of the first semiconductor 131 and the second semiconductor 132 may include a source region, a drain region, and a channel region formed between the source region and the drain region.

[0069] The first insulating layer 140 may be disposed on the semiconductor layers 131 and 132. The first insulating layer 140 may be disposed on the buffer layer 120 and may cover the semiconductor layers 131 and 132. The first insulating layer 140 may insulate the first conductive lines 151 and 153 from the semiconductor layers 131 and 132. The first insulating layer 140 may be an inorganic insulating layer including silicon nitride, silicon oxide, silicon oxynitride, etc. In one embodiment, the first insulating layer 140 may be a silicon oxide layer having a thickness from about 600 angstroms to about 1400 angstroms.

[0070] The first conductive lines 151 and 153 may be disposed on the first insulating layer 140. The first conductive lines 151 and 153 may include a first gate electrode 151 and a first capacitor electrode 153 spaced apart from each other (for ease of understanding and clarity, the first gate electrode 151 and the first capacitor electrode 153 are represented by the same reference numerals as the corresponding first conductive lines 151 and 153, respectively). The first gate electrode 151 may overlap the channel region of the first semiconductor 131.

[0071] Figure 4 It is shown Figure 3 sectional view of the first conductive lines 151 and 153 in FIG.

[0072] refer to Figure 4 , the first conductive line 400 may include a plurality of layers 410 , 420 , and 430 . Figure 4 The first conductor 400 in may correspond to Figure 3 The first conductive line 400 may include a first layer 410 , a second layer 420 disposed on the first layer 410 , and a third layer 430 disposed on the second layer 420 .

[0073] The first layer 410 may include aluminum (Al) or an aluminum alloy. Aluminum may have a relatively low resistivity, and therefore, the first layer 410 may be used as a main conductive layer of the first wire 400. In one embodiment, the first layer 410 may have a single-layer structure. In such an embodiment, the first layer 410 may include aluminum or an aluminum alloy having high conductivity. In one embodiment, the thickness TH41 of the first layer 410 may be in the range of from about 1000 angstroms to about 1800 angstroms.

[0074] The second layer 420 may include a refractory metal nitride, for example, titanium nitride (TiN x ). The second layer 420 may be disposed between the first layer 410 and the third layer 430, and may be used as an auxiliary conductive layer, for example, a diffusion barrier layer that prevents diffusion of materials between the first layer 410 and the third layer 430. Because the second layer 420 is formed between the first layer 410 and the third layer 430, diffusion of materials between the first layer 410 and the third layer 430 may be reduced or substantially prevented. Therefore, a metal alloy having a relatively high resistivity may be prevented from being formed at an interface between the first layer 410 and the third layer 430. In one embodiment, the second layer 420 may have a single-layer structure. In such an embodiment, the second layer 420 may include titanium nitride (TiN x In one embodiment, the thickness TH42 of the second layer 420 may be in a range from about 100 angstroms to about 300 angstroms.

[0075] The third layer 430 may include a refractory metal, for example, titanium (Ti). The third layer 430 may not have an interface therein. The third layer 430 may be used as a capping layer to prevent the hillock of aluminum included in the first layer 410 from being generated in a high temperature process. In one embodiment, the third layer 430 may have a single layer structure. In such an embodiment, the third layer 430 may be composed of titanium (Ti). In one embodiment, the thickness TH43 of the third layer 430 may be in the range of from about 300 angstroms to about 700 angstroms.

[0076] In one embodiment, the thickness TH43 of the third layer 430 may be smaller than the thickness TH41 of the first layer 410. Since the third layer 430 serves as a capping layer, the third layer 430 may have a relatively small thickness to reduce a step portion due to the first conductive line 400. In one embodiment, the thickness TH42 of the second layer 420 may be smaller than the thickness TH41 of the first layer 410 and the thickness TH43 of the third layer 430. Since the second layer 420 includes a refractory metal nitride having a relatively high resistivity, the second layer 420 may have a thickness smaller than the thicknesses of the first layer 410 and the third layer 430 including a metal.

[0077] Reference again Figure 3 , the second insulating layer 160 may be disposed on the first conductive lines 151 and 153. The second insulating layer 160 may be disposed on the first insulating layer 140 and may cover the first conductive lines 151 and 153. The second insulating layer 160 may insulate the second conductive lines 172 and 173 from the first conductive lines 151 and 153. The second insulating layer 160 may be an inorganic insulating layer including silicon nitride, silicon oxide, silicon oxynitride, etc. In one embodiment, the second insulating layer 160 may be a silicon nitride layer having a thickness from about 600 angstroms to about 1400 angstroms.

[0078] The second conductive lines 172 and 173 may be disposed on the second insulating layer 160. The second conductive lines 172 and 173 may include a second gate electrode 172 and a second capacitor electrode 173 spaced apart from each other (for ease of understanding and clarity, the second gate electrode 172 and the second capacitor electrode 173 are represented by the same reference numerals as the corresponding second conductive lines 172 and 173, respectively). The second gate electrode 172 may overlap the channel region of the second semiconductor 132. The second capacitor electrode 173 may overlap the first capacitor electrode 153. The first capacitor electrode 153 and the second capacitor electrode 173 may form a capacitor CAP.

[0079] The third insulating layer 180 may be disposed on the second conductive lines 172 and 173. The third insulating layer 180 may be disposed on the second insulating layer 160 and may cover the second conductive lines 172 and 173. The third insulating layer 180 may insulate the third conductive lines 191a, 191b, 192a, and 192b from the second conductive lines 172 and 173. The third insulating layer 180 may be an organic insulating layer including an acrylic resin, an epoxy resin, a polyimide resin, a polyester resin, etc., or an inorganic insulating layer including silicon nitride, silicon oxide, silicon oxynitride, etc. The third insulating layer 180 may be a multilayer structure having an inorganic layer and an organic layer disposed on the inorganic layer or an organic layer disposed between the inorganic layers.

[0080] The third conductive lines 191a, 191b, 192a, and 192b may be disposed on the third insulating layer 180. The third conductive lines 191a, 191b, 192a, and 192b may include a first source electrode 191a, a first drain electrode 191b, a second source electrode 192a, and a second drain electrode 192b that are spaced apart from each other (for ease of understanding and clarity, the first source electrode 191a, the first drain electrode 191b, the second source electrode 192a, and the second drain electrode 192b are represented by the same reference numerals as the corresponding third conductive lines 191a, 191b, 192a, and 192b, respectively). The first source electrode 191a and the first drain electrode 191b may contact the source region and the drain region of the first semiconductor 131, respectively, via contact holes that pass through the first insulating layer 140, the second insulating layer 160, and the third insulating layer 180.

[0081] The second source electrode 192a may contact the source region of the second semiconductor 132 via a first contact hole CH1 exposing a portion of the second semiconductor 132, and may contact the second capacitor electrode 173 via a second contact hole CH2 exposing a portion of the second capacitor electrode 173. The first contact hole CH1 may pass through the first insulating layer 140, the second insulating layer 160, and the third insulating layer 180, and the second contact hole CH2 may pass through the third insulating layer 180. In this case, the depth of the first contact hole CH1 may be greater than the depth of the second contact hole CH2.

[0082] The second drain electrode 192b may contact the drain region of the second semiconductor 132 via a contact hole passing through the first insulating layer 140, the second insulating layer 160, and the third insulating layer 180. The first semiconductor 131, the first gate electrode 151, the first source electrode 191a, and the first drain electrode 191b may form a first transistor TR1, and the second semiconductor 132, the second gate electrode 172, the second source electrode 192a, and the second drain electrode 192b may form a second transistor TR2.

[0083] Figure 5 It is shown Figure 3 A cross-sectional view of the second wires 172 and 173 in FIG.

[0084] refer to Figure 5 , the second conductive line 500 may include a plurality of layers 510 , 520 , and 530 . Figure 5 The second conductor 500 in may correspond to Figure 3 The second conductive line 500 may include a first layer 510 , a second layer 520 disposed on the first layer 510 , and a third layer 530 disposed on the second layer 520 .

[0085] The first layer 510 may include aluminum (Al) or an aluminum alloy. Aluminum may have a relatively low resistivity, and therefore, the first layer 510 may be used as the main conductive layer of the second wire 500. In one embodiment, the first layer 510 may have a single-layer structure. In such an embodiment, the first layer 510 may include aluminum or an aluminum alloy. In one embodiment, the thickness TH51 of the first layer 510 may be in the range of from about 1000 angstroms to about 1800 angstroms. In one embodiment, the first layer 510 of the second wire 500 may include a material substantially the same as the material of the first layer 410 of the first wire 400, and may have a thickness substantially the same as the thickness of the first layer 410 of the first wire 400.

[0086] The second layer 520 may include a refractory metal nitride, for example, titanium nitride (TiN x ). The second layer 520 may be disposed between the first layer 510 and the third layer 530, and may serve as an auxiliary conductive layer to prevent diffusion of materials between the first layer 510 and the third layer 530. Because the second layer 520 is formed between the first layer 510 and the third layer 530, diffusion of materials between the first layer 510 and the third layer 530 may be reduced or substantially prevented. Therefore, a metal alloy having a relatively high resistivity may be prevented from being formed at the interface between the first layer 510 and the third layer 530. In one embodiment, the second layer 520 may have a single-layer structure. In such an embodiment, the second layer 520 may include a refractory metal nitride, for example, titanium nitride (TiN x In one embodiment, the thickness TH52 of the second layer 520 may be in a range from about 100 angstroms to about 300 angstroms. In one embodiment, the second layer 520 of the second conductive line 500 may include a material substantially the same as that of the second layer 420 of the first conductive line 400, and may have a thickness substantially the same as that of the second layer 420 of the first conductive line 400.

[0087] The third layer 530 may include titanium (Ti). The third layer 530 may be used as a capping layer to prevent hillocks of aluminum included in the first layer 510 from being generated in a high temperature process. In one embodiment, the thickness TH53 of the third layer 530 may be in a range from about 600 angstroms to about 1000 angstroms.

[0088] The third layer 530 may have a multilayer structure. The third layer 530 may include a plurality of stacked sublayers 531, 532, and 533. In one embodiment, the third layer 530 may include three sublayers 531, 532, and 533. For example, the third layer 530 may include a first sublayer 531, a second sublayer 532, and a third sublayer 533 stacked sequentially with an interface disposed between adjacent sublayers. Each of the three sublayers 531, 532, and 533 may have a columnar grain having a discontinuous portion at the interface. However, the present disclosure is not limited thereto, and in another embodiment, the third layer 530 may include two or four sublayers. In another embodiment, the third layer 530 may include five or more sublayers. Hereinafter, it is exemplarily described that the third layer 530 includes three sublayers 531, 532, and 533 in the present embodiment.

[0089] In an embodiment, the plurality of sub-layers 531, 532, and 533 may include substantially the same material. In such an embodiment, each of the plurality of sub-layers 531, 532, and 533 may include a refractory metal, such as titanium (Ti), a refractory metal nitride, or a refractory metal oxide.

[0090] In another embodiment, the plurality of sub-layers 531, 532, and 533 may include materials different from each other. In such an embodiment, one of the plurality of sub-layers 531, 532, and 533 may include titanium (Ti), and another of the plurality of sub-layers 531, 532, and 533 may include titanium nitride (TiN). x ) or titanium oxide (TiO x ). For example, each of the first sublayer 531 and the third sublayer 533 may include titanium, and the second sublayer 532 may include titanium nitride.

[0091] In one embodiment, the thicknesses of the plurality of sub-layers 531, 532, and 533 may be substantially equal. For example, when the total thickness TH53 of the third layer 530 including the three sub-layers 531, 532, and 533 is about 600 angstroms, the thickness of each of the sub-layers 531, 532, and 533 may be about 200 angstroms. However, the present disclosure is not limited thereto, and in another embodiment, the thicknesses of the plurality of sub-layers 531, 532, and 533 may be different from each other.

[0092] In one embodiment, the thickness TH53 of the third layer 530 may be smaller than the thickness TH51 of the first layer 510. Since the third layer 530 serves as a capping layer, the third layer 530 may have a relatively small thickness to reduce a step portion due to the second conductive line 500. In one embodiment, the thickness TH52 of the second layer 520 may be smaller than the thickness TH51 of the first layer 510 and the thickness TH53 of the third layer 530. Since the second layer 520 includes a refractory metal nitride having a relatively high resistivity, the second layer 520 may have a thickness smaller than the thicknesses of the first layer 510 and the third layer 530 including a metal.

[0093] In one embodiment, the thickness TH53 of the third layer 530 of the second conductive line 500 may be greater than or substantially equal to the thickness TH43 of the third layer 430 of the first conductive line 400. When the first contact hole CH1 and the second contact hole CH2 are formed simultaneously, since the depth of the first contact hole CH1 is greater than the depth of the second contact hole CH2 as described above, the third layer 530 of the second conductive line 500 may be etched during the formation of the first contact hole CH1. Since the third layer 530 of the second conductive line 500 has a relatively large thickness, the second layer 520 and the first layer 510 of the second conductive line 500 may be prevented from being etched.

[0094] Fig. 6A and Figure 6B It is shown Figure 4 FIG. 4 is a diagram of grains in the third layer 430 of the first conductive line 400 in FIG. Fig. 7A , Figure 7B and Figure 7C It is shown Figure 5 FIG. 5 is a diagram of grains in the third layer 530 of the second conductive line 500 in FIG.

[0095] In an embodiment, the thickness of each of the sublayers 531, 532, and 533 of the third layer 530 of the second conductive line 500 may be smaller than the thickness TH43 of the third layer 430 of the first conductive line 400. When the metal layer has a multilayer structure including a plurality of sublayers, the metal layer may include grains having a size smaller than that of grains included in the metal layer having a single-layer structure. Fig. 6A and Figure 6B shows grains having a relatively large size included in the third layer 430 of the first conductive line 400, and Fig. 7A , Figure 7B and Figure 7CThe grains having a relatively small size included in the third layer 530 of the second conductive line 500 are shown. The number of grains per unit volume included in the third layer 530 of the second conductive line 500 having a multilayer structure including a plurality of sublayers 531, 532, and 533 may be greater than the number of grains per unit volume included in the third layer 430 of the first conductive line 400 having a single-layer structure. Therefore, the average size of the grains included in the third layer 530 of the second conductive line 500 may be smaller than the average size of the grains included in the third layer 430 of the first conductive line 400. For example, the average height of the columnar grains included in the third layer 530 of the second conductive line 500 may be smaller than the average height of the columnar grains included in the third layer 430 of the first conductive line 400. Therefore, the thickness of each of the sublayers 531, 532 and 533 of the third layer 530 of the second conductive line 500 corresponding to the height of the columnar grains grown in a direction perpendicular to the substrate 110 included in the third layer 530 of the second conductive line 500 may be less than the thickness TH43 of the third layer 430 of the first conductive line 400 corresponding to the height of the columnar grains included in the third layer 430 of the first conductive line 400.

[0096] Reference again Figure 3 , the fourth insulating layer 210 may be disposed on the third conductive lines 191a, 191b, 192a, and 192b. The fourth insulating layer 210 may be disposed on the third insulating layer 180 and may cover the third conductive lines 191a, 191b, 192a, and 192b. The fourth insulating layer 210 may provide a planarized surface above the third conductive lines 191a, 191b, 192a, and 192b. The fourth insulating layer 210 may be an organic insulating layer including an acrylic resin, an epoxy resin, a polyimide resin, a polyester resin, etc., or an inorganic insulating layer including silicon nitride, silicon oxide, silicon oxynitride, etc.

[0097] The first electrode 220 may be disposed on the fourth insulating layer 210. The first electrode 220 may be patterned for each pixel. The first electrode 220 may be electrically connected to the second transistor TR2 via a contact hole formed in the fourth insulating layer 210. The first electrode 220 may include a metal, a transparent conductive oxide, or the like.

[0098] The fifth insulating layer 230 may be disposed on the first electrode 220. The fifth insulating layer 230 may be disposed on the fourth insulating layer 210 and may cover an edge of the first electrode 220. The fifth insulating layer 230 may include an opening exposing a portion of the first electrode 220. For example, the opening of the fifth insulating layer 230 may expose a central portion of the first electrode 220, and thus, the fifth insulating layer 230 may define an emission region corresponding to the central portion of the first electrode 220. The fifth insulating layer 230 may include an organic insulating material such as an acrylic resin, an epoxy resin, a polyimide resin, a polyester resin, and the like.

[0099] The emission layer 240 may be disposed on the first electrode 220. The emission layer 240 may be disposed on a portion of the first electrode 220 exposed by the opening of the fifth insulating layer 230. Electrons and holes may be combined in the emission layer 240 to emit light. In one embodiment, a hole injection layer (HIL) and / or a hole transport layer (HTL) for injecting holes may be provided between the first electrode 220 and the emission layer 240, and the hole transport layer (HTL) has excellent hole transport performance and increases the chance of recombination of holes and electrons by limiting the movement of unbound electrons in the emission layer 240. In one embodiment, a hole blocking layer (HBL) for limiting the movement of unbound holes in the emission layer 240, an electron transport layer (ETL) for easily transporting electrons to the emission layer 240, and / or an electron injection layer (EIL) for injecting electrons may be provided on the emission layer 240.

[0100] The second electrode 250 may be disposed on the emission layer 240. The second electrode 250 may be formed together over a plurality of pixels PX. The second electrode 250 may include a metal or a transparent conductive oxide, etc. The first electrode 220, the emission layer 240, and the second electrode 250 may form an organic light emitting diode OLED. In one embodiment, the first electrode 220 may be an anode of the organic light emitting diode OLED, and the second electrode 250 may be a cathode of the organic light emitting diode OLED. However, the present disclosure is not limited thereto, and in another embodiment, the first electrode 220 may be a cathode of the organic light emitting diode OLED, and the second electrode 250 may be an anode of the organic light emitting diode OLED.

[0101] In the following, reference will be made to Figure 3 , Figures 8 to 12 A method of manufacturing a display device including a conductive line according to an embodiment is described.

[0102] Figure 8 , Fig. 9 , Fig.10 , Fig.11 and Fig.12 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment.

[0103] refer to Figure 8 , an inorganic insulating material may be deposited on the substrate 110 to form a buffer layer 120 . Then, a semiconductor material may be deposited on the buffer layer 120 and patterned to form semiconductor layers 131 and 132 including a first semiconductor 131 and a second semiconductor 132 .

[0104] refer to Fig. 9 , an inorganic insulating material may be deposited on the buffer layer 120 on which the semiconductor layers 131 and 132 are formed to form a first insulating layer 140. Then, a conductive material such as a metal may be deposited on the first insulating layer 140 and patterned to form first conductive lines 151 and 153 including a first gate electrode 151 and a first capacitor electrode 153.

[0105] More specifically, the formation of the first conductive lines 151 and 153 may be described by depositing aluminum (Al) or an aluminum alloy, and titanium nitride (TiN) may be deposited on the aluminum (Al) or the aluminum alloy. x ), can be made of titanium nitride (TiN x ) is deposited on titanium (Ti), and the deposited aluminum (Al) or aluminum alloy, titanium nitride (TiN x ) and titanium (Ti) are patterned to form Figure 4 The first conductive line 400 shown includes a first layer 410, a second layer 420, and a third layer 430. The third layer 430 of the first conductive line 400 can be formed by vacuum deposition such as sputtering. The third layer 430 of the first conductive line 400 can be formed by continuous deposition of titanium (Ti). The deposition of materials without interrupting the vacuum during the entire deposition process is called continuous deposition. By this continuous deposition, Fig. 6A and Figure 6B As shown, the third layer 430 of the first conductive line 400 may be formed to have a single-layer structure including columnar grains having a relatively large size.

[0106] refer to Fig.10 , an inorganic insulating material may be deposited on the first insulating layer 140 on which the first conductive lines 151 and 153 are formed to form a second insulating layer 160. Then, a conductive material such as a metal may be deposited on the second insulating layer 160, and the conductive material may be patterned to form second conductive lines 172 and 173 including a second gate electrode 172 and a second capacitor electrode 173. In this case, a capacitor CAP including the first capacitor electrode 153 and the second capacitor electrode 173 may be formed. Then, impurities may be doped to form a source region and a drain region of the first semiconductor 131 and a source region and a drain region of the second semiconductor 132.

[0107] More specifically, the formation of the second conductive lines 172 and 173 may be described by depositing aluminum (Al) or an aluminum alloy, and titanium nitride (TiN) may be deposited on the aluminum (Al) or the aluminum alloy. x ), and can be made on titanium nitride (TiN x ) is deposited on titanium (Ti), titanium nitride (TiN x ) and / or titanium oxide (TiO x ), and the deposited aluminum (Al) or aluminum alloy, titanium nitride (TiN x ) and titanium (Ti), titanium nitride (TiN x ) and / or titanium oxide (TiO x ) is patterned to form Figure 5 The second conductive line 500 shown includes a first layer 510, a second layer 520, and a third layer 530. The third layer 530 of the second conductive line 500 may be formed by vacuum deposition such as sputtering. The third layer 530 of the second conductive line 500 may be formed by titanium (Ti), titanium nitride (TiN x ) and / or titanium oxide (TiO x ) is formed by discontinuous deposition of titanium (Ti), titanium nitride (TiN) and x ) and titanium oxide (TiO x ), performing a vacuum interruption in which a first deposition process is terminated, and depositing titanium (Ti), titanium nitride (TiN) thereon in a second deposition process x ) and titanium oxide (TiO x ), performing a vacuum interruption in which the second deposition process is terminated, and depositing titanium (Ti), titanium nitride (TiN x ) and titanium oxide (TiO x ) and patterning it to form a third layer 530 of the second conductive line 500 including a first layer 510, a second layer 520, and a third layer 530. This deposition of material with at least one vacuum interruption in the entire deposition process is called discontinuous deposition. The deposition conditions (e.g., time, temperature, etc.) in the formation of the first sublayer 531, the deposition conditions in the formation of the second sublayer 532, and the deposition conditions in the formation of the third sublayer 533 may be substantially the same as or different from each other. In addition, the first sublayer 531, the second sublayer 532, and the third sublayer 533 may be formed of substantially the same material or different materials. Therefore, a discontinuous first sublayer 531, a second sublayer 532, and a third sublayer 533 having interfaces formed therebetween may be formed. By this discontinuous deposition, as 7A to 7C As shown, the third layer 530 of the second conductive line 500 may be formed to have a multi-layer structure including grains having a relatively small size.

[0108] In one embodiment, the thickness of the third layer 530 of the second conductive line 500 may be greater than or substantially equal to the thickness of the third layer 430 of the first conductive line 400. As the thickness of the metal layer increases, a large amount of residue may be generated during the patterning process of the metal layer. However, according to the present embodiment, the third layer 530 of the second conductive line 500 having a relatively large thickness may be formed by discontinuous deposition, thereby including a plurality of sub-layers 531, 532, and 533. In addition, the grains included in the third layer 530 of the second conductive line 500 may have a relatively small size, so that an excessive amount of residue may be prevented from being generated during the patterning process of the third layer 530 of the second conductive line 500.

[0109] refer to Fig.11 , an organic insulating material or an inorganic insulating material may be deposited on the second insulating layer 160 on which the second conductive lines 172 and 173 are formed to form a third insulating layer 180. Then, the third insulating layer 180, the second insulating layer 160, and the first insulating layer 140 may be etched to form contact holes including the first contact hole CH1, and the third insulating layer 180 may be etched to form the second contact hole CH2. The first contact hole CH1 and the second contact hole CH2 may be formed substantially simultaneously.

[0110] refer to Fig.12 , a conductive material may be deposited on the third insulating layer 180 to fill the contact holes including the first contact hole CH1 and the second contact hole CH2, and the conductive material may be patterned to form third conductive lines 191a, 191b, 192a, and 192b including the first source electrode 191a, the first drain electrode 191b, the second source electrode 192a, and the second drain electrode 192b. In this case, a first transistor TR1 including the first semiconductor 131, the first gate electrode 151, the first source electrode 191a, and the first drain electrode 191b, a switching transistor, and a second transistor TR2 including the second semiconductor 132, the second gate electrode 172, the second source electrode 192a, and the second drain electrode 192b, a driving transistor may be formed.

[0111] refer to Figure 3, an organic insulating material or an inorganic insulating material may be deposited on the third insulating layer 180 on which the third conductive lines 191a, 191b, 192a, and 192b are formed, and the organic insulating material or the inorganic insulating material may be patterned to form a fourth insulating layer 210, which exposes a portion of the second drain electrode 192b. Then, a conductive material such as a metal, a transparent conductive oxide, etc. may be deposited on the fourth insulating layer 210, and the conductive material may be patterned to form the first electrode 220. Then, an organic insulating material may be deposited on the fourth insulating layer 210 on which the first electrode 220 is formed, and the organic insulating material may be patterned to form a fifth insulating layer 230 exposing a portion of the first electrode 220. Then, an organic material may be deposited on the exposed portion of the first electrode 220 to form an emission layer 240. Then, a conductive material such as a metal, a transparent conductive oxide, etc. may be deposited on the emission layer 240 and the fifth insulating layer 230, and the conductive material may be patterned to form a second electrode 250. In this case, an organic light emitting diode OLED including the first electrode 220 , the emission layer 240 , and the second electrode 250 may be formed.

[0112] The display device according to the embodiment may be applied to a display device included in a computer, a notebook computer, a mobile phone, a smart phone, a smart tablet computer, a PMP, a PDA, an MP3 player, or the like.

[0113] Although the conductive lines, display devices, and methods of manufacturing the display devices according to the embodiments have been described with reference to the accompanying drawings, the illustrated embodiments are examples and may be modified and changed by a technician having ordinary knowledge in the relevant technical field without departing from the technical spirit described in the present disclosure.

Claims

1. A display device, wherein: The display device comprises: substrate; A semiconductor layer disposed on the substrate; A first conductive line disposed on the semiconductor layer; and a second conductive line disposed on the first conductive line, Wherein, the second conducting wire comprises: A first layer comprising aluminum or an aluminum alloy; a second layer disposed on the first layer, the second layer comprising a refractory metal nitride; and a third layer disposed on the second layer, the third layer including a refractory metal and having a multilayer structure including a plurality of stacked sublayers, the third layer having an interface disposed between adjacent sublayers, wherein each of the plurality of stacked sub-layers has columnar grains, and the columnar grains have discontinuous portions at the interface, The thickness of the third layer of the second conductive line is greater than or equal to the thickness of the third layer of the first conductive line, An average size of grains included in the third layer of the second conductive line is smaller than an average size of grains included in the third layer of the first conductive line.

2. The display device according to claim 1, wherein: The refractory metal nitride includes titanium nitride, and the refractory metal includes titanium.

3. The display device according to claim 2, wherein: The first conductive line comprises: A first layer comprising aluminum or an aluminum alloy; a second layer disposed on the first layer, the second layer comprising titanium nitride; and The third layer is disposed on the second layer, the third layer includes titanium and has a single-layer structure.

4. The display device according to claim 3, wherein: A thickness of each of the plurality of stacked sub-layers of the third layer of the second conductive line is smaller than a thickness of the third layer of the first conductive line.

5. The display device according to claim 2, wherein: The display device further includes a third wire arranged on the second wire, The third conductive line contacts the semiconductor layer via a first contact hole exposing a portion of the semiconductor layer, and the third conductive line contacts the second conductive line via a second contact hole exposing a portion of the second conductive line.

6. The display device according to claim 5, wherein: The depth of the first contact hole is greater than the depth of the second contact hole.

7. The display device according to claim 1, wherein: The display device further includes: a first electrode disposed on the second wire; an emission layer disposed on the first electrode; and A second electrode is disposed on the emission layer.

8. A method for manufacturing a display device, wherein: The method comprises: forming a semiconductor layer on a substrate; forming a first conductive line on the semiconductor layer; and forming a second conductive line on the first conductive line, the second conductive line comprising: a first layer comprising aluminum or an aluminum alloy, a second layer comprising a refractory metal nitride, and a third layer comprising a refractory metal, wherein the third layer of the second conductive line has a multilayer structure including a plurality of stacked sublayers, and the forming of the second conductive line includes forming a vacuum interruption between the sublayers, The method further comprises: forming an interface between adjacent sub-layers in the plurality of stacked sub-layers of the third layer, each of the adjacent sub-layers having columnar grains, the columnar grains having a discontinuous portion at the interface, The thickness of the third layer of the second conductive line is greater than or equal to the thickness of the third layer of the first conductive line, An average size of grains included in the third layer of the second conductive line is smaller than an average size of grains included in the third layer of the first conductive line.

9. The method according to claim 8, wherein: The first conductive line comprises: a first layer comprising aluminum or an aluminum alloy, a second layer comprising titanium nitride, and the third layer comprising titanium, During the forming of the third layer of the first conductive line, the third layer of the first conductive line is formed without vacuum interruption.

10. The method according to claim 8, wherein: The method further comprises: forming a first insulating layer covering the semiconductor layer before forming the first conductive line; forming a second insulating layer covering the first conductive line before forming the second conductive line; forming a third insulating layer covering the second conductive line; forming a first contact hole through the first insulating layer, the second insulating layer, and the third insulating layer to expose a portion of the semiconductor layer, and forming a second contact hole through the third insulating layer to expose a portion of the second conductive line; and A third conductive line is formed on the third insulating layer, and the third conductive line fills the first contact hole and the second contact hole.

11. The method according to claim 10, wherein: The first contact hole and the second contact hole are formed simultaneously.

12. The method according to claim 8, wherein: The method further comprises: forming a first electrode on the second conductive line; forming an emission layer on the first electrode; and A second electrode is formed on the emission layer.

13. A display device, wherein: The display device comprises: substrate; A switching transistor comprising a first gate electrode, wherein the first gate electrode comprises aluminum or an aluminum alloy, a refractory metal nitride, and a refractory metal sequentially disposed on the substrate; a driving transistor including a second gate electrode including aluminum or an aluminum alloy, a refractory metal nitride, and a refractory metal sequentially disposed on the substrate; a light emitting diode having an electrode connected to the driving transistor and disposed on the substrate, wherein the refractory metal in the second gate electrode comprises a plurality of stacked sub-layers, the plurality of stacked sub-layers having interfaces disposed between adjacent sub-layers, wherein each of the plurality of stacked sub-layers has columnar grains, and the columnar grains have discontinuous portions at the interface, The thickness of the refractory metal of the driving transistor is greater than or equal to the thickness of the refractory metal of the switching transistor, An average size of crystal grains included in the refractory metal in the driving transistor is smaller than an average size of crystal grains included in the refractory metal in the switching transistor.

14. The display device according to claim 13, wherein: The refractory metal nitride includes titanium nitride, and the refractory metal includes titanium.

15. The display device according to claim 14, wherein: The plurality of stacked sub-layers of the refractory metal in the driving transistor include a titanium layer and a titanium nitride layer or a titanium oxide layer disposed on the titanium layer.

16. The display device according to claim 14, wherein: The plurality of stacked sub-layers of the refractory metal in the driving transistor include a plurality of titanium layers stacked sequentially and the interface is between adjacent titanium layers.

17. The display device according to claim 16, wherein: The display device further includes a capacitor connected between a source electrode and a gate electrode of the driving transistor, the capacitor including a first electrode having the same structure as the first gate electrode and a second electrode having the same structure as the second gate electrode.

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