Intelligent semiconductor switch

Abstract

The present disclosure describes an intelligent semiconductor switch and a method for operating an intelligent semiconductor switch integrated in a chip package. According to one embodiment, the method includes driving a first semiconductor switch and a second semiconductor switch of a half-bridge according to an input signal received at an input terminal of the chip package in a first mode in which a status control signal received at a control terminal of the chip package has a first logic level. The method includes setting an operating parameter according to a pulse pattern of an input signal received at the input terminal in a second mode in which the status control signal received at the control terminal of the chip package has a second logic level.

Description

Field of the Invention

[0001] The present invention relates to the field of semiconductor switches having an integrated driver circuit for driving a semiconductor switch. Such semiconductor products are often also referred to as intelligent semiconductor switches. Background Art

[0002] There are many semiconductor products that are often referred to as intelligent semiconductor switches. An intelligent semiconductor switch typically includes a transistor (e.g., a MOSFET) and a suitable driver switch for driving the transistor in a chip package. Generally, an externally generated binary control signal (logic signal) is transmitted to the driver circuit through a pin, and this control signal signals to the driver circuit whether one or more transistors should be turned on or off. In the case of multiple transistors, multiple control signals can also be used.

[0003] The driver circuit in an intelligent semiconductor switch can also have various sensors for measuring operating parameters (e.g., load current, temperature, etc.) and circuits for detecting operating states (e.g., low voltage detection, overheating, etc.). In addition, the driver circuit of an intelligent semiconductor switch can provide the possibility of setting certain parameters (such as the slew rate). Some intelligent semiconductor switches provide, for example, the possibility of connecting a resistor to a pin of the intelligent semiconductor switch, where the resistance value of the resistor sets one or more parameters used by the driver circuit. Alternatively, one of the multiple parameters used by the driver circuit can be set by the level of the signal transmitted to the pin. In the case where multiple parameters need to be set, a separate pin is required for each parameter, which increases the total cost. In particular, a chip package with many pins is more expensive than a chip package with few pins. Summary of the Invention

[0004] A semiconductor device and a method for operating an intelligent semiconductor switch integrated in a chip package will be described below. According to one embodiment, the method includes driving a first semiconductor switch and a second semiconductor switch of a half-bridge according to an input signal received at an input terminal of the chip package in a first mode in which a state control signal received at a control terminal of the chip package has a first logic level. The method includes setting an operating parameter according to a pulse pattern of the input signal received at the input terminal in a second mode in which the state control signal received at the control terminal of the chip package has a second logic level.

[0005] According to one embodiment, the semiconductor device has: a half-bridge having a first semiconductor switch and a second semiconductor switch connected to a half-bridge output node; a logic circuit designed to provide control signals for the first semiconductor switch and the second semiconductor switch; an output terminal connected to the half-bridge output node; a control terminal for receiving a state control signal; and an input terminal for receiving an input signal. The logic circuit is designed to: in a first mode where the state control signal has a first logic level, generate control signals for the first semiconductor switch and the second semiconductor switch according to the input signal, and in a second mode where the state control signal has a second logic level, set the operating parameters of the semiconductor device according to the pulse pattern of the input signal received at the input terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Embodiments are described in more detail below with reference to the drawings. These drawings are not necessarily to scale, and the embodiments are not limited to the aspects shown. Instead, it is important to present the principles on which the embodiments are based. Shown in the drawings are:

[0007] Figure 1 An exemplary application is illustrated in which an intelligent semiconductor switch is used to drive an electric motor.

[0008] Figure 2 Illustrated is Figure 1 an exemplary embodiment of an intelligent semiconductor switch.

[0009] Figure 3 An embodiment of an intelligent semiconductor switch is illustrated in which one less pin is required compared to the example of Figure 2 ...

[0010] Figure 4 is a state diagram of a finite state machine (FSM) representing the functions of the logic circuit included in the example of Figure 3 ...

[0011] Figure 5 Includes timing diagrams for further illustrating the functions of the intelligent semiconductor switch of Figure 3 ...

[0012] Figure 6 is a state diagram of a finite state machine (FSM) representing the functions of a logic circuit according to another embodiment.

[0013] Figure 7 and Figure 8 include timing diagrams for further illustrating an intelligent semiconductor switch having a finite state machine (FSM) according to Figure 6 ...

[0014] Figure 9 is a flowchart for explaining a method of operating an intelligent semiconductor switch. Detailed implementation

[0015] Figure 1 Illustrates an exemplary application of the intelligent semiconductor switch 100 in the field of motor control. According to Figure 1 , the intelligent semiconductor switch 100 is integrated in a chip package having seven pins (VS, OUT, GND, INH, IN, IS, and SR). The pin OUT serves as the output terminal of the intelligent semiconductor switch 100, and this output terminal is connected to the first terminal of a load (motor M). The other terminal of the load can be connected to a reference potential, which can be defined, for example, by a first supply potential V SS (e.g., ground potential). The first (low) supply potential V ss and the second (high) supply potential V DD are transmitted to the intelligent semiconductor switch 100 on the supply pins GND and VS (supply terminals).

[0016] In addition, the intelligent semiconductor switch 100 has a plurality of control pins. The input pin IN (input terminal) is designed to receive (e.g., binary) control signal V IN . The control signal V IN indicates that the intelligent semiconductor switch 100 should output the first supply potential V ss or the second supply potential V DD (ignoring a very small internal voltage drop) on the output pin OUT. For example, the control signal V IN can be a pulse width modulation signal, which causes the intelligent semiconductor switch 100 to drive the motor M with a pulse width modulation voltage V OUT . Basically, the pins VS, OUT, and GND can be the three terminals of a transistor half-bridge, where the pin OUT is the half-bridge output (see Figure 2 or Figure 3 ).

[0017] In the example shown, the intelligent semiconductor switch 100 has an inhibit pin INH (Inhibit-Pin), which is designed to receive another control signal (inhibit signal, Inhibit-Signal), and the level (low level or high level) of this control signal indicates that the intelligent semiconductor switch 100 is to prevent the output of voltage V OUT on the output pin OUT. In this "inhibited" state, the output pin OUT can be connected to the supply potential V DD , V ss through a high-impedance voltage path, and the voltage V on the output OUTOUT Basically determined by the load.

[0018] Pin IS is mainly used to output the measured information, such as a measurement signal representing the load current or a temperature measurement signal. The measured information can be received, for example, by an external controller circuit and taken into account when generating the control signal V IN In many applications, it is desired to set specific operating parameters, such as the switching rate, and thus set the output voltage V OUT The rise time and fall time during switching. In this example, the operating parameters of the intelligent semiconductor switch, such as the switching rate, can be set according to a selection signal applied to another pin SR. For example, the selection signal applied to SR can be generated by connecting a defined resistor R SR to pin SR. The intelligent semiconductor switch can feed a defined current i SR into the resistor (see Figure 2 ), thus generating a voltage level V SR = i SR × R SR . In this example, the voltage level V SR determines the switching rate. In currently common intelligent semiconductor switches, a separate pin is required to set the operating parameters. In the Figure 1 example, pin SR is used to set the switching rate. Other examples of the operating parameters of the intelligent semiconductor switch are the overcurrent limit (for turning off the intelligent semiconductor switch in case of a short circuit) or the temperature threshold (for turning off the intelligent semiconductor switch in case of overheating).

[0019] An example of a known intelligent semiconductor switch is the Infineon BTN8962TA module (high-current PN half-bridge NovalithIC TM ), which mainly includes (in addition to some peripheral components) a transistor half-bridge and an integrated drive circuit. Figure 2 is a simplified block diagram for illustrating an example of an intelligent semiconductor switch, where for simplicity, components not necessary for further discussion are omitted.

[0020] According to Figure 2 , the intelligent semiconductor switch includes a transistor half-bridge formed by transistors M1 and M2, where M1 represents the high-side transistor of the half-bridge and M2 represents the low-side transistor of the half-bridge. The high-side transistor M1 is connected between the power supply pin VS and the output pin OUT, and the low-side transistor M2 is connected between the output pin OUT and the power supply pin GND (ground pin). Transistors M1 and M2 can be MOSFETs with an intrinsic body diode ( Figure 2 not shown in the figure). The control signals V G1 , VG2 (The gate voltage) is generated by the above-described drive circuit. For this purpose, in the example shown, the drive circuit has gate drivers 11 and 12, and the gate drivers 11 and 12 generate control signals V for the transistors M1 and M2 according to the logic signals S1 and S2. G1 、V G2 . The drive circuit has a logic circuit 20 for generating the logic signals S1 and S2. In the example shown, the low-side transistor M2 is of the n-channel type, and the high-side transistor M1 is of the p-channel type. However, this is not necessarily the case, and according to the specific implementation, both transistors M1 and M2 can be of the n-channel type.

[0021] The logic circuit 20 is designed to generate the logic signals S1 and S2 for the gate drivers 11 and 12 according to the indications of the logic signals S IN and S INH . The logic signals S IN and S INH respectively represent the logic levels of the control signals V IN and V INH applied to the pins IN and INH. The control signal V IN received on the pin IN is transmitted to the comparator 31, and the logic signal S IN is output to the logic circuit at the output of the comparator 31. For example, the comparator 31 can be a Schmitt trigger having two switching thresholds so as to recognize an input voltage V IN exceeding 1.6V as a high level (logic level S IN = 1), and recognize an input voltage V IN less than 1.4V as a low level (logic level S IN = 0), where the allowable voltage range for the input voltage V IN can be between -0.3V and +5.3V. The input of the comparator 11 can be connected to a pull-down current source 33 or alternatively to a pull-down resistor so as to pull the level of the input voltage V IN to zero if another input voltage level is not actively applied (e.g., by an external microcontroller). The comparator 32 and the pull-down current source 34 have substantially the same functions as the comparator 31 and the current source 33; the comparator 32 generates the logic signal S INH from the voltage V INH received on the pin INH. It is easy to understand that the current sources 33 and 34 can also be omitted in other embodiments, or can be replaced by pull-down resistors externally connected to the intelligent semiconductor switch 100. The above-mentioned values for the voltage VIN should only be understood as illustrative examples and can be different in other implementations.

[0022] According to one embodiment, the logic circuit 20 can be configured to generate logic signals S1 and S2 for the gate driver 11 according to the following equation: S1 = S IN ∧S INH , and the operator “∧” represents logical AND, and the operator represents logical NOT (inversion). It is readily understood that the mentioned logic equations must be regarded as simplified representations that do not take into account functions such as overcurrent shutdown and overtemperature shutdown. In many embodiments, the logic circuit 20 will be more complex.

[0023] In Figure 2 the illustrated embodiment, the intelligent semiconductor switch 100 includes a temperature sensor circuit 22 that is designed to generate an overtemperature signal OT when the measured chip temperature exceeds a temperature threshold. The intelligent semiconductor switch 100 further includes a current sensor circuit 21 that is designed to generate an overcurrent signal OC when the load current i1 through the high-side transistor M1 exceeds a current threshold. The signals OT and OC are transmitted to the logic circuit 20, and the logic circuit 20 can be designed to deactivate (turn off) or prevent activation (turn on) of the transistors M1 and M2 of the half-bridge when the signal OT indicates overtemperature or when the signal OC indicates overcurrent. According to one embodiment, in the case of detecting overtemperature or detecting overcurrent, the half-bridge remains detected until the inhibit signal V IN (again) changes from low level to high level. However, it is readily understood that in other embodiments, the overtemperature and overcurrent events are handled in a manner different from that in the Figure 2 example.

[0024] In addition, according to Figure 2 the embodiment provides the possibility of setting the switching speed (Slew-Rate) of the transistor (within certain limits). As already mentioned above, in Figure 1 and Figure 2 the example, the switching speed is set based on the voltage signal V SR applied to the pin SR, where the level of the signal V SR is determined by an external resistor R SS (ground) connected between the pin SR and the reference potential V SR . For this purpose, the intelligent semiconductor switch can have a slew rate adjustment circuit 23 that outputs a constant current i SR on the pin SR, thereby applying a voltage V SR = i SR ×R SR . The slew rate adjustment circuit 23 is further designed to drive the gate driver based on the voltage level V SR (seeFigure 2 , a conversion rate control signal S SR ), such that a desired switching speed or a desired conversion rate is achieved. A suitable conversion rate adjustment circuit 23 is known per se and is included, for example, in the module BTN8962TA mentioned above.

[0025] In Figure 2 's example, the current sensor circuit 21 is designed to output a measurement signal (e.g., current signal i S ) on the pin IS, and this measurement signal represents the load current i1 through the high-side transistor M1. For example, the overcurrent signal OC shown in S can be generated by comparing the current signal i Figure 2 (or the corresponding voltage signal) with a threshold value by means of a comparator. The current sensor circuit 21 can be implemented in various ways. For example, a so-called Sense-FET can be used for current measurement. The Sense-FET is coupled to the high-side transistor M1 in a manner similar to a current mirror and is designed to output a current that is substantially proportional to the load current i1. Other possible ways of current measurement (such as using a current measurement resistor) are also possible.

[0026] Figure 3 The embodiment shown in Figure 2 is very similar to the previous example of Figure 2 and Figure 3 . The differences between the examples of Figure 3 and Figure 3 will be mainly discussed below. In the embodiment of Figure 3 , one less pin is required. Compared with the previous example, there is no pin SR for setting operating parameters such as the conversion rate in Figure 3 . Instead, the input pin IN can be used to read one or more operating parameters, and the reading of the (one or more) operating parameters can be performed, for example, in a time interval such as during which the output of the intelligent semiconductor switch is inactive due to the level of the control voltage V INH (e.g., low level) (inhibit signal) on the pin INH. The intelligent semiconductor switch 100 includes a drive circuit 101 containing a logic circuit 20, and the logic circuit 20 is designed to identify the operating parameters input through the pin IN and, in the case of the conversion rate, output the detected parameter in a suitable form (parameter SR) to the conversion rate adjustment circuit 23'. Then, the circuit 23 (like the circuit 23 in the previous example) drives the gate drivers 11 and 12 according to the received parameter SR, such that the switching edges of the gate drivers 11 and 12 have a desired (corresponding to the parameter SR) conversion rate. Examples of how to read the parameter SR will be described later with reference to Figure 4 and Figure 5 .

[0027] and Figure 2 Unlike the previous example, Figure 3 The driving circuit 101 of the intelligent semiconductor switch 100 has a multiplexer 24, which realizes that in addition to the current measurement signal provided by the current measurement circuit 21, other values are output on the pin IS. In this example, the logic circuit 20 can be designed to provide a current (for example, by means of a digital-to-analog converter with a current output), which current, for example, represents the measured temperature (current signal iT) or represents the currently set operating parameters (for example, the conversion rate) (current signal i SR ). The logic circuit 20 can drive the multiplexer through the control signal so as to output the desired measurement signal on the pin IS. In some embodiments, the current output on the pin IS is always superimposed with the offset current i OS It will be readily appreciated that this depends on the specific implementation and does not necessarily have to be the case.

[0028] The logic circuit 20 may implement a finite state machine, which is also called a Finite State Machine (FSM). The function of the FSM may be represented by a state diagram. Figure 4 A state diagram representing the functionality of the logic circuit 20 and the entire intelligent semiconductor switch is shown in simplified form. Figure 5 , the associated signal waveforms are shown by way of example in a timing diagram.

[0029] according to Figure 3 , distinguishing the states "normal operation" (state S1), "SR selection / temperature measurement" (state S2) and "standby" (state S3). It is easy to understand that this is a simplified representation and that in a more detailed study, the individual states can be further subdivided. However, according to Figure 4 The simplified representation of is sufficient for the following discussion. State S1 (normal operation) is defined in the following manner: the logic circuit 20 controls the voltage V INH A logic value of "1" is sent on pin INH (in Figure 4 In this state, when the input voltage V IN When a logic value "1" (eg, a high level) is present on the input pin IN, the high-side transistor M1 is turned on, and when the input voltage V INWhen a logic value “0” (e.g., low level) is presented on the input pin IN, the low-side transistor M2 is turned on. It is easy to understand that when the high-side transistor M1 is turned on, the low-side transistor M2 is turned off, and vice versa, so that the two transistors of the half-bridge are never turned on simultaneously. In state S1 (normal operation), the current output on the pin IS represents the load current i1 through the high-side transistor. In other embodiments, the current output on the output pin OUT is measured instead of the current i1.

[0030] When the control voltage V INH (inhibiting signal) changes its level and presents a logic value “0” (e.g., high level), if the input voltage V IN also presents a logic “0” (V IN goes to a low level, represented by “IN = 0” in Figure 4 ), then the FSM changes to state S3, or if the input voltage V IN presents a logic “1” (V IN goes to a high level, represented by “IN = 1” in Figure 4 ), then the FSM changes to state S2. In state S3 (standby), the output of the half-bridge is high impedance, and only an offset current i OS (i S = i OS ) is output on the IS pin, where the offset current can also be zero. In state S2, a current i S is output on the pin IS, and this current i S indicates the currently selected conversion rate value (i S = i SR ) or the measured chip temperature (i S = i T ). The actual value of the current i S depends on the frequency of changing to state S2 since leaving state S1 (normal operation). Generally, the actual value of the current i S depends on the pulse pattern of the input voltage V IN (see Figure 5 ).

[0031] With the Figure 5 timing diagram, the function of the intelligent semiconductor switch according to Figure 4 with an FSM (logic circuit 20) according to Figure 3 is further illustrated. The first timing diagram (from above) shows an exemplary waveform of the voltage V INH (inhibiting signal) on the pin INH. First, the FSM is in state S1 (normal operation), and changes to state S3 (standby) at time t A . After that, at time t B, the FSM returns to state S1 (normal operation). The second timing diagram illustrates an exemplary waveform of the input voltage V IN (input signal) on pin IN. With each rising edge (i.e., from low level to high level) in the input voltage V IN , the FSM changes from state S3 (standby) to state S2 (SR selection / temperature measurement), and with each falling edge (i.e., from high level to low level) in the input voltage V IN , the FSM changes back to state S3. In state S3, only the offset current i S = i OS is output on pin IS. In state S2, a current is output on pin IS that represents the currently set operating parameter value (i.e., the conversion rate in this example) or the measured chip temperature. An example of the current output on pin IS is shown in the Figure 5 third timing diagram. The currently set parameter representing the desired conversion rate can be seen in the fourth timing diagram. In this example, eight different values (from SR = 0 to SR = 7) can be set for the parameter SR (conversion rate).

[0032] According to Figure 5 , the input voltage V IN has rising edges (transitioning to state S2) at times t0, t2, t4, t6, t8. The current output on pin IS in state S2 depends on the frequency at which the input voltage V IN changes to state S2 starting from the end of state S1 (normal operation) (i.e., starting from time tA). At the first transition to state S2 (time t0), the current i S = i SR (SR = 0) is output on pin IS, and this current represents the currently set parameter value (SR = 0 in this example). At each subsequent transition to state S2 (times t1 to t8), the parameter value is incremented by 1. When the parameter value SR = 7, "incremented by 1" means changing from SR = 7 to SR = 0, i.e., overflowing from the highest value to the lowest value. Starting from the third transition to state S2 (time t2), (so to speak as a "feedback"), the currently set parameter value SR is output, where the height of the current i S = i SR indicates the currently selected parameter value. At the second transition to state S2 (time t1), if the intelligent semiconductor switch measures the chip temperature, a current i S = i T representing the measured temperature is output instead of the current representing the parameter value. Therefore, the set parameter value SR depends on the pulse pattern of the input voltage V IN . In the simplest case, it can be (e.g., by an external controller) by applying the input voltage V on pin ININ Only two pulses are used (at times t0 and t1) to query the currently set parameter value SR and measure the currently measured chip temperature. INH When the voltage V IN Set the switching state of the half bridge.

[0033] Figure 6 Another embodiment of a FSM is shown, which implements the additional functionality of an intelligent semiconductor switch. Figure 4 Unlike the previous examples of , temperature measurement and parameter selection are implemented as separate states S2 and S4, which may be advantageous for some applications. Figure 4 similar, Figure 6 A simplified state diagram is shown which represents the function of the logic circuit 20 and thus the function of the entire intelligent semiconductor switch. Figure 7 and Figure 8 , the associated signal waveforms for different application cases are shown by way of example.

[0034] according to Figure 6 , distinguishing the states "normal operation" (state S1), "temperature measurement" (state S2), "standby" (state S3) and "SR selection" (state S4). As mentioned, this state diagram is a simplified representation and in a more detailed study, the individual states can be further subdivided. However, according to Figure 6 The simplified representation of is sufficient for the following discussion. State S1 (normal operation) is defined in the following manner: the logic circuit 20 controls the voltage V INH A logic value of "1" is sent on pin INH (in Figure 6 In this state, when the input voltage V IN When a logic value "1" (eg, a high level) is present on the input pin IN, the high-side transistor M1 is turned on, and when the input voltage V IN When a logic value "0" (e.g., a low level) is presented on the input pin IN, the low-side transistor M2 is turned on. It is easy to understand that when the high-side transistor M1 is turned on, the low-side transistor M2 is turned off, and vice versa, so that the two transistors of the half bridge are never turned on at the same time. In state S1 (normal operation), the current output on the pin IS represents the load current i1 through the high-side transistor. In other embodiments, the current output on the output pin OUT is measured instead of the current i1.

[0035] When the control voltage V INH (inhibit signal) changes its level and presents a logic value of "0" (for example, a high level), if the input voltage VIN also presents a logic "0" (V IN goes to a low level, represented by "IN = 0" in Figure 6 ), then the FSM changes to state S3, or if the input voltage V IN presents a logic "1" (V IN goes to a high level, represented by "IN = 1" in Figure 6 ), then the FSM changes to state S2. In state S3 (standby), the output of the half - bridge is high - impedance, and only an offset current i OS (i S = i OS ) is output on the IS pin, where the offset current can also be zero. In state S2, a current is is output on the pin IS, and this current i S indicates the measured chip temperature (i S = i T ) (see Figure 3 , temperature sensor 22). In state S2, a change in the logic level of the input voltage V IN from "1" to "0" causes a transition to the standby mode S3, in which, as an example in Figure 4 , only an offset current i S = i OS is output on the output IS, and this offset current can also be zero.

[0036] In state S3, one or more changes to state S4 can be used to set the operating parameter SR (e.g., conversion rate), where the selected parameter depends on the pulse pattern on the input pin IN. For example, the selected operating parameter depends on the frequency of the level change of the input voltage V IN . Examples of the selection of the desired operating parameter SR will be described in more detail later with reference to Figure 8 . In the embodiment described here, at each change from state S3 to state S4, the operating parameter SR is incremented by 1, where an overflow occurs when the highest parameter value (e.g., SR = 7) is incremented, resulting in the lowest parameter value (e.g., SR = 0). In state S4, a current i S is output on the pin IS, and this current i S represents the currently selected parameter value. In this state, the current i S can be regarded as a feedback signal that feeds back the currently selected operating parameter to an external controller. In states S2, S3, and S4, a change in the logic level of the control voltage V INH (inhibit signal) causes a transition to state S1 (normal operation).

[0037] The following is with the aid of Figure 7 and Figure 8The timing diagram exemplarily further illustrates two different application scenarios. The timing diagram exemplarily depicts the function of an intelligent semiconductor switch according to Figure 6 with an FSM (logic circuit 20) according to Figure 3 . In Figure 7 , the first timing diagram (from above) shows an exemplary waveform of the voltage V INH (inhibit signal) on the pin INH. The second timing diagram shows an exemplary waveform of the input voltage V IN on the pin IN. The third timing diagram shows the waveform of the gate voltage V G1 of the high-side switch M1 (in this example, it is an n-channel MOSFET), and the fourth timing diagram shows the waveform of the output current i S on the pin IS.

[0038] First, the FSM is in state S3 (standby). At time t A , the input voltage V IN changes from "0" to "1" (logic level), and thus the FSM transitions to state S4, and the output current i S on the pin IS represents the currently selected operating parameter SR. In this example, from time t A onwards, the input voltage V IN remains at the logic level "1". From time t1 onwards, the voltage V INH (inhibit signal) on the pin INH periodically changes from "0" to "1" and back from "1" to "0" (logic level). The rising edge occurs at time t1, and the subsequent falling edge occurs at time t2. The next cycle starts with the next rising edge at time t3 (the corresponding falling edge at time t4).

[0039] With each level change of the inhibit signal V INH (or S INH , see Figure 3 ), the FSM changes to state S1 at the rising edge (at times t1, t3,...) or to state S2 at the falling edge (at times t2, t4,...). In state S1 (normal operation), the high-side transistor M1 is actively turned on (the gate voltage V G1 is at a high level, higher than the threshold voltage of the transistor), whereas in state S2 (standby), the half-bridge is passive, i.e., both transistors M1 and M2 are turned off, but freewheeling can occur through the intrinsic body diode of the low-side transistor M2 ( Figure 3 not shown in the figure). At the same time, in state S2, the output current i S = i T is output on the pin IS, and this current represents the measured chip temperature. Thus, in Figure 7In the example shown, the temperature can be measured quasi-continuously; a temperature measurement value can be obtained in each switching cycle. Figure 7 In the bottom figure, the following moments are marked with "x" at which the external controller can sample the current i S (and thus temperature information can be sampled). During the FSM state S1, the current i S represents the load current through the high-side transistor M1, which can also be measured (for example, by an external controller). Figure 7 In the example shown in Figure 1, the load current remains essentially constant as the chip temperature increases.

[0040] Figure 8 Another application case is involved in which an operating parameter SR of an intelligent semiconductor switch (for example, a switching rate during a switching process) is selected and set before normal operation begins. Figure 8 The first timing diagram (from the top) shows the voltage V on pin INH. INH The second timing diagram shows the input voltage V IN The third timing diagram shows the output current i on pin IS. S The example shown starts in normal operation ( Figure 6 The state S1 of the FSM, and at time t A , voltage V INH The logic level of the pin changes from "1" to "0", and the FSM changes to state S3 (standby), while the output offset current i S =i OS Starting from state S3, an input signal V with a certain pulse pattern (i.e. a certain sequence of logic levels or a certain sequence of level changes) can be applied to pin IN. IN To set the operating parameters S3. IN At each change (rising edge) of the logic level from "0" to "1", the FSM changes to state S4 (SR selection) and the input signal V IN At each change (falling edge) of the logic level from "1" to "0" of the FSM, the FSM changes back to state S3 (standby). In the example shown, the selected operating parameter SR depends on the input signal V IN The frequency of rising edges is identified in the FSM, that is, the frequency at which the FSM changes from state S3 to state S4. In state S4, the current i S The current i is output as a feedback signal at pin IS. S Indicates the currently selected / set operating parameter SR. At time t B , prohibit signal VINH The logic level of t changes from "0" to "1", and the FSM thus transitions to a normal operating state (active operating mode, state S1), in which, as already explained, the input signal V ON Set the switching state of the half bridge and output the current i at pin IS S , the current i S represents the current through the high-side transistor M1 of the half-bridge (see Figure 3 ).

[0041] Figure 7 and Figure 8 Two distinctly different applications of the same intelligent semiconductor switch are shown. Figure 7 In the example of FIG. 1 , only the high-side switch M1 of the half bridge is actively turned on and off, while the low-side switch M2 is not actively turned on, but only carries the intrinsic body diode current of the low-side switch M2 when the high-side switch M1 is turned off. In fact, the low-side switch M2 is turned off by the inhibit signal V INH To control the switch operation, the prohibition signal V INH For example, it can be pulse width modulated. The temperature measurement and current measurement are performed almost simultaneously, and the current information and the temperature information are output alternately on the pin IS, so that at least one current measurement value and at least one temperature measurement value can be sampled in each PWM cycle. Figure 8 In the example of FIG. 1 , in normal operation (normal mode, from time t onwards), the two transistors M1 and M2 of the half bridge are connected according to the input signal V IN is actively driven. In this case, temperature measurement is only possible when normal mode is interrupted.

[0042] In both embodiments of the FSM (see Figure 4 and Figure 6 ), state S1 (normal operation) can be assigned to a first active (operating) mode of the intelligent semiconductor switch, in which the half-bridge is actively driven. The remaining states can be assigned to a second passive mode of the intelligent semiconductor switch. In this mode, the half-bridge is not actively driven, but temperature measurement and setting of one or more operating parameters can be performed.

[0043] At this point, it should be noted that the logic levels ("0" and "1") mentioned depend on the actual implementation. Depending on the implementation of the intelligent semiconductor switch, one or more signals may use inverted logic levels. In the above description, the signal is not always at the signal V INH With S INH and V IN With S IN Between (see Figure 3 ). This distinction is not necessary for the described embodiment, since the signal V INHWith S INH and V IN With S IN represent the same information.

[0044] Figure 9 is an embodiment for explaining a method of operating an intelligent semiconductor switch and for further explaining Figure 3 the function of the example. According to Figure 9 , the intelligent semiconductor switch can operate in a first mode (active mode) and a second mode (passive mode). If a state control signal having a first logic level (e.g., high level) is received on the control terminal of the chip package (see Figure 3 , pin INH) (see Figure 3 , signal V INH or S INH ), then the intelligent semiconductor switch operates in the active mode. Similarly, if the state control signal has a second logic level (e.g., low level), then the intelligent semiconductor switch operates in the passive mode (see Figure 9 , step V1).

[0045] In the first active mode, the method includes driving a first semiconductor switch and a second semiconductor switch of a half-bridge according to an input signal (see Figure 3 , M1, M2) (see Figure 9 , step V2), and the input signal is received on the input terminal of the chip package (see Figure 3 , pin IN) (see Figure 8 , after time t B ). In the second passive mode, the method includes setting operating parameters according to the pulse pattern of the input signal received at the input terminal (see Figure 7 and 8 , time interval t A to t B ) (see Figure 9 , step V3). The first active mode basically corresponds to the state S1 of the FSM (normal operation, normal mode, see Figure 4 and Figure 6 ). The second passive mode includes the remaining states S2 and S3, and S4 if necessary. In this passive mode, the potential at the output node of the half-bridge (see Figure 3 , output pin OUT) depends on the load (and its state), and as mentioned, freewheeling through the intrinsic body diodes of transistors M1 and M2 is possible.

Claims

1. A semiconductor device, comprising: A half - bridge having a first semiconductor switch and a second semiconductor switch, wherein the first semiconductor switch and the second semiconductor switch are connected to a half - bridge output node; A logic circuit designed to provide control signals for the first semiconductor switch and the second semiconductor switch; An output terminal connected to the half - bridge output node; A control terminal for receiving a status control signal; And An input terminal for receiving an input signal; Wherein the logic circuit is designed to: In a first mode where the status control signal has a first logic level, generate the control signals for the first semiconductor switch and the second semiconductor switch according to the input signal; And In a second mode where the status control signal has a second logic level, generate another signal to set operating parameters of the half - bridge based on a pulse pattern of the input signal received at the input terminal, wherein the operating parameters set a switching speed, an overheat limit, or a temperature threshold of the half - bridge.

2. The semiconductor device according to claim 1, further comprising: A driver circuit designed to generate a drive signal based on the input signal received at the input terminal and the operating parameters, and the drive signal is provided to the first semiconductor switch.

3. The semiconductor device according to claim 2, Wherein the operating parameters set the switching speed of the half - bridge.

4. The semiconductor device according to claim 1, further comprising: A temperature sensor circuit designed to generate a temperature measurement signal representing a temperature associated with the half - bridge; A current sensor circuit designed to generate a current measurement signal representing a current flowing through one of the semiconductor switches; And Another terminal coupled to the current sensor circuit and the temperature sensor circuit through a selection circuit; Wherein the logic circuit is designed to: in the first mode, drive the selection circuit such that the current measurement signal is output at the another terminal, and in the second mode, the temperature measurement signal or an operating parameter signal representing the operating parameters is output.

5. The semiconductor device according to claim 4, Wherein after switching to the second mode, the temperature measurement signal is output at the another terminal, and subsequently, the operating parameter signal representing the operating parameters is output according to a change frequency of a logic level of the input signal.

6. A method for operating an intelligent semiconductor switch integrated in a chip package, comprising: In a first mode where a first status control signal received at a control terminal of the chip package has a first logic level, driving a first semiconductor switch and a second semiconductor switch of a half - bridge according to an input signal received at an input terminal of the chip package; In a second mode in which a second state control signal received on the control terminal of the chip package has a second logic level, another signal is generated to set operating parameters of the half-bridge based on a pulse pattern of the input signal received on the input terminal, where the operating parameters set a switching speed, an overheat limit, or a temperature threshold of the half-bridge.

7. The method according to claim 6, wherein in the first mode, a current measurement signal is output on another terminal, the current measurement signal representing a current through one of the semiconductor switches.

8. The method according to claim 6, wherein in the second mode, a temperature measurement signal or an operating parameter signal representing the operating parameters is output on another terminal according to the pulse pattern of the input signal received on the input terminal.

9. The method according to claim 8, Among them, after transitioning to the second mode, first the temperature measurement signal is output on the other terminal, and subsequently, after an edge in the input signal, the operating parameter signal representing the operating parameters is output.

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