Ultra-Low Power Analog Switches

Abstract

The present invention discloses an ultra-low power consumption analog switch, which is applied to the fields of analog circuit technology and semiconductor integrated circuit technology, and comprises a power supply voltage detection circuit (102), a high voltage selection circuit (107), a low voltage selection circuit (108), a first level shifter (112), a second level shifter (113), a logic control circuit (111), a pull-up tube (13), a pull-down tube (14), a first drive circuit (109), a second drive circuit (110), a first main switch (11), a second main switch (12) and a switch tube substrate selection circuit (101). The analog switch proposed by the present invention can quickly turn off the switch tube after the power supply is turned off, thereby blocking the transmission of positive and negative voltage signals at the input end, greatly improving the isolation of the switch tube when the power supply voltage is turned off, and the analog switch has the characteristics of ultra-low power consumption.

Description

Technical Field

[0001] The present invention belongs to the field of analog circuit technology and semiconductor integrated circuit technology, and more specifically to an ultra-low power consumption analog switch. Background Art

[0002] Analog switches are mainly used to complete the signal switching function in the signal chain. The MOS tube switch method is used to realize the shutdown or opening of the signal chain. Because its function is similar to that of a switch, but it is realized by the characteristics of analog devices, it is called an analog switch. According to different application requirements, analog switches can be divided into audio analog switches, video analog switches, digital switches and general analog switches.

[0003] For analog switches used to transmit audio signals, the isolation of the switch in the power-off state is an important indicator. Audio analog switches usually use a pair of parallel pmos and nmos tubes. This switch can meet the requirements of transmitting positive and negative voltages. However, if the switch is not processed, it cannot be guaranteed that the switch tube is in the off state after the power supply voltage is off.

[0004] In the prior art, a pull-up resistor and a pull-down resistor are usually connected to the gate of the switch tube respectively. On the one hand, this method cannot ensure that the switch tube can be quickly turned off after the power is lost. On the other hand, this method will introduce large static power consumption and cannot meet the ultra-low power consumption requirements in application scenarios.

[0005] Therefore, it is an urgent problem for those skilled in the art to provide an ultra-low power analog switch that has the ability to handle positive and negative voltages and can isolate positive and negative voltages after power failure. Summary of the invention

[0006] In view of this, the present invention provides an ultra-low power consumption analog switch having the capability of processing positive and negative voltages and isolating positive and negative voltages after power failure, thereby greatly improving the isolation of the switch after power failure and greatly reducing the static power consumption of the switch during normal operation.

[0007] In order to achieve the above object, the present invention adopts the following technical solution:

[0008] An ultra-low power analog switch, comprising:

[0009] A power supply voltage detection circuit, a high voltage selection circuit, a low voltage selection circuit, a first level shifter, a second level shifter, a logic control circuit, a pull-up tube, a pull-down tube, a first drive circuit, a second drive circuit, a first main switch, a second main switch and a switch tube substrate selection circuit;

[0010] Wherein, the power supply voltage detection circuit, the first output port of the power supply voltage detection circuit is connected to the gate of the pull-up tube; the drain of the pull-up tube is connected to the output port of the first driving circuit and the gate of the first main switch;

[0011] The second output port of the power supply voltage detection circuit is connected to the gate of the pull-down tube; the drain of the pull-down tube is connected to the output port of the second drive circuit and the gate of the second main switch;

[0012] The second output port of the power supply voltage detection circuit is connected to the third input ports of the first level shifter and the second level shifter, the output port of the first level shifter is connected to the third input port of the first driving circuit, and the output port of the second level shifter is connected to the third input port of the second driving circuit;

[0013] The first input / output port of the switch tube substrate selection circuit is connected to the source of the first main switch and the second main switch, and the second input / output port is connected to the drain of the first main switch and the second main switch;

[0014] The first output port of the logic control circuit is connected to the fourth input port of the first level shifter, and the second output port of the logic control circuit is connected to the fourth input port of the second level shifter;

[0015] The output port of the high voltage selection circuit is connected to the first input port of the power supply voltage detection circuit, the first input port of the first level shifter, the first input port of the second level shifter, the first input port of the first drive circuit, the first input port of the second drive circuit, the source of the pull-up tube and the substrate of the pull-up tube;

[0016] The output port of the low voltage selection circuit is connected to the second input port of the power supply voltage detection circuit, the second input port of the first level shifter, the second input port of the second level shifter, the second input port of the first drive circuit, the second input port of the second drive circuit, the source of the pull-down tube and the substrate of the pull-down tube;

[0017] The first input / output port and the second input / output port of the switch tube substrate selection circuit, and the input ports of the high voltage selection circuit and the low voltage selection circuit are connected to an external signal circuit.

[0018] Preferably, the power supply voltage detection circuit includes: a first input port, a second input port, a first output port, a second output port, a resistor, an inverter, at least 5 pmos transistors and at least 7 nmos transistors.

[0019] Preferably, the switch tube substrate selection circuit includes: a first input / output port, a second input / output port, a first output port and a second output port, and at least 2 pmos transistors and at least 2 nmos transistors.

[0020] It can be seen from the above technical solutions that, compared with the prior art, the present invention provides a low-power analog switch, which has the following beneficial technical effects:

[0021] (1) The switch input and output are completely symmetrical and can conduct in both directions;

[0022] (2) The switch tube has the characteristic of transmitting positive and negative voltage signals;

[0023] (3) After the power is off, the switch tube can be turned off quickly;

[0024] (4) After the power is turned off, the switch tube blocks the transmission of positive and negative voltage signals, greatly improving the isolation of the switch after power off; the switch tube has the characteristic of extremely low static power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0026] Figure 1 This is a block diagram of the ultra-low power consumption analog switch circuit of the present invention;

[0027] Figure 2 It is a power supply voltage detection circuit diagram in the present invention;

[0028] Figure 3 A circuit diagram for selecting a substrate for a switch tube in the present invention;

[0029] Figure 4 The high voltage selection circuit diagram of the present invention;

[0030] Figure 5 The low voltage selection circuit diagram of the present invention;

[0031] Figure 6 A schematic diagram of voltage changes at input and output ports after power failure in the present invention;

[0032] Figure 7 A schematic diagram of the changes in the output voltage of the power supply voltage detection circuit, the gate voltage of the main switch tube, and the external input voltage signal when the voltage is off in the present invention;

[0033] exist Figure 1-Figure 7 middle:

[0034] 102-power supply voltage detection circuit, 111-logic control circuit, 112-first level shifter, 113-second level shifter, 109-first drive circuit, 110-second drive circuit, 107-high voltage selection circuit, 108-low voltage selection circuit, 13-pull-up tube, 14-pull-down tube, 11-first main switch, 12-second main switch, 101-switch tube substrate selection circuit. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] Example 1

[0037] See attached Figure 1-5 As shown, the embodiment of the present invention discloses an ultra-low power consumption analog switch, including a power supply voltage detection circuit 102, a high voltage selection circuit 107, a low voltage selection circuit 108, a first level shifter 112, a second level shifter 113, a logic control circuit 111, a pull-up tube 13, a pull-down tube 14, a first driving circuit 109, a second driving circuit 110, a first main switch 11, a second main switch 12 and a switch tube substrate selection circuit 101;

[0038] The power supply voltage detection circuit 102, the first output port of the power supply voltage detection circuit 102 (i.e., the terminal 305 of the power supply voltage detection circuit 102) is connected to the gate of the pull-up tube 13; the drain of the pull-up tube 13 is connected to the output port of the first driving circuit 109 and the gate of the first main switch 11;

[0039] The second output port of the power supply voltage detection circuit 102 (i.e., the terminal 304 of the power supply voltage detection circuit 102) is connected to the gate of the pull-down tube 14; the drain of the pull-down tube 14 is connected to the output port of the second driving circuit 110 and the gate of the second main switch 12;

[0040] The second output port of the power supply voltage detection circuit 102 (i.e., the terminal 304 of the power supply voltage detection circuit 102) is connected to the third input ports of the first level shifter 112 and the second level shifter 113, the output port of the first level shifter 112 is connected to the third input port of the first driving circuit 109, and the output port of the second level shifter 113 is connected to the third input port of the second driving circuit 110;

[0041] The first input / output port of the switch tube substrate selection circuit 101 (i.e., the terminal 103 of the switch tube substrate selection circuit 101) is connected to the source of the first main switch 11 and the second main switch 12, and the second input / output port (i.e., the terminal 104 of the switch tube substrate selection circuit 101) is connected to the drain of the first main switch 11 and the second main switch 12;

[0042] The first output port of the logic control circuit 111 is connected to the fourth input port of the first level shifter 112, and the second output port of the logic control circuit 111 is connected to the fourth input port of the second level shifter 113;

[0043] The output port of the high voltage selection circuit 107 (i.e., the terminal 105 of the high voltage selection circuit 107) is connected to the first input port of the power supply voltage detection circuit 102, the first input port of the first level shifter 112 (i.e., the terminal 105 of the first level shifter 112), the first input port of the second level shifter 113 (i.e., the terminal 105 of the first level shifter 113), the first input port of the first driving circuit 109 (i.e., the terminal 105 of the first driving circuit 109), the first input port of the second driving circuit 110 (i.e., the terminal 105 of the first driving circuit 110), the source of the pull-up tube 13, and the substrate of the pull-up tube 13;

[0044] The output port of the low voltage selection circuit 108 (i.e., the terminal 106 of the low voltage selection circuit 108) is connected to the second input port of the power supply voltage detection circuit 102, the second input port of the first level shifter 112 (i.e., the terminal 106 of the first level shifter 112), the second input port of the second level shifter 113 (i.e., the terminal 106 of the second level shifter 113), the second input port of the first drive circuit 109 (i.e., the terminal 106 of the first drive circuit 109), the second input port of the second drive circuit 110 (i.e., the terminal 106 of the first drive circuit 110), the source of the pull-down tube 14, and the substrate of the pull-down tube 14;

[0045] The first input / output port (i.e., terminal 103 of the switch tube substrate selection circuit 101) and the second input / output port (i.e., terminal 104 of the switch tube substrate selection circuit 101), the input ports of the high voltage selection circuit 107 and the low voltage selection circuit 108 are connected to the external signal circuit.

[0046] In a specific embodiment, referring to the attached Figure 2As shown, the power supply voltage detection circuit 102 includes: a first input port (i.e., terminal 105 of the power supply voltage detection circuit 102), a second input port (i.e., terminal 106 of the power supply voltage detection circuit 102), a first output port (i.e., terminal 305 of the power supply voltage detection circuit 102), a second output port (i.e., terminal 304 of the power supply voltage detection circuit 102), a resistor 39, an inverter 310, a first transistor 31, a second transistor 32, a third transistor 33, a fourth transistor 34, a ninth transistor 311, and a fifth transistor 35, a sixth transistor 36, a seventh transistor 37, an eighth transistor 38, a tenth transistor 312, an eleventh transistor 313, and a twelfth transistor 314, wherein the first transistor 31, the second transistor 32, the third transistor 33, the fourth transistor 34, and the ninth transistor 311 are pmos transistors, and the fifth transistor 35, the sixth transistor 36, the seventh transistor 37, the eighth transistor 38, the tenth transistor 312, the eleventh transistor 313, and the twelfth transistor 314 are nmos transistors.

[0047] The connection mode of the power supply voltage detection circuit 102 is as follows: the first input port of the power supply voltage detection circuit 102 is connected to the substrate of the first transistor 31, the source of the first transistor 31, the substrate of the second transistor 32, the source of the second transistor 32, the substrate of the third transistor 33, the source of the third transistor 33, the substrate of the fourth transistor 34, the source of the fourth transistor 34, the substrate of the ninth transistor 311, and the source of the ninth transistor 311;

[0048] The second input port of the power supply voltage detection circuit 102 is connected to the substrate of the seventh transistor 37, the source of the seventh transistor 37, the substrate of the eighth transistor 38, the source of the eighth transistor 38, the substrate of the twelfth transistor 314, and the source of the twelfth transistor 314;

[0049] The second output port of the power supply voltage detection circuit 102 is connected to the drain of the third transistor 33, the drain of the ninth transistor 311, the drain of the seventh transistor 37, the gate of the eighth transistor 38 and the gate of the twelfth transistor 314;

[0050] The first output port of the power supply voltage detection circuit 102 is connected to the drain of the fourth transistor 34, the gate of the ninth transistor 311, the gate of the seventh transistor 37, the drain of the eighth transistor 38 and the drain of the twelfth transistor 314;

[0051] The drain of the first transistor 31, the gate of the second transistor 32, the drain of the fifth transistor 35, the gate of the tenth transistor 312, the source of the tenth transistor 312 and the substrate of the tenth transistor 312 are connected;

[0052] The drain of the second transistor 32, the gate of the first transistor 31, the gate of the third transistor 33, the drain of the sixth transistor 36 and the drain of the eleventh transistor (313) are connected;

[0053] The gate of the fifth transistor 35 is connected to one end of the resistor 39 and the input port of the inverter 310 respectively, and the source and substrate of the fifth transistor 35 are grounded;

[0054] The gate of the sixth transistor 36 is connected to the output port of the inverter 310;

[0055] The source and substrate of the eleventh transistor 313 are grounded.

[0056] In a specific embodiment, the tenth transistor 312 and the twelfth transistor 314 are 1VT-type NMOS transistors.

[0057] In a specific embodiment, referring to the attached Figure 3 As shown, the switch tube substrate selection circuit 101 includes: a first input / output port (i.e., terminal 103 of the switch tube substrate selection circuit 101), a second input / output port (i.e., terminal 104 of the switch tube substrate selection circuit 101), a first output port (i.e., terminal 201 of the switch tube substrate selection circuit 101) and a second output port (i.e., terminal 202 of the switch tube substrate selection circuit 101), as well as a thirteenth transistor 21, a fourteenth transistor 22, a fifteenth transistor 23 and a sixteenth transistor 24.

[0058] The connection mode of the switch tube substrate selection circuit 101 is as follows: the first input port of the switch tube substrate selection circuit 101 is connected to the drain of the thirteenth transistor 21, the gate of the fourteenth transistor 22, the drain of the fifteenth transistor 23 and the gate of the sixteenth transistor 24;

[0059] The second input port of the switch tube substrate selection circuit 101 is connected to the gate of the thirteenth transistor 21, the drain of the fourteenth transistor 22, the gate of the fifteenth transistor 23 and the drain of the sixteenth transistor 24;

[0060] The first output port of the switch tube substrate selection circuit 101 is connected to the substrate of the thirteenth transistor 21 , the source of the thirteenth transistor 21 , the substrate of the fourteenth transistor 22 , and the source of the fourteenth transistor 22 respectively.

[0061] In a specific embodiment, the thirteenth transistor 21 and the fourteenth transistor 22 are pmos transistors, and the fifteenth transistor 23 and the sixteenth transistor 24 are nmos transistors.

[0062] In a specific embodiment, referring to the attached Figure 4As shown, the high voltage selection circuit 107 includes: a first input port (i.e., terminal 103 of the high voltage selection circuit 107), a second input port (i.e., terminal 104 of the high voltage selection circuit 107), an output port (i.e., terminal 105 of the high voltage selection circuit 107), a seventeenth transistor 41, an eighteenth transistor 42, a nineteenth transistor 43, a twentieth transistor 44, and a resistor 45, wherein the drain of the seventeenth transistor 41 is connected to the first input port and the gate of the eighteenth transistor 42, and the gate of the seventeenth transistor 41 is connected to the gate of the eighteenth transistor 42. The drain of the transistor 42 is connected to the second input port, the source and substrate of the seventeenth transistor 41 are connected to the source of the eighteenth transistor 42, the substrate of the eighteenth transistor 42, the drain of the nineteenth transistor 43 and the gate of the twentieth transistor 44, the gate of the nineteenth transistor 43 is connected to the drain of the twentieth transistor 44 and one end of the resistor 45, the source and substrate of the nineteenth transistor 43 are connected to the source of the twentieth transistor 44, the substrate of the twentieth transistor 44 and the output port, and the other end of the resistor 45 is connected to the power supply voltage. Among them, the seventeenth transistor 41, the eighteenth transistor 42, the nineteenth transistor 43, and the twentieth transistor 44 are pmos transistors.

[0063] In a specific embodiment, referring to the attached Figure 5 As shown, the low voltage selection circuit 108 includes: a first input port (i.e., terminal 103 of the low voltage selection circuit 108), a second input port (i.e., terminal 104 of the low voltage selection circuit 108), an output port (i.e., terminal 106 of the low voltage selection circuit 108), a twenty-first transistor 51, a twenty-second transistor 52, a twenty-third transistor 53, and a twenty-fourth transistor 54, the drain of the twenty-first transistor 51 is connected to the first input terminal and the gate of the twenty-second transistor 52, the gate of the twenty-first transistor 51 is connected to the drain of the twenty-second transistor 52 and the second input port, the source and substrate of the twenty-first transistor 51 are connected to the source of the twenty-second transistor 52, the substrate of the twenty-second transistor 52, the drain of the twenty-third transistor 53, and the gate of the twenty-fourth transistor 54, the gate of the twenty-third transistor 53 and the drain of the twenty-fourth transistor 54 are grounded, and the source and substrate of the nineteenth transistor 43 are connected to the source of the twentieth transistor 44, the substrate of the twentieth transistor 44, and the output port. Among them, the twenty-first transistor 51, the twenty-second transistor 52, the twenty-third transistor 53 and the twenty-fourth transistor 54 are nmos transistors.

[0064] In a specific embodiment, the main switch 11 is a pmos transistor with an isolation ring, and the main switch 12 is a nmos transistor with an isolation ring.

[0065] In a specific embodiment, the thirteenth transistor 21 and the fourteenth transistor 22 are pmos transistors with isolation rings, and the fifteenth transistor 23 and the sixteenth transistor 24 are nmos transistors with isolation rings.

[0066] In a specific embodiment, the seventeenth transistor 41 , the eighteenth transistor 42 , the nineteenth transistor 43 and the twentieth transistor 44 are pmos transistors with isolation rings.

[0067] In a specific embodiment, the twenty-first transistor 51 , the twenty-second transistor 52 , the twenty-third transistor 53 and the twenty-fourth transistor 54 are nmos transistors with isolation rings.

[0068] In another specific embodiment, the tenth transistor 312 and the twelfth transistor 314 in the power voltage detection circuit 102 are 1Vt-type NMOS transistors.

[0069] Example 2

[0070] Refer to Attachment 1-5:

[0071] When the main switch tubes 11 and 12 transmit positive voltage, the voltage of the first input port (i.e., terminal 103 of the switch tube substrate selection circuit 101) of the switch tube substrate selection circuit 101 is greater than the voltage of the second input port (i.e., terminal 104 of the switch tube substrate selection circuit 101), so the fourteenth transistor 22 in the switch tube substrate selection circuit 101 is turned off, the thirteenth transistor 21 is turned on, and the voltage of the first input port with a higher voltage is selected as the substrate voltage of the switch tube 11, and the voltage of the first output port (i.e., terminal 201 of the switch tube substrate selection circuit 101) is equal to the voltage of the first input port, the fifteenth transistor 23 in the switch tube substrate selection circuit 101 is turned off, and the sixteenth transistor 24 is turned on, and the voltage of the second input port with a lower voltage is selected as the substrate voltage of the switch tube 12, and the voltage of the second output port (i.e., terminal 202 of the switch tube substrate selection circuit 101) is equal to the voltage of the second input port.

[0072] When the main switch tubes 11 and 12 transmit negative voltage, the voltage of the first input port of the switch tube substrate selection circuit 101 is less than the voltage of the second input port, so the thirteenth transistor 21 in the switch tube substrate selection circuit 101 is turned off, the fourteenth transistor 22 is turned on, and the second input port voltage with a higher voltage is selected as the substrate voltage of the switch tube 11, and the voltage of the first output port is equal to the voltage of the second input port, the sixteenth transistor 24 in the switch tube substrate selection circuit 101 is turned off, and the fifteenth transistor 23 is turned on, and the first input port voltage with a lower voltage is selected as the substrate voltage of the switch tube 12, and the voltage of the second output port is equal to the voltage of the first input port.

[0073] The voltage finally selected by the high voltage selection circuit 107 is the highest voltage among the power supply voltage, the first input port voltage and the second input port voltage.

[0074] The voltage finally selected by the low voltage selection circuit 108 is the lowest voltage among GND, the first input port voltage and the second input port voltage.

[0075] See attached Figure 6 As shown: when the power supply voltage is powered on, the logic control circuit 111 controls the on and off of the switch tube; when the power supply voltage is powered off, the power supply voltage drops to 0V, the voltage state of the first input port of the high voltage selection circuit 107 and the low voltage selection circuit 108 (i.e., the 103 input port of the high voltage selection circuit 107 and the low voltage selection circuit 108), the first input / output port and the second input / output port of the switch tube substrate selection circuit 101 (i.e., the 103 / 104 input and output ports of the switch tube substrate selection circuit 101), the output port of the high voltage selection circuit 107 (i.e., the 105 terminal of the high voltage selection circuit 107), and the output port of the low voltage selection circuit 108 (i.e., the 106 terminal of the low voltage selection circuit 108). The maximum input voltage of the audio signal is V MAX , the minimum input voltage is V MIN , the maximum output voltage of the output port of the high voltage selection circuit 107 is V MAX , the minimum output voltage is 0V, the maximum output voltage of the output port of the low voltage selection circuit 108 is 0V, and the minimum output voltage is V MIN When the power supply voltage is 0, the voltages of the first input port (i.e., terminal 105 of the power supply voltage detection circuit 102) and the second input port (i.e., terminal 106 of the power supply voltage detection circuit 102) of the power supply voltage detection circuit 102 are as follows: Figure 6 shown.

[0076] See attached Figure 7 As shown: the gate voltages of the fifth transistor 35 and the sixth transistor 36 are both 0V. Since the tenth transistor 312 is an LVT-type NMOS tube, its threshold voltage is about -0.2V, and point a is pulled up to the voltage of the first input port (i.e., terminal 105 of the power supply voltage detection circuit 102). When the voltage at terminal a exceeds the threshold voltage of transistor 313, the voltage at point b is pulled down to 0. According to the working principle of the level shifter, the voltages of the first output port (i.e., terminal 104 of the power supply voltage detection circuit 102) and the second output port (i.e., terminal 105 of the power supply voltage detection circuit 102) of the power supply voltage detection circuit 102 are as follows: Figure 7As shown. Among them, the first output port of the power supply voltage detection circuit 102 (i.e., terminal 305 of the power supply voltage detection circuit 102) is connected to the gate of the pull-up tube 13, and the second output port of the power supply voltage detection circuit 102 (i.e., terminal 304 of the power supply voltage detection circuit 102) is connected to the gate of the pull-down tube 14. Due to the functions of the pull-up tube 13 and the pull-down tube 14, the gate voltage of the main switch tube 11 is always consistent with the voltage of terminal 105, and the gate voltage of the main switch tube 12 is always consistent with the voltage of terminal 106. Since the gate voltage of the main switch tube 11 is always maintained at no less than the input voltage of terminal 103, and the gate voltage of the main switch tube 12 is always maintained at no more than the input voltage of terminal 103, the main switch tubes 11 and 12 are always kept in the off state.

[0077] The second output port of the power supply voltage detection circuit 102 (i.e., terminal 304 of the power supply voltage detection circuit 102) is connected to the third input ports of the level shifters 112 and 113. When the power supply voltage is off, the output of the level shifter 112 is not lower than the voltage of the input terminal 103, and the output of the level shifter 113 is not higher than the voltage of the terminal 103.

[0078] When the overall circuit is operating normally, according to the level shifter principle, the voltage output of the second output port of the power supply voltage detection circuit 102 (i.e., terminal 304 of the power supply voltage detection circuit 102) is a low level, i.e., the lowest voltage among terminals 103, 104 and GND, the pull-down tube 14 is in an off state, the first output port of the power supply voltage detection circuit 102 (i.e., terminal 305 of the power supply voltage detection circuit 102) outputs a high level, i.e., the highest voltage among terminals 103, 104 and the power supply voltage, the pull-up tube 13 is in an off state, the states of the main switch tubes 11 and 12 are controlled by the logic control circuit 111, the tenth transistor 312 and the twelfth transistor 314 of the LVT type are inverse ratio tubes, and the static power consumption is extremely low during normal operation.

[0079] It can be concluded that the analog switch proposed in the present invention can quickly shut down the switch tube after the power is off, blocking the transmission of positive and negative voltage signals at the input end, greatly improving the isolation of the switch tube when the power voltage is off, and the analog switch has the characteristics of ultra-low power consumption.

[0080] The above description of the disclosed embodiments is provided in a progressive manner to enable those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An ultra-low power consumption analog switch, characterized in that: include: A power supply voltage detection circuit (102), a high voltage selection circuit (107), a low voltage selection circuit (108), a first level shifter (112), a second level shifter (113), a logic control circuit (111), a pull-up tube (13), a pull-down tube (14), a first drive circuit (109), a second drive circuit (110), a first main switch (11), a second main switch (12), and a switch tube substrate selection circuit (101); The first output port of the power supply voltage detection circuit (102) is connected to the gate of the pull-up tube (13); the drain of the pull-up tube (13) is connected to the output port of the first drive circuit (109) and the gate of the first main switch (11); The second output port of the power supply voltage detection circuit (102) is connected to the gate of the pull-down tube (14); the drain of the pull-down tube (14) is connected to the output port of the second drive circuit (110) and the gate of the second main switch (12); The second output port of the power supply voltage detection circuit (102) is connected to the third input ports of the first level shifter (112) and the second level shifter (113), the output port of the first level shifter (112) is connected to the third input port of the first drive circuit (109), and the output port of the second level shifter (113) is connected to the third input port of the second drive circuit (110); The first input / output port of the switch tube substrate selection circuit (101) is connected to the source of the first main switch (11) and the second main switch (12), and the second input / output port is connected to the drain of the first main switch (11) and the second main switch (12); The first output port of the logic control circuit (111) is connected to the fourth input port of the first level shifter (112), and the second output port of the logic control circuit (111) is connected to the fourth input port of the second level shifter (113); The output port of the high voltage selection circuit (107) is connected to the first input port of the power supply voltage detection circuit (102), the first input port of the first level shifter (112), the first input port of the second level shifter (113), the first input port of the first drive circuit (109), the first input port of the second drive circuit (110), the source of the pull-up tube (13) and the substrate of the pull-up tube (13); The output port of the low voltage selection circuit (108) is connected to the second input port of the power supply voltage detection circuit (102), the second input port of the first level shifter (112), the second input port of the second level shifter (113), the second input port of the first drive circuit (109), the second input port of the second drive circuit (110), the source of the pull-down tube (14) and the substrate of the pull-down tube (14); The first input / output port and the second input / output port of the switch tube substrate selection circuit (101), the input ports of the high voltage selection circuit (107) and the low voltage selection circuit (108) are connected to an external signal circuit; The power supply voltage detection circuit (102) comprises: a first input port, a second input port, a first output port, a second output port, a resistor (39), an inverter (310), a first transistor (31), a second transistor (32), a third transistor (33), a fourth transistor (34), a ninth transistor (311), and a fifth transistor (35), a sixth transistor (36), a seventh transistor (37), an eighth transistor (38), a tenth transistor (312), an eleventh transistor (313), and a twelfth transistor (314); The first transistor (31), the second transistor (32), the third transistor (33), the fourth transistor (34) and the ninth transistor (311) are pmos transistors, and the fifth transistor (35), the sixth transistor (36), the seventh transistor (37), the eighth transistor (38), the tenth transistor (312), the eleventh transistor (313) and the twelfth transistor (314) are nmos transistors; The tenth transistor (312) and the twelfth transistor (314) are 1vt type nmos transistors; The first input port of the power supply voltage detection circuit (102) is connected to the substrate of the first transistor (31), the source of the first transistor (31), the substrate of the second transistor (32), the source of the second transistor (32), the substrate of the third transistor (33), the source of the third transistor (33), the substrate of the fourth transistor (34), the source of the fourth transistor (34), the substrate of the ninth transistor (311) and the source of the ninth transistor (311); The second input port of the power supply voltage detection circuit (102) is connected to the substrate of the seventh transistor (37), the source of the seventh transistor (37), the substrate of the eighth transistor (38), the source of the eighth transistor (38), the substrate of the twelfth transistor (314) and the source of the twelfth transistor (314); The second output port of the power supply voltage detection circuit (102) is connected to the drain of the third transistor (33), the drain of the ninth transistor (311), the drain of the seventh transistor (37), the gate of the eighth transistor (38) and the gate of the twelfth transistor (314); The first output port of the power supply voltage detection circuit (102) is connected to the drain of the fourth transistor (34), the gate of the ninth transistor (311), the gate of the seventh transistor (37), the drain of the eighth transistor (38) and the drain of the twelfth transistor (314); The drain of the first transistor (31), the gate of the second transistor (32), the drain of the fifth transistor (35), the gate of the tenth transistor (312), the source of the tenth transistor (312) and the substrate of the tenth transistor (312) are connected; The drain of the second transistor (32), the gate of the first transistor (31), the gate of the third transistor (33), the drain of the sixth transistor (36) and the drain of the eleventh transistor (313) are connected; The gate of the fifth transistor (35) is respectively connected to one end of the resistor (39) and the input port of the inverter (310), and the source and substrate of the fifth transistor (35) are grounded; The gate of the sixth transistor (36) is connected to the output port of the inverter (310); The source and substrate of the eleventh transistor (313) are grounded.

2. The ultra-low power consumption analog switch according to claim 1, characterized in that: The switch tube substrate selection circuit (101) comprises: a first input / output port, a second input / output port, a first output port and a second output port, and a thirteenth transistor (21), a fourteenth transistor (22), a fifteenth transistor (23) and a sixteenth transistor (24); The thirteenth transistor (21) and the fourteenth transistor (22) are pmos transistors, and the fifteenth transistor (23) and the sixteenth transistor (24) are nmos transistors; The first input port of the switch tube substrate selection circuit (101) is connected to the drain of the thirteenth transistor (21), the gate of the fourteenth transistor (22), the drain of the fifteenth transistor (23) and the gate of the sixteenth transistor (24); The second input port of the switch tube substrate selection circuit (101) is connected to the gate of the thirteenth transistor (21), the drain of the fourteenth transistor (22), the gate of the fifteenth transistor (23) and the drain of the sixteenth transistor (24); The first output port of the switch tube substrate selection circuit (101) is respectively connected to the substrate of the thirteenth transistor (21), the source of the thirteenth transistor (21), the substrate of the fourteenth transistor (22) and the source of the fourteenth transistor (22).

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