Magnification Interface and Corresponding Measurement System and Method for Calibrating the Magnification Interface

Abstract

Embodiments of the present disclosure relate to an amplification interface and corresponding measurement systems and methods for calibrating the amplification interface. An amplification interface includes: the drain of a first FET connected to a first node, the drain of a second FET connected to a second node, and the sources of the first FET and the second FET connected to a third node. A first bias current generator and a second bias current generator are connected to the first node and the second node. A third FET is connected between the third node and a reference voltage. An adjustment circuit drives the gate of the third FET to adjust the common mode of the voltage at the first node and the voltage at the second node to a desired value. A current generator applies a calibration current to the first node and / or the second node. A differential current integrator has a first input and a second input connected to the second node and the first node, respectively. The integrator supplies a voltage that represents the integral of the difference between the currents received at the second input and the first input.

Description

[0001] Priority Statement

[0002] This application claims priority to Italian Patent Application No. 102019000001851, filed on February 8, 2019, the content of which is hereby incorporated by reference in its entirety to the maximum extent permitted by law. Technical Field

[0003] Embodiments of this specification relate to measurement systems. Background Art

[0004] Figure 1 A typical measurement system is shown. Generally, a measurement system includes a sensor 10 and a processing circuit 40.

[0005] Specifically, the sensor 10 is configured to provide a measurement signal MS representing the quantity to be measured. For example, the sensor 1 can be an environmental sensor, such as a temperature sensor, a brightness sensor, etc. The processing circuit 40 is configured to process the measurement signal MS.

[0006] Typically, the measurement signal MS is supplied directly not to the processing circuit 40 but to an amplifier circuit 20, which is configured to generate an amplified measurement signal AS. Generally, the amplifier circuit 20 is capable of performing various operations. For example, by a sensor supplying a current signal at the output, the amplifier circuit 20 can supply a voltage signal at the output. Additionally, the amplifier circuit 20 can be configured to amplify the variations of the measurement signal MS such that preferably it covers the input dynamic range of the downstream circuit with its maximum variations.

[0007] For example, the processing circuit 40 is typically a digital circuit, such as a programmed microprocessor. In this case, the processing circuit 40 has an associated analog-to-digital (A / D) converter 30, which is configured to receive the amplified signal AS at its input and to supply a digital signal DS at its output, the digital signal DS including digital samples of the amplified signal AS.

[0008] For example, the sensor 10 can include one or more TMOS transistors. Specifically, the term TMOS designates a specific MOS (metal-oxide-semiconductor) device. Specifically, the device includes a MOS transistor thermally isolated from the substrate of the integrated circuit including the transistor. Typically, a TMOS with a suspended structure is obtained to help maximize the thermal isolation of the rest of the die in which the TMOS is obtained.

[0009] Accordingly, the transistor can be exposed to temperature variations different from those of the substrate / die. Small temperature variations in the device can cause changes in the I-V (current-voltage) characteristics of the transistor itself, and such changes can be detected appropriately. For example, the temperature variation of the transistor may be due to infrared (IR) radiation impinging on the TMOS itself, or may be due to gas flow on the TMOS itself. Accordingly, such TMOS devices are often referred to as "thermally isolated MOS" (due to the thermal isolation of the MOS) or simply "thermal MOS" (due to its ability to detect temperature variations).

[0010] For example, this type of sensor is described in U.S. Patent Application Publication Nos. 2006 / 0244067, 2011 / 0315880, and 2017 / 0205366, which are incorporated herein by reference. Such suspended MOS transistors can be fabricated, for example, by using appropriate microfabrication and dry etching processes through a conventional CMOS-SOI or SOI-CMOS (silicon-on-insulator complementary metal-oxide semiconductor) process.

[0011] TMOS is an element for developing a new generation of sensing devices such as infrared (IR) temperature sensors, intrusion sensors, airflow sensors, etc. Using TMOS transistors as active sensing elements has advantages in terms of internal gain, multiplexing within the sensor, and high-temperature sensitivity. Since TMOS can be used under subthreshold conditions where the power consumption is extremely low, TMOS can be battery-powered, enabling wide applications in mobile phones, smart homes, IoT (Internet of Things), and the security and confidentiality industries.

[0012] As described in U.S. Patent Application Publication No. 2017 / 0205366, the TMOS sensor needs to be properly biased, and then the small signal generated by the sensor (due to the temperature variation set by the TMOS itself) needs to be amplified and post-processed.

[0013] Therefore, the design of the read circuit architecture is crucial for appropriately detecting the signal generated by the TMOS sensor.

[0014] Accordingly, there is a need in the art to provide a way that can overcome one or more of the limitations of conventional techniques. SUMMARY OF THE INVENTION

[0015] According to one or more embodiments, one or more of the above objects are achieved by an amplification interface. The embodiments also relate to a corresponding measurement system and a method for calibrating the amplification interface.

[0016] Various embodiments of the present disclosure relate to an amplification interface for a first FET and a second FET, such as MOS transistors, preferably n-channel MOS transistors. Specifically, in various embodiments, these transistors are TMOS transistors, where the gate terminals are connected to a reference voltage. Thus, in various embodiments, the amplification interface includes a first node, a second node, and a third node, where the drain terminal of the first FET is connected to the first node, the drain terminal of the second FET is connected to the second node, and the source terminals of the first FET and the second FET are connected to the third node.

[0017] In various embodiments, a first bias current generator generates a first bias current, and the output of the first bias current generator is connected to the first node. Moreover, a second bias current generator generates a second bias current, and the output of the second bias current generator is connected to the second node. In various embodiments, the first bias current generator and the second bias current generator are PTAT (proportional to absolute temperature) type current generators.

[0018] In various embodiments, the amplification interface includes a third FET, where the drain terminal of the third FET is connected to the third node, and the source terminal of the third FET is connected to the reference voltage. The regulation circuit is configured to drive the gate terminal of the third FET such that the common mode of the voltage at the first node and the voltage at the second node is regulated to a desired value.

[0019] In various embodiments, the amplification interface includes a differential current integrator, which includes a first input terminal connected to the second node and a second input terminal connected to the first node. Thus, the differential integrator supplies a voltage at its output via two output terminals, which represents the integral of the difference between the current received at the second input terminal of the differential current integrator and the current received at the first input terminal of the differential current integrator.

[0020] For example, in various embodiments, the differential current integrator includes a differential operational amplifier, where the first input terminal of the differential operational amplifier is connected to the second node, and the second input terminal of the differential operational amplifier is connected to the first node. Moreover, a first capacitor is connected between the first output terminal of the differential operational amplifier and the first input terminal of the differential operational amplifier, and a second capacitor is connected between the second output terminal of the differential operational amplifier and the second input terminal of the differential operational amplifier. In various embodiments, the differential current integrator further has a first electronic switch and a second electronic switch connected in parallel to the first capacitor and the second capacitor respectively, where the first electronic switch and the second electronic switch are driven by a reset signal so as to be able to reset the differential current integrator.

[0021] In various embodiments, the amplification interface may include a sample-and-hold circuit that stores the output voltage of a differential current integrator in accordance with a control signal.

[0022] Accordingly, the control circuit may generate a reset signal such that the differential current integrator is periodically reset during a reset interval and activated during a measurement interval. Further, during each measurement interval, the control circuit may set the control signal to a first logic value for storing the output voltage within a sampling interval and may set the control signal to a second logic value for holding the stored output voltage within a hold interval.

[0023] In various embodiments, the amplification interface further includes an RC oscillator that includes a capacitor and a resistor, which define an oscillation period of the RC oscillator, and the control circuit may generate a control signal such that the sampling interval corresponds to a multiple of the oscillation period of the RC oscillator.

[0024] In this case, by appropriately designing a first bias current generator and a second bias current generator (which are proportional to absolute temperature (PTAT) type generators), an (integrating) capacitor of the differential current integrator, and the capacitor and resistor of the RC oscillator, both the process spread and temperature variations of these components can be compensated. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Now, embodiments of the present disclosure will be described with reference to the accompanying drawings, which are provided by way of non-limiting example only, and in which:

[0026] Figure 1 A measurement system is shown;

[0027] Figure 2 A first embodiment of an amplification interface is shown;

[0028] Figure 3 Shows Figure 2 an embodiment of the operation of the amplification interface;

[0029] Figure 4 A second embodiment of an amplification interface is shown;

[0030] Figure 5 Shows Figure 4 an embodiment of the operation of the amplification interface;

[0031] Figure 6 A third embodiment of an amplification interface is shown;

[0032] Figure 7 A fourth embodiment of an amplification interface is shown; and

[0033] Figure 8 shows Figure 2 、 Figure 4 、 Figure 6 and Figure 7 the details of the amplification interface of Detailed implementation mode

[0034] In the following description, various specific details are illustrated, which are intended to achieve an in-depth understanding of the embodiments. Embodiments may be provided without one or more of the specific details or in the case of having other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure various aspects of the embodiments.

[0035] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that the specific configurations, structures, or features described with respect to that embodiment are included in at least one embodiment. Thus, phrases such as "in an embodiment" and "in one embodiment" that may appear in various aspects of this specification do not necessarily refer to the same embodiment. Moreover, in one or more embodiments, specific configurations, structures, or features may be combined in any suitable manner.

[0036] The reference numerals used herein are provided only for convenience and thus do not limit the scope of protection or the scope of the embodiments.

[0037] In the following description of Figures 2 to 7 , parts, elements, or components that have been referred to Figure 1 are designated by the same reference numerals as those previously used in these figures. These elements have been described and will not be repeated hereinafter so as not to clutter the detailed description of the present invention.

[0038] As previously explained, various embodiments of this specification relate to an electronic amplification interface that is designed to "read" signals generated by a TMOS sensor.

[0039] Figure 2 A first embodiment of a measurement system is shown, which includes a TMOS sensor 10, an electronic amplification interface, and an optional analog-to-digital converter 30.

[0040] Specifically, in this embodiment, the TMOS sensor 10 includes two TMOS transistors M BLIND and M EXP . In the embodiment under consideration, these transistors are, for example, n-channel type FETs (field effect transistors).

[0041] In various embodiments, these two TMOS transistors are provided within the same integrated circuit / die and have the same characteristics, particularly with respect to the dimensions of the transistors; that is, transistor M BLIND is substantially a copy of transistor M EXP . Preferably, TMOS transistors M BLIND and M EXP are positioned close to each other.

[0042] In the embodiment under consideration, the electronic amplification interface is configured to amplify the differential signal between the two transistors, for example, the differential signal between the drain terminals of transistors M BLIND and M EXP . For example, as described hereinafter, this makes it possible to reject the common-mode signals and interferences reaching the two transistors of the TMOS sensor.

[0043] In the embodiment under consideration, the differential signal is generated by the fact that TMOS transistor M EXP is "exposed", that is, it is configured to be exposed to the temperature variations generated by the quantity to be measured thereon, while the other TMOS transistor M BLIND is "blind", that is, it is configured such that the physical quantity to be measured has no effect on it.

[0044] For example, in various embodiments, the quantity to be measured is the infrared radiation generated by an object disposed at a certain distance from the TMOS sensor 10. The infrared radiation is a function of the temperature of the object itself. Thus, the measurement of the infrared radiation emitted by the object makes it possible to indirectly measure the temperature of the object. Thus, in this case, transistor M BLIND is shielded from the IR radiation, while transistor M EXP is configured to receive the IR radiation generated by the object. Thus, the power of the IR radiation received by transistor M EXP causes a slight heating of transistor M EXP (but not transistor M BLIND ). Thus, this temperature difference generates a change in the differential signal across the sensor 10, which change should be amplified by the amplification interface. In fact, generally speaking, a small temperature change in transistor M EXP produces a small displacement within the I-V characteristic of transistor M EXP , which in turn generates a small change in the differential signal between transistors M BLIND and M EXP .

[0045] Thus, generally speaking, the physical quantity to be measured (IR radiation, gas flow, etc.) generates a change in transistor M EXP (but not transistor M BLIND) The temperature change causes a change in the electrical characteristics of the transistor, which in turn causes a change in the differential signal that the amplification interface should amplify. Conversely, the amplification interface can be configured such that a common-mode change on transistors M EXP and M EXP (e.g., a change in ambient temperature, generally any common-mode interference) will not result in any change in the differential signal, so the effect of this common-mode change is filtered / compensated.

[0046] Although this specification has been conceived and designed to amplify as much as possible the signal generated by the TMOS sensor 10, the proposed electronic amplification interface is functional and also applicable to the case of using two MOS transistors instead of TMOS transistors, because the amplification interface is configured to amplify the differential signal between two transistors, such as the differential signal at the drain terminals of two n-channel transistors.

[0047] As previously explained, the electronic amplification interface can amplify the differential signal between two transistors M BLIND and M EXP . To generate such a differential signal, a circuit for generating an appropriate bias for transistors M BLIND and M EXP is utilized.

[0048] For example, in the considered embodiment, for this purpose, the electronic amplification interface includes two current generators 206 and 208. Specifically, current generator 206 is connected in series with the drain terminal and the source terminal of transistor M BLIND , and current generator 208 is connected in series with the drain terminal and the source terminal of transistor M EXP .

[0049] For example, in the considered embodiment, transistors M BLIND and M EXP are n-channel transistors. In this case, also as described in U.S. Patent Application Publication No. 2017 / 0205366, current generator 206 can be (e.g., directly) connected between the drain terminal of transistor M BLIND and the reference voltage V DD , and this reference voltage V DD corresponds, for example, to the supply voltage of the integrated circuit and / or processing circuit 40 as shown in Figure 1 . Similarly, current generator 208 can be (e.g., directly) connected between the drain terminal of transistor M EXP and the reference voltage V DD .

[0050] In the considered embodiment, the gate terminal of transistor M BLIND is (e.g., directly) connected to the gate terminal of transistor M EXPof the gate terminal, and the transistor M EXP of the gate terminal is (e.g., directly) connected to the reference voltage V CM2 . Generally, when using two ordinary transistors instead of the TMOS transistor, an input signal can be applied between the gate terminals of the transistors M BLIND and M EXP .

[0051] However, although according to the teachings of U.S. Patent Application Publication No. 2017 / 0205366, the source terminals of the transistors M BLIND and M EXP are directly grounded, Figure 2 the illustrated embodiment also includes a common-mode control circuit. Specifically, in the considered embodiment, the source terminal of the transistor M BLIND is (e.g., directly) connected to the source terminal of the transistor M EXP , and the source terminal of this transistor M EXP is in turn (e.g., directly) connected to the reference voltage, e.g., grounded GND, by means of the transistor M B . Considering that in the considered embodiment, the TMOS transistor is of the n-channel type, preferably, the transistor M B is also of the n-channel type. Therefore, in the considered embodiment, the drain terminal of the transistor M B is (e.g., directly) connected to the source terminal of the transistor M BLIND / the source terminal of the transistor M EXP , i.e., terminal 106, and the source terminal of the transistor M B is (e.g., directly) connected to the reference voltage / GND.

[0052] Therefore, in the considered embodiment, the sensor 10 is connected to the amplification interface through three terminals:

[0053] - Terminal 102, which corresponds to the drain terminal of the transistor M BLIND ;

[0054] - Terminal 104, which corresponds to the drain terminal of the transistor M EXP ; and

[0055] - Terminal 106, which corresponds to the source terminals of the transistors M BLIND and M EXP .

[0056] In various embodiments, each of the current generators 206 and 208 supplies a current I B . For example, the current generators 206 and 208 can be implemented with current mirrors. Therefore, in the considered embodiment, the transistor M EXP and the transistor MBLIND The bias current of is substantially equal to I B , while the current of transistor M B is substantially equal to 2·I B .

[0057] Therefore, this part of the circuit substantially corresponds to, for example, the OTA (operational transconductance amplifier) described in U.S. Patent No. 6,693,485, the content of which is incorporated herein by reference.

[0058] However, in the considered embodiment, the gate terminal of transistor M B is not driven by a constant signal, but by control circuit 204. Specifically, the above control circuit 204 is configured to monitor the voltage V BLIND on the drain terminal of transistor M O1P and the voltage V EXP on the drain terminal of transistor M O1N , and to generate a drive signal for the gate terminal of transistor M B based on these voltages. Specifically, in the considered embodiment, control circuit 204 is configured to control (through the feedback of voltages V O1P and V O1N ) the voltage on the gate of transistor M B such that the common mode of voltages V O1P and V O1N will be equal to the reference voltage V CM1 , that is, control circuit 204 is configured to regulate the gate-source voltage V B of transistor M GS such that:

[0059] (V O1P +V O1N ) / 2 = V CM1

[0060] For example, in various embodiments, control circuit 204 can be implemented using a regulator that includes at least one I (integral) component and possibly includes a P (proportional) component. For example, control circuit 204 can be implemented by one or more operational amplifiers.

[0061] In various embodiments, the amplification interface is configured such that transistors M BLIND and M EXP are biased to operate in the subthreshold region. For example, once the bias currents of transistors M EXP and M BLIND are fixed to be equal to I B , these transistors can be sized to have a sufficiently high (width-to-length W / L) ratio to help ensure the voltage V between the gate terminal and the source terminalGS below the threshold voltage V of the transistor T ; that is, V GS < V T .

[0062] Now, next, analyze the influence of the temperature T of the TMOS transistor on the differential signal. Specifically, assume that transistors M BLIND and M EXP are biased in the sub-threshold condition, then, for example, the model described by Clifton Fonstad in "MOSFETs in the Sub-threshold Region (i.e., a bit below VT)" on October 28, 2009 (the content of which is incorporated herein by reference) can be used to model the current at the drain terminal I T : D For the definition of the parameters of Equation (1), reference can be made to the cited literature. Specifically, the inventors have noted that the following parameters of the equation depend on the temperature T of the transistor: μ

[0063]

[0064] representing the electron mobility, and V e which is the threshold voltage of the transistor T .

[0065] In various embodiments, the voltages V CM1 and V CM2 are selected such that the voltage between the drain terminal and the source terminal V BLIND and M EXP of transistors M DS is high relative to the thermal voltage φ t ; for example, V DS > 3φ t . In this case, Equation (1) simplifies to:

[0066]

[0067] Moreover, substituting kT / q for the thermal voltage φ t and assuming that the mobility μ e of the transistor can be approximated as:

[0068]

[0069] where μ e0 and T 0 are two constants, then the current I D of the transistor can be written as:

[0070]

[0071] That is

[0072]

[0073] where I D0 is a constant

[0074] In subsequent processing, the temperature difference between the two TMOS transistors that gives rise to the differential signal is denoted as

[0075]

[0076] Therefore, the change in the current of the TMOS transistor caused by a small change in the temperature of the transistor itself can be evaluated by calculating the derivative of the temperature with respect to Equation (5) and then multiplying the result by the difference ΔT TMOS , and we obtain by differentiating Equation (5):

[0077]

[0078] where the factor (I Dq ) / (nkT) is the small-signal transconductance of the TMOS transistor, which is denoted by g m

[0079] Considering the solution obtained when I D ≈I B we obtain

[0080]

[0081] The multiplication factor α VGS (T)

[0082]

[0083] can be considered equal to

[0084]

[0085] Since

[0086]

[0087] that is, α VGS (T) represents the non-normalized temperature coefficient of the voltage V GS of the transistor

[0088] The inventors have noted that for typical values, the term α VGS (T) has little effect on temperature variations. In fact, by making g m ​(T) is substantially independent of temperature, term g m (T) · α VGS (T) will also be a good approximation that is independent of temperature.

[0089] In general, the current of the TMOS transistor can thus be written as the sum of a bias value and a small-signal value:

[0090] I D，EXP = I B + i SIG_EXP (10)

[0091] I D，BLIND = I B + i SIG_BLIND (11)

[0092] where the small-signal contribution is due to small temperature variations obtained on TMOS transistors M EXP and M BLIND respectively:

[0093]

[0094]

[0095] Therefore, in the considered embodiment, the amplifier circuit does not amplify the voltage difference between the drain terminals of transistors M BLIND and M EXP , but the circuit amplifies the current i S corresponding to the current difference in equations (12) and (13).

[0096] To this end, the drain terminal of transistor M BLIND and the drain terminal of transistor M EXP are connected to the differential current integrator 20. Specifically, circuit 22 includes two input terminals, one of which receives the first current i 1 , while the other input terminal receives the second current i 2 . Moreover, circuit 22 is configured to generate an output signal proportional to the integral of the difference between currents i 2 and i 1 , such as voltage V out .

[0097] For example, in the considered embodiment, circuit 22 is implemented by a single operational amplifier 202 (such as an OTA). However, in general, circuit 22 may also include multiple operational amplifiers.

[0098] Specifically, in the considered embodiment, the first input terminal (usually the negative terminal) of operational amplifier 202 is (e.g., directly) connected to transistor M EXPThe drain terminal, i.e., terminal 104, thus receives current i 1 The second input terminal (usually the positive terminal) of the operational amplifier 202 is (e.g., directly) connected to the drain terminal of the transistor M BLIND i.e., terminal 102, thus receiving current i 2 The first terminal (usually the positive output terminal) of the differential output of the operational amplifier 202 is connected to the first input terminal of the operational amplifier 202 through a first feedback network, and the second output terminal (usually the negative output terminal) of the operational amplifier 202 is connected to the first input terminal of the operational amplifier 202 through a second feedback network. Specifically, the first feedback network and the second feedback network each include at least one integrating capacitor. For example, in the embodiment under consideration, the capacitor C GAIN1 (e.g., directly) is connected between the first output terminal and the first input terminal, and the capacitor C GAIN2 (e.g., directly) is connected between the second output terminal and the second input terminal.

[0099] Thus, in the embodiment under consideration, the current i 1 charges the capacitor C GAIN1 , the current i 2 charges the capacitor C GAIN2 , and the output voltage corresponds to the voltage difference across the capacitors C GAIN1 and C GAIN2 . Thus, considering Figure 2 the inverting configuration shown, the amplifier 20 is configured to amplify the current i S = i 2 - i 1 .

[0100] Thus, also considering equations (10) and (11), in various embodiments, the amplifier circuit 20 receives at its input the current

[0101] i S = i SIG_EXP - i SIG_BLIND (14)

[0102] In various embodiments, the amplification interface may also include a current generator 50 that supplies an additional compensation current i SC to the integrator 20 at its input. For example, in the embodiment under consideration, the current generator 50 includes: a first current generator 52 that supplies a current I SC / 2 to the first input terminal of the integrator circuit 20; and a second current generator 58 that supplies a current -I SC / 2 to the second input terminal of the integrator circuit 20.

[0103] Thus, in various embodiments, the amplifier circuit 20 receives a current at the input

[0104]

[0105] Thus, also considering equations (12) and (13), the current i S corresponds to the following formula:

[0106]

[0107] The optional current I SC (as will be described in more detail below) substantially enables offset correction to be performed in the output signal V out . Such offset correction of the output can be used to correct any possible leakage or unwanted signals that may cause the circuit 20 and / or the A / D converter 30 to exit proper operation of the dynamic range.

[0108] Then, the current i according to equation (14) or equation (16) is supplied to the integrator circuit 20 at the input S , and the integrator circuit 20 is configured to generate an output signal representing the integral of the current i S .

[0109] To enable the correct measurement of the current i S , the integrator circuit 20 further includes a reset circuit that is configured to selectively discharge the capacitors C GAIN1 and C GAIN2 . For example, in the considered embodiment, the reset circuit is implemented by a first electronic switch SW GAIN1 connected in parallel with the capacitor C RST1 and a second electronic switch SW GAIN2 connected in parallel with the capacitor C RST2 .

[0110] In various embodiments, the amplification interface may further include a sample and hold circuit 80. Specifically, this circuit 80 represents an analog memory that is configured to store the value of the voltage V out from the output of the integrator 20 according to the control signal SAMPLE. For example, in the simplest case, such a circuit 80 can be implemented with a capacitor C S that is selectively connected to the voltage V S through one or more electronic switches, for example, according to the signal SAMPLE. For example, out . Figure 2 Schematically shows two switches SW S1 and SW S2 . The capacitor C SIt can even correspond to the input capacitance of the A / D converter 30.

[0111] For example, in the considered embodiment, the reset signal RST and the signal SAMPLE are generated by a single control circuit 70, and the single control circuit 70 sets the reset signal RST to a first logic level (usually high) within a first time interval T 1 for resetting the analog integrator, and sets the reset signal RST to a second logic level (usually low) within a second time interval T 2 for activating the analog integrator 20. Thus, the duration T 2 represents the measurement interval, which corresponds to the integration period used by the analog integrator 20. In various embodiments, the time intervals T 1 and T 2 are constant.

[0112] Generally speaking, based on the implementation of the circuit 80, the signal SAMPLE can also correspond to the reset signal RST or its inverted version. However, preferably, the control circuit 70 is configured to generate the signal SAMPLE to ensure that the voltage V GAIN1 and C GAIN2 is sampled by the circuit 80 before setting the reset signal RST to discharge the capacitors C out . For example, in the considered embodiment, the discharge starts when the signal RST is switched from the second logic level (low) to the first level (high), and after the interval T 4 , the signal SAMPLE is set to a low logic value, and this interval T 4 is shorter than the interval T 2 , that is, T 4 < T 2 .

[0113] For example, in various embodiments, the control circuit 70 uses a counter / timer 702 to generate the reset signal RST. The counter / timer 702 is configured to increment a count value according to a clock signal CLK, and set the logic level of the reset signal RST by comparing the count value with at least one first threshold that identifies the duration of the measurement interval T 2 . Similarly, the control circuit 70 can set the logic level of the signal SAMPLE by comparing the count value with at least one second threshold that identifies the duration of the interval T 4 . Therefore, in various embodiments, the control circuit 70 is configured to generate the signals RST and SAMPLE synchronously with the clock signal CLK, and the clock signal CLK has a given oscillation frequency f osc ; that is, the time intervals during which these signals are set to "0" or "1" are the oscillation period 1 / fosc a given multiple of

[0114] As Figure 2 schematically illustrated in, such a clock signal CLK may be supplied by a suitable oscillator 72. Specifically, as will be described in more detail below, the oscillator 72 may be an oscillator including at least one RC element, and the at least one RC element defines the oscillation frequency f osc .

[0115] Figure 3 Possible operations of the control circuit 70 and the integrator circuit 20 are shown in. Specifically, as previously explained, the control circuit 70 generates a reset signal RST; specifically, the control circuit 70 is configured to periodically repeat the following operations:

[0116] - At time t 0 , the signal RST is set to a first logic level (high) to reset the analog integrator 20; and

[0117] - At time t 1 , the signal RST is set to a second logic level (low), thereby determining the end of the reset step, i.e., the start of the integration step.

[0118] Therefore, the time interval between times t 0 and t 1 corresponds to the reset interval T 1 , and the time interval between times t 1 and the next time t 0 ' corresponds to the measurement interval T 2 .

[0119] In the considered embodiment, an example of the signal SAMPLE is also shown. Specifically, as previously explained, the signal SAMPLE stores the value of the voltage V out before the analog integrator 20 is reset.

[0120] For example, for this purpose, the signal SAMPLE may be set to a first logic value within a sampling time T 2 relative to the start of the measurement interval T 1 (i.e., relative to time t 4 ). During this sampling time T 4 , the circuit 80 stores the value of the signal V out , and during the hold time T 5 = T 2 - T 4 , it does not store the value of the signal V out , but remains at the interval T 4The value stored at the end. Thus, in order to enable comparison of different measured values, the measurement interval T 2 The duration of is not particularly important, but the time T 4 should be constant.

[0121] For example, in the considered embodiment, when the signal SAMPLE is "1" (high logic level), the differential voltage V ADC In the considered embodiment corresponds to the voltage on the capacitor C S (additional capacitor and / or the input capacitance of the A / D converter 30), corresponding to the voltage V out Corresponding. At time t 2 , that is, when the signal SAMPLE is set to "0" (low logic level), the capacitor C S Is disconnected from the output of the integrator 20, and due to the memory function of the capacitor C S , so the voltage V ADC Remains fixed at the last voltage value taken at this time t 2 . From time t 2 Until the next time t 0 '(when the signal RESET becomes "1" to cancel the differential signal V out And the signal SAMPLE becomes "1" to make the voltage V ADC Reach the value V out ), the voltage V ADC Remains fixed at the value to be sampled. Therefore, at time t 2 And t 0 'Between, the A / D converter 30 receives a fixed analog signal at the input and can perform digital conversion of this analog level.

[0122] As previously explained, in various embodiments, the reset time T 1 , the sampling time T 4 And the hold time T 5 Can be determined by means of an oscillator and a counter 702, and thus can correspond to the following:

[0123] T 1 =N R / f osc (17)

[0124] T 4 =N S / f osc (18)

[0125] T 5 =N H / f osc (19)

[0126] In various embodiments, the value N R , N S and N H are integers and may optionally also be programmable.

[0127] Thus, Figure 3 the amplification interface shown enables one or more corresponding samples of the voltage V 5 to be acquired / sampled by the A / D converter 30 during each holding interval T PERIOD = T 1 + T 4 + T 5 at the moments t 2 of the voltage V out . For example, in Figure 3 , the processing circuit 40 may acquire, via the A / D converter 30, a sequence of n samples SAMPLE out (1), V out (2),..., V out (n) respectively representing the voltage V 1 , SAMPLE 2 ,..., SAMPLE n .

[0128] Specifically, referring to the embodiment shown in Figure 2 , during the reset step T 1 , the switches SW RST1 , SW RST2 , SW S1 and SW S2 (driven via the signals RST and SAMPLE) are closed. Thus, the current i S flows in the switches SW RST1 and SW RST2 and is absorbed by the output of the OTA202. In fact, assuming that the switches SW RST1 and SW RST2 are closed, the differential output V out is zero because, by the definition of virtual short circuit, the differential voltage between the input terminals of the operational amplifier 202 is zero. Specifically, in the embodiment under consideration, between the moments t 0 and t 1 , the signal RST is "1" and the signal SAMPLE is "1". In this step, the signal current i S flows in the closed switches SW RST1 and SW RST2 . If these switches have a very low on-state resistance (ideally zero), the signal current i S will cause a zero voltage drop and thus the differential voltage V out is zero (asFigure 3 as shown). Moreover, the voltage output from circuit 80 / the voltage V at the input to the A / D converter ADC equals V out as long as switches SW S1 and SW S2 are closed.

[0129] Thus, although the control circuit 204 is configured to regulate the gate-source voltage V B of transistor M GS such that (V O1P + V O1N ) / 2 = V CM1 , the operational amplifier 202 utilizes the differential component (V O1P - V O1N ) to be zero.

[0130] During the sampling phase T 4 , switches SW RST1 and SW RST2 are opened and switches SW S1 and SW S2 are closed. Thus, the current i S charges capacitors C GAIN1 and C GAIN2 , thereby changing the voltage V out at the differential output of the OTA 202, and similarly changing V ADC as long as switches SW S1 and SW S2 are closed. Specifically, in the considered embodiment, at time t 1 , the signal RST is set to "0", so switches SW RST1 and SW RST2 are opened, and thus the current i S flows in capacitors C GAIN1 and C GAIN2 to charge them. For example, in Figure 3 , assuming the current i S is substantially constant, the charging ramps of capacitors C GAIN1 and C GAIN2 have a constant slope. Between times t 2 and t 0 ', due to the effect of capacitor C S , the voltage V ADC then remains stored as the value taken at time t 2 .

[0131] Finally, during the hold phase T 5 , switches SW RST1 and SW RST2Remains disconnected, so the differential output V out Continues to be charged by the current i S ; however, during this phase (different from the sampling phase) T 4 In, the switch SW S1 And SW S2 Are disconnected. Therefore, throughout the hold phase T 5 In, the voltage V ADC Is held "frozen" constant at the voltage V 2 Taken at time t out Value.

[0132] As previously explained, during the sampling phase, the current i S Is for the capacitor C GAIN1 And C GAIN2 Charging. Specifically, by choosing the capacitance of these capacitors such that C GAIN1 = C GAIN2 = C GAIN , the current i S Is integrated by this capacitance C GAIN .

[0133] Therefore, during the sampling window between the corresponding times t 1 And t 2 , the j-th general sample V out (j) can be obtained as the integral of the current i S :

[0134]

[0135] For example, for simplicity, assume the current i S (t) is substantially constant and equal to the value i 1 And t 3 During the time interval between, and considering that the duration of the interval T S,j Is constant, for example, T 1 = N 1 / f S , then equation (20) can be written as follows: osc

[0136]

[0137] For example, substituting the expression defined by equation (16) for the current i s,j , then equation (21) can be written as follows:

[0138]

[0139] The inventors have noticed that equation (22) can then be rewritten as follows:

[0140]

[0141] In fact, equation (23) emphasizes the fact that if the bias current I is selected for a given characteristic B and the clock frequency f osc , then this implementation can be made robust and insensitive to process variations (i.e., variations in resistance and capacitance). Specifically, in various embodiments, current generators 206 and 208 and oscillator 72 are configured such that the coefficient I B / f osc will remain constant.

[0142] Specifically, in various embodiments, current generators 206 and 208 are configured as PTAT current generators, i.e., current generators that supply a current proportional to temperature.

[0143] These PTAT current generators are well known. For example, Figure 8 shows a possible embodiment of a PTAT current generator.

[0144] In the considered embodiment, the above current generator includes a first bipolar transistor Q1 (e.g., a pnp transistor) and a second bipolar transistor Q2 (e.g., a pnp transistor). For example, in the considered embodiment, the collector and base of transistor Q1 and the collector and base of transistor Q2 are connected to a reference voltage, e.g., ground.

[0145] Furthermore, an appropriate biasing circuit is provided for transistors Q1 and Q2. For example, in the considered embodiment, there is a first current generator in the form of FET M3, e.g., a first current generator of p-channel type, which supplies a bias current to the emitter of transistor Q1; and a second current generator in the form of FET M4, e.g., a second current generator of p-channel type, which supplies a bias current to the emitter of transistor Q2.

[0146] The bias current supplied by transistor M4 (i.e., the current flowing through transistor Q2) also flows through resistor R BIAS . Specifically, in the considered embodiment, the source terminal of transistor M3 (e.g., directly) is connected to a supply voltage, e.g., V DD , and the drain terminal of transistor M3 (e.g., directly) is connected to the emitter of transistor Q1. Similarly, the source terminal of transistor M4 (e.g., directly) is connected to a supply voltage, e.g., V DD , and the drain terminal of transistor M4 (e.g., directly) is connected to the first terminal of resistor R BIAS , and resistor R BIASThe second terminal (e.g., directly) is connected to the emitter of transistor Q2.

[0147] Thus, transistors Q1 and Q2 are biased, and the voltage on the emitter of transistor Q1 is related to the emitter-base voltage V of transistor Q1 EB1 correspondingly, and the voltage on the emitter of transistor Q2 is related to the emitter-base voltage V of transistor Q2 EB2 correspondingly.

[0148] Then, the voltage difference ΔV BE = V EB1 - V EB2 is applied to resistor R BIAS . Specifically, in the considered embodiment, for this purpose, the current generator includes an operational amplifier 230, where:

[0149] - The first input terminal (usually the negative terminal) of the operational amplifier 230 (e.g., directly) is connected to the emitter of transistor Q3 / the drain terminal of transistor M3;

[0150] - The second input terminal (usually the positive terminal) of the operational amplifier 230 (e.g., directly) is connected to the drain terminal of transistor M4; and

[0151] - The output terminal of the operational amplifier 230 drives the gate terminals of transistors M3 and M4.

[0152] Thus, in the considered embodiment, since the operational amplifier 230 correspondingly regulates the current flowing through resistor R BIAS , a voltage V BIAS is applied across resistor R through the virtual short circuit of the operational amplifier 230. EB1 Therefore, in the considered embodiment, the current flowing through resistor R BIAS corresponds to the reference current i REF , which reference current i REF depends on resistor R BIAS and the voltage difference ΔV BE = V EB1- V EB2 .

[0153] In the considered embodiment, the current i REF is then also transferred to the output of the current generator; that is, the current generator supplies a current I REF proportional to the current i B . For example, in the considered embodiment, transistor M1 is used, where the source terminal (e.g., directly) is connected to the supply voltage, the gate terminal (e.g., directly) is connected to the gate terminal of transistor M4, and the drain terminal supplies the current I BThus, the transistor M1 can correspond to the current generator 206 connected to the terminal 102. Figure 2 The current generator 208 can be provided by adding a transistor M2, where the source terminal (e.g., directly) is connected to the power supply voltage, the gate terminal (e.g., directly) is connected to the gate terminal of the transistor M4, and the drain terminal supplies the current I to the terminal 104. B .

[0154] Other embodiments of the PTAT current generator are described, for example, in U.S. Patent No. 8,159,206 or "An Ultra-Low Power CMOS PTAT Current Source" by Carlos Christoffersen et al., Proceedings of the Argentine-Uruguay School of Micro-Nanoelectronics, Technology and Applications 2010, EAMTA 2010, the contents of both are incorporated herein by reference.

[0155] Thus, in various embodiments, the PTAT current generator includes one or more transistors that supply a reference voltage ΔV corresponding to the voltage difference applied to the bias resistor R BIAS , and may apply the current (i BE ) flowing through the resistor R BIAS to the output of the current generator through one or more current mirrors, that is REF

[0156]

[0157] For example, the current of the PTAT current generator can be defined as:

[0158]

[0159] Specifically, in the embodiment shown in Figure 8 , the parameter b is the ratio between the area A2 of the transistor Q2 and the area A1 of the transistor Q1, that is, A2 = b·A1, where b > 1. Therefore, the parameter b is a constant that can be fixed with good accuracy (the ratio of areas).

[0160] Conversely, in various embodiments, the oscillator 72 is based on an RC oscillator. These RC oscillators can be from, for example, U.S. Patent No. 6,590,463, the contents of which are incorporated herein by reference. Specifically, the RC oscillator includes a resistor R osc and a capacitor C osc , and the clock frequency f osc ​Proportional to the reciprocal of the RC product; i.e.,

[0161]

[0162] The proportionality can be made explicit by introducing the gain coefficient G of the oscillator osc i.e

[0163]

[0164] In this context, the inventors have noted that by appropriately sizing the above values, the effects of process spread can be (at least partially) compensated. Specifically, in various embodiments, oscillator 72 is configured such that:

[0165] R osc = M·R BIAS (28)

[0166] C osc = P·C GAIN (29)

[0167] where P and M are coefficients.

[0168] Thus, in various embodiments, the resistance R of oscillator 72 is obtained by the same process osc as well as the resistance R of current generators 206 and 208 BIAS . Further, in various embodiments, these resistances are provided in the same integrated circuit / die and are preferably arranged adjacent to each other such that they are exposed to the same temperature variations.

[0169] Likewise, in various embodiments, the capacitance C of oscillator 72 is obtained by the same process osc as the capacitance C of integrator 20 GAIN . Further, in various embodiments, these capacitances are provided in the same integrated circuit / die and are preferably arranged adjacent to each other such that they are exposed to the same temperature variations.

[0170] Thus, in various embodiments, equation (23) corresponds to

[0171]

[0172] This equation also emphasizes the current I SC for the differential output signal V outReasons for offset correction. Specifically, as previously explained, the current generator 50 together with the circuit 204 performing common-mode control can correct any possible leakage or unwanted signals that may cause the OTA block 202 and / or the A / D converter 30 to exit the normal operating dynamic range, or in other cases may cause the TMOS transistors to deviate from the desired operating point. Therefore, the proposed system is robust against compensating for possible leakage current signals injected into the high-impedance nodes V O1N and V O1NP (i.e., the input terminals of the integrator circuit 20). Specifically, the common-mode components of these leakage signals are compensated by the circuit 204, thereby preventing common-mode drift. Conversely, the differential leakage components can be eliminated by tuning (i.e., trimming) the value of the current I SC supplied by the current generator 50.

[0173] The manner in which the current I SC is generated defines the type of offset compensation performed.

[0174] For example, in various embodiments, the current generator is programmable to supply a variable current I SC . For example, for this purpose, a circuit (e.g., the processing circuit 40) can monitor the voltage V out and change the current I out according to the voltage V SC . For example, in this case, reference can be made to Italian patent application number 102019000001847, the content of which is incorporated herein by reference.

[0175] Specifically, this document describes an amplification interface where the current generator 50 can be an IDAC (current digital-to-analog converter), and thus it supplies a current with a variable amplitude according to a digital signal having multiple bits.

[0176] Moreover, this document describes the fact that in the case of an amplifier provided by an analog integrator, the current generator can also supply a current modulated, for example, by a PWM (pulse-width modulation) signal, thereby changing the mean value of the current supplied by the current generator 50. For example, the current generator 50 can supply a positive current or a negative current according to a drive signal. Therefore, when the drive signal has a first logic value, the current generator 50 supplies a positive current, and when the drive signal has a second logic value, the current generator 50 supplies a negative current. Thus, the control circuit 70 can determine, for each measurement interval T 2 a first duration T 3 during which the drive signal has the first logic value and a second duration (T 2 -T 3 ) during which the drive signal has the second logic value. Therefore, by changing the duration T 3 , for each measurement interval T2 Select the mean value of the current I supplied by the current generator 50 SC Since the analog integrator supplies the integration of the current at the output, the A / D converter 30 cannot sense this modulation. At the end of the measurement / sampling interval, the integration of this current only represents the mean value of the current.

[0177] For example, by applying this to Figure 2 the circuit scheme shown, the control circuit 70 can be configured during each measurement interval T 2 for:

[0178] - Activate the current generator 52 and deactivate the generator 58 within a duration T 3 ; and

[0179] - Deactivate the current generator 52 and activate the generator 58 within a duration (T 2 - T 3 ).

[0180] Thus, in this case, the current generators 52 and 58 can be configured to supply corresponding constant currents. Preferably, in this case, the current generators 52 and 58 supply currents with the same magnitude but opposite signs.

[0181] However, the current generator 50 may not even be programmable.

[0182] For example, in various embodiments, the current generator 50 generates the current I SC as a bandgap current, where a reference voltage V REF supplied by a bandgap voltage generator is used (i.e., a voltage that does not change with temperature). For example, reference can be made to Kleczek et al.'s "Low voltage area efficient current-mode CMOS bandgap reference in deep submicron technology" 2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES) (2014): 247-251, the content of which is hereby incorporated by reference. Specifically, this document describes various solutions for generating PTAT or bandgap currents in the introduction section.

[0183] In this case, the obtained offset correction is also independent of temperature. For example, in this case, the current I SC is generally as follows:

[0184]

[0185] In various embodiments, the resistance R of current generator 50 is obtained by the same process BIAS2 and the resistance R of current generators 206 and 208 BIAS . Further, in various embodiments, these resistances are provided in the same integrated circuit / die and are preferably arranged adjacent to each other such that they are exposed to the same temperature variations; i.e.,

[0186]

[0187] Thus, in this case, equation (30) can be rearranged as follows:

[0188]

[0189] Conversely, in other embodiments, current generator 50 generates a current I SC as a PTAT current (i.e., a current proportional to temperature), e.g.,

[0190]

[0191] such as

[0192]

[0193] In various embodiments, the resistance R of current generator 50 is obtained by the same process BIAS2 and the resistance R of current generators 206 and 208 BIAS . Further, in various embodiments, these resistances are provided in the same integrated circuit / die and are preferably arranged adjacent to each other such that they are exposed to the same temperature variations; e.g.,

[0194]

[0195] Thus, in this case, equation (30) can be rearranged as follows:

[0196]

[0197] It can be noted from equations (33) and (37) how the dependence of the output signal on the process spread for manufacturing the resistors and capacitors is eliminated in the proposed manner, since only the proportionality factors B, M, and P are present.

[0198] Due to the architectural choices made and due to the bias current I B and the clock frequency f oscWith the proper selection, this result has been obtained. Moreover, it can be concluded from Equation (33) that in the first case (bandgap type I SC ), the possible offset independent of temperature can be corrected, while in the second case (PTAT type I SC ), the possible offset varying with temperature can be corrected. Generally speaking, the current generator 50 can also be implemented by two current generators, where the first current generator supplies the current I of the bandgap type SC1 , and the second current generator supplies the current I of the PTAT type SC2 , thus enabling the correction of the offset contribution, which has a temperature-variable part in addition to the temperature-invariant part.

[0199] Figure 4 shows a second embodiment. Generally speaking, compared with Figure 2 , the amplification interface further includes three circuits 210, 212, and 214. In addition, the control circuit 70 is configured to generate two control signals C1 and C2 for these circuits, and the amplifier 20 or the processing circuit 40 includes a circuit module 216, which is configured to process the digital samples supplied by the A / D converter 30.

[0200] Specifically, the circuits 210, 212, and 214 are chopper circuits, which invert the connection between two corresponding circuits.

[0201] Specifically, in the considered embodiment, the current generator 208 is connected to the first input terminal (e.g., the negative terminal) of the current integrator 20, and the current generator 206 is connected to the second input terminal (e.g., the positive terminal) of the current integrator 20.

[0202] In this case, according to the signals C1 and C2, the chopper circuit 210 is configured to selectively connect the transistor M EXP to the first input terminal or the second input terminal of the current integrator 20, and similarly, connect the transistor M BLIND to the second input terminal or the first input terminal of the current integrator 20 selectively.

[0203] For example, in the considered embodiment, the chopper circuit 210 includes: a switch SW 5 , which is used to selectively connect the transistor M BLIND to the second input terminal of the current integrator 20 according to the signal C1; and a switch SW 7 , which is used to selectively connect the transistor M BLIND to the first input terminal of the current integrator 20 according to the signal C2. Moreover, the chopper circuit 210 includes: a switch SW 8 , which is used to connect the transistor M according to the signal C1EXP Selectively connected to the first input terminal of the current integrator 20; and a switch SW 6 , which is used to connect the transistor M according to the signal C2 EXP Selectively connected to the second input terminal of the current integrator 20.

[0204] Similarly, according to the signals C1 and C2, the chopper circuit 214 is configured to selectively connect the current generator 58 to the first input terminal or the second input terminal of the current integrator 20, and similarly, connect the current generator 52 selectively to the second input terminal or the first input terminal of the current integrator 20.

[0205] For example, in the considered embodiment, the chopper circuit 214 includes: a switch SW 1 , which is used to selectively connect the current generator 52 to the second input terminal of the current integrator 20 according to the signal C1; and a switch SW 2 , which is used to selectively connect the current generator 52 to the first input terminal of the current integrator 20 according to the signal C2. Moreover, the chopper circuit 214 includes: a switch SW 4 , which is used to selectively connect the current generator 58 to the first input terminal of the current integrator 20 according to the signal C1; and a switch SW 4 , which is used to selectively connect the current generator 58 to the second input terminal of the current integrator 20 according to the signal C2.

[0206] Therefore, the chopper circuits 210 and 214 enable the connections of the transistors M EXP and M BLIND as well as the current generators 52 and 58 to the input terminals of the current integrator 20 to be inverted.

[0207] In the considered embodiment, the chopper circuit 212 is configured to invert the connection from the output of the integrator 20 to the input of the A / D converter 30, that is, to invert the output voltage V out of the current integrator 20.

[0208] For example, in the considered embodiment, the chopper circuit 212 includes: a switch SW 9 , which is used to selectively connect the positive output terminal of the current integrator 20 to the positive input terminal of the A / D converter 30 according to the signal C1; and a switch SW 10 , which is used to selectively connect the positive output terminal of the current integrator 20 to the negative input terminal of the A / D converter 30 according to the signal C2. Moreover, the chopper circuit 212 includes: a switch SW 12 ​, which is used to selectively connect the negative output terminal of the current integrator 20 to the negative input terminal of the A / D converter 30 according to the signal C1; and the switch SW 11 , which is used to selectively connect the negative output terminal of the current integrator 20 to the positive input terminal of the A / D converter 30 according to the signal C2.

[0209] Generally speaking, the chopper circuit 212 can also implement Figure 2 the switches SW of the sample-and-hold circuit 80 S1 and SW S2 . In fact, in the considered embodiment, by disconnecting the switches S 9 , S 10 , S 11 and S 12 , the A / D converter is disconnected from the output of the integrator 20.

[0210] Figure 5 Shows the possible operations of the control circuit 70.

[0211] In the considered embodiment, during each interval T PERIOD , the control circuit 70 drives one of the signals C1 or C2, while the other signal maintains its logic level. For example, during the first interval, the signal C1 changes, and during the second interval, the signal C2 changes.

[0212] Therefore, the operation of the circuit during the first interval generally corresponds to the operation described with reference to Figure 2 , where the current generator 58 and the transistor M EXP are connected to the first input terminal of the integrator 20, and the current generator 52 and the transistor M BLIND are connected to the second input terminal of the integrator 20. Moreover, the signal C1 performs the function of the signal SAMPLE described in reference Figure 3 . Therefore, in the considered embodiment, the control circuit 70:

[0213] - At time t 0 , reset the integrator 20 (using the switches SW RST1 and SW RST2 and the signal RST);

[0214] - At time t 1 , activate the integrator 20 (using the switches SW RST1 and SW RST2 and the signal RST); and

[0215] - At time t 2 , disconnect the output of the integrator (using the switches SW 9 and SW 12and signal C1), enabling the voltage V ADC to be sampled.

[0216] Conversely, the operation of the circuit is inverted during the second interval. Specifically, current generator 58 and transistor M EXP are connected to the second input terminal of integrator 20, and current generator 52 and transistor M BLIND are connected to the first input terminal of integrator 20. Moreover, signal C2 performs the function of signal SAMPLE described with reference to Figure 3 . Thus, in the embodiment considered, the control circuit:

[0217] - At time t 0 , reset integrator 20 (using switches SW RST1 and SW RST2 and signal RST);

[0218] - At time t 1 , activate integrator 20 (using switches SW RST1 and I 2 and signal RST); and

[0219] - At time t 2 , disconnect the output of the integrator (using switches SW 10 and SW 11 and signal C2), enabling the voltage V ADC to be sampled.

[0220] For this reason, integrator 20 will integrate a current i S with an opposite sign to the current i S during the second interval compared to the first interval (since the inputs of integrator 20 are essentially inverted).

[0221] Thus, the output voltage V out also increases during one interval (e.g., the first interval for the case provided by way of example) and decreases during another interval (e.g., the second interval for the case provided by way of example). However, by inverting the output of integrator 20, the voltage V ADC will always exhibit the same behavior.

[0222] In various embodiments, block 216 thus calculates the mean of the digital samples and can be, for example, a moving average filter that receives samples with a sampling frequency of 1 / T PERIOD at its input from ADC 30 and generates a signal with a sampling frequency of 1 / T PERIOD at its output, where each sample is obtained by averaging the last n samples received from the ADC (where n is preferably even).

[0223] Generally speaking, in Figure 2 the embodiment, a block 216 can also be introduced downstream of the ADC 30 to average the output signal generated at the sampling frequency T PERIOD so as to obtain an averaged signal, thereby reducing the noise. Generally speaking, in addition, in Figure 4 the manner, the introduction of the block 216 also enables the reduction of noise. However, in Figure 4 , this is not only a possible improvement, but its introduction also enables the elimination of the components presented by the output signal at the chopping frequency.

[0224] Generally speaking, a chopping operation similar to this can be used to eliminate the offset of the OTA 202. On the contrary, in the considered embodiment, this chopping operation is also extended to compensate for the differences between current generators. Therefore, in the considered embodiment, the chopping frequency is half of the sampling frequency.

[0225] Specifically, as previously mentioned, the integrator 20 is configured to integrate the current during the first interval:

[0226]

[0227] and integrate the current during the second interval:

[0228]

[0229] Therefore, the signal V obtained from the integration OUT has slopes with different signs during the first interval and the second interval. However, if other signal inversions performed by the circuit 212 inserted before the A / D converter 30 are also considered, the signal always has the same sign.

[0230] Therefore, from a mathematical perspective, the signal V ADC must be equal to the signal obtained through the embodiment Figure 2 shown. On the contrary, in the actual implementation, the two current generators 206 and 208 may exhibit mismatches (hereinafter represented by ΔI B ), and / or the OTA block 202 may exhibit an equivalent offset at the input (hereinafter represented by V off_OTA ).

[0231] Assuming the existence of two non-idealities ΔI B and V off_OTA , then in the embodiment Figure 2 shown, the two consecutive samples V out (j) and V out (j + 1) will have the following values:

[0232]

[0233]

[0234] In contrast, in the Figure 4 illustrated embodiment, two consecutive samples V out (j) and V out (j + 1) will have the following values:

[0235]

[0236]

[0237] Therefore, by calculating the average of the two values, or generally, calculating an even number of samples, block 216 filters out the non-ideality ΔI B and V off_OTA effects.

[0238] Generally, the filtering of these quantities due to the chopping technique is of the high-pass type; that is, in the case where they are d.c. quantities or they are quantities that vary at low frequencies, they will be filtered out. Therefore, it should be noted that the filtering not only eliminates the mismatch ΔI B between the two generators, but also eliminates the low-frequency noise I B introduced by the two generators. Therefore, from the perspective of signal-to-noise ratio, the performance of the system is also improved.

[0239] As long as the same module 216 applied to the Figure 2 system at the output by averaging samples such as those described in equations (40) and (41) does not produce the same effect of eliminating the above-mentioned non-ideality, the effects of ΔI B and V off_OTA will not be filtered out.

[0240] Figure 6 The scheme of the third embodiment is shown in. Compared with the Figure 4 architecture, the difference is that the offset correction signal (from the current generator) is directly added to the signal generated by the TMOS sensor 10. Specifically, in the considered embodiment, the current generator 52 is connected to the drain terminal of the transistor M BLIND , and the current generator 528 is connected to the drain terminal of the transistor M EXP .

[0241] In this case, only the chopper circuit 210 is sufficient. Figure 6 The final output signal of the illustrated embodiment is exactly the same as the output signal presented by the Figure 4 embodiment; therefore, the previous description also applies here.

[0242] The figure shown in Figure 7 is a diagram of the fourth circuit architecture proposed by the present invention. Compared with the architecture of Figure 4 (however, similar modifications can be made in the embodiments shown in Figure 6 ), the difference is that the chopper circuit 212 has been moved downstream of the A / D converter 30. Therefore, in the embodiments under consideration, a digital type chopper circuit or module 212' is used, for example, implemented by means of a digital circuit module of the processing circuit 40. Therefore, this circuit or module is configured to supply to the circuit 216 the value of the digital samples supplied by the A / D converter 30 or the value of the digital samples supplied by the A / D converter 30 multiplied by -1 according to the signals C1 and C2.

[0243] Therefore, in various embodiments, the proposed method enables the signal generated by the TMOS transistor to be amplified without being affected by the process variations of the resistors and capacitors.

[0244] In various embodiments, in addition to appropriately selecting the bias current I B and the reference clock frequency f osc , this is also obtained due to the proposed architecture.

[0245] In various embodiments, the proposed method enables the offset and the variation of the offset to be corrected according to the temperature.

[0246] In addition, in various embodiments, the method proposed in its second implementation also enables the non-ideality in the bias current and the offset of the OTA to be filtered.

[0247] Generally speaking, the proposed method is designed to amplify the signal generated by the TMOS transistor, and can also be used in the following cases: transistors M BLIND and M EXP are two ordinary MOS transistors, or generally FETs, and at their inputs (i.e., the gate terminals of the two transistors), there is a differential signal to be amplified.

[0248] Of course, without prejudice to the principles of the present disclosure, the details of the construction and embodiments can vary widely with respect to what is only described and illustrated herein by way of example, without thereby departing from the scope of the present invention as defined by the appended claims.

[0249] The claims form an integral part of the technical teaching provided in the description herein.

Claims

1. An amplification interface, comprising: A first field-effect transistor (FET) having a drain terminal connected to a first node and a source terminal connected to a third node; A second FET having a drain terminal connected to a second node and a source terminal connected to the third node; A first bias current generator configured to apply a first bias current to the first node; A second bias current generator configured to apply a second bias current to the second node; A third FET having a drain terminal connected to the third node and a source terminal connected to a reference voltage; An adjustment circuit configured to drive a gate terminal of the third FET so as to adjust a common-mode voltage at the first node and a common-mode voltage at the second node to a given value; At least one current generator configured to apply a correction current to one of the first node and the second node; and A differential current integrator including a first input terminal connected to the second node and a second input terminal connected to the first node, wherein the differential current integrator is configured to provide an output voltage via two output terminals, the output voltage indicating an integral of a difference between a first output current and a second output current, the first output current being received at the first input terminal of the differential current integrator from the second node, and the second output current being received at the second input terminal of the differential current integrator from the first node.

2. The amplification interface according to claim 1, wherein the adjustment circuit is configured to drive the gate terminal of the third FET such that: (V O1P +V O1N ) / 2 = V CM1 , where V O1P corresponds to the common-mode voltage at the first node, V O1N corresponds to the common-mode voltage at the second node, and V CM1 corresponds to the given value.

3. The amplification interface according to claim 1, wherein the differential current integrator includes a differential operational amplifier, the differential operational amplifier comprising: A first capacitor connected between a first output terminal and the first input terminal of the differential operational amplifier; and A second capacitor connected between a second output terminal and the second input terminal of the differential operational amplifier.

4. The amplification interface according to claim 3, wherein the differential current integrator further includes a first electronic switch and a second electronic switch connected in parallel with the first capacitor and the second capacitor respectively, wherein the first electronic switch and the second electronic switch are driven via a reset signal.

5. The amplification interface according to claim 4, further comprising a sample-and-hold circuit configured to: Store the output voltage when a control signal has a first logic value; and Maintain the output voltage when the control signal has a second logic value different from the first logic value.

6. The amplification interface according to claim 5, including a control circuit configured to: Generate the reset signal such that the differential current integrator is periodically reset during a reset interval and activated during a measurement interval; and During each measurement interval, set the control signal to the first logic value within a sampling interval and set the control signal to the second logic value within a hold interval.

7. The amplification interface according to claim 6 further includes an RC oscillator having a capacitor and a resistor, the capacitor and the resistor defining an oscillation period of the RC oscillator, and wherein the control circuit is configured to generate the control signal such that the sampling interval corresponds to a multiple of the oscillation period of the RC oscillator.

8. The amplification interface according to claim 1, wherein the first bias current and the second bias current are proportional to absolute temperature PTAT.

9. The amplification interface according to claim 1, wherein the first FET and the second FET include n-channel MOS transistors.

10. The amplification interface according to claim 1, wherein the first FET and the second FET are thermally isolated transistors, and wherein the gate terminals of the first FET and the second FET are connected to another reference voltage.

11. The amplification interface according to claim 1, wherein the at least one current generator comprises: a first current generator configured to apply a positive correction current to the first node in addition to the first bias current, and a second current generator configured to apply a negative correction current to the second node in addition to the second bias current.

12. The amplification interface according to claim 11 further includes a first chopper circuit connected between the first input terminal and the second input terminal of the differential current integrator and the first node and the second node.

13. The amplification interface according to claim 12 further includes a second chopper circuit connected between the first current generator and the second current generator and the first node and the second node.

14. The amplification interface according to claim 13 further includes a third chopper circuit connected between the two output terminals of the differential current integrator and the two output terminals of the amplification interface.

15. The amplification interface according to claim 1, wherein the first FET and the second FET form an amplifier having a voltage offset, and wherein the correction current compensates for the voltage offset.

16. A measurement system, comprising: an amplification interface, including: a first field effect transistor (FET) having a drain terminal connected to a first node and a source terminal connected to a third node; a second FET having a drain terminal connected to a second node and a source terminal connected to the third node; a first bias current generator configured to apply a first bias current to the first node; a second bias current generator configured to apply a second bias current to the second node; a third FET having a drain terminal connected to the third node and a source terminal connected to a reference voltage; an adjustment circuit configured to drive the gate terminal of the third FET so as to adjust the common-mode voltage at the first node and the common-mode voltage at the second node to a given value; at least one current generator configured to apply a correction current to one of the first node and the second node; and a differential current integrator including a first input terminal connected to the second node and a second input terminal connected to the first node, wherein the differential current integrator is configured to provide an output voltage via two output terminals, the output voltage indicating an integration of a difference between a first output current and a second output current, the first output current being received at the first input terminal of the differential current integrator from the second node, and the second output current being received at the second input terminal of the differential current integrator from the first node; an analog-to-digital converter connected to the two output terminals of the differential current integrator of the amplification interface; and a processing circuit connected to an output of the analog-to-digital converter.

17. The measurement system according to claim 16, wherein the adjustment circuit is configured to drive the gate terminal of the third FET such that: (V O1P +V O1N ) / 2 = V CM1 , where V O1P corresponds to the common-mode voltage at the first node, V O1N corresponds to the common-mode voltage at the second node, and V CM1 corresponds to the given value.

18. The measurement system according to claim 16, wherein the differential current integrator includes a differential operational amplifier, the differential operational amplifier comprising: a first capacitor connected between a first output terminal and the first input terminal of the differential operational amplifier; and a second capacitor connected between a second output terminal and the second input terminal of the differential operational amplifier.

19. The measurement system according to claim 18, wherein the differential current integrator further includes a first electronic switch and a second electronic switch connected in parallel with the first capacitor and the second capacitor respectively, wherein the first electronic switch and the second electronic switch are driven via a reset signal.

20. The measurement system according to claim 18, wherein the first FET and the second FET form an amplifier with a voltage offset, and wherein the correction current compensates for the voltage offset.

21. An amplification interface, comprising: a first node, a second node, and a third node; a first field-effect transistor (FET) having a drain connected to the first node and a source connected to the third node; a second FET having a drain terminal connected to the second node and a source connected to the third node; a first bias current generator having an output connected to the first node, the first bias current generator being configured to apply a first bias current to the first node; a second bias current generator having an output connected to the second node, the second bias current generator being configured to apply a second bias current to the second node; a third FET having a drain connected to the third node and a source connected to a reference voltage; an adjustment circuit configured to drive the gate terminal of the third FET so as to adjust voltages at the first node and the second node to a given value; and at least one current generator configured to apply a correction current to the first node and / or the second node.

22. The amplification interface according to claim 21, wherein the adjustment circuit is configured to drive the gate terminal of the third FET such that: (V O1P +V O1N ) / 2 = V CM1 , where V O1P corresponds to the voltage at the first node, V O1N corresponds to the voltage at the second node, and V CM1 corresponds to the given value.

23. The amplification interface according to claim 21, wherein the first FET and the second FET are thermally insulated transistors, and wherein the gate terminals of the first FET and the second FET are connected to another reference voltage.

24. The amplification interface according to claim 21, wherein the at least one current generator comprises: a first current generator configured to apply a positive correction current to the first node, and a second current generator configured to apply a negative correction current to the second node.

25. The amplification interface according to claim 21, wherein the first FET and the second FET form an amplifier with a voltage offset, and wherein the correction current compensates for the voltage offset.

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