Weight unit and electronic device

Abstract

The present invention discloses a weight unit and an electronic device. The weight unit includes: a first field-effect transistor (FET) and a first resistive memory element, the first resistive memory element being connected to the drain of the first field-effect transistor; and a second field-effect transistor and a second resistive memory element, the second resistive memory element being connected to the drain of the second field-effect transistor. The drain of the first field-effect transistor is connected to the gate of the second field-effect transistor, and the drain of the second field-effect transistor is connected to the gate of the first field-effect transistor.

Description

[0001] Priority

[0002] This application claims the benefit of priority of U.S. Provisional Application No. 62 / 807,534, filed on Feb. 19, 2019, and U.S. Application No. 16 / 448,799, filed on Jun. 21, 2019, in the USPTO, the entire disclosures of which are hereby incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to a weight cell configuration in which the on / off ratio is closer to the on / off ratio of a transistor (10 4 to 10 5 ). Background Art

[0004] There is an increasing demand for hardware accelerators for machine learning (ML) applications. The dominant computation in most of these ML applications is matrix-vector multiplication. It is possible to perform matrix-vector multiplication very efficiently in analog form through a crossbar network. However, in order to represent weights, memory elements must be introduced in each weight cell. Static random access memory (SRAM) is large and power-inefficient. Non-volatile memory options such as redundant random access memory (RRAM), flash memory (FLASH), or spin-torque transfer magnetic random access memory (STT-MRAM) are often affected by a set of other challenges including low on / off ratio, high deviation, and non-compatible programming voltages. Summary of the Invention

[0005] According to one embodiment, a weight cell is provided. The weight cell includes: a first field effect transistor (FET) and a first resistive memory element connected to the drain of the first FET; and a second FET and a second resistive memory element connected to the drain of the second FET. The drain of the first FET is connected to the gate of the second FET, and the drain of the second FET is connected to the gate of the first FET.

[0006] According to one embodiment, an electronic device is provided. The electronic device includes an array of weight units, each weight unit including: a first field effect transistor (FET) and a first resistive memory element, the first resistive memory element being connected to the drain of the first FET; and a second FET and a second resistive memory element, the second resistive memory element being connected to the drain of the second FET, the drain of the first FET being connected to the gate of the second FET, and the drain of the second FET being connected to the gate of the first FET. The electronic device includes: a processor configured to perform inference with the weight unit array by: setting an input to a row of weight units in the weight unit array according to a logical value of a corresponding neuron; and reading an output of a column of weight units in the weight unit array.

[0007] According to one embodiment, an electronic device is provided. The electronic device includes an array of weight units, each weight unit including: a first field effect transistor (FET) and a first resistive memory element, the first resistive memory element being connected to the drain of the first FET; and a second FET and a second resistive memory element, the second resistive memory element being connected to the drain of the second FET, the drain of the first FET being connected to the gate of the second FET, and the drain of the second FET being connected to the gate of the first FET. The processor is configured to write to the resistive memory element according to a direction of a current supplied to the resistive memory element. BRIEF DESCRIPTION OF DRAWINGS

[0008] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a circuit diagram of a weight unit according to an embodiment.

[0010] Figure 2 is a circuit diagram of an array of weight units according to an embodiment.

[0011] Figure 3 is a graph of a current output of an array of weight units according to an embodiment.

[0012] Figure 4 is a block diagram of an electronic device in a network environment according to an embodiment.

[0013] REFERENCE NUMERAL DESCRIPTION

[0014] 100, 202, 204, 206, 208, 210, 212, 214, 216: weight units;

[0015] 102: first magnetic tunnel junction;

[0016] 104: second magnetic tunnel junction;

[0017] 106: The first field effect transistor;

[0018] 108: The second field effect transistor;

[0019] 110, 120: Drain;

[0020] 112, 122: Gate;

[0021] 114, 124: Source;

[0022] 200: Weight cell array;

[0023] 300: Curve graph;

[0024] 302, 304, 306: Line;

[0025] 400: Network environment;

[0026] 401, 402, 404: Electronic device;

[0027] 408: Server / Electronic device;

[0028] 420: Processor;

[0029] 421: Main processor;

[0030] 423: Auxiliary processor;

[0031] 430: Memory;

[0032] 432: Volatile memory;

[0033] 434: Non-volatile memory;

[0034] 436: Internal memory;

[0035] 438: External memory;

[0036] 440: Program;

[0037] 442: Operating system;

[0038] 444: Middleware;

[0039] 446: Application program;

[0040] 450: Input device;

[0041] 455: Sound output device;

[0042] 460: Display device;

[0043] 470: Audio module;

[0044] 476: Sensor module;

[0045] 477: Interface;

[0046] 478: Connection terminal;

[0047] 479: Haptic module;

[0048] 480: Camera module;

[0049] 488: Power management module;

[0050] 489: Battery;

[0051] 490: Communication module;

[0052] 492: Wireless communication module;

[0053] 494: Wired communication module;

[0054] 496: Subscriber identification module;

[0055] 497: Antenna module;

[0056] 498: First network;

[0057] 499: Second network;

[0058] G, Conductance;

[0059] I out : First output / output line;

[0060] Second output / output line;

[0061] Iout1, Iout1B, Iout2, Iout2B, Iout3, Iout3B, Iout4, Iout4B: Output lines;

[0062] V in , Input / input line;

[0063] Input. Detailed implementation

[0064] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that although the same elements are illustrated in different drawings, the same elements will be denoted by the same reference numerals. In the following description, specific details such as detailed configurations and components are provided only to assist in the overall understanding of the embodiments of the present disclosure. Therefore, those skilled in the art should understand that various changes and modifications can be made to the embodiments described herein without departing from the scope of the present disclosure. In addition, descriptions of well-known functions and configurations are omitted for clarity and conciseness. The terms described below are defined in consideration of the functions in the present disclosure and may vary according to the user, the user's intention, or custom. Therefore, the definition of the terms should be determined based on the content throughout the specification.

[0065] The present disclosure may have various modifications and various embodiments, and the embodiments will be described in detail below with reference to the accompanying drawings. However, it should be understood that the present disclosure is not limited to the embodiments, but includes all modifications, equivalents, and alternatives within the scope of the present disclosure.

[0066] Although ordinal terms such as first and second may be used to describe various elements, the structural elements are not limited by the terms. The terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, a first structural element may be referred to as a second structural element. Similarly, a second structural element may also be referred to as a first structural element. As used herein, the term "and / or" includes any and all combinations of one or more related items.

[0067] The terms used herein are only for describing various embodiments of the present disclosure and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form. In the present disclosure, it should be understood that the terms "include" or "have" indicate the presence of features, numbers, steps, operations, structural elements, components, or combinations thereof, and do not exclude the presence or addition probability of one or more other features, values, steps, operations, structural elements, components, or combinations thereof.

[0068] Unless otherwise defined, all terms used herein have the same meaning as those understood by those skilled in the art to which the present disclosure pertains. For example, terms defined in commonly used dictionaries will be interpreted as having the same meaning as the context in the relevant technical field, and will not be interpreted as having an ideal or overly formal meaning unless clearly defined in the present disclosure.

[0069] An electronic device according to an embodiment may be one of various types of electronic devices. The electronic device may include, for example, a portable communication device (e.g., a smart phone), a computer, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. According to an embodiment of the present disclosure, the electronic device is not limited to those electronic devices described above.

[0070] The terms used in this disclosure are not intended to limit this disclosure, but are intended to include various changes, equivalents, or alternatives for the corresponding embodiments. Regarding the description of the drawings, like reference numerals may be used to refer to like or related elements. Unless the relevant context clearly indicates otherwise, the singular form of a noun corresponding to an object may include one or more of such things. As used herein, each of such phrases as "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" may include all possible combinations of the objects listed together with the corresponding one in such phrases. As used herein, terms such as "first", "second", "the first", and "the second" may be used to distinguish a corresponding component from another component, but are not intended to limit the components in other aspects (e.g., importance or order). It is expected that if an element (e.g., a first element) is referred to as "coupled with", "coupled to", "connected with", or "connected to" another element (e.g., a second element) (with or without the term "operatively" or "communicatively"), it indicates that the element may be directly (e.g., wired), wirelessly, or via a third element coupled with the other element.

[0071] As used herein, the term "module" may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with other terms such as "logic", "logic block", "component", and "circuit". A module may be a single integrated component adapted to perform one or more functions, or a minimum unit or a part thereof. For example, according to an embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0072] In an exemplary scenario, a resistive weight unit for semi-digital matrix vector multiplication includes two STT memory devices and an n-type field effect transistor (FET). The STT memory device may be in one of two states: a high resistance state or a low resistance state. Unfortunately, for STT-MRAM, the ratio of on-resistance to off-resistance is very low (usually only about 2 to 3). The present disclosure provides a weight unit configuration in which the on / off ratio is closer to the on / off ratio of a transistor (10 4 to 10 5)。In addition, the weight cell produces complementary outputs on two lines - an output and an output bar. If the product of the input signal and the weight of the weight cell is logic 1, then the output line will have a constant current and the output line bar will have zero current. Conversely, if the product is logic 0, then the output line will have zero current and the output line bar will have a constant current.

[0073] Figure 1 is a circuit diagram of a weight cell 100 according to an embodiment. The weight cell 100 includes a first magneto tunnel junction (MTJ) 102, a second MTJ 104, a first FET 106, and a second FET 108. The FETs 106 and 108 are depicted as n-type FETs (NFETs), but p-type FETs (PFETs) can be utilized. The FET 106 includes a drain 110, a gate 112, and a source 114. Similarly, the FET 108 includes a drain 120, a gate 122, and a source 124. The weight cell 100 includes cross-coupling such that the drain 110 of the FET 106 is connected to the gate 122 of the FET 108, and the drain 120 of the FET 108 is connected to the gate 112 of the FET 106.

[0074] The MTJ 102 has a conductance G, while the MTJ 104 has a conductance The weight cell (100) includes four independent external connections: an input V to the MTJ 102 in and an input to the MTJ 104 a first output I connected to the source 114 of the FET 106 out and a second output connected to the source 124 of the FET 108 Each of the MTJ 102 and MTJ 104 can be in one of two states, a high-conductance state G H or a low-conductance state G L . The cross-coupling allows for a high on / off ratio of the output. The MTJ 102 and MTJ 104 have different conductance states and the configuration determines the logic value. For example, if the weight cell 100 has a logic value of 1, then G = G L and Similarly, if the weight cell 100 has a logic value of 0, then G = G H and as depicted in Table 1.

[0075] Table 1

[0076]

[0077] During inference, the weight cell performs a multiplication operation in analog form based on the potential on the input line and the state of the weight cell 100. The product is the analog current on output line I out and the controlled complementary output on output line . The logical value of the input is determined by the same potential applied to the two input lines V in and . If the two lines are set high, then the input has a logical value of 1. If the two lines are set low, then the input has a logical value of 0. The state of the weight cell 100 is determined by the conductance states of the two MTJs 102 and MTJ 104. If G is in the high-conductance state and is in the low-conductance state, then the weight cell 100 has a logical value of 0. If G is in the low-conductance state and is in the high-conductance state, then the weight cell 100 has a logical value of 1.

[0078] Output line I out and are held at ground. For a logical input value of 1, the potential applied to the input line reads a voltage V r corresponding to a value suitable for reading and much lower than the value that would cause a write interference fault.

[0079] The output is provided according to the current applied to the output line. The output current (e.g., the read current) is zero or equal to I r = G L V r respectively, within the limits of zero leakage current and zero series resistance of the channel transistor.

[0080] Figure 2 is a circuit diagram of the weight cell array 200 according to an embodiment. The weight cell array 200 includes weight cells 202 to weight cell 216. To perform inference with the weight cell array 200, the inputs to each row of weight cells are set according to the logical values of the corresponding neurons (i.e., the inputs to cells 202 to 208 and inputs and the inputs to cells 210 to 216 and inputs ). Then the output lines are read in parallel along each column of weight cells (i.e., output lines Iout1 to output line Iout4B), and the total current on the output is measured and divided by I r to obtain the product of the binary multiplication between the N input neurons and the N binary weights in a given column. Additionally, if the number of logical 1s in the input vector is known, then the dot product can be independently extracted from the current on the output lines. Thus the dot product is as in equation (1).

[0081] where M ≤ N (1)

[0082] Figure 3 is the graph 300 of the current output of the weight cell array 200 according to an embodiment. Referring to the weight cell array 200, each weight cell has a logical value. The weight cell 202 has a logical value of 1, the weight cell 204 has a logical value of 1, the weight cell 206 has a logical value of 0, the weight cell 208 has a logical value of 0, the weight cell 210 has a logical value of 1, the weight cell 212 has a logical value of 0, the weight cell 214 has a logical value of 1 and the weight cell 216 has a logical value of 0.

[0083] Referring to the graph 300, the currents read at the output of each column are different, indicating different values for different pairs of logical values along each column. The output at Iout1 is plotted at line 302, the outputs at Iout2 and Iout3 are plotted at line 304, and the output at Iout4 is plotted at line 306.

[0084] Writing to a given cell requires a separate step depending on whether the MTJ is written with a "down" current or an "up" current (the "down" current or "up" current is defined as the direction of the current relative to the weight cell). Table 2 shows the values for down writing, while Table 3 shows the values for up writing.

[0085] Table 2

[0086]

[0087] Down current writing is writing where the current flows from the top of the weight cell to the bottom of the weight cell. To write a down current, both V in and are fixed to the write voltage V w , the write voltage V W is large enough to write the potential of the MTJ, and then the output line of the MTJ to be written is held at ground while the output lines of the MTJs not to be written are raised to V w . In the array, the down write operation is performed row by row, where the V in and of the programmed row are set to V w , and all other V in and lines to each of the other rows are set to 0.

[0088] Table 3 shows the values for up writing.

[0089] Table 3

[0090]

[0091] Upward current writing is writing in which current flows from the bottom of the weight cell to the top of the weight cell. To write an upward current, I out and are both held at V w , and the input line of the MTJ to be written upward is set to ground while the other MTJ is set to V w . In the array, the upward write operation is performed column by column, where by setting I out and to V w and setting all other I out lines and lines corresponding to the remaining columns to 0 enables a given column for upward writing.

[0092] Other non-volatile memory technologies can be utilized to replace STT-MRAM, such as pulse code modulation (PCM), flash memory, ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), etc. The transistor can be alternatively implemented with a p-type field effect transistor. In the case of a PFET, all polarities are reversed for inference and writing.

[0093] Figure 4 is a block diagram of an electronic device 401 in a network environment 400 according to one embodiment. Refer to Figure 4, in a network environment 400, an electronic device 401 can communicate with an electronic device 402 via a first network 498 (e.g., a short-range wireless communication network), or communicate with an electronic device 404 or a server 408 via a second network 499 (e.g., a long-range wireless communication network). The electronic device 401 can communicate with the electronic device 404 via the server 408. The electronic device 401 can include a processor 420, a memory 430, an input device 450, a sound output device 455, a display device 460, an audio module 470, a sensor module 476, an interface 477, a haptic module 479, a camera module 480, a power management module 488, a battery 489, a communication module 490, a subscriber identification module (SIM) 496, or an antenna module 497. At least one of the components can be omitted from the electronic device 401 (e.g., the display device 460 or the camera module 480), or one or more other components can be added to the electronic device 401. Some of the components can be implemented as a single integrated circuit (IC). For example, the sensor module 476 (e.g., a fingerprint sensor, an iris sensor, or an illuminance sensor) can be embedded in the display device 460 (e.g., a display).

[0094] The processor 420 can execute software (e.g., a program 440) to control at least one other component (e.g., a hardware or software component) of the electronic device 401 coupled to the processor 420, and can perform various data processing or calculations. As at least part of the data processing or calculations, the processor 420 can load commands or data received from another component (e.g., the sensor module 476 or the communication module 490) in the volatile memory 432, process the commands or data stored in the volatile memory 432, and store the resulting data in the non-volatile memory 434. The processor 420 can include a main processor 421 (e.g., a central processing unit (CPU) or an application processor (AP)) and an auxiliary processor 423 (e.g., a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)) that can operate independently of the main processor 421 or in combination with the main processor 421. Additionally or alternatively, the auxiliary processor 423 can be adapted to consume less power than the main processor 421, or perform a specific function. The auxiliary processor 423 can be implemented separately from the main processor 421 or as part of the main processor 421.

[0095] When the main processor 421 is in an inactive (e.g., sleep) state, the auxiliary processor 423 may control at least some of the functions or states related to at least one of the components of the electronic device 401 (e.g., the display device 460, the sensor module 476, or the communication module 490) instead of the main processor 421, or when the main processor 421 is in an active state (e.g., executing an application), control at least some of the functions or states together with the main processor 421. The auxiliary processor 423 (e.g., an image signal processor or a communication processor) may be implemented as part of another component (e.g., the camera module 480 or the communication module 490) that is functionally related to the auxiliary processor 423.

[0096] The memory 430 may store various data used by at least one component of the electronic device 401 (e.g., the processor 420 or the sensor module 476). The various data may include, for example, software (e.g., the program 440) and input data or output data related to the commands of the software. The memory 430 may include a volatile memory 432 or a non-volatile memory 434.

[0097] The program 440 may be stored in the memory 430 as software and may include, for example, an operating system (OS) 442, middleware 444, or an application 446.

[0098] The input device 450 may receive commands or data to be used by other components of the electronic device 401 (e.g., the processor 420) from the outside of the electronic device 401 (e.g., a user). The input device 450 may include, for example, a microphone, a mouse, or a keyboard.

[0099] The sound output device 455 may output a sound signal to the outside of the electronic device 401. The sound output device 455 may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as playing multimedia or recording, and the receiver may be used for receiving incoming calls. The receiver may be implemented separately from the speaker or implemented as part of the speaker.

[0100] The display device 460 may visually provide information to the outside of the electronic device 401 (e.g., a user). The display device 460 may include, for example, a display, a hologram device, or a projector, and a control circuit for controlling the corresponding one of the display, the hologram device, and the projector. The display device 460 may include a touch circuit adapted to detect a touch or a sensor circuit (e.g., a pressure sensor) adapted to measure the intensity of a force caused by the touch.

[0101] The audio module 470 can convert sound into an electrical signal and vice versa. The audio module 470 can obtain sound via the input device 450, or output sound via the sound output device 455 or the headphones of an external electronic device 402 that is directly (e.g., wired) or wirelessly coupled to the electronic device 401.

[0102] The sensor module 476 can detect the operating state of the electronic device 401 (e.g., power or temperature) or the environmental state outside the electronic device 401 (e.g., the state of the user), and then generate an electrical signal or data value corresponding to the detected state. The sensor module 476 can include, for example, a gesture sensor, a gyro sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0103] The interface 477 can support one or more specified protocols for the electronic device 401 that is to be directly (e.g., wired) or wirelessly coupled to an external electronic device 402. The interface 477 can include, for example, a high-definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.

[0104] The connection terminal 478 can include a connector through which the electronic device 401 can be physically connected to an external electronic device 402. The connection terminal 478 can include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0105] The haptic module 479 can convert an electrical signal into a mechanical stimulus (e.g., vibration or movement) or an electrical stimulus, which can be recognized by the user via a tactile sensation or a proprioceptive sensation. The haptic module 479 can include, for example, a motor, a piezoelectric element, or an electrical stimulator.

[0106] The camera module 480 can capture a still image or a moving image. The camera module 480 can include one or more lenses, an image sensor, an image signal processor, or a flash.

[0107] The power management module 488 can manage the power supplied to the electronic device 401. The power management module 488 can be implemented as at least part of, for example, a power management integrated circuit (PMIC).

[0108] The battery 489 can supply power to at least one component of the electronic device 401. The battery 489 can include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0109] The communication module 490 can support establishing a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device 401 and an external electronic device (e.g., the electronic device 402, the electronic device 404, or the server 408), and communicating via the established communication channel. The communication module 490 can include one or more communication processors, which can operate independently of the processor 420 (e.g., the AP) and support direct (e.g., wired) communication or wireless communication. The communication module 490 can include a wireless communication module 492 (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 494 (e.g., a local area network (LAN) communication module or a power line communication (PLC) module). A corresponding one of these communication modules can communicate with an external electronic device via a first network 498 (e.g., a short-range communication network, such as Bluetooth TM 、Wireless-Fidelity (Wi-Fi) Direct, or the Infrared Data Association (IrDA) standard) or a second network 499 (e.g., a long-range communication network, such as a cellular network, the Internet, or a computer network (e.g., a LAN or a wide area network (WAN))). These various types of communication modules can be implemented as a single component (e.g., a single IC), or can be implemented as multiple separate components (e.g., multiple ICs). The wireless communication module 492 can use the subscriber information (e.g., the international mobile subscriber identity (IMSI)) stored in the subscriber identification module 496 to identify and authenticate the electronic device 401 in a communication network (e.g., the first network 498 or the second network 499).

[0110] The antenna module 497 may transmit signals or power to the outside of the electronic device 401 (e.g., an external electronic device) or receive signals or power from the outside of the electronic device 401. The antenna module 497 may include one or more antennas, and may select at least one antenna suitable for a communication scheme in a communication network for, e.g., the first network 498 or the second network 499 from the one or more antennas. Then, signals or power may be transmitted or received between the communication module 490 and an external electronic device via the selected at least one antenna.

[0111] At least some of the above components may be coupled to each other and transmit signals (e.g., commands or data) therebetween via an inter-peripheral communication scheme (e.g., a bus, general purpose input and output (GPIO), serial peripheral interface (SPI), or mobile industry processor interface (MIPI)).

[0112] According to one embodiment, commands or data may be transmitted or received between the electronic device 401 and an external electronic device 404 via a server 408 coupled to the second network 499. Each of the electronic devices 402 and 404 may be a device of the same type or a different type from the electronic device 401. All or some of the operations to be performed at the electronic device 401 may be performed at one or more of the external electronic device 402, external electronic device 404, or external electronic device 408. For example, if the electronic device 401 should perform a function or service automatically or in response to a request from a user or another device, then the electronic device 401 may, instead of performing the function or service, or in addition to performing the function or service, request one or more external electronic devices to perform at least part of the function or service. The one or more external electronic devices that receive the request may perform at least part of the requested function or service or additional functions or additional services related to the request, and transmit the results of the performance to the electronic device 401. The electronic device 401 may provide the results (with or without further processing the results) as at least part of a reply to the request. To this end, for example, cloud computing, distributed computing, or client-server computing technologies may be used.

[0113] One embodiment can be implemented as software (e.g., program 440) that includes one or more instructions stored in a storage medium (e.g., internal memory 436 or external memory 438), which can be read by a machine (e.g., electronic device 401). For example, a processor of the electronic device 401 can invoke at least one of the one or more instructions stored in the storage medium and execute at least one of the one or more instructions with or without using one or more other components under the control of the processor. Thus, the machine can be operated to perform at least one function according to the at least one invoked instruction. The one or more instructions can include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium can be provided in the form of a non-transitory storage medium. The term "non-transitory" indicates that the storage medium is a tangible device and does not include signals (e.g., electromagnetic waves), but this term does not distinguish between storing data semi-permanently in the storage medium and storing data temporarily in the storage medium.

[0114] According to one embodiment, the method of the present disclosure can be included and provided in a computer program product. The computer program product can be traded between a seller and a buyer as a product. The computer program product can be distributed in the form of a machine-readable storage medium (e.g., compact disc read only memory; CD-ROM), or distributed online (e.g., downloaded or uploaded) via an application store (e.g., Play Store TM ) or directly between two user devices (e.g., smartphones). If distributed online, at least part of the computer program product can be generated temporarily or stored at least temporarily in a machine-readable storage medium, such as the memory of a manufacturer's server, the server of an application store, or a relay server.

[0115] According to one embodiment, each of the above components (e.g., a module or a program) can include a single entity or multiple entities. One or more of the above components can be omitted, or one or more other components can be added. Alternatively or additionally, multiple components (e.g., modules or programs) can be integrated into a single component. In this case, the integrated component can still perform the one or more functions in the same or similar manner as each of the multiple components before integration by the corresponding one of the multiple components. The operations performed by a module, a program, or another component can be implemented sequentially, in parallel, repeatedly, or heuristically, or one or more of the operations can be executed in a different order or omitted, or one or more other operations can be added.

[0116] Although certain embodiments of the present disclosure have been described in the detailed description of the present disclosure, the present disclosure can be modified in various forms without departing from the scope of the present disclosure. Therefore, the scope of the present disclosure should not be determined only based on the described embodiments, but should be determined based on the appended claims and their equivalents.

Claims

1. A weight unit, comprising: a first field effect transistor and a first resistive memory element, the first resistive memory element being connected to the drain of the first field effect transistor; and a second field effect transistor and a second resistive memory element, the second resistive memory element being connected to the drain of the second field effect transistor, wherein the drain of the first field effect transistor is connected to the gate of the second field effect transistor, and the drain of the second field effect transistor is connected to the gate of the first field effect transistor, and wherein the weight unit generates a logic value based on the conductance of the first resistive memory element and the conductance of the second resistive memory element.

2. The weight unit according to claim 1, wherein the first field effect transistor and the second field effect transistor comprise n-type field effect transistors.

3. The weight unit according to claim 1, wherein the first field effect transistor and the second field effect transistor comprise p-type field effect transistors.

4. The weight unit according to claim 1, wherein the first resistive memory element and the second resistive memory element comprise magnetic tunnel junctions.

5. The weight unit according to claim 1, wherein the first resistive memory element and the second resistive memory element comprise resistive random access memory elements.

6. The weight unit according to claim 1, wherein the first resistive memory element and the second resistive memory element comprise ferroelectric random access memory elements.

7. The weight unit according to claim 1, wherein the first resistive memory element and the second resistive memory element comprise pulse code modulation memory elements.

8. The weight unit according to claim 1, further comprising a first external connection to the source of the first field effect transistor and a second external connection to the source of the second field effect transistor.

9. The weight unit according to claim 8, further comprising a third external connection to the lead of the first resistive memory element and a fourth external connection to the lead of the second resistive memory element.

10. The weight unit according to claim 1, further comprising a first external connection to the lead of the first resistive memory element and a second external connection to the lead of the second resistive memory element.

11. The weight unit according to claim 10, further comprising a third external connection to the source of the first field effect transistor and a fourth external connection to the source of the second field effect transistor.

12. An electronic device, comprising: an array of weight units, each weight unit comprising: a first field effect transistor and a first resistive memory element, the first resistive memory element being connected to the drain of the first field effect transistor; and A second field-effect transistor and a second resistive memory element, the second resistive memory element being connected to the drain of the second field-effect transistor, the drain of the first field-effect transistor being connected to the gate of the second field-effect transistor, and the drain of the second field-effect transistor being connected to the gate of the first field-effect transistor; and a processor configured to perform inference using the weight cell array by: setting an input to a row of weight cells in the weight cell array according to a logic value of a corresponding neuron; and reading an output of a column of weight cells in the weight cell array.

13. The electronic device according to claim 12, wherein the processor is further configured to perform inference by measuring a total current from the output of the read column of weight cells and dividing the total current by an output current.

14. The electronic device according to claim 12, wherein the first resistive memory element and the second resistive memory element comprise magnetic tunnel junctions.

15. The electronic device according to claim 12, wherein the first field-effect transistor and the second field-effect transistor comprise n-type field-effect transistors.

16. An electronic device, comprising: a weight cell array, each weight cell comprising: a first field-effect transistor and a first resistive memory element, the first resistive memory element being connected to the drain of the first field-effect transistor; and a second field-effect transistor and a second resistive memory element, the second resistive memory element being connected to the drain of the second field-effect transistor, the drain of the first field-effect transistor being connected to the gate of the second field-effect transistor, and the drain of the second field-effect transistor being connected to the gate of the first field-effect transistor; and a processor configured to write to the first resistive memory element and the second resistive memory element according to directions of currents supplied to the first resistive memory element and the second resistive memory element.

17. The electronic device according to claim 16, wherein the processor is configured to write to the first resistive memory element and the second resistive memory element by fixing a voltage input to the weight cell to a write voltage when the direction of the current is downward.

18. The electronic device according to claim 16, wherein the processor is configured to write to the first resistive memory element and the second resistive memory element by holding a current output from the weight cell to a write voltage when the direction of the current is upward.

19. The electronic device according to claim 16, wherein the first resistive memory element and the second resistive memory element comprise magnetic tunnel junctions.

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