Full adder, chip, and computing device

Abstract

The present invention relates to a full adder, a chip, and a computing device. A full adder is disclosed, including: a plurality of primary logic units and at least one secondary logic unit, wherein the output end of each primary logic unit is connected to the input end of the first secondary logic unit in the at least one secondary logic unit. The plurality of primary logic units include: a first primary logic unit, a second primary logic unit, and a third primary logic unit, which are respectively configured to generate a first intermediate signal M, a second intermediate signal N, and a carry-related signal C based on a first input signal A, a second input signal B, and a carry input signal C input to the full adder in Furthermore, the first secondary logic unit is configured to generate a sum output signal SUM of the full adder based on the first intermediate signal M, the second intermediate signal N, and the carry-related signal C.

Description

Technical Field

[0001] The present disclosure generally relates to full adders. Specifically, it relates to a full adder for improving balance, a chip including the full adder, and a computing device including the chip. Background Art

[0002] A full-adder is a binary addition circuit capable of calculating a carry from a lower bit. Compared with a half-adder, a full-adder not only considers whether there is a carry in the calculation result of the current bit, but also considers the carry from the previous bit to the current bit. Cascading multiple one-bit full adders can obtain a multi-bit full adder. Hereinafter, unless otherwise specified, the full adder refers to a one-bit full adder.

[0003] Figure 1A A schematic diagram of a full adder is shown. Generally speaking, a full adder can be implemented by an electronic circuit with three inputs and two outputs. Among them, on the input side, A and B represent two addends, and C in represents the carry number from the adjacent lower bit. Correspondingly, on the output side, SUM represents the sum of the current bit, and C out represents the carry number to the adjacent higher bit.

[0004] Figure 1B A truth table of the full adder is shown. As Figure 1B shown, when the number of numbers with a logical value of "1" in A, B, and C in on the input side is odd, the value of SUM will be "1". Otherwise, the value of SUM will be "0". In addition, when the number of numbers with a logical value of "1" in A, B, and C in on the input side exceeds 1, the value of C out will be "1", otherwise, the value of C out will be "0".

[0005] Typical sum logic expressions and carry logic expressions in a full adder are as follows:

[0006]

[0007] C out = AB+(A + B)C in (2-1).

[0008] Among them, the typical carry logic expression (2-1) can also be expressed as:

[0009]

[0010] As a basic logic circuit, the full adder is widely used in various electronic devices. For a full adder, improving balance and reducing glitches are important challenges. Therefore, there is a need for new technologies. Summary of the Invention

[0011] According to one aspect of the present disclosure, there is provided a full adder, including: a plurality of primary logic units and at least one secondary logic unit, wherein the output end of each primary logic unit is connected to the input end of the first secondary logic unit in the at least one secondary logic unit. The plurality of primary logic units include: a first primary logic unit configured to generate a first intermediate signal M based on a first input signal A, a second input signal B, and a carry input signal C input to the full adder; a second primary logic unit configured to generate a second intermediate signal N based on the first input signal A, the second input signal B, and the carry input signal C; and a third primary logic unit configured to generate a carry-related signal C based on the first input signal A, the second input signal B, and the carry input signal C. In addition, the first secondary logic unit is configured to generate a sum output signal SUM of the full adder based on the first intermediate signal M, the second intermediate signal N, and the carry-related signal C. in generate a first intermediate signal M; a second primary logic unit configured to generate a second intermediate signal N based on the first input signal A, the second input signal B, and the carry input signal C in generate a second intermediate signal N; and a third primary logic unit configured to generate a carry-related signal C based on the first input signal A, the second input signal B, and the carry input signal C in generate a carry-related signal C. In addition, the first secondary logic unit is configured to generate a sum output signal SUM of the full adder based on the first intermediate signal M, the second intermediate signal N, and the carry-related signal C.

[0012] According to another aspect of the present disclosure, there is provided a chip including the full adder as described above.

[0013] According to still another aspect of the present disclosure, there is provided a computing device including the chip as described above.

[0014] Other features and advantages of the present disclosure will become clearer through the following detailed description of the exemplary embodiments of the present disclosure with reference to the accompanying drawings. Brief Description of the Drawings

[0015] The drawings forming a part of the specification depict embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure.

[0016] Referring to the accompanying drawings, the present disclosure can be more clearly understood from the following detailed description, wherein:

[0017] Figure 1A A schematic diagram of a full adder is shown.

[0018] Figure 1B A truth table of the full adder is shown.

[0019] Figure 2 A logic circuit diagram of an implementation of a prior art full adder is shown.

[0020] Figure 3Shows a logic circuit diagram of another implementation of a full adder in the prior art.

[0021] Figure 4 Shows a circuit diagram of yet another implementation of a full adder in the prior art.

[0022] Figure 5 Shows a schematic diagram of a full adder according to one or more exemplary embodiments of the present disclosure.

[0023] Figure 6 Shows a schematic diagram of a full adder according to the first embodiment of the present disclosure.

[0024] Figure 7 Shows a schematic diagram of a full adder according to the second embodiment of the present disclosure.

[0025] Note that in the embodiments described below, sometimes the same reference numerals are used commonly between different drawings to denote the same parts or parts having the same functions, and their repeated descriptions are omitted. In some cases, similar reference numerals and letters are used to denote similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0026] For ease of understanding, the positions, sizes, ranges, etc. of the various structures shown in the drawings and the like sometimes do not represent the actual positions, sizes, ranges, etc. Therefore, the present disclosure is not limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like. Detailed Description of the Invention

[0027] The inventors of the present application have recognized that traditional full adders still face significant challenges in terms of balance.

[0028] Figure 2 Shows a logic circuit diagram of an implementation of a full adder in the prior art. This logic circuit is implemented based on the logical relationships in the above logical expressions (1-1) and (2-2).

[0029] As Figure 2 shown, the full adder 200 includes a first exclusive-OR gate XOR1, a second exclusive-OR gate XOR2, a first AND gate AND1, a second AND gate AND2, and a first OR gate OR1. Among them, signals A and B representing two addends are input to two input terminals of the first exclusive-OR gate XOR1, the output terminal of the first exclusive-OR gate XOR1 is connected to one input terminal of the second exclusive-OR gate XOR2, and a signal C in representing the carry digit from the adjacent lower bit is input to the other input terminal of the second exclusive-OR gate XOR2. Thus, a sum output signal SUM representing the sum is obtained at the output terminal of the second exclusive-OR gate XOR2.

[0030] In addition, signals A and B are input to two input terminals of the first AND gate AND1, and the output terminal of the first AND gate AND1 is connected to one input terminal of the first OR gate OR1; the output terminal of the first XOR gate XOR1 is connected to one input terminal of the second AND gate AND2, and signal C in is input to the other input terminal of the second AND gate AND2, and the output terminal of the second AND gate AND2 is connected to the other input terminal of the first OR gate OR1. Thus, a carry output signal C representing the carry to the adjacent higher bit is obtained at the output terminal of the first OR gate OR1 out .

[0031] Figure 3 Fig. shows a logic circuit diagram of another implementation of a full adder in the prior art

[0032] Figure 3 The main difference between the implementation shown in Figure 2 and the implementation shown in out is that the following variant of the above logical expressions (2-1) / (2-2) is used to obtain the carry output signal C out . Specifically, the carry C

[0033]

[0034] That is, when is satisfied, the logical value of C out depends on C in , otherwise, the logical value of C out depends on A

[0035] As Figure 3 shown, the full adder 300 includes a first XOR gate XOR1, a second XOR gate XOR2, and a multiplexer MUX

[0036] Based on the same logical expression (1-1), Figure 3 the implementation of the summation logic operation shown in Figure 2 is basically the same as that shown in

[0037] and will not be described again here in In addition, signal A and signal C out are respectively input to two channel input terminals of the multiplexer MUX, and the output terminal of the first XOR gate XOR1 is connected to the channel selection terminal of the multiplexer MUX. Thus, based on the logical expression (2-3), a carry output signal C representing the carry to the adjacent higher bit is obtained at the output terminal of the multiplexer MUX

[0038] The full adder of the prior art described above is implemented based on the typical sum logic expression (1-1) and carry logic expressions (2-1)-(2-3), and the design idea of the logic circuit is relatively simple.

[0039] However, the inventors of the present application have recognized that "glitches" are prevalent in the output signals obtained by these implementation methods. On the one hand, relative delays between the signals performing logical operations of "AND", "OR" or their combinations in the same logic cell may cause glitches. On the other hand, poor balance (delay is affected by input signals) of certain logic cells may also introduce glitches in subsequent processing. Moreover, the full adders in these implementation methods are also unbalanced as a whole, which is not conducive to cascaded arrangement.

[0040] For example, the exclusive-OR gate logic cells commonly used in these implementation methods are unbalanced, and the logical operations performed therein may generate glitches in the output signals.

[0041] The following will take the first exclusive-OR gate XOR1 as an example for analysis. Assume that the output signal of the first exclusive-OR gate XOR1 is S, then S satisfies the following logical relationship:

[0042]

[0043] Note that the signals performing logical operations of "AND", "OR" or their combinations in the first exclusive-OR gate XOR1 include both the signals A and B directly input to the first exclusive-OR gate XOR1 and the inverted signals after inverting the signals A and B Since an inverter is generally required to invert the signal, and the inverter will introduce a certain amount of delay, thus generating a relative delay between the signals A and B and the inverted signals For example, in some embodiments, the delay is on the order of about 100 ps. Generally speaking, the magnitude of this relative delay is not negligible for the logical operations in this unit and may disrupt the synchronization between the signals. Thus, the output signal S of the first exclusive-OR gate XOR1 may contain glitches. Additionally, based on the logical expression (3), it can be seen that the first exclusive-OR gate XOR1 itself is unbalanced, and the logic cells taking the output signal S of the first exclusive-OR gate XOR1 as the input signal may also generate glitches.

[0044] Therefore, the sum output signal SUM and the carry output signal C obtained by using exclusive-OR gate logic cells respectively based on the sum logic expression (1-1) and the carry logic expressions (2-2) / (2-3) out may both contain glitches.

[0045] That is, Figure 2 and Figure 3The full adder of the prior art shown in is unbalanced, and the sum output signal SUM and carry output signal C therein out may both contain glitches.

[0046] Moreover, based on a similar principle, the inverted output signal after inverting the output signal S will also possibly contain glitches. Among them, satisfies the following logical relationship:

[0047]

[0048] That is, the XNOR gate logic unit is unbalanced, and the logical operation performed therein may generate glitches in the output signal.

[0049] In addition, Figure 3 the multiplexer used in the full adder 300 shown in is also unbalanced, and the logical operation performed therein may also generate glitches in the output signal.

[0050] The following will take the multiplexer MUX as an example for analysis. The output signal C of the multiplexer MUX out satisfies the following logical relationship:

[0051]

[0052] According to the logical expression (2-4), the signals performing the logical operations of "AND", "OR" or their combination in the multiplexer MUX include both the signal S and the inverted signal after inverting the signal S As can be seen from the above analysis in combination with the XOR gate, there is a relative delay between the signal S and and the magnitude of this relative delay is not negligible for the logical operation in this unit, resulting in the output signal C of the multiplexer MUX out may contain glitches. Moreover, according to the logical expression (2-4), the multiplexer MUX itself is also unbalanced.

[0053] In addition, when the multiplexer MUX is used in the logic circuit of the full adder, the signal S is the output signal of the first XOR gate XOR1. As discussed above, the signal S and its inverted signal itself may contain glitches, which may further increase the glitches in the output signal C out therein.

[0054] Moreover, when the multiplexer MUX is used in the logic circuit of the full adder, the signal input to the channel selection terminal of the multiplexer MUX is the output signal S of the first XOR gate XOR1 with signals A and B as input signals, and the signal input to the channel input terminal of the multiplexer MUX is the signal A and the signal C in. That is, the input signals of the multiplexer MUX include both signals A and C in , and also include signal S obtained by performing an exclusive - OR operation on signals A and B. Since the exclusive - OR operation unit (here it is the first exclusive - OR gate XOR1) will introduce a certain amount of delay, so signal and signals A and C in have a relative delay. Generally speaking, the magnitude of this relative delay cannot be ignored for the logical operation of this logical operation unit, which may further increase the glitch in the output signal C out . In addition, the imbalance of the first exclusive - OR gate XOR1 will also increase the glitch in the output signal C out of the multiplexer MUX with S as the input signal.

[0055] Thus, the carry output signal C obtained by using an exclusive - OR gate and a multiplexer based on the carry - generating logic expression (2 - 4) out may also contain glitches.

[0056] Figure 4 shows the circuit diagram of another implementation of the full - adder in the prior art.

[0057] Figure 4 The main feature of the implementation shown in out is to use the carry output signal C out of the full - adder to obtain the sum output signal SUM of the full - adder. Specifically, the sum output signal SUM can also be expressed as:

[0058]

[0059] Figure 4 The full - adder in is implemented based on the logical relationships in the above - mentioned logical expressions (1 - 2) and (2 - 1).

[0060] Advantageously, Figure 4 the implementation of the full - adder shown in avoids using an exclusive - OR gate or a multiplexer MUX to obtain the sum output signal SUM and the carry output signal C out , thus avoiding the glitches introduced by the above - mentioned logical units.

[0061] However, the inventors of the present application recognize that there may still be glitches in the sum output signal SUM obtained by using the sum - generating logic expression (1 - 2).

[0062] Specifically, the input signal of this sum logical operation i' is obtained by performing a carry - generating logical operation on signals A, B, and C. That is, in the above - mentioned sum logical operation, the signals performing logical operations of "AND", "OR" or their combinations include both the input signals A, B, and C i', including input signals A, B, C in The signal obtained by performing carry logic operation Since the relevant logic operations will introduce a certain amount of delay, and input signals A, B, C in Generally speaking, the relative delay is not negligible for the logic operation and may destroy the synchronization of the signal, thereby possibly generating glitches in the output signal SUM.

[0063] Therefore, the inventor of the present application realizes that the traditional full adder may have certain deficiencies in balance and the output signal usually has burrs. It is expected to improve the balance of the full adder and reduce the burrs, so an improved full adder is needed.

[0064] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure.

[0065] The following description of at least one exemplary embodiment is in fact merely illustrative and is in no way intended to limit the present disclosure and its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in the present disclosure. However, those skilled in the art will appreciate that they merely illustrate exemplary ways of the present disclosure that can be implemented, rather than exhaustive ways. In addition, the drawings need not be drawn to scale, and some features may be enlarged to illustrate the details of specific components.

[0066] Technologies, methods, and apparatus known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, such technologies, methods, and apparatus should be considered part of the authorization specification.

[0067] In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0068] Figure 5 A schematic diagram of a full adder 500 according to one or more exemplary embodiments of the present disclosure is shown.

[0069] like Figure 5 As shown, the full adder 500 includes a plurality of primary logic units and at least one secondary logic unit, wherein the output end of each primary logic unit is at least connected to the input end of the first secondary logic unit 521 in the at least one secondary logic unit.

[0070] In various embodiments, the plurality of primary logic units includes a first primary logic unit 511. Among them, the first primary logic unit 511 is configured to be based on a first input signal A, a second input signal B, and a carry input signal C input to the full adder 500 in to generate a first intermediate signal M.

[0071] The plurality of primary logic units further includes a second primary logic unit 512. Among them, the second primary logic unit 512 is configured to be based on the first input signal A, the second input signal B, and the carry input signal C in to generate a second intermediate signal N.

[0072] In addition, the plurality of primary logic units further includes a third primary logic unit 513. Among them, the third primary logic unit 513 is configured to be based on the first input signal A, the second input signal B, and the carry input signal C in to generate a carry-related signal C.

[0073] In various embodiments, a first secondary logic unit 521 is configured to generate a sum output signal SUM of the full adder 500 based on the first intermediate signal M, the second intermediate signal N, and the carry-related signal C.

[0074] In some embodiments, as needed, the at least one secondary logic unit further includes a second secondary logic unit 522.

[0075] As Figure 5 shown, the output end of the third primary logic unit 513 is connected to the input end of the second secondary logic unit 522.

[0076] The second secondary logic unit 522 is configured to generate a carry output signal C of the full adder 500 based on the carry-related signal C out .

[0077] Alternatively, in some embodiments, the carry-related signal C is directly output as the carry output signal C of the full adder 500 out .

[0078] If the logical relationships between the first intermediate signal M, the second intermediate signal N, and the carry-related signal C with respect to the first input signal A, the second input signal B, and the carry input signal C are represented by F11, F12, and F13 respectively in , then the logical operations performed by the first primary logic unit 511, the second primary logic unit 512, and the third primary logic unit 513 can be respectively expressed as:

[0079] M = F11(A, B, C in ) (5-1);

[0080] N = F12(A, B, C in ) (6 - 1);

[0081] C = F13(A, B, C in ) (7 - 1).

[0082] Correspondingly, if the logical relationship between the sum output signal SUM and the first intermediate signal M, the second intermediate signal N, and the carry - related signal C is represented by F21, then the logical operation performed by the first - stage logic unit can be expressed as:

[0083] SUM = F21(M, N, C) (8 - 1).

[0084] Thus, in various embodiments of the present invention, by means of the carry output signal or its related signal C, the sum logical expression of the full - adder 500 can be derived as expression (8 - 1), so as to perform logical operations on the input signals A, B, C in and the intermediate signals M, N, C respectively in two - stage logic units arranged in sequence. Since the intermediate signals M, N, C have a delay introduced due to undergoing logical operations with respect to the input signals A, B, C in , this arrangement of two - stage logic units advantageously avoids performing logical operations such as "AND", "OR" or their combinations on the input signals A, B, C in and the intermediate signals M, N, C in the same logic unit, thereby reducing the glitches in the sum output signal SUM.

[0085] Preferably, in some embodiments, the logical relationship between the output signal of each primary logic unit or the inverted output signal obtained by inverting the output signal with respect to the input signal of the primary logic unit can be represented by a logical expression including only one or both of the basic logical operators "AND" and "OR".

[0086] For example, one of M or in it, one of N or in it, one of C or in it with respect to A, B, C in can be represented by a logical expression including only one or both of the basic logical operators "AND" and "OR".

[0087] Thus, according to the logical operation laws, the signals performing logical operations such as "AND", "OR" or their combinations in each primary logic unit exclusively include each input signal input to the primary logic unit or the inverted input signal obtained by inverting each input signal.

[0088] For example, in some embodiments, the signals performing logical operations such as "AND", "OR" or their combinations in each primary logic unit are the input signals A, B, Cin 。

[0089] Alternatively, in some embodiments, the signals for performing logical operations of "AND", "OR", or a combination thereof in each primary logic unit are inverted input signals

[0090] Advantageously, compared to logic units such as exclusive - OR gates or multiplexers used in the prior art, the primary logic units in these embodiments can be balanced by themselves, and the logical operations performed therein may not generate glitches

[0091] In some embodiments, the input signals A, B, C in are synchronous. That is, the input signals of the primary logic units in these embodiments are synchronous

[0092] Therefore, in some embodiments, the intermediate signals output by each primary logic unit may not contain glitches

[0093] Advantageously, the carry - output signal C out may not contain glitches

[0094] Preferably, in some embodiments, the logical relationship between the output signal of the first - stage logic unit or the inverted output signal obtained by inverting the output signal with respect to the input signals of the first - stage logic unit can be represented by a logical expression including only one or both of the basic logical operators "AND" and "OR"

[0095] For example, the logical relationship between SUM or one of them with respect to M, N, C can be represented by a logical expression including only one or both of the basic logical operators "AND" and "OR"

[0096] Thus, according to the laws of logical operations, the signals for performing logical operations of "AND", "OR", or a combination thereof in the first - stage logic unit exclusively include the intermediate signals input to the first - stage logic unit or the inverted intermediate signals obtained by inverting each of the intermediate signals

[0097] For example, in some embodiments, the signals for performing logical operations of "AND", "OR", or a combination thereof in the first - stage logic unit are the intermediate signals M, N, C

[0098] Alternatively, in some embodiments, the signals for performing logical operations of "AND", "OR", or a combination thereof in the first - stage logic unit are inverted input signals

[0099] Advantageously, compared with logic units such as exclusive - OR gates or multiplexers used in the prior art, the first - stage secondary logic units in these embodiments can be balanced, and the logical operations performed therein may not generate glitches per se.

[0100] Preferably, in some embodiments, the first intermediate signal M, the second intermediate signal N, and the carry - related signal C are synchronous in time. That is, the input signals of the first - stage secondary logic units in these embodiments are synchronous in time.

[0101] Therefore, in some embodiments, the sum output signal output by the first - stage secondary logic unit may not contain glitches.

[0102] Alternatively, in some embodiments, at least a part of the first intermediate signal M, the second intermediate signal N, and the carry - related signal C are synchronous in time.

[0103] For example, in some embodiments, the first intermediate signal M and the second intermediate signal N are synchronous in time.

[0104] In addition, in some embodiments, the first intermediate signal M, the second intermediate signal N, and the carry - related signal C are substantially synchronous in time.

[0105] Those skilled in the art can easily understand that two or more signals being substantially synchronous in time means that the delay between these signals is negligible relative to the logical operation time of these signals. Thus, the corresponding glitches will not have a significant impact on the quality of the output signal.

[0106] Optionally, in some embodiments, the full - adder 500 further includes a delay component (not shown). This delay component is used to make the first intermediate signal M, the second intermediate signal N, and the carry - related signal C synchronous in time.

[0107] As analyzed in detail above, the full - adder 500 according to one or more embodiments of the present invention reduces the glitches in the output signal and improves the balance of the full - adder 500 in the following aspects.

[0108] First, by means of the carry - out signal or its related signal C, the input signals A, B, C in are respectively subjected to logical operations with the intermediate signals M, N, C in two - stage logic units (primary logic unit and secondary logic unit) arranged in sequence.

[0109] Second, each primary logic unit and the first - stage secondary logic unit are required to meet the following requirements: the logical relationship between the output signal of the logic unit or the inverted output signal obtained by inverting the output signal with respect to the input signal of the logic unit can be represented by a logical expression including only one or both of the basic logical operators "AND" and "OR".

[0110] Thus, the signals for performing logic operations of "AND", "OR", or a combination thereof in this logic unit exclusively include each signal input to this logic unit or the inverted signals obtained by inverting each of these signals.

[0111] The above two aspects can advantageously improve the balance of each primary logic unit and the first secondary logic unit, thereby improving the balance of the full adder 500, and the logic operations performed in each primary logic unit and the first secondary logic unit themselves may not generate glitches.

[0112] Finally, each signal input to the same logic unit is synchronized or substantially synchronized in time. Among them, if each of the signals A, B, C input to the same primary logic unit in is synchronized, the intermediate signals output by each primary logic unit may not include glitches. Correspondingly, the output signal C of the second secondary logic unit out may not include glitches.

[0113] Preferably, in some embodiments, each of the intermediate signals M, N input to the first secondary logic unit is synchronized or substantially synchronized in time with C. Thus, the output signal SUM of the first secondary logic unit may not include or substantially not include glitches.

[0114] Figure 6 FIG. shows a schematic diagram of a full adder 600 according to a first embodiment of the present disclosure.

[0115] As Figure 6 shown, the full adder 600 includes a first primary logic unit 611, a second primary logic unit 612, a third primary logic unit 613, and a first secondary logic unit 621.

[0116] Among them, the output terminals of each of the primary logic units 611, 612, 613 are connected to the input terminal of the first secondary logic unit 621.

[0117] In addition, the full adder 600 further includes a second secondary logic unit 622.

[0118] Among them, the output terminal of the third primary logic unit 613 is connected to the input terminal of the second secondary logic unit 622.

[0119] In the first embodiment, as Figure 6 shown, the logic operation performed by the first primary logic unit 611 can be expressed as:

[0120] M = ABC in (5-2);

[0121] The logic operation performed by the second primary logic unit 612 can be expressed as:

[0122] N = A + B + C in (6 - 2); and

[0123] The logical operation performed by the third primary logic unit 613 can be expressed as:

[0124]

[0125] On this basis, the logical operation performed by the first secondary logic unit 621 can be expressed as:

[0126] SUM = M + NC (8 - 2).

[0127] Moreover, the logical operation performed by the second secondary logic unit 622 can be expressed as:

[0128]

[0129] In some embodiments, the second secondary logic unit 622 can be an inverter.

[0130] Compared with the full adder of the prior art, the full adder 600 according to this embodiment can advantageously reduce the glitches in the output sum signal SUM and carry signal C out and improve the balance of the full adder.

[0131] First, by means of the inverted signal C of the carry output signal C out , the full adder 600 performs logical operations on the input signals A, B, C in and the intermediate signals M, N, C in the sequentially arranged primary logic units 611, 612, 613 and secondary logic units 621, 622 respectively. Advantageously, this arrangement of two - stage logic units avoids performing logical operations of "AND", "OR" or their combinations on the input signals A, B, C in and the intermediate signals M, N, C in the same logic unit.

[0132] Second, as shown in the logical expressions (5 - 2)-(7 - 2), the logical relationships of the intermediate signals or inverted intermediate signals M, N of the full adder 600 with respect to the input signals A, B, C in can be represented by logical expressions including only one or both of the basic logical operators "AND" and "OR".

[0133] Similarly, as shown in the logical expression (8 - 2), the logical relationship of the sum output signal SUM output by the first secondary logic unit 621 of the full adder 600 with respect to the input intermediate signals M, N, C can be represented by a logical expression including only one or both of the basic logical operators "AND" and "OR".

[0134] In addition, as shown in the logical expression (9), the second secondary logic unit 622 of the full adder 600 only inverts the intermediate signal C.

[0135] Therefore, each of the primary / secondary logic units in the full adder 600 according to the present embodiment is balanced, and the full adder 600 as a whole is also balanced. Moreover, the logical operations performed in each of the primary / secondary logic units may not generate glitches.

[0136] In some embodiments, the input signals A, B, C in are synchronous. Therefore, in some embodiments, the intermediate signals M, N, C output by each of the primary logic units 611, 612, 613 may not contain glitches.

[0137] Therefore, the carry output signal C of the full adder 600 according to the present embodiment out may not contain glitches.

[0138] By comparing the logical expressions (5-2)-(7-2) of the primary logic units 611, 612, 613, it can be seen that the intermediate signal M and the intermediate signal N may be synchronous in time. Relatively, there may be a small amount of delay between the intermediate signals M, N and the intermediate signal C.

[0139] In some embodiments, the delay between the intermediate signals M, N and the intermediate signal C may be on the order of 10 ps.

[0140] Thus, it can be considered that the intermediate signals M, N and the intermediate signal C are substantially synchronous in time.

[0141] Therefore, the sum output signal SUM of the full adder 600 according to the present embodiment can substantially not contain glitches.

[0142] Optionally, in some embodiments, delay control may be performed on some of the signals among the intermediate signals M, N and C to make them synchronous in time.

[0143] Figure 7 FIG. shows a schematic diagram of a full adder 700 according to a second embodiment of the present disclosure.

[0144] As Figure 7 shown, the full adder 700 includes a first primary logic unit 711, a second primary logic unit 712, a third primary logic unit 713, and a first secondary logic unit 721.

[0145] Among them, the output terminals of each of the primary logic units 711, 712, 713 are connected to the input terminal of the first secondary logic unit 721.

[0146] In the second embodiment, asFigure 7 As shown, the logical operation performed by the first primary logic unit 711 can be expressed as:

[0147]

[0148] The logical operation performed by the second primary logic unit 712 can be expressed as:

[0149] And

[0150] The logical operation performed by the third primary logic unit 713 can be expressed as:

[0151] C = AB+(A + B)C in (7 - 3).

[0152] On this basis, the logical operation performed by the first secondary logic unit 721 can be expressed as:

[0153]

[0154] Moreover, as shown in FIG. 7, in the second embodiment, the intermediate signal C output by the third primary logic unit 713 is directly output as the carry output signal C of the full adder 700 out .

[0155] Compared with the full adder of the prior art, the full adder 700 according to this embodiment can also advantageously reduce the glitches in the output sum signal SUM and carry signal C out and improve the balance of the full adder.

[0156] First, by means of the carry output signal C out , the full adder 700 performs logical operations on the input signals A, B, C in and the intermediate signals M, N, C in the sequentially arranged primary logic units 711, 712, 713 and secondary logic unit 721 respectively. Advantageously, this arrangement of two - stage logic units avoids performing logical operations of "AND", "OR" or their combinations between the input signals A, B, C in and the intermediate signals M, N, C in the same logic unit.

[0157] Second, as shown in the logical expressions (5 - 3)-(7 - 3), the logical relationship of the intermediate signal or inverted intermediate signal C of the full adder 700 with respect to the input signals A, B, C in can be represented by a logical expression including only one or both of the basic logical operators "AND" and "OR".

[0158] Similarly, as shown in the logical expression (8-3), the inverted signal of the sum output signal SUM output by the first secondary logic unit 721 of the full adder 700 The logical relationship with respect to the input intermediate signals M, N, C can be represented by a logical expression including only one or both of the basic logical operators "AND" and "OR".

[0159] Therefore, each primary / secondary logic unit in the full adder 700 according to this embodiment is balanced itself, and the full adder 700 as a whole is also balanced. Moreover, the logical operations performed in each primary / secondary logic unit itself may not generate glitches.

[0160] In some embodiments, the input signals A, B, C in are synchronous. Therefore, in some embodiments, the intermediate signals M, N, C output by each primary logic unit 711, 712, 713 may not contain glitches.

[0161] Therefore, the carry output signal C of the full adder 700 according to this embodiment out may not contain glitches.

[0162] By comparing the logical expressions (5-3)-(7-3) of the primary logic units 711, 712, 713, it can be seen that the intermediate signal M and the intermediate signal N may be synchronous in time. Relatively, there may be a small amount of delay between the intermediate signals M, N and the intermediate signal C.

[0163] In some embodiments, the delay between the intermediate signals M, N and the intermediate signal C may be on the order of 10 ps.

[0164] Thus, it can be considered that the intermediate signals M, N and the intermediate signal C are substantially synchronous in time.

[0165] Therefore, the sum output signal SUM of the full adder 700 according to this embodiment can be substantially free of glitches.

[0166] Optionally, in some embodiments, delay control can be performed on some of the signals among the intermediate signals M, N and C to make them synchronous in time.

[0167] In addition, compared with the full adder 600 according to the first embodiment, the full adder 700 according to this embodiment can further reduce the glitches in the output signal and reduce the occupied area of the device.

[0168] Such as Figure 4As shown in the circuit diagram, logic units are typically implemented in the form of NAND or NOR rather than AND or OR. Thus, compared to the circuits in the primary logic units 611 and 612 in the full adder 600 for implementing the logic operation (5-2)-(6-2), the circuits in the primary logic units 711 and 712 in the full adder 700 for implementing the logic operation (5-3)-(6-3) are simpler. In some embodiments, additional inverters are required in the circuits of the primary logic units 611 and 612 in the full adder 600, which increases the relative delay between the intermediate signals M, N and the intermediate signal C and increases the occupied area for arranging the inverters.

[0169] In addition, the full adder 600 also needs to use an inverter 622 to obtain the intermediate signal C and the carry output signal C out both, thereby further increasing the occupied area for arranging the inverter.

[0170] It should be noted that in some embodiments, the circuits for implementing the logic operation (7-3) in the full adder 700 and the circuits for implementing the logic operation (7-2) in the full adder 600 can both adopt common logic units for obtaining the carry output signal, and they have little difference in size and operation time.

[0171] In summary, the full adder 700 according to this embodiment can further reduce the glitches in the output signal and reduce the occupied area of the device compared to the full adder 600 according to the first embodiment.

[0172] Those skilled in the art can easily understand that although the above two embodiments of the full adder are described herein, the full adder according to the present invention is not limited thereto, but can be adjusted as needed.

[0173] The full adder according to the present disclosure can be implemented in various appropriate ways such as software, hardware, or a combination of software and hardware.

[0174] In one implementation, a chip can include the full adder as described above. The chip can also be included in a computing device.

[0175] The words "front", "rear", "top", "bottom", "above", "below", etc. in the specification and claims, if any, are used for descriptive purposes and do not necessarily describe an invariant relative position. It should be understood that such words are interchangeable under appropriate circumstances, so that the embodiments of the present disclosure described herein, for example, can operate in other orientations different from those shown or otherwise described herein.

[0176] As used herein, the term "exemplary" means "serving as an example, instance, or illustration" and not a "model" to be precisely copied. Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, the present disclosure is not limited by any theory expressed or implied in the foregoing technical field, background art, summary, or detailed description.

[0177] As used herein, the term "substantially" means including any minor variations caused by defects in design or manufacture, tolerances of devices or elements, environmental effects, and / or other factors. The term "substantially" also allows for differences from a perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in an actual implementation.

[0178] Additionally, the previous description may have referred to elements or nodes or features being "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connected" means that one element / node / feature is directly connected (or in direct communication) to another element / node / feature electrically, mechanically, logically, or otherwise. Similarly, unless otherwise expressly stated, "coupled" means that one element / node / feature can be connected to another element / node / feature directly or indirectly, mechanically, electrically, logically, or otherwise, to allow interaction, even if the two features may not be directly connected. That is, "coupled" is intended to encompass both direct and indirect connections of elements or other features, including connections using one or more intermediate elements.

[0179] Additionally, for reference purposes only, terms such as "first," "second," etc. may also be used herein and are not intended to be limiting. For example, unless the context clearly indicates otherwise, the terms "first," "second," and other such numerical terms referring to a structure or element do not imply an order or sequence.

[0180] It should also be understood that when the term "comprising / including" is used herein, it indicates the presence of the stated features, wholes, steps, operations, units, and / or components, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units, and / or components and / or combinations thereof.

[0181] In the present disclosure, the term "provide" is used broadly to encompass all ways of obtaining an object, so "providing an object" includes, but is not limited to, "purchasing," "preparing / manufacturing," "arranging / setting," "installing / assembling," and / or "ordering" the object, etc.

[0182] Those skilled in the art should be aware that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed among additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of a particular operation, and the order of operations can be changed in various other embodiments. However, other modifications, variations, and substitutions are also possible. Therefore, the present specification and the drawings should be regarded as illustrative rather than restrictive.

[0183] Although some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for illustration and not for limiting the scope of the present disclosure. The embodiments disclosed herein can be combined arbitrarily without departing from the spirit and scope of the present disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A full adder, characterized in that, Comprising: A plurality of primary logic units and at least one secondary logic unit, wherein the output terminal of each primary logic unit is at least connected to the input terminal of a first secondary logic unit among the at least one secondary logic unit. The plurality of primary logic units include: The first primary logic unit is configured to generate a first intermediate signal M based on a first input signal A, a second input signal B, and a carry input signal C input to the full adder in ; A second primary logic unit, configured to generate a second intermediate signal N based on a first input signal A, a second input signal B, and a carry input signal C in and A third primary logic unit, configured to generate a carry-related signal C based on a first input signal A, a second input signal B, and a carry input signal C in and The first secondary logic unit is configured to generate the sum output signal SUM of the full adder based on a first intermediate signal M, a second intermediate signal N, and a carry-related signal C.

2. The full adder according to claim 1, wherein The logical relationship between the output signal of each primary logic unit or the inverted output signal obtained by inverting the output signal with respect to the input signal of the primary logic unit can be represented by a logical expression including only one or both of the basic logical operators "AND" and "OR".

3. The full adder according to claim 1, wherein The logical relationship between the output signal of the first secondary logic unit or the inverted output signal obtained by inverting the output signal with respect to the input signal of the first secondary logic unit can be represented by a logical expression including only one or both of the basic logical operators "AND" and "OR".

4. The full adder according to claim 1, characterized in that, Wherein at least a part of the signals among the first intermediate signal M, the second intermediate signal N, and the carry-related signal C are synchronous in time.

5. The full adder according to claim 1, characterized in that, It further includes a delay component for making the first intermediate signal M, the second intermediate signal N, and the carry-related signal C synchronous in time.

6. The full adder according to claim 1, wherein The at least one secondary logic unit further includes a second secondary logic unit. Wherein the output terminal of the third primary logic unit is connected to the input terminal of the second secondary logic unit, and The second secondary logic unit is configured to generate a carry output signal C of the full adder based on a carry-related signal C out .

7. The full adder according to claim 1, wherein The carry-related signal C is output as the carry output signal C of the full adder out .

8. The full adder according to claim 6, characterized in that, Wherein The logical operation performed by the first primary logic unit can be expressed as: M = ABC in ; The logical operation performed by the second primary logic unit can be expressed as: N = A + B + C in ; The logical operation performed by the third primary logic unit can be expressed as: and The logical operation performed by the first secondary logic unit can be expressed as: SUM = M + NC.

9. The full adder according to claim 6, characterized in that, Wherein The logical operation performed by the second secondary logic unit can be expressed as:

10. The full adder according to claim 7, characterized in that, Wherein The logical operation performed by the first primary logic unit can be expressed as: The logical operation performed by the second primary logic unit can be expressed as: The logical operation performed by the third primary logic unit can be expressed as: C = AB + (A + B)C in ; and The logical operation performed by the first secondary logic unit can be expressed as:

11. A chip, characterized in that, The chip includes the full adder according to any one of claims 1-10.

12. A computing device, characterized in that, The computing device includes the chip according to claim 11.

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