Systems and methods for selecting a clock

Abstract

Embodiments of the present disclosure relate to systems and methods for selecting a clock. According to one embodiment, a system includes a circuit equipped with an oscillator and a processing unit including a clock controller. The circuit equipped with the oscillator has an oscillator control circuit configured to be coupled to an external oscillator. The clock controller includes an interface circuit, a security circuit, and a detection block. The interface circuit is configured to exchange handshake signals with the oscillator control circuit. The security circuit is configured to receive an external oscillator clock signal and is configured to select the external oscillator clock signal as the system clock. The detection block is configured to detect a fault in the external oscillator clock signal. After a fault is detected, a different clock signal is selected as the system clock and the interface circuit is caused to interrupt the transmission of the external oscillator clock signal to the external oscillator.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to Italian Patent Application No. 102019000002967, filed on February 28, 2019, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] This description generally relates to processing systems and corresponding devices and methods, and more particularly, to systems and methods for selecting a clock. Background Art

[0004] Various emerging application scenarios, such as the Internet of Things (IoT) or the automotive field, have promoted an increased interest in microcontroller-based applications with radio frequency capabilities.

[0005] A certain degree of integration between the microcontroller and the radio frequency circuit, especially third-party intellectual property cores for radio frequency transceivers, is thus also desired in general-purpose products employing a microcontroller to ensure proper handling of these aspects, such as consumer products (e.g., household appliances such as televisions, refrigerators, washing machines, etc.). Therefore, more attention is paid to the shared functions between such RF circuits, especially between the radio frequency intellectual property core and the general-purpose microcontroller or system-on-chip (SoC).

[0006] In a processing unit for general applications, such as a microcontroller or a system-on-chip (SOC) (e.g., STM32 microcontroller), a crystal oscillator is provided inside or outside the microcontroller chip for stable and precise frequency generation. When the crystal oscillator is external, especially when embedded in a third-party IP (such as a radio frequency transceiver circuit), it is necessary to share the crystal oscillator coupled to the RF transceiver circuit. However, in the case of a failure or in the case of co-using resources between the RF transceiver circuit and the microcontroller, coupling the oscillator signal from the RF transceiver to the microcontroller for use as an external oscillator clock signal may pose problems in terms of the safe and stable execution of the microcontroller, resulting in a race condition that should be avoided. Summary of the Invention

[0007] According to one embodiment, a system includes: a circuit equipped with an oscillator, the circuit equipped with an oscillator including an oscillator control circuit configured to couple with an external oscillator, the oscillator control circuit being configured to cause the external oscillator to provide an external oscillator clock signal to the circuit equipped with an oscillator; a processing unit including a clock controller, the clock controller being configured to manage clock signals to select a system clock for the processing unit. The clock controller is coupled to the oscillator control circuit to receive the external oscillator clock signal and is configured to selectively provide the external oscillator clock signal as the system clock, and the clock controller includes: an interface circuit configured to exchange handshake signals with the oscillator control circuit to enable the external oscillator clock signal to be transmitted to the clock controller; a security circuit configured to receive the external oscillator clock signal and configured to select the external oscillator clock signal as the system clock; a detection block configured to detect a fault in the external oscillator clock signal and, after detecting the fault, issue a fault signal indicating the fault, wherein after the fault signal is issued, the security circuit is configured to select a different clock signal as the system clock and cause the interface circuit to interrupt the transmission of the external oscillator clock signal to the clock controller.

[0008] According to another embodiment, a method includes receiving an external oscillator clock signal from a circuit configured with an oscillator and selectively providing the external oscillator clock signal as a system clock; exchanging handshake signals between a clock controller and the circuit equipped with an oscillator to enable the external oscillator clock signal to be transmitted to the clock controller; receiving the external oscillator clock signal; detecting a fault in the received external oscillator clock signal; in response to detecting the fault, issuing a fault signal; and after the fault signal is issued, selecting a different clock signal as the system clock and operating on the handshake signal to interrupt the transmission of the external oscillator clock signal to the clock controller.

[0009] According to another embodiment, a system includes: a clock detection circuit having a clock input coupled to an external clock source, the clock detection circuit configured to determine the presence of an external clock signal at the clock input and assert an external clock presence signal when the external clock signal is present; a clock interface circuit having a clock ready input configured to be coupled to a clock ready output of the external clock source, the clock interface circuit including: a ready filter configured to assert a ready enable signal when the external clock signal is active and an external clock ready signal is asserted at the clock ready input for a first predetermined period; an interrupt generation circuit configured to generate an external clock fault interrupt signal when the external clock presence signal is deasserted; and a clock selection circuit configured to provide the external clock signal to a system clock output when both the external clock presence signal and the external clock ready signal are asserted, and configured to provide a different clock signal to the system clock output when the external clock presence signal is deasserted.

[0010] According to another embodiment, a method includes: detecting the presence of an external clock signal and detecting the presence of an external clock ready signal, the external clock ready signal indicating the availability of the external clock signal from an external clock generator; asserting a ready enable signal when both the external clock ready signal and the external clock signal are present for a first predetermined period; after asserting the ready enable signal, routing the external clock signal to a system clock output; asserting an external clock fault signal when the presence of the external clock signal is no longer detected; and when the external clock fault signal is asserted, routing a different clock signal to the system clock output and asserting an external clock fault interrupt signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0012] Figure 1 is a block diagram illustrating a system including a processing unit and another circuit coupled to a crystal oscillator;

[0013] Figure 2 illustrates a security system circuit implementation in one or more embodiments;

[0014] Figure 3 illustrates a control interface circuit implementation in one or more embodiments; and

[0015] Figure 4 illustrates Figure 3 the timing diagram of the signals shown in DETAILED DESCRIPTION

[0016] In the following description, one or more specific details are described in order to provide a deeper understanding of the exemplary embodiments of the present description. The embodiments may be obtained without one or more specific details, or by other methods, components, materials, etc. In other cases, known structures, materials, or operations are not described or explained in detail so that some aspects of the embodiments will not be obscured.

[0017] Reference to "an embodiment" or "an embodiment" in the framework of this description is intended to indicate that a particular configuration, structure, or characteristic related to that embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in an embodiment" may appear in one or more points of this description and do not necessarily refer to the same embodiment. Moreover, particular configurations, structures, or characteristics may be combined in any appropriate manner in one or more embodiments.

[0018] The reference signs used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0019] Embodiments relate to processing systems and corresponding apparatus and methods. The system may include a processing unit, and another circuit including an oscillator control circuit, the oscillator control circuit being coupled to an external oscillator. The oscillator control circuit is configured to control the external oscillator to provide an external oscillator clock signal to the other circuit, and the processing unit includes a clock controller configured to manage the clock signal to select a system clock for the processing unit.

[0020] One or more embodiments may be applied to a system including a microcontroller or a system-on-chip (SoC) device for general applications operating in association with a radio frequency transceiver, particularly for long range (LoRa) applications.

[0021] One or more embodiments may be directed to corresponding devices (e.g., consumer products, such as microcontroller-based consumer products, such as household appliances) and corresponding methods. Some embodiments advantageously provide secure and stable execution and avoid problems with concurrent use of shared clock signals. One or more embodiments provide improved system robustness while maintaining performance of applications in execution. One or more embodiments provide maximized resource sharing and avoid duplication of control logic, such as temporization counters.

[0022] Figure 1FIG. 0 illustrates a system 10 for sharing an oscillator clock signal between a processing unit and an oscillator-equipped circuit. The system 10 includes a circuit 12 coupled to a crystal oscillator 50, which is herein defined as the oscillator-equipped circuit. The crystal oscillator 50 is preferably external to the circuit 12. In the example herein, the circuit 12 is an RF transceiver for LoRa applications (such as the SX1262 from Semtech). The system 10 includes a processing unit 11, particularly a general-purpose application microcontroller 11, where only a clock controller 13 included in the microcontroller 11 is shown for illustrative purposes of the general-purpose application microcontroller 11. The clock controller is used to select a system clock system_clk to be transmitted to the core (e.g., central processing unit 30) of the microcontroller 11. Such a general-purpose application microcontroller 11 can be implemented by a STM32 general-purpose microcontroller. Generally, the oscillator-equipped circuit 12 can be third-party intellectual property with respect to the IP of the general-purpose microcontroller 11.

[0023] Preferably, the oscillator-equipped circuit 12 and the general-purpose application microcontroller 11 can be arranged on the same support of the circuit, particularly on the same PCB (printed circuit board), and thus the system 10 is arranged on this PCB.

[0024] The oscillator-equipped circuit 12 includes an external crystal oscillator controller 121, which is coupled to the external crystal oscillator 50. The oscillator-equipped circuit 12 includes an RF transmitter / receiver 122, which is configured to issue an external oscillator enable signal rf_xosc_en to the external crystal oscillator controller 121 so that the external crystal oscillator 50 can be used as the clock signal of the oscillator-equipped circuit 12.

[0025] The clock controller 13 is configured to interact with the crystal oscillator source (i.e., the external crystal oscillator controller 121). The clock controller 13 controls the oscillator 50 through a security activation block 131 that implements a handshake control interface 131. The security activation block 131 supplies an enable signal xosc_en to the external crystal oscillator controller 121 and in turn receives a ready signal xosc_ready from a delay section 121a, which may include a delay counter.

[0026] The external crystal oscillator controller 121 is coupled to the crystal oscillator 50 to generate an external oscillator clock signal xosc_clk. The signal xosc_clk is the output from the crystal oscillator after a delay time. The clock controller 13 then includes a security system circuit 132, which receives the external oscillator clock signal xosc_clk and the external oscillator ready signal xosc_ready and is configured to select such signals as the system clock sys_clk.

[0027] The security system circuit 132 also receives a security enable signal css_on from the programming interface 133 of the clock controller 13 to activate such security system circuit 132. The programming interface 133 includes programming registers and operates under the control of commands issued by the CPU 30.

[0028] The security system circuit 132 is configured to issue a fault signal clk_fail if there is a fault in the external oscillator clock signal xosc_clk. Such a fault signal xosc_clk is sent to the security activation block 131 and the programming interface 133, and the programming interface 133 forwards the corresponding interrupt xosc_fail_it to the CPU 30.

[0029] The programming interface 133 is configured to generate a clock activation signal clk_on for the security activation block 131 to signal the circuit to enable the use of the external crystal oscillator 50 via the handshake control signals xosc_en, xosc_rd.

[0030] Parts of the system 10 are schematically shown in Figure 2 which details the blocks and circuits related to the security system circuit 131.

[0031] In various embodiments, the security activation block 131 operates as a control interface for the handshake control signals to enable the operation of the external crystal oscillator 50. Under the control of the CPU 30, it receives the clock activation signal clk_on from the programming interface 131 to activate the oscillator 50, and receives the detected fault signal clk_fail to deactivate the oscillator 50.

[0032] The security system circuit 132 includes a clock finite state machine 1321, which is the control logic of the clock controller 13 and operates under the control of commands issued by the programming interface 133, and the programming interface 133 in turn operates under the control of the CPU 30. The security system circuit 132 includes a selection block 1322, particularly a multiplexer, which receives the external oscillator clock signal xosc_ck at one input and other clock signals src_clks from the clock source 60 at its other inputs. The clock source is generally an oscillator inside the microcontroller 11, although the oscillator may not be specifically placed inside the security system circuit 132, but the security system circuit 132 can simply be coupled to them. The clock finite state machine 1321 issues a selection signal clk_sel to the selection block 1322 to select the system clock signal sys_clk from among the input clock signals including the oscillator clock signal xosc_clk and the other clock signals src_clks. The source ready signal src_ready supplied to the clock finite state machine 1321 indicates which of the other clock signals is stable and ready for use. In particular, there is a source ready signal for each clock source to notify the clock controller of the availability of selectable sources.

[0033] The security system circuit 132 then includes a detection block 1323, which is configured to detect a fault in the external oscillator clock signal xosc_ck and issue a fault signal clk_fail to the clock finite state machine 1321 and the programming interface 133.

[0034] The detection block 1323 is enabled by the security activation signal css_on and the external oscillator ready signal xosc_ready. Both signals should be true (logical AND is shown) to enable the operation of the detection block 1323. The detection block 1323 then operates only when the external oscillator 50 is in use and the security function is requested by the CPU 30.

[0035] In the case of fault detection by the detection block 1323, the fault signal clk_fail sent to the clock finite state machine 1321 determines that the clock finite state machine 1321 switches the system clock sys_clk to a stable clock source among the other clock signals src_clks via the selection signal sel_clk. Then the security system circuit 132 is configured to turn off the external oscillator clock signal xosc_ck after receiving the fault signal clk_fail via the detection block 1323. The programming interface 133 is also configured to trigger an interrupt xosc_fail_it after receiving the fault signal clk_fail from the detection block 1323.

[0036] In Figure 3System 10 is shown, and the blocks and circuits related to the time filtering function of signal Xosc_ready implemented by safety activation block 131 are detailed. As described above, safety activation block 131 is a handshake interface that allows control of the sharing of an external oscillator clock between circuits 11 and 12. The safety activation block also includes the implementation of a time filtering function to avoid glitches generated due to competition for the clock signal by circuits 11 and 12. Therefore, clock controller 13 implements a configurable / programmable filtering mechanism on the Xosc ready control signal through block 131 to address the enable control delay inside circuit 12 equipped with an oscillator, and the enable control delay may cause spurious glitches on the ready signal.

[0037] Safety activation block 131 thus includes interface enable control circuit 1311, which, as described above, receives external oscillator enable signal hse_en, and this enable signal hse_en can correspond to Figure 1 signal clk_on, and issues external oscillator enable signal xosc_en to circuit 12 equipped with an oscillator for the handshake protocol, and also issues external oscillator enable signal xosc_en to ready filter 1312. Ready filter 1312 also receives external oscillator ready signal xosc_ready and external oscillator clock signal xosc_clk. Ready filter 1312 is configured to issue ready enable signal rdy_en based on the value of the handshake signal and external oscillator clock signal xosc_clk.

[0038] Therefore, ready enable signal rdy_en is issued as the output of ready filter 1312. Ready filter 1312 changes state after a time window has passed, for example, to a high logic level, and ready filter 1312 is used to perform gating of external oscillator ready signal xosc_rdy, specifically by feeding the two signals as inputs to AND gate 1313 to generate the microcontroller-gated ready signal hse_rdy. Subsequently, clock signal Xosc_clk in turn is gated using the microcontroller-gated ready signal hse_rdy, specifically by another AND gate 1314, such that microcontroller external oscillator clock signal hse_clk is obtained. This takes into account the timing delay of signal xosc_en inside circuit 12 equipped with an oscillator and can be free from spurious glitches or other effects generated by race conditions.

[0039] Figure 3 The timing diagram of the signals shown in is represented in Figure 4For example, hse-clock_n represents an unfiltered version of the external oscillator clock signal hse_clock; P1 represents the moment when the signal xosc_clock is enabled by circuit 12; P2 represents the moment when the signal xosc_clock is enabled by the microcontroller 11; P3 represents the moment when the signal xosc_ready drops when the signal xosc_en is high; P4 represents the moment when the signal hse_clock is lost when the signal xosc_en is high; P5 represents the moment when the signal hse_clock, i.e., the filtered hse clock signal, remains low during the transition window; and P6 represents the moment when the signal hse_clock is transmitted after the filtering expires.

[0040] DT indicates the delay time required for the Xosc controller 121 of the RF IP 12 to turn on xosc_clock, which is the time calculated by the internal delay counter 121a thereof. RW indicates the race window where there is a risk of control race, and FT indicates the filtering time interval of the rdy_en signal, where such rdy_en signal remains in the low logic state.

[0041] From Figure 4 It can be seen that there is a potential race risk in the case of attempting to control the external oscillator 50 from both the circuit 12 and the microcontroller 11. The block 131 is configured to ensure that the external oscillator clock signal xosc_ck is transmitted to the core of the microcontroller 11 as the external clock hse_clk of the microcontroller only after a time filtering window, such as a given time interval.

[0042] The ready filter 1312 is configured or programmed to have a delay time DT, the magnitude of which is sized to cover only the time window during which the risk of clock loss or glitches may occur, e.g., window RW. After this time, which is much smaller than the delay time DT, the ready filter 1312 generates a ready enable rdy_en signal, which allows the external oscillator ready signal xosc_rdy to be transmitted through the AND gate 1313 to the microcontroller clock ready signal hse_rdy. If the external oscillator ready signal xosc_rdy is asserted (xosc_clk is on), then after exceeding the time window RW, the external oscillator clock signal xosc_ck is transmitted through the AND gate 1314 to the microcontroller external clock hse_clk; if the external oscillator ready signal xosc_rdy is low (xosc_clk has been turned off by the controller 121 of the external oscillator of circuit 12, as described in the timing diagram), then after the delay time DT, the external oscillator clock signal xosc_ck is transmitted to the microcontroller external clock hse_clk of the microcontroller 11, the delay time DT being the time required to turn on the external oscillator clock signal xosc_ck again due to the request xosc_en from the microcontroller 12 and counted by the corresponding delay block 121a of the oscillator controller 12.

[0043] Thus, the ready filter 1312 asserts the rdy_en signal after a filtering time FT, which allows the transmission of the ready signal xosc_rdy from the oscillator-equipped circuit 12.

[0044] It should be understood that the embodiments are not limited to applications in the context of microcontroller (e.g., STM32 microcontroller) applications, which utilize embedded RF IP for IoT (e.g., SW1262 Semtech) for LoRa applications, e.g., for consumer applications based on multipurpose microprocessors, such as household appliances, etc.

[0045] Accordingly, one or more embodiments can provide a system including: a processing unit (e.g., a general-purpose microcontroller such as an STM 32 or a system-on-chip or a subsystem thereof), a circuit (e.g., RF transceiver circuit 12), the circuit including oscillator control circuitry coupled to an external oscillator, such oscillator control circuitry being configured to control the external oscillator to provide an external oscillator clock signal to the circuitry coupled to the oscillator, the processing unit including a clock controller (e.g., capable of generating a clock signal externally or internally) configured to manage the clock signal to select a system clock for the processing unit, e.g., the HSE clock signal of an STM32 microcontroller, wherein: such clock controller is coupled to the oscillator control circuitry to receive the external oscillator clock signal and is configured to selectively provide such external oscillator clock signal as the system clock, e.g., the HSE clock signal as described above, the clock controller including an interface circuit and a safety circuit, the interface circuit being configured to exchange handshake signals (e.g., enable signal xosc_en and ready signal xosc_ready), with the oscillator control circuitry, in particular with the delay counter of the RF circuit, to enable the external oscillator clock signal to be transmitted to the clock controller; the safety circuit includes receiving the external oscillator clock signal and is configured to select such signal as the system clock under the control of a detection block (e.g., block 1313), the detection block being configured to detect a fault in the external oscillator clock signal and to issue a fault signal indicating the fault after detecting the fault. After issuing the fault signal, such safety circuit is configured to select a different clock signal as the system clock, e.g., select from the signals src_clks, and to operate on the interface circuit to interrupt the transmission of the external oscillator clock signal to the clock controller.

[0046] In one or more embodiments, after a fault signal is issued from the detection block, the clock controller can be configured to trigger an interrupt xosc_fail_it to the processing unit core, e.g., CPU 30.

[0047] In one or more embodiments, the interface block can include gating circuit means, e.g., circuits 1311, 1312, 1313, 1314, configured to perform gating on the ready signal of the handshake signal with a time filtering window to enable the external oscillator clock signal to be transmitted as the system clock.

[0048] In one or more embodiments, the circuitry coupled to the oscillator can include a radio frequency transceiver.

[0049] In one or more embodiments, a safety circuit includes control logic, in particular a finite state machine (e.g., the control logic of a clock controller that may already be provided in a microcontroller to select a system clock signal), the logic control operating under the control of a central processing unit of a processing unit, which is configured to select such a signal as the system clock based on a fault signal, and after the fault signal is issued, select a different clock signal as the system clock and operate on an interface circuit to interrupt the transmission of an external oscillator clock signal to the clock controller.

[0050] In various embodiments, logic circuits known in the art may be used to implement the circuits described herein.

[0051] In one or more embodiments, a device (e.g., a microcontroller-based appliance) may include a processor circuit, e.g., CPU 30, to receive an external clock, an external oscillator clock signal, by means of a system according to one or more embodiments.

[0052] A method of operating a system according to one or more embodiments may include: receiving an external oscillator clock signal from a circuit equipped with an oscillator, and optionally providing the external oscillator clock signal as the system clock, exchanging handshake signals between a clock controller and an oscillator control circuit to enable the external oscillator clock signal to be transmitted to the clock controller, and receiving the external oscillator clock signal, and selecting the external oscillator clock signal as the system clock under the control of a fault detection operation in the external oscillator clock signal, after detecting a fault, issuing a fault signal indicating the fault, after the fault signal is issued, selecting a different clock signal as the system clock, and operating on the handshake signal to interrupt the transmission of the external oscillator clock signal to the clock controller.

[0053] In one or more embodiments, the method may include triggering an interruption to a processing circuit core after the fault signal is issued.

[0054] In one or more embodiments, the method may include performing gating on a ready signal of the handshake signal using a time filtering window to enable the external oscillator clock signal to be transmitted as the system clock.

[0055] Without prejudice to the basic principles, details and embodiments may vary, even significantly, relative to what has been described (by way of example only) without departing from the scope of protection.

Claims

1. A system for selecting a clock, comprising: A circuit equipped with an oscillator, including: an oscillator control circuit configured to be coupled to an external oscillator, the oscillator control circuit being configured to cause the external oscillator to provide an external oscillator clock signal to the circuit equipped with the oscillator; and A processing unit, including a clock controller, the clock controller being configured to manage clock signals to select a system clock for the processing unit, wherein The clock controller is coupled to the oscillator control circuit to receive the external oscillator clock signal, and the clock controller is configured to selectively provide the external oscillator clock signal as the system clock, the clock controller including: An interface circuit, including: An interface enable control circuit, configured to: Receive a clock activation signal, After receiving the clock activation signal, exchange handshake signals with the oscillator control circuit by sending an oscillator enable signal to the oscillator control circuit and receiving the external oscillator clock signal and an external oscillator ready signal in response to sending the oscillator enable signal, wherein the external oscillator ready signal is a static signal indicating the availability of the external oscillator clock signal from the external oscillator, and the external oscillator clock signal is a switching signal separated from the external oscillator ready signal, and A gating circuit, configured to gate the external oscillator ready signal and the external oscillator clock signal after a predetermined period in which the external oscillator ready signal and the external oscillator clock signal have been in an active state, wherein the predetermined period is at least one complete clock cycle of the external oscillator clock signal, A safety circuit, configured to receive the gated external oscillator clock signal and configured to select the gated external oscillator clock signal as the system clock, and A detection block, configured to detect a fault in the external oscillator clock signal, and after detecting the fault, issue a fault signal indicating the fault, wherein after the issuance of the fault signal, the safety circuit is configured to select a different clock signal as the system clock and cause the interface circuit to interrupt the transmission of the external oscillator clock signal to the clock controller.

2. The system according to claim 1, wherein, The clock controller is configured to assert an interrupt after issuing the fault signal from the detection block to the processor.

3. The system according to claim 1, wherein The circuit equipped with the oscillator includes a radio frequency transceiver.

4. The system according to claim 1, wherein, The safety circuit includes a finite state machine that operates under the control of a central processing unit of the processing unit, the finite state machine being configured to select the system clock based on the fault signal and, after the issuance of the fault signal, select the different clock signal as the system clock and cause the interface circuit to interrupt the transmission of the external oscillator clock signal to the clock controller.

5. The system according to claim 1, wherein, The processing unit further includes a processor having a clock input configured to receive the external oscillator clock signal.

6. The system according to claim 5, wherein, The processor includes a general-purpose microcontroller or a system-on-chip.

7. A method for selecting a clock, comprising: Exchanging handshake signals between a clock controller and a circuit equipped with an oscillator to enable transmission of an external oscillator clock signal to the clock controller, wherein exchanging the handshake signals includes: Sending an oscillator enable signal from the clock controller to the circuit equipped with an oscillator; In response to sending the oscillator enable signal, receiving the external oscillator clock signal and an external oscillator ready signal from the circuit equipped with an oscillator, wherein the external oscillator ready signal is a static signal indicating the availability of the external oscillator clock signal from the circuit equipped with the oscillator, and the external oscillator clock signal is a switching signal separated from the external oscillator ready signal; After the external oscillator ready signal and the external oscillator clock signal are both active for a predetermined period, gating the external oscillator ready signal and the external oscillator clock signal, wherein the predetermined period is at least one complete clock cycle of the external oscillator clock signal; Selecting the gated external oscillator clock signal as the system clock; Detecting a fault in the received external oscillator clock signal; In response to detecting the fault, issuing a fault signal; and After issuing the fault signal, selecting a different clock signal as the system clock and operating on the handshake signals to interrupt the transmission of the external oscillator clock signal to the clock controller.

8. The method according to claim 7, comprising asserting an interrupt to a processing circuit core after issuing the fault signal.

9. A system for selecting a clock, comprising: A clock interface circuit having a clock ready input configured to be coupled to a clock ready output of an external clock output of an external clock source, the clock interface circuit including a ready filter configured to assert a ready enable signal in response to an external clock signal generated by the external clock source at the external clock ready output being valid and an external clock presence signal generated by the external clock source being asserted for a first predetermined period, wherein the first predetermined period is at least one complete clock cycle of the external clock signal, the external clock presence signal and the ready enable signal are static signals, and the external clock signal is a switching signal separated from the external clock presence signal and the external clock presence signal; An interrupt generation circuit configured to generate an external clock fault interrupt signal when the external clock presence signal is de-asserted; And A clock selection circuit configured to provide the external clock signal to a system clock output when the ready enable signal is asserted and to provide a different clock signal to the system clock output when the external clock presence signal is de-asserted.

10. The system according to claim 9, wherein, The clock selection circuit includes: A finite state machine coupled to the clock interface circuit, the finite state machine configured to generate a selection output based on the external clock presence signal and the external clock ready signal; and A multiplexer having a first input, a second input, and a select input, the first input being coupled to the external clock source, the second input being coupled to another clock source providing the different clock signal, and the select input being coupled to the select output of the finite state machine.

11. The system of claim 9, further comprising the external clock source, wherein the external clock source includes an external clock controller configured to be coupled to an external oscillator, the external clock controller including a delay counter configured to assert the external clock present signal when an output of the external oscillator is active for a second predetermined period.

12. The system according to claim 11, wherein The external oscillator includes a crystal oscillator.

13. The system according to claim 11, wherein, The external clock source is disposed on a first chip, and the clock interface circuit, the interrupt generation circuit, and the clock selection circuit are disposed on a second chip separate from the first chip.

14. The system according to claim 13, wherein, The first chip includes a microcontroller having a clock input coupled to the system clock output of the clock selection circuit.

15. The system according to claim 13, wherein, The second chip includes an RF transceiver circuit.

16. A method for selecting a clock, comprising: detecting the presence of an external clock signal and an external clock ready signal, the external clock ready signal indicating the availability of the external clock signal from an external clock generator; asserting a ready enable signal in response to the external clock ready signal being asserted and the external clock signal being valid for a first predetermined period, wherein the first predetermined period is at least one complete clock cycle of the external clock signal, and the external clock ready signal and the ready enable signal are static signals, and the external clock signal is a switching signal separate from the external clock ready signal and the ready enable signal; routing the external clock signal to a system clock output after the assertion of the ready enable signal; asserting an external clock fault signal when the presence of the external clock signal is no longer detected; and when the external clock fault signal is asserted, routing a different clock signal to the system clock output and asserting an external clock fault interrupt signal.

17. The method of claim 16, further comprising sending an external clock enable signal to the external clock generator.

18. The method of claim 17, further comprising providing the system clock output to a microprocessor.

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