A voltage stabilizer

Abstract

The present invention discloses a voltage stabilizer, belonging to the field of electronics. The voltage stabilizer of the present invention includes a bias circuit, a voltage stabilization circuit and an output circuit; the voltage stabilizer can start working and realize the voltage stabilization function when the power supply voltage exceeds the preset stable voltage of the chip; when the internal main power supply works normally, the voltage stabilizer can assist the main power supply to output current, and when the main power supply in the chip is abnormal, the voltage stabilizer provides a stable voltage to maintain the internal data of the chip from being lost. The voltage stabilizer can provide continuous and stable voltage for certain circuits when the main power supply inside the chip is not turned on, so as to avoid the situation where the chip loses power due to abnormal internal main power supply or data is lost before startup.

Description

Technical Field

[0001] The invention relates to the field of electronics, and in particular to a sub-microampere voltage regulator. Background Art

[0002] At present, most power management chips usually use low drop outregulators (LDO) for voltage regulation. Traditional low drop outregulators such as Figure 1 As shown, the output VOUT is generally fed back to the amplifier input via a voltage divider resistor to complete the closed-loop control. This type of LDO usually consumes relatively large power (for example, more than 5uA). However, in some application scenarios that require low power consumption (for example, electronic equipment is in standby mode), although the LDO does not need to work continuously, in order to prevent some modules from losing data due to power failure, an ultra-low power consumption voltage regulator module is still required to continuously supply power to them. Existing low voltage drop linear regulators cannot meet the needs of the above scenarios. Utility Model Content

[0003] In view of the above problems, a voltage regulator is provided which is designed to reduce power consumption and can provide a continuous and stable voltage to certain circuits when the main power supply inside the chip is not turned on.

[0004] The present invention provides a voltage stabilizer, comprising:

[0005] A bias circuit, comprising a first output terminal and a second output terminal, for converting an input voltage into a first bias voltage signal and a second bias voltage signal;

[0006] A voltage stabilizing circuit, comprising a first input terminal, a second input terminal and a third output terminal, wherein the first input terminal is connected to the first output terminal, the second input terminal is connected to the second output terminal, and the voltage stabilizing circuit is used to output a first voltage signal according to the input voltage, the first bias voltage signal and the second bias voltage signal;

[0007] The output circuit includes a third input terminal, a fourth input terminal and a fourth output terminal, the third input terminal is connected to the third output terminal, the fourth input terminal is connected to the second output terminal, and the output circuit is used to generate a second voltage signal according to the input voltage, the first voltage signal and the second bias voltage signal, and output the second voltage signal.

[0008] Preferably, the bias circuit further includes:

[0009] a first PMOS tube, wherein a source of the first PMOS tube is connected to a power supply terminal, and a gate of the first PMOS tube is connected to a drain of the first PMOS tube;

[0010] a second PMOS tube, wherein a source of the second PMOS tube is connected to a source of the first PMOS tube and the power supply terminal, and a gate of the second PMOS tube is connected to a gate of the first PMOS tube and a drain of the first PMOS tube;

[0011] A first NMOS tube, wherein the drain of the first NMOS tube is connected to the gate of the first PMOS tube, and the drain of the first PMOS tube is connected to the gate of the second PMOS tube to form a first output end of the bias circuit;

[0012] a second NMOS transistor, wherein the source of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is connected to the drain of the second NMOS transistor, the gate of the first NMOS transistor and the drain of the second PMOS transistor to form a second output end of the bias circuit;

[0013] A first resistor, one end of the first resistor is connected to the source of the first NMOS transistor, and the other end of the first resistor is connected to the source of the second NMOS transistor and grounded.

[0014] Preferably, the voltage stabilizing circuit further includes:

[0015] a third PMOS tube, wherein the gate of the third PMOS tube forms the first input terminal of the voltage stabilizing circuit, and the source of the third PMOS tube is connected to the power supply terminal;

[0016] a third NMOS tube, wherein the drain of the third NMOS tube is connected to the drain of the third PMOS tube, and the source of the third NMOS tube is grounded;

[0017] a fourth NMOS transistor, wherein a gate of the fourth NMOS transistor forms a second input terminal of the voltage stabilizing circuit, and a source of the fourth NMOS transistor is grounded;

[0018] a sixth NMOS tube, wherein a gate of the sixth NMOS tube is connected to a drain of the third PMOS tube and a drain of the third NMOS tube, and a drain of the sixth NMOS tube is connected to a source of the third PMOS tube;

[0019] A second resistor, one end of the second resistor is connected to the gate of the third NMOS tube and the drain of the fourth NMOS tube, and the other end of the second resistor is connected to the source of the sixth NMOS tube to form a third output end of the voltage stabilizing circuit.

[0020] Preferably, the output circuit further includes:

[0021] a fifth NMOS transistor, wherein a gate of the fifth NMOS transistor forms a fourth input terminal of the output circuit, and a source of the fifth NMOS transistor is grounded;

[0022] A seventh NMOS tube, wherein the gate of the seventh NMOS tube forms the third input terminal of the output circuit, the drain of the seventh NMOS tube is connected to the power supply terminal, and the source of the seventh NMOS tube is connected to the drain of the fifth NMOS tube to jointly form the fourth output terminal of the output circuit.

[0023] Beneficial effects of the above technical solution:

[0024] In the technical scheme, the voltage stabilizer of the present invention includes a bias circuit, a voltage stabilization circuit and an output circuit; the voltage stabilizer can start working and realize the voltage stabilization function when the power supply voltage exceeds the preset stable voltage of the chip; when the internal main power supply works normally, the voltage stabilizer can assist the main power supply to output current, and when the main power supply in the chip is abnormal, the voltage stabilizer provides a stable voltage to maintain the internal data of the chip from being lost. The voltage stabilizer can provide continuous and stable voltage for certain circuits when the main power supply inside the chip is not turned on, avoiding the situation where the chip loses power due to abnormal internal main power supply or data is lost before startup. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a circuit diagram of an existing low voltage difference linear regulator;

[0026] Figure 2 A circuit diagram of an embodiment of the bias circuit of the present invention;

[0027] Figure 3 A circuit diagram of an embodiment of the voltage stabilizing circuit of the present invention;

[0028] Figure 4 A circuit diagram of an embodiment of the voltage stabilizer according to the present invention. DETAILED DESCRIPTION

[0029] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them.

[0030] The embodiments of the present invention and all other embodiments obtained by ordinary technicians in this field without making any creative work are within the scope of protection of the present invention.

[0031] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0032] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0033] like Figures 2 to 4As shown, the present invention provides a voltage stabilizer, comprising: a bias circuit 1, a voltage stabilizing circuit 2 and an output circuit 3; wherein,

[0034] The bias circuit 1 comprises two first output terminals VB1 and a second output terminal VB2, and is used to convert an input voltage into a first bias voltage signal and a second bias voltage signal;

[0035] Furthermore, if Figure 2 and Figure 4 The bias circuit 1 shown may also include: a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2 and a first resistor R1;

[0036] a first PMOS transistor MP1, wherein a source of the first PMOS transistor MP1 is connected to a power supply terminal VCC, and a gate of the first PMOS transistor MP1 is connected to a drain of the first PMOS transistor MP1;

[0037] a second PMOS transistor MP2, wherein the source of the second PMOS transistor MP2 is connected to the source of the first PMOS transistor MP1 and the power supply terminal VCC, and the gate of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1 and the drain of the first PMOS transistor MP1;

[0038] A first NMOS transistor MN1, wherein the drain of the first NMOS transistor MN1 is connected to the gate of the first PMOS transistor MP1, the drain of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 to form a first output terminal VB1 of the bias circuit 1;

[0039] A second NMOS transistor MN2, wherein the source of the second NMOS transistor MN2 is grounded, and the gate of the second NMOS transistor MN2 is connected to the drain of the second NMOS transistor MN2, the gate of the first NMOS transistor MN1 and the drain of the second PMOS transistor MP2 to form a second output terminal VB2 of the bias circuit 1;

[0040] A first resistor R1, one end of the first resistor R1 is connected to the source of the first NMOS transistor MN1, and the other end of the first resistor R1 is connected to the source of the second NMOS transistor MN2 and grounded.

[0041] A voltage stabilizing circuit 2, comprising a first input terminal, a second input terminal and a third output terminal VB3, wherein the first input terminal is connected to the first output terminal VB1, the second input terminal is connected to the second output terminal VB2, and the voltage stabilizing circuit 2 is used to output a first voltage signal according to the input voltage, the first bias voltage signal and the second bias voltage signal;

[0042] Furthermore, if Figure 3 and Figure 4 The voltage stabilizing circuit 2 shown in the figure may further include: a third PMOS transistor MP3, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a sixth NMOS transistor MN6 and a second resistor RM;

[0043] A third PMOS transistor MP3, wherein the gate of the third PMOS transistor MP3 forms the first input terminal of the voltage stabilizing circuit 2, and the source of the third PMOS transistor MP3 is connected to the power supply terminal VCC;

[0044] a third NMOS transistor MN3, wherein the drain of the third NMOS transistor MP3 is connected to the drain of the third PMOS transistor MP3, and the source of the third NMOS transistor MN3 is grounded;

[0045] A fourth NMOS transistor MN4, wherein the gate of the fourth NMOS transistor MN4 forms the second input terminal of the voltage stabilizing circuit 2, and the source of the fourth NMOS transistor MN4 is grounded;

[0046] a sixth NMOS transistor MN6, wherein a gate of the sixth NMOS transistor MN6 is connected to a drain of the third PMOS transistor MP3 and a drain of the third NMOS transistor MN3, and a drain of the sixth NMOS transistor MN6 is connected to a source of the third PMOS transistor MP3;

[0047] A second resistor RM, one end of which is connected to the gate of the third NMOS transistor MN3 and the drain of the fourth NMOS transistor MN4, and the other end of which is connected to the source of the sixth NMOS transistor MN6 to form a third output terminal VB3 of the voltage stabilizing circuit 2.

[0048] The second resistor RM is a trimming resistor.

[0049] The output circuit 3 includes a third input terminal, a fourth input terminal and a fourth output terminal, the third input terminal is connected to the third output terminal VB3, the fourth input terminal is connected to the second output terminal VB2, and the output circuit 3 is used to generate a second voltage signal according to the input voltage, the first voltage signal and the second bias voltage signal, and output the second voltage signal.

[0050] Furthermore, if Figure 3 and Figure 4 The output circuit 3 shown may further include: a fifth NMOS transistor MN5 and a seventh NMOS transistor MN7;

[0051] a fifth NMOS transistor MN5, wherein a gate of the fifth NMOS transistor MN5 forms a fourth input terminal of the output circuit 3, and a source of the fifth NMOS transistor MN5 is grounded;

[0052] A seventh NMOS tube MN7, a gate of the seventh NMOS tube MN7 forms a third input terminal of the output circuit 3, a drain of the seventh NMOS tube MN7 is connected to the power supply terminal VCC, and a source of the seventh NMOS tube MN7 is connected to the drain of the fifth NMOS tube MN5 to form a fourth output terminal of the output circuit 3.

[0053] In the bias circuit 1, the current flowing through the first PMOS transistor MP1 is defined by the ratio of the gate-source voltage difference between the second NMOS transistor MN2 and the first NMOS transistor MN1 to the first resistor R1, and the first PMOS transistor MP1 mirrors the current value to the third PMOS transistor MP3 through a current mirror. Figure 3 As shown, the gate static operating point of the sixth NMOS tube MN6 is determined by the current flowing through the third PMOS tube MP3, and the gate static operating point of the third NMOS tube MN3 is determined by the current flowing through the fourth NMOS tube MN4. At the same time, the third NMOS tube MN3 and the sixth NMOS tube MN6 form a negative feedback. When the drain voltage of the third PMOS tube MP3 rises, the gate-source voltage difference of the sixth NMOS tube MN6 increases, so that the gate voltage of the third NMOS tube MN3 decreases, thereby lowering the drain voltage of the third PMOS tube MP3, thereby achieving the purpose of fast stabilization of the operating point. Since the fourth NMOS tube MN4 mirrors the drain current of the second NMOS tube MN2 by means of a current mirror, when the width-to-length ratio of the fourth NMOS tube MN4 remains unchanged, adjusting the second resistor RM can effectively adjust the gate static operating points of the third NMOS tube MN3 and the sixth NMOS tube MN6. Figure 4 As shown, VOUT = VG7-VGS7, so the voltage regulation function can be achieved under small load current.

[0054] In this embodiment, a DC bias is generated by the first PMOS tube MP1, the second PMOS tube MP2, the first NMOS tube MN1, the second NMOS tube MN2, and the first resistor R1, and the static operating point of the third NMOS tube MN3, the sixth NMOS tube MN6, and the seventh NMOS tube MN7 is stabilized by changing the resistance value of the second resistor RM, thereby achieving output voltage stability. The third PMOS tube MP3, the sixth NMOS tube MN6, and the third NMOS tube MN3 form a negative feedback structure, and the operating point can be quickly stabilized when the power supply voltage suddenly changes. The circuit has the advantages of novel structure, adjustable output voltage, no need for capacitor compensation, small chip area, and cost saving.

[0055] In this embodiment, the voltage stabilizer can start working and realize the voltage stabilization function when the power supply voltage exceeds the preset stable voltage of the chip; when the internal main power supply works normally, the voltage stabilizer can assist the main power supply to output current, and when the main power supply in the chip is abnormal, the voltage stabilizer provides a stable voltage to maintain the internal data of the chip from being lost. The voltage stabilizer can provide continuous and stable voltage for certain circuits when the main power supply inside the chip is not turned on, avoiding the situation where the chip loses power due to abnormal internal main power supply or data is lost before startup. The voltage stabilizer of the present invention has the advantages of novel structure, adjustable output voltage, no need for capacitor compensation, small chip area, cost saving, etc.

[0056] The above description is only a preferred embodiment of the present invention, and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A voltage stabilizer, characterized in that: It includes bias circuit, voltage stabilization circuit and output circuit, among which: The bias circuit comprises a first output terminal and a second output terminal, and the bias circuit is used to convert an input voltage into a first bias voltage signal and a second bias voltage signal; The voltage stabilizing circuit includes a first input terminal, a second input terminal and a third output terminal, wherein the first input terminal is connected to the first output terminal, the second input terminal is connected to the second output terminal, and the voltage stabilizing circuit is used to output a first voltage signal according to the input voltage, the first bias voltage signal and the second bias voltage signal. The voltage stabilizing circuit also includes: a third PMOS tube, the gate of the third PMOS tube forms the first input terminal of the voltage stabilizing circuit, the source of the third PMOS tube is connected to the power supply terminal; a third NMOS tube, the drain of the third NMOS tube is connected to the drain of the third PMOS tube, and the a fourth NMOS tube, the gate of the fourth NMOS tube forming the second input terminal of the voltage stabilizing circuit, and the source of the fourth NMOS tube being grounded; a sixth NMOS tube, the gate of the sixth NMOS tube being connected to the drain of the third PMOS tube and the drain of the third NMOS tube, and the drain of the sixth NMOS tube being connected to the source of the third PMOS tube; a second resistor, one end of the second resistor being connected to the gate of the third NMOS tube and the drain of the fourth NMOS tube, and the other end of the second resistor being connected to the source of the sixth NMOS tube to form a third output terminal of the voltage stabilizing circuit; The output circuit includes a third input terminal, a fourth input terminal and a fourth output terminal, the third input terminal is connected to the third output terminal, the fourth input terminal is connected to the second output terminal, the output circuit is used to generate a second voltage signal according to the input voltage, the first voltage signal and the second bias voltage signal, and output the second voltage signal, the output circuit also includes: a fifth NMOS tube, the gate of the fifth NMOS tube forms the fourth input terminal of the output circuit, and the source of the fifth NMOS tube is grounded; a seventh NMOS tube, the gate of the seventh NMOS tube forms the third input terminal of the output circuit, the drain of the seventh NMOS tube is connected to the power supply terminal, and the source of the seventh NMOS tube is connected to the drain of the fifth NMOS tube to jointly form the fourth output terminal of the output circuit.

2. The voltage stabilizer according to claim 1, characterized in that: The bias circuit further comprises: a first PMOS transistor, wherein the source of the first PMOS transistor is connected to the power supply terminal, and the gate of the first PMOS transistor is connected to the drain of the first PMOS transistor; a second PMOS transistor, wherein the source of the second PMOS transistor is connected to the source of the first PMOS transistor and the power supply terminal, and the gate of the second PMOS transistor is connected to the gate of the first PMOS transistor and the drain of the first PMOS transistor; a first NMOS transistor, wherein the drain of the first NMOS transistor is connected to the gate of the first PMOS transistor, the drain of the first PMOS transistor and the gate of the second PMOS transistor to form a first output terminal of the bias circuit; a second NMOS transistor, wherein the source of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is connected to the drain of the second NMOS transistor, the gate of the first NMOS transistor and the drain of the second PMOS transistor to form a second output terminal of the bias circuit; a first resistor, wherein one end of the first resistor is connected to the source of the first NMOS transistor, and the other end of the first resistor is connected to the source of the second NMOS transistor and grounded.

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