FinFET device structure

Abstract

The present invention provides a fin field effect transistor (FinFET) device structure and a method for forming the FinFET device structure. The FinFET device structure includes a substrate and a first fin structure and a second fin structure extending above the substrate. The FinFET device structure also includes a first transistor formed on the first fin structure and a second transistor formed on the second fin structure. The FinFET device structure also includes an interlayer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 20nm to about 40nm. Embodiments of the present invention also relate to a fin field effect transistor (FinFET) device with a controllable end-to-end critical dimension and a method for forming the same.

Description

[0001] This application is a divisional application of patent application number 201510437327.X, entitled “Fin Field Effect Transistor (FinFET) Device with Controllable End-to-End Critical Dimension and Formation Method thereof” filed on July 23, 2015. Technical Field

[0002] Embodiments of the present invention relate to integrated circuits, and more particularly, to fin field effect transistor (FinFET) device structures. Background Art

[0003] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements on the material layers. Many integrated circuits are typically manufactured on a single semiconductor wafer, and the individual dies on the wafer are separated by sawing along scribe lines between the integrated circuits.

[0004] As the semiconductor industry has entered the nanotechnology process node in pursuit of higher device density, higher performance and lower cost, the challenges from manufacturing and design issues have led to the development of three-dimensional designs such as fin field effect transistors (FinFETs). FinFETs are manufactured with thin vertical "fins" (or fin structures) extending from the substrate. The channel of the FinFET is formed in the vertical fin. A gate is provided above the fin. The advantages of FinFETs can include reduced short channel effects and higher currents.

[0005] While existing FinFET devices and methods of making FinFET devices have been generally adequate for their intended purposes, they have not been completely satisfactory in all respects. Summary of the invention

[0006] An embodiment of the present invention provides a fin field effect transistor (FinFET) device structure, comprising: a substrate; a first fin structure and a second fin structure extending above the substrate; a first transistor formed on the first fin structure; a second transistor formed on the second fin structure; and an interlayer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, wherein the end-to-end gap has a width in a range from about 10 nm to about 50 nm.

[0007] Another embodiment of the present invention provides a fin field effect transistor (FinFET) device structure, comprising: a substrate; an isolation structure formed on the substrate; a first fin structure embedded in the isolation structure; a first transistor formed on the first fin structure; a second transistor formed on the first fin structure and the isolation structure; and an interlayer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, wherein the end-to-end gap has a width in a range from about 10 nm to about 50 nm.

[0008] Another embodiment of the present invention provides a method for forming a fin field effect transistor (FinFET) device structure, comprising: providing a substrate; forming a first fin structure and a second fin structure, wherein the first fin structure and the second fin structure extend above the substrate; forming a dielectric layer on the first fin structure and the second fin structure; forming a polysilicon layer, a hard mask layer and a photoresist layer on the dielectric layer; patterning the photoresist layer to form a first trench in the photoresist layer, wherein the first trench has a first width; conformally forming a coating in the first trench to form a second trench in the photoresist layer, wherein the second trench has a second width, and the second width is smaller than the first width; patterning the hard mask layer by using the photoresist layer as a mask; patterning the polysilicon layer by using the hard mask layer as a mask to form an end-to-end gap between the first fin structure and the second fin structure, wherein the end-to-end gap has a third width, and the third width is smaller than the first width.

[0009] Embodiments of the present application provide a fin field effect transistor (FinFET) device with controllable end-to-end critical dimension and a method for forming the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0011] Figure 1 A perspective view of a fin field effect transistor (FinFET) device structure according to some embodiments of the present invention is shown.

[0012] Figure 2 A top view of a fin field effect transistor (FinFET) device structure is shown in accordance with some embodiments of the present invention.

[0013] FIG. 3A to FIG. 3ICross-sectional illustrations of various stages in forming a fin field effect transistor (FinFET) device structure are shown in accordance with some embodiments of the present invention.

[0014] FIG. 4A to FIG. 4G Cross-sectional illustrations of various stages in forming a fin field effect transistor (FinFET) device structure are shown in accordance with some embodiments of the present invention. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. It should be understood that additional operations may be provided before, during, and after the method, and that some operations described may be replaced or eliminated for other embodiments of the method.

[0017] Embodiments are provided for forming a fin field effect transistor (FinFET) device structure. Figure 1 A perspective view of a fin field effect transistor (FinFET) device structure 100 is shown in accordance with some embodiments of the present invention.

[0018] FinFET device structure 100 includes substrate 102. Substrate 102 can be made of silicon or other semiconductor materials. Alternatively or additionally, substrate 102 can include other elemental semiconductor materials such as germanium. In some embodiments, substrate 102 is made of compound semiconductors such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, substrate 102 is made of alloy semiconductors such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In some embodiments, substrate 102 includes an epitaxial layer. For example, substrate 102 has an epitaxial layer located above a bulk semiconductor.

[0019] The FinFET device structure 100 also includes one or more fin structures 104 (e.g., Si fins) extending from the substrate 102. The fin structure 104 may optionally include germanium. The fin structure 104 may be formed using a suitable process such as photolithography and etching processes. In some embodiments, the fin structure 104 is etched from the substrate 102 using a dry etch or plasma process.

[0020] An isolation structure 108, such as a shallow trench isolation (STI) structure, is formed to surround the fin structure 104. Figure 1 As shown, in some embodiments, the isolation structure 108 surrounds the lower portion of the fin structure 104, and the upper portion of the fin structure 104 protrudes from the isolation structure 108. In other words, a portion of the fin structure 104 is embedded in the isolation structure 108. The isolation structure 108 prevents electrical interference or crosstalk.

[0021] The FinFET device structure 100 also includes a gate stack structure including a gate electrode 110 and a gate dielectric layer 106. The gate stack structure is formed over a central portion of the fin structure 104. In some embodiments, multiple gate stack structures are formed over the fin structure 104. Many other layers may also be present in the gate structure, such as capping layers, interface layers, spacer elements, and / or other suitable components.

[0022] The gate dielectric layer 106 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, a dielectric material having a high dielectric constant (high-k), or a combination thereof. Examples of high-k dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, etc., or a combination thereof.

[0023] The gate electrode 110 may include polysilicon or metal. The metal includes tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), molybdenum (Mo), copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), zirconium (Zr), platinum (Pt) or other applicable materials. The gate electrode 110 may be formed by a post-gate process (or a gate replacement process). In some embodiments, the gate stack structure includes additional layers such as an interface layer, a capping layer, a diffusion / barrier layer or other applicable layers.

[0024] The fin structure 104 includes a channel region 112 surrounded or wrapped by a gate electrode 110 and a gate dielectric layer 106. The fin structure 104 may be doped to provide a suitable channel for an n-type FinFET (NMOS device) or a p-type FinFET (PMOS device). The fin structure 104 may be doped using a suitable process such as an ion implantation process, a diffusion process, an annealing process, other applicable processes, or a combination thereof. The fin structure 104 includes a source region 114 and a drain region 116, with the channel region 112 located between the source region 114 and the drain region 116. The FinFET device 100 may be a device included in a microprocessor, a memory cell (e.g., a static random access memory (SRAM)), and / or other integrated circuits.

[0025] Figure 2 A top view of a fin field effect transistor (FinFET) device structure 100 is shown according to some embodiments of the present invention. The FinFET device structure 100 includes a plurality of fin structures 104 and a plurality of gate electrodes 110. The gate electrodes 110 traverse over the fin structures 104. An isolation structure 108 surrounds the FinFET device structure 100.

[0026] like Figure 2 As shown, the fin structures 104 may be substantially parallel to each other. The gate electrodes 110 may also be parallel to each other and substantially perpendicular to the fin structures 104. In some embodiments, when viewed from a top view, the gate electrodes 110 are also referred to as gate electrode lines.

[0027] The first transistor 300a is formed on the first fin structure 104a, and the second transistor 300b is formed on the second fin structure 104b. In some embodiments, a third width (W3) between the first transistor 300a and the second transistor 300b is in a range from about 10 nm to about 50 nm.

[0028] FIG. 3A to FIG. 3I Shown are cross-sectional diagrams of various stages in forming a fin field effect transistor (FinFET) device structure 100 in accordance with some embodiments of the present invention. FIG. 3A to FIG. 3I It is along Figure 2 A cross-sectional illustration taken along line AA'.

[0029] Reference Figure 3A , a first fin structure 104a and a second fin structure 104b are formed over the substrate 102. In some embodiments, the substrate 102 is etched to form the first fin structure 104a and the second fin structure 104b by depositing and patterning a hard mask layer (not shown) on the substrate 102. The hard mask layer forms a pattern covering a portion of the substrate 102. Then, the substrate 102 is etched to form trenches between the areas covered by the hard mask layer. As a result, the first fin structure 104a and the second fin structure 104b are formed between the trenches.

[0030] Then, a dielectric material (e.g., silicon oxide) is deposited in the trench to cover the first fin structure 104a and the second fin structure 104b. The dielectric material is planarized downward to the top surface of the first fin structure 104a and the second fin structure 104b or the top surface of the hard mask layer, and then the dielectric material is etched to a level below the top surface of the first fin structure 104a and the second fin structure 104b. As a result, the upper portions of the first fin structure 104a and the second fin structure 104b protrude above the isolation structure 108, and the lower portions of the first fin structure 104a and the second fin structure 104b are surrounded and covered by the isolation structure 108.

[0031] Optionally, in some other embodiments, the isolation structure 108 is first formed above the substrate 102. A trench is formed between the isolation structures 108 to expose the substrate 102. Then, a semiconductor material such as silicon, silicon germanium, or other applicable materials is grown in the trenches, for example, by using an epitaxial process to form the first fin structure 104a and the second fin structure 104b. After the first fin structure 104a and the second fin structure 104b are grown to a desired height, the isolation structure 108 is etched down to a level below the top surface of the first fin structure 104a and the second fin structure 104b. As a result, portions of the first fin structure 104a and the second fin structure 104b protrude above the isolation structure 108.

[0032] like Figure 3A As shown, a dielectric layer 302 and a polysilicon layer 304 are sequentially formed on the first fin structure 104a, the second fin structure 104b and the isolation structure 108. Then, a first hard mask layer 306a and a second hard mask layer 306b are formed on the polysilicon layer 304. The first hard mask layer 306a can be made of silicon oxide, silicon nitride, silicon oxynitride or other applicable materials. The second hard mask layer 306b can be made of silicon oxide, silicon nitride, silicon oxynitride or other applicable materials. The first hard mask layer 306a and the second hard mask layer 306b are formed by a patterning process. The patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, rinsing and drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process.

[0033] like Figure 3B As shown, according to some embodiments of the present invention, after forming the first hard mask layer 306a and the second hard mask layer 306b, a first photoresist layer 308a and a second photoresist layer 308b are formed on the second hard mask layer 306b.

[0034] In some embodiments, the first photoresist layer 308a is a carbon-rich layer such as silicon carbide (SiC or SixC). In some embodiments, the second photoresist layer 308b is a silicon-rich layer such as silicon oxide (SiOx), silicon nitride (SixNy), or silicon oxynitride (SiON).

[0035] Then, the first photoresist layer 308a and the second photoresist layer 308b are patterned to form a trench 350 in the first photoresist layer 308a and the second photoresist layer 308b. The trench has a first width W1. In some embodiments, the first width W1 is in a range from about 40 nm to about 80 nm.

[0036] like Figure 3C As shown, according to some embodiments of the present invention, after forming the trench 350, a coating 310 is conformally formed in the trench 350 and on the second photoresist layer 308b. The coating 310 is a fluoropolymer. The coating 310 is configured to reduce the width of the trench 350. After forming the coating 310, the trench 350 has a reduced second width W2. Therefore, the second width W2 is less than the second width W1.

[0037] The coating 310 is formed by a coating process using a coating gas. In some embodiments, the coating process is a plasma process. The coating gas includes a fluorine-containing gas such as tetrafluoromethane (CF4), difluoromethane (CH2F2), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), other applicable gases, or combinations thereof. The flow rate of the coating gas is in the range of from about 0.1sccm to about 100sccm. The bias voltage used in the plasma process is in the range of from 0V to 100V. The power used in the plasma process is in the range of from about 500 watts to about 1500 watts.

[0038] The coating thickness of coating 310 depends on the coating time. The coating time is in the range of from about 1 second to about 50 seconds. If the coating time is too long, coating 310 may completely fill groove 350, and thus the pattern of groove 350 cannot be used to pattern the underlying layer. If the coating time is too short, coating 310 is too thin to reduce the size of groove 350.

[0039] It should be noted that, in order to prevent some unwanted residues (from the photoresist layer 308a or 308b) from remaining in the trench 350, a pre-cleaning process is performed on the trench 350 before forming the coating layer 310. When the trench 350 is cleaned, the line end bridging problem that may be caused by the residues formed in the trench 350 is avoided.

[0040] The pre-cleaning process is performed by using a fluorine-containing gas. The fluorine-containing gas includes tetrafluoromethane (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), other applicable gases, or a combination thereof. In some embodiments, the duration of performing the pre-cleaning process is in the range of from about 1 s to about 20 s.

[0041] like Figure 3D As shown, according to some embodiments of the present invention, after forming the coating layer 310 in the trench 350, a first etching process 11 is performed to remove a portion of the coating layer 310 located on the second photoresist layer 308b. In some embodiments, the first etching process 11 is a dry etching process.

[0042] It should be noted that the portion of the coating layer 310 located on the second photoresist layer 308b is removed, but the portion of the coating layer 310 formed on the sidewall and bottom of the trench 350 remains. The remaining coating layer 310 serves to narrow the width of the trench 350. The top of the remaining coating layer 310 located on the sidewall of the trench 350 is slightly etched. Therefore, the top surface of the coating layer 310 is not parallel to the top surface of the second photoresist layer 308b.

[0043] Then, if Figure 3E As shown, according to some embodiments of the present invention, the second etching process 13 is performed to remove a portion of the coating layer 310 and the second photoresist layer 308b. In some embodiments, the second etching process 13 is also a dry etching process.

[0044] like Figure 3F As shown, according to some embodiments of the present invention, after the second etching process 13, a third etching process 15 is performed to remove the coating layer 310, the first photoresist layer 308a, a portion of the first hard mask layer 306a and a portion of the second hard mask layer 306b. In some embodiments, the third etching process 15 is a dry etching process.

[0045] It should be noted that the bottom of the trench 350 is selectively etched by the third etching process 15. In addition, the portion of the second hard mask layer 306b directly below the coating layer 310 is then etched to expose a portion of the first hard mask layer 306a. Then, the exposed first hard mask layer 306a is removed. The first hard mask layer 306a is an etch stop layer.

[0046] Results, such as Figure 3F As shown, the first hard mask layer 306a and the second hard mask layer 306b are patterned to form a trench 352. The trench 352 has a third width W3. The third width W3 is slightly greater than the second width W2, and the third width W3 is still less than the first width W1. In some embodiments, the third width W3 is in a range from about 10 nm to about 50 nm.

[0047] like Figure 3GAs shown, according to some embodiments of the present invention, after forming the trench 352, the dielectric layer 302 and the polysilicon layer 304 are patterned by using the first hard mask layer 306a and the second hard mask layer 306b as masks. As a result, the trench 354 is formed in the polysilicon layer 304. In other words, the trench 354 is referred to as an end-to-end gap.

[0048] Then, if Figure 3H As shown, according to some embodiments of the present invention, the first hard mask layer 306a and the second hard mask layer 306b on the polysilicon layer 304 as masks are removed, and a dielectric material is filled in the trench 354 (or the so-called end-to-end gap).

[0049] After the dielectric material is filled, a portion of the dielectric material outside the trench 354 is removed by a planarization process such as a chemical mechanical polishing process (CMP). As a result, an inter-layer dielectric (ILD) structure 320 is formed.

[0050] Then, if Fig. 3I As shown, according to some embodiments of the present invention, the polysilicon layer 304 and the dielectric layer 302 are removed, and a gate dielectric layer 106 and a gate electrode 110 are formed on the fin structure 104. In some embodiments, the gate dielectric layer 106 is a high dielectric constant (high-k) dielectric layer, and the gate electrode 110 is a metal gate electrode. In other words, a HK / MG stacked structure is formed on the fin structure 104.

[0051] The metal gate electrode includes an n-type work function metal or a p-type work function metal. The n-type work function metal includes tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn) or zirconium (Zr). The p-type work function metal includes titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN) or ruthenium (Ru). The metal gate is formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plating process, an electroless plating process or other applicable processes.

[0052] On the left side of the ILD structure 320, the first transistor 300a is composed of the gate dielectric layer 106, the gate electrode 110, and the source / drain (not shown). On the right side of the ILD structure 320, the second transistor 300b is composed of the gate dielectric layer 106, the gate electrode 110, and another source / drain (not shown). The first transistor 300a and the second transistor 300b are located on opposite sidewalls of the ILD structure 320. In some embodiments, the first transistor 300a is an n-type metal oxide semiconductor field effect transistor (NMOSFET), and the second transistor 300b is a p-type metal oxide semiconductor field effect transistor (PMOSFET).

[0053] like Fig. 3I As shown, the sidewall of the ILD structure 320 has a bottom and a top, the gate dielectric layer 106 covers the bottom of the sidewall of the ILD structure 320 , and the gate electrode 110 covers the top of the sidewall of the ILD structure 320 .

[0054] In some embodiments, the ILD structure 320 has a third width W3 in a range from about 20 nm to about 40 nm. In other words, an end-to-end critical dimension (CD) between the first transistor 300 a and the second transistor 300 b is defined by the third width W3 .

[0055] In some embodiments, a cap distance ( S1 ) between a sidewall of the ILD structure 320 and a sidewall of the first fin structure 104 a is in a range from about 0.01 nm to about 50 nm.

[0056] It should be noted that as the size of the FinFET device structure 100 decreases, it becomes more difficult to control the end-to-end critical dimension (CD). Therefore, the present invention uses a coating to control the end-to-end critical dimension (CD).

[0057] The coating 310 is used to reduce the width of the trench 350 from the first width W1 to the second width W2. By using the smaller second width W2, a trench 354 having a third width W3 is obtained in the polysilicon layer 304, the third width W3 being smaller than the first width W1. Thus, a smaller end-to-end critical dimension (CD) (such as Figure 3H In addition, the profile of the polysilicon layer 304 is more vertical.

[0058] Furthermore, when the end-to-end critical dimension (CD) (such as Figure 3H When the third width W3 in the embodiment is smaller, the end cap distance (S1) becomes larger. A larger end cap distance (S1) is beneficial to forming a HK / MG stacking structure.

[0059] FIG. 4A to FIG. 4GShown are cross-sectional diagrams of various stages in forming a fin field effect transistor (FinFET) device structure 100 in accordance with some embodiments of the present invention. FIG. 4A to FIG. 4G It is along Figure 2 A cross-sectional illustration taken along line BB'.

[0060] Reference Figure 4A , a fin structure 104 and an isolation structure 108 are formed on a substrate 102. A portion of the fin structure 104 protrudes above the isolation structure 108. A dielectric layer 302 and a polysilicon layer 304 are sequentially formed on the fin structure 104 and the isolation structure 108. Then, a first hard mask layer 306a and a second hard mask layer 306b are formed on the polysilicon layer 304.

[0061] like Figure 4B As shown, according to some embodiments of the present invention, after forming the second hard mask layer 306b, a photoresist layer 308 is formed on the second hard mask layer 306b. The photoresist layer 308 is a single layer or a plurality of layers.

[0062] Then, the photoresist layer 308 is patterned to form a groove 350 in the photoresist layer 308. One or more grooves 350 may be formed. The number of grooves 350 may be adjusted according to actual applications. The groove 350 has a fourth width W4. In some embodiments, the fourth width W4 is in a range from about 40 nm to about 80 nm.

[0063] like Figure 4C As shown, according to some embodiments of the present invention, after forming trench 350 in photoresist layer 308 , coating layer 310 is conformally formed in trench 350 and on photoresist layer 308 .

[0064] The coating layer 310 is a fluorine-containing polymer. The coating layer 310 is configured to reduce the width of the groove 350. After forming the coating layer 310, the groove 350 has a reduced fifth width W5. Therefore, the fifth width W5 is smaller than the fourth width W4.

[0065] In some embodiments, coating 310 is formed by a plasma process using a coating gas including a fluorine-containing gas such as tetrafluoromethane (CF4), difluoromethane (CH2F2), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), other suitable gases, or combinations thereof.

[0066] like Figure 4DAs shown, according to some embodiments of the present invention, after forming the coating layer 310, the photoresist layer 308, the coating layer 310, a portion of the first hard mask layer 306a, and a portion of the second hard mask layer 306b are etched through multiple etching processes. As a result, one or more trenches 352 are formed in the first hard mask layer 306a and the second hard mask layer 306b. The trench 352 has a sixth width W6, and the sixth width W6 is slightly greater than the fifth width W5.

[0067] Then, if Figure 4E As shown, according to some embodiments of the present invention, the dielectric layer 302 and the polysilicon layer 304 are patterned by using the first hard mask layer 306a and the second hard mask layer 306b as masks. As a result, trenches 354 (or end-to-end gaps) are formed in the polysilicon layer 304.

[0068] Then, if Figure 4F As shown, according to some embodiments of the present invention, the first hard mask layer 306 a and the second hard mask layer 306 b on the polysilicon layer 304 as masks are removed, and a dielectric material is filled in the trench 354 .

[0069] After filling the trench 354, a portion of the excess dielectric material located outside the trench 354 is removed by a planarization process such as a chemical mechanical polishing process (CMP). As a result, an inter-layer dielectric (ILD) structure 320 is formed.

[0070] Then, if Figure 4G As shown, according to some embodiments of the present invention, the polysilicon layer 304 and the dielectric layer 302 are removed, and a gate dielectric layer 106 and a gate electrode 110 are formed on the fin structure 104. In some embodiments, the gate dielectric layer 106 is a high dielectric constant (high-k) dielectric layer, and the gate electrode 110 is a metal gate electrode. In other words, a HK / MG stacked structure is formed on the fin structure 104.

[0071] like Figure 4G As shown, the gate dielectric layer 106 and the gate electrode 110 are divided into four parts, and form a first transistor 400a, a second transistor 400b, a third transistor 400c and a fourth transistor 400d respectively. The first transistor 400a is composed of the gate dielectric layer 106 and the gate electrode 110, and the second transistor 400b is composed of the gate dielectric layer 106 and the gate electrode 110.

[0072] The ILD structure 320 is located between the first transistor 400a and the second transistor 400b. In addition, the ILD structure 320 is located between the third transistor 400c and the fourth transistor 400d.

[0073] In some embodiments, a sixth width (W6) between the first transistor 400a and the second transistor 400b is in a range from about 10 nm to about 50 nm. In other words, an end-to-end critical dimension (CD) between the two transistors is defined by the sixth width W6.

[0074] It should be noted that the patterned photoresist layer 308 has a groove 350 having a width of the fourth width W4, and after the coating layer 310 is formed in the groove 350, the groove 350 has a reduced fifth width W5. The patterned photoresist layer 308 is used to pattern the first hard mask layer 306a and the second hard mask layer 306b below. Once the groove 350 has the reduced fifth width W5, the groove 352 formed in the first hard mask layer 306a and the second hard mask layer 306b also has a reduced sixth width W6. Then, the groove 354 also has a reduced sixth width W6 compared to the original fourth width W4 of the groove 350. Therefore, the end-to-end critical dimension (CD) (or the sixth width W6) is controlled by adjusting the thickness of the coating layer 310. In addition, since the polysilicon layer 304 is selectively etched by the above-mentioned etching process (such as the third etching process 15), the profile of the polysilicon layer 304 is more vertical.

[0075] An embodiment for forming a fin field effect transistor (FinFET) device structure is provided. A first fin structure and a second fin structure are formed on a substrate. A first transistor is formed on the first fin structure, and a second transistor is formed on the second fin structure. An interlayer dielectric (ILD) structure is formed between the first transistor and the second transistor. The end-to-end critical dimension (CD) between the first transistor and the second transistor is defined by the width of the ILD structure. The width of the ILD structure is defined by a first trench formed in the ILD structure, and the first trench is indirectly defined by a second trench in a photoresist layer, which is formed on a hard mask layer and the fin structure. By forming a coating in the second trench, the width of the second trench is reduced, and therefore the width of the ILD structure is indirectly reduced. Therefore, the end-to-end critical dimension (CD) is well controlled by adjusting the coating thickness of the coating.

[0076] In addition, due to the reduction of the end-to-end critical dimension, the end cap distance is large enough to form a HK / MG structure. In addition, a vertical profile of the gate structure is obtained. In addition, before forming the coating, a pre-cleaning process is performed on the second trench to remove residues, and thus the line end bridging problem is avoided.

[0077] In some embodiments, a fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a substrate and a first fin structure and a second fin structure extending above the substrate. The FinFET device structure also includes a first transistor formed on the first fin structure and a second transistor formed on the second fin structure. The FinFET device structure also includes an interlayer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 10 nm to about 50 nm.

[0078] In the above FinFET device structure, the first transistor is an n-type metal oxide semiconductor field effect transistor (NMOSFET), and the second transistor is a p-type metal oxide semiconductor field effect transistor (PMOSFET).

[0079] In the above FinFET device structure, it also includes: an isolation structure formed on the substrate, wherein the upper portion of the first fin structure and the upper portion of the second fin structure protrude from the isolation structure.

[0080] In the above-mentioned FinFET device structure, wherein the first transistor includes: a first gate dielectric layer formed on the top surface and side walls of the first fin structure; and a first gate electrode formed on the first gate dielectric layer; and wherein the second transistor includes: a second gate dielectric layer formed on the top surface and side walls of the second fin structure; and a second gate electrode formed on the second gate dielectric layer.

[0081] In the above-mentioned FinFET device structure, wherein the first transistor includes: a first gate dielectric layer formed on the top surface and side walls of the first fin structure; and a first gate electrode formed on the first gate dielectric layer; and wherein the second transistor includes: a second gate dielectric layer formed on the top surface and side walls of the second fin structure; and a second gate electrode formed on the second gate dielectric layer, wherein the side walls of the ILD structure have a bottom and a top, the first gate dielectric layer covers the bottom of the side walls of the ILD structure, and the first gate electrode covers the top of the side walls of the ILD structure.

[0082] In the above-mentioned FinFET device structure, wherein the first transistor includes: a first gate dielectric layer formed on the top surface and side walls of the first fin structure; and a first gate electrode formed on the first gate dielectric layer; and wherein the second transistor includes: a second gate dielectric layer formed on the top surface and side walls of the second fin structure; and a second gate electrode formed on the second gate dielectric layer, wherein the first gate dielectric layer and the second gate dielectric layer are high-k dielectric layers, and the first gate electrode and the second gate electrode are metal gate electrodes.

[0083] In some embodiments, a fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a substrate and an isolation structure formed on the substrate. The FinFET device structure also includes a first fin structure embedded in the isolation structure and a first transistor formed on the first fin structure. The FinFET device structure also includes a second transistor formed on the first fin structure and the isolation structure. The FinFET device structure includes an interlayer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 10 nm to about 50 nm.

[0084] In the above-mentioned FinFET device structure, wherein the first transistor includes: a first gate dielectric layer formed on the first fin structure; and a first gate electrode formed on the first gate dielectric layer; and wherein the second transistor includes: a second gate dielectric layer formed on the first fin structure and the isolation structure; and a second gate electrode formed on the second gate dielectric layer.

[0085] In the above-mentioned FinFET device structure, wherein the first transistor includes: a first gate dielectric layer formed on the first fin structure; and a first gate electrode formed on the first gate dielectric layer; and wherein the second transistor includes: a second gate dielectric layer formed on the first fin structure and the isolation structure; and a second gate electrode formed on the second gate dielectric layer, wherein the first gate dielectric layer and the second gate dielectric layer are high-k dielectric layers, and the first gate electrode and the second gate electrode are metal gate electrodes.

[0086] In the above-mentioned FinFET device structure, wherein the first transistor includes: a first gate dielectric layer formed on the first fin structure; and a first gate electrode formed on the first gate dielectric layer; and wherein the second transistor includes: a second gate dielectric layer formed on the first fin structure and the isolation structure; and a second gate electrode formed on the second gate dielectric layer, wherein the sidewall of the ILD structure has a bottom and a top, the first gate dielectric layer covers the bottom of the sidewall of the ILD structure, and the first gate electrode covers the top of the sidewall of the ILD structure.

[0087] In the above-mentioned FinFET device structure, it also includes: a second fin structure formed adjacent to the first fin structure; a third transistor formed on the isolation structure and the second fin structure; and an interlayer dielectric (ILD) structure formed in a second end-to-end gap between the second transistor and the third transistor, wherein the second end-to-end gap has a width in the range from about 10nm to about 50nm.

[0088] In some embodiments, a method for forming a fin field effect transistor device structure is provided. The method includes providing a substrate and forming a first fin structure and a second fin structure extending above the substrate. The method also includes forming a dielectric layer on the first fin structure and the second fin structure and forming a polysilicon layer, a hard mask layer and a photoresist layer on the dielectric layer. The method also includes patterning the photoresist layer to form a first groove in the photoresist layer, and the first groove has a first width. The method includes conformally forming a coating in the first groove to form a second groove in the photoresist layer, and the second groove has a second width, and the second width is less than the first width. The method also includes patterning the hard mask layer by using the photoresist layer as a mask, and patterning the polysilicon layer by using the hard mask as a mask to form an end-to-end gap between the first fin structure and the second fin structure. The end-to-end gap has a third width, and the third width is less than the first width.

[0089] In the above method, the further step includes: forming an interlayer dielectric (ILD) structure in the end-to-end gap.

[0090] In the above method, wherein the third width is in a range from about 10 nm to about 50 nm.

[0091] In the above method, before forming the coating layer in the first groove, the method further includes: cleaning the photoresist layer with a fluorine-containing gas.

[0092] In the above method, before forming the coating in the first groove, it also includes: cleaning the photoresist layer with a fluorine-containing gas, wherein the fluorine-containing gas includes tetrafluoromethane (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3) or a combination thereof.

[0093] In the above method, forming the photoresist layer includes: forming a first photoresist layer on the hard mask layer, wherein the first photoresist layer is a carbon-rich layer; and forming a second photoresist layer on the first photoresist layer, wherein the second photoresist layer is a silicon-rich layer.

[0094] In the above method, wherein forming the coating layer in the first groove includes using a coating process, and the coating process is performed by using a fluorine-containing gas.

[0095] In the above method, wherein forming the coating layer in the first groove includes using a coating process, and the coating process is performed by using a fluorine-containing gas, wherein a coating time of the coating process is in a range from about 1 second to about 50 seconds.

[0096] In the above method, forming the hard mask layer includes: forming a first hard mask layer on the polysilicon layer; and forming a second hard mask layer on the first hard mask layer.

[0097] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A fin field effect transistor (FinFET) device structure, comprising: substrate; a first fin structure and a second fin structure extending above the substrate; an isolation structure formed between the first fin structure and the second fin structure; A first transistor formed on the first fin structure; a second transistor formed on the second fin structure; a third transistor formed on the first fin structure; a first interlayer dielectric structure formed in an end-to-end gap between the first transistor and the second transistor, wherein sidewalls of the end-to-end gap are vertical sidewalls and the end-to-end gap has a width in a range from 10 nm to 50 nm; and a second interlayer dielectric structure formed between the first transistor and the third transistor, wherein the second interlayer dielectric structure is located directly above the first fin structure and a bottom surface of the second interlayer dielectric structure is above a top surface of the first fin structure, wherein the first gate dielectric layer of the first transistor and the second gate dielectric layer of the second transistor are formed as a continuous gate dielectric layer, the continuous gate dielectric layer continuously extends through the bottom of the first interlayer dielectric structure, and the first interlayer dielectric structure is disposed on the continuous gate dielectric layer, The first gate dielectric layer of the first transistor and the third gate dielectric layer of the third transistor are disconnected gate dielectric layers, and the second interlayer dielectric structure extends through the disconnected gate dielectric layers. The second interlayer dielectric structure is laterally offset from the isolation structure, and the second interlayer dielectric structure does not overlap with the isolation structure in a vertical direction, and the bottom surface of the second interlayer dielectric structure is higher than the top surface of the isolation structure.

2. The fin field effect transistor (FinFET) device structure according to claim 1, wherein: The first transistor is an n-type metal oxide semiconductor field effect transistor (NMOSFET), and the second transistor is a p-type metal oxide semiconductor field effect transistor (PMOSFET).

3. The fin field effect transistor (FinFET) device structure according to claim 1, further comprising: An isolation structure is formed on the substrate, wherein an upper portion of the first fin structure and an upper portion of the second fin structure protrude from the isolation structure.

4. The fin field effect transistor (FinFET) device structure according to claim 1, wherein: The first gate dielectric layer is formed on the top surface and sidewalls of the first fin structure, and the second gate dielectric layer is formed on the top surface and sidewalls of the second fin structure; the first transistor further includes: a first gate electrode formed on the first gate dielectric layer; and Wherein, the second transistor further comprises: A second gate electrode is formed on the second gate dielectric layer.

5. The fin field effect transistor (FinFET) device structure according to claim 4, wherein: The sidewall of the first interlayer dielectric structure has a bottom and a top, the first gate dielectric layer covers the bottom of the sidewall of the first interlayer dielectric structure, and the first gate electrode covers the top of the sidewall of the first interlayer dielectric structure.

6. The fin field effect transistor (FinFET) device structure according to claim 4, wherein: The first gate dielectric layer and the second gate dielectric layer are high-k dielectric layers, and the first gate electrode and the second gate electrode are metal gate electrodes.

7. The fin field effect transistor (FinFET) device structure according to claim 1, wherein: A capping distance between a sidewall of the first interlayer dielectric structure and a sidewall of the first fin structure is in a range from 0.01 nm to 50 nm.

8. A fin field effect transistor (FinFET) device structure, comprising: substrate; an isolation structure formed on the substrate; a first fin structure embedded in the isolation structure; A first transistor formed on the first fin structure; a second transistor formed on the first fin structure and the isolation structure; a second fin structure formed adjacent to the first fin structure; a third transistor formed on the isolation structure and the second fin structure; an isolation structure formed between the first fin structure and the second fin structure; as well as a first interlayer dielectric structure formed in a first end-to-end gap between the second transistor and the third transistor, a second interlayer dielectric structure formed in a second end-to-end gap between the first transistor and the second transistor, wherein sidewalls of the second end-to-end gap are vertical sidewalls and the second end-to-end gap has a width in a range from 10 nm to 50 nm, The second interlayer dielectric structure is located directly above the first fin structure and the bottom surface of the second interlayer dielectric structure is above the top surface of the first fin structure. wherein the second gate dielectric layer of the second transistor and the third gate dielectric layer of the third transistor are formed as a continuous gate dielectric layer, the continuous gate dielectric layer continuously extends through the bottom of the first interlayer dielectric structure, and the first interlayer dielectric structure is disposed on the continuous gate dielectric layer, The first gate dielectric layer of the first transistor and the second gate dielectric layer of the second transistor are disconnected gate dielectric layers, and the second interlayer dielectric structure extends through the disconnected gate dielectric layers. The second interlayer dielectric structure is offset from the isolation structure, and the second interlayer dielectric structure does not overlap with the isolation structure in a vertical direction, and the bottom surface of the second interlayer dielectric structure is higher than the top surface of the isolation structure.

9. The fin field effect transistor (FinFET) device structure according to claim 8, wherein: The first gate dielectric layer is formed on the first fin structure, the second gate dielectric layer is formed on the first fin structure and the isolation structure, and the first transistor further includes: a first gate electrode formed on the first gate dielectric layer; and Wherein, the second transistor further comprises: A second gate electrode is formed on the second gate dielectric layer.

10. The fin field effect transistor (FinFET) device structure according to claim 9, wherein: The first gate dielectric layer and the second gate dielectric layer are high-k dielectric layers, and the first gate electrode and the second gate electrode are metal gate electrodes.

11. The fin field effect transistor (FinFET) device structure according to claim 9, wherein: The sidewall of the second interlayer dielectric structure has a bottom and a top, the first gate dielectric layer covers the bottom of the sidewall of the second interlayer dielectric structure, and the first gate electrode covers the top of the sidewall of the second interlayer dielectric structure.

12. The fin field effect transistor (FinFET) device structure according to claim 8, wherein: The first end-to-end gap has a width in a range from 10 nm to 50 nm.

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