Semiconductor memory device

Abstract

Embodiments of the present invention provide a semiconductor memory device with a good connection between a select gate line and a contact. A semiconductor memory device according to an embodiment of the present invention includes: a plurality of first conductor layers stacked in a first direction; a first semiconductor layer extending in the first direction within the plurality of first conductor layers; a first charge accumulation layer provided between the plurality of first conductor layers and the first semiconductor layer; a plurality of second conductor layers stacked in the first direction above the plurality of first conductor layers; and a third conductor layer extending in the first direction within one or more layers of the plurality of second conductor layers other than the lowermost layer, starting from the upper surface of the lowermost layer of the plurality of second conductor layers, and contacting the upper surfaces of the respective plurality of second conductors.

Description

[0001] [Related Application]

[0002] This application claims priority based on Japanese Patent Application No. 2019-53449 (filing date: March 20, 2019). This application incorporates the entire contents of the base application by reference thereto. Technical Field

[0003] The embodiment relates to a semiconductor memory device. Background Art

[0004] As a semiconductor memory device capable of non-volatile data storage, a NAND (Not AND) flash memory is known. In a semiconductor memory device such as the NAND flash memory, in order to achieve high integration and large capacity, a three-dimensional memory structure is gradually adopted. A structure for leading out a contact connected to a laminated wiring layer in the three-dimensional memory structure is known. Summary of the Invention

[0005] The embodiment provides a semiconductor memory device with good connection between a select gate line and a contact.

[0006] A semiconductor memory device according to an embodiment includes: a plurality of first conductor layers laminated in a first direction; a first semiconductor layer extending in the first direction within the plurality of first conductor layers; a first charge accumulation layer provided between the plurality of first conductor layers and the first semiconductor layer; a plurality of second conductor layers laminated in the first direction above the plurality of first conductor layers; and a third conductor layer extending in the first direction from the upper surface of the lowermost layer among the plurality of second conductor layers and within one or more layers other than the lowermost layer among the plurality of second conductor layers, and in contact with the upper surfaces of the plurality of second conductors respectively.

[0007] Preferably, a first cross-section of the third conductor layer along the lower surface of the upper one of two adjacent ones among the plurality of second conductor layers in the first direction is similar to a second cross-section of the third conductor layer along the lower surface of the lower one of the two adjacent ones.

[0008] Preferably, the difference between the diameter of the first cross-section and the diameter of the second cross-section corresponds to the difference in length of the two adjacent second conductor layers along a second direction intersecting the first direction.

[0009] Preferably, when viewed from the first direction, the outer edge of the first cross-section is located at a substantially equal interval width from the outer edge of the second cross-section.

[0010] Preferably, the semiconductor memory device further includes a first insulator layer, which includes a first portion and a second portion. The first portion divides the plurality of second conductor layers into a first region and a second region arranged along a third direction intersecting with the first direction and the second direction. The second portion extends along the third direction and divides the first region into a third region and a fourth region arranged along the second direction.

[0011] Preferably, the third conductor layer is disposed in the third region or the fourth region of the plurality of second conductor layers.

[0012] A semiconductor memory device according to another embodiment includes: a plurality of first conductor layers stacked in a first direction; a first semiconductor layer extending in the first direction within the plurality of first conductor layers; a first charge accumulation layer disposed between the plurality of first conductor layers and the first semiconductor layer; a plurality of second conductor layers stacked in the first direction above the uppermost layer among the plurality of first conductor layers; and a first insulator layer including a first portion and a second portion. The first portion extends in a second direction intersecting with the first direction and divides the plurality of second conductor layers into a first region and a second region arranged along a third direction intersecting with the first direction and the second direction. The second portion extends along the third direction and divides the first region into a third region and a fourth region arranged along the second direction.

[0013] Preferably, the semiconductor memory device further includes a third conductor layer. The third conductor layer extends in the first direction in the third region or the fourth region of the plurality of second conductor layers and electrically connects the plurality of second conductor layers to each other.

[0014] Preferably, the third conductor layer extends in the first direction from the upper surface of the lowermost layer among the plurality of second conductor layers and within one or more layers other than the lowermost layer among the plurality of second conductor layers.

[0015] Preferably, the third conductor layer is in contact with the upper surfaces of the plurality of second conductors.

[0016] Preferably, the upper end of the third conductor layer is located above the upper surface of the uppermost layer among the plurality of second conductor layers. The semiconductor memory device further includes a fourth conductor layer, which extends in the first direction from the upper edge of the upper end of the third conductor layer and has a diameter smaller than that of the third conductor layer.

[0017] Preferably, the first portion and the second portion of the first insulator layer are arranged in a T shape when viewed from the first direction.

[0018] Preferably, the third conductor layer extends in the first direction within the plurality of second conductor layers, the lower end of the third conductor layer is located in the same layer as the lower end of the first insulator layer, and the upper end of the third conductor layer is located in the same layer as the upper end of the first insulator layer.

[0019] A semiconductor memory device according to another embodiment includes: a plurality of first conductor layers stacked in a first direction; a first semiconductor layer extending in the first direction within the plurality of first conductor layers; a first charge accumulation layer provided between the plurality of first conductor layers and the first semiconductor layer; a plurality of second conductor layers stacked in the first direction above the uppermost layer among the plurality of first conductor layers; a third conductor layer extending in the first direction within the plurality of second conductor layers and connected to each of the plurality of second conductor layers; and a first insulator layer that divides the plurality of second conductor layers into a first region and a second region along a plane including the first direction and a second direction intersecting the first direction; and the lower end of the third conductor layer is located in the same layer as the lower end of the first insulator layer, and the upper end of the third conductor layer is located in the same layer as the upper end of the first insulator layer.

[0020] Preferably, the first semiconductor layer further extends in the first direction within the plurality of second conductor layers, and the first charge accumulation layer is further provided between the plurality of second conductor layers and the first semiconductor layer.

[0021] Preferably, the semiconductor memory device further includes:

[0022] a second semiconductor layer extending in the first direction within the plurality of second conductor layers; and a second insulator layer provided between the plurality of second conductor layers and the second semiconductor layer.

[0023] Preferably, the second insulator layer includes a second charge accumulation layer.

[0024] According to the embodiment, a semiconductor memory device with good connection between the select gate line and the contact can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a block diagram showing the overall configuration of a memory system including the semiconductor memory device of the first embodiment.

[0026] Figure 2 is a circuit configuration diagram showing a part of a memory cell array of the semiconductor memory device of the first embodiment.

[0027] Figure 3It is a top view of the memory cell array of the semiconductor memory device according to the first embodiment as viewed from above.

[0028] Figure 4 It is a cross-sectional view of the cell region of the memory cell array along the Figure 3 IV-IV line.

[0029] Figure 5 It is a cross-sectional view of the lower part of the memory cell stack along the Figure 4 V-V line.

[0030] Figure 6 It is a cross-sectional view of the upper part of the memory cell stack along the Figure 4 VI-VI line.

[0031] Figure 7 It is a cross-sectional view of the wiring region of the memory cell array along the Figure 3 VII-VII line.

[0032] Figure 8 It is a top view of the region VIII of the selection gate line of Figure 3 magnified and viewed from above.

[0033] Figures 9 - 24 It is a cross-sectional view of the memory cell array for explaining the manufacturing steps of the semiconductor memory device according to the first embodiment.

[0034] Figure 25 It is a top view of the memory cell array of a comparative example for explaining the effect of the semiconductor memory device according to the first embodiment as viewed from above.

[0035] Figure 26 It is a cross-sectional view of the wiring region of the memory cell array along the Figure 25 XXVI-XXVI line.

[0036] Figure 27 It is a top view of the memory cell array of the semiconductor memory device according to the first modification of the first embodiment as viewed from above.

[0037] Figure 28 It is a cross-sectional view of the wiring region of the memory cell array along the Figure 27 XXVIII-XXVIII line.

[0038] Figure 29 It is a top view of the memory cell array of the semiconductor memory device according to the second modification of the first embodiment as viewed from above.

[0039] Figure 30 It is a cross-sectional view of the wiring region of the memory cell array along the Figure 29 XXX-XXX line.

[0040] Figure 31 This is a cross-sectional view of a wiring area of a memory cell array of a semiconductor memory device according to the second embodiment.

[0041] Figures 32 - 43 This is a cross-sectional view of a memory cell array for explaining the manufacturing steps of a semiconductor memory device according to the second embodiment. Detailed Embodiments

[0042] Hereinafter, embodiments will be described with reference to the accompanying drawings. Each embodiment illustrates a device or method for embodying the technical idea of the invention. The accompanying drawings are schematic or conceptual diagrams, and the dimensions, ratios, etc. of each drawing are not necessarily the same as the actual ones. The technical idea of the present invention is not specified by the shape, structure, configuration, etc. of the components.

[0043] In addition, in the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. The numbers after the characters of the reference symbols are referred to by the reference symbols including the same characters, and are used to distinguish between components having the same configuration. When it is not necessary to distinguish between the components denoted by the reference symbols including the same characters from each other, these components are respectively referred to by the reference symbols including only the characters.

[0044] In addition, in the following description, the "diameter" of a certain layer means the average value of the diameters on the outside of the layer in a cross-section parallel to the product layer surface of the layer. The "center" of the cross-section of a certain layer means the centroid of the cross-section.

[0045] 1. First Embodiment

[0046] A semiconductor memory device according to the first embodiment will be described.

[0047] 1.1 Configuration

[0048] First, the configuration of the semiconductor memory device according to the first embodiment will be described.

[0049] 1.1.1 Semiconductor Memory Device

[0050] Figure 1 This is a block diagram for explaining the configuration of a semiconductor memory device according to the first embodiment. The semiconductor memory device 1 is a NAND-type flash memory capable of storing data non-volatilely and is controlled by an external memory controller 2. The communication between the semiconductor memory device 1 and the memory controller 2 supports, for example, the NAND interface specification.

[0051] As Figure 1 shown, the semiconductor memory device 1 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0052] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer of 1 or more). A block BLK is a collection of a plurality of memory cells that can non-volatily store data, and is used as, for example, a unit for data deletion. In addition, a plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described below.

[0053] The command register 11 stores the command CMD received by the semiconductor memory device 1 from the memory controller 2. The command CMD includes, for example, commands for causing the sequencer 13 to perform read operations, write operations, delete operations, etc.

[0054] The address register 12 stores the address information ADD received by the semiconductor memory device 1 from the memory controller 2. The address information ADD includes, for example, a block address BA, a page address PA, and a column address CA. For example, the block address BA, the page address PA, and the column address CA are used for selecting the block BLK, the word line, and the bit line, respectively.

[0055] The sequencer 13 controls the overall operation of the semiconductor memory device 1. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, the sense amplifier module 16, etc. based on the command CMD stored in the command register 11, and performs read operations, write operations, delete operations, etc.

[0056] The driver module 14 generates the voltages used in read operations, write operations, delete operations, etc. And the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line based on, for example, the page address PA stored in the address register 12.

[0057] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BA stored in the address register 12. And the row decoder module 15 transmits the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0058] The sense amplifier module 16 applies the desired voltage to each bit line according to the write data DAT received from the memory controller 2 in a write operation. In addition, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line in a read operation, and transmits the determination result as the read data DAT to the memory controller 2.

[0059] The semiconductor memory device 1 and the memory controller 2 described above may also be combined to form one semiconductor device. As such a semiconductor device, for example, an SD TMA memory card such as a Secure Digital card, or a solid state drive (SSD), etc.

[0060] 1.1.2 Circuit Configuration of Memory Cell Array

[0061] Figure 2 It is a circuit diagram for explaining the configuration of the memory cell array of the semiconductor memory device according to the first embodiment. Figure 2 It represents one block BLK among the multiple blocks BLK included in the memory cell array 10.

[0062] As Figure 2 shown, the block BLK includes, for example, 4 string components SU0 to SU3. Each string component SU includes a plurality of NAND strings NS respectively associated with bit lines BL0 to BLm (m is an integer of 1 or more). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, and selection transistors ST1 and ST2. The memory cell transistor MT includes a control gate and a charge accumulation layer, and stores data non-volatilely. The selection transistors ST1 and ST2 are respectively used for selecting the string component SU during various operations.

[0063] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. The drain of the selection transistor ST1 is connected to the associated bit line BL, and the source of the selection transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MT7. The drain of the selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source of the selection transistor ST2 is connected to the source line SL.

[0064] In the same block BLK, the control gates of the memory cell transistors MT0 to MT7 are commonly connected to the word lines WL0 to WL7 respectively. The gates of the selection transistors ST1 in the string components SU0 to SU3 are commonly connected to the selection gate lines SGD0 to SGD3 respectively. The gate of the selection transistor ST2 is commonly connected to the selection gate line SGS.

[0065] In the circuit configuration of the memory cell array 10 described above, the bit line BL is shared by the NAND strings NS assigned the same column address in each string component SU. The source line SL is shared, for example, among multiple blocks BLK.

[0066] A set of multiple memory cell transistors MT connected in a string component SU to a common word line WL is, for example, referred to as a cell component CU. For example, the storage capacity of the cell component CU including the memory cell transistors MT each storing 1-bit data is defined as "1 page of data". The cell component CU can have a storage capacity of 2 pages of data or more according to the number of bits of data stored in the memory cell transistors MT.

[0067] In addition, the circuit configuration of the memory cell array 10 included in the semiconductor memory device 1 of the first embodiment is not limited to the configuration described above. For example, the number of memory cell transistors MT, selection transistors ST1, and ST2 included in each NAND string NS can be designed to be any number respectively. The number of string components SU included in each block BLK can be designed to be any number.

[0068] 1.1.3 Structure of Memory Cell Array

[0069] Hereinafter, an example of the structure of the memory cell array of the semiconductor memory device of the first embodiment will be described.

[0070] In addition, in the following drawings to be referred to, the X-axis corresponds to the extending direction of the word line WL, the Y-axis corresponds to the extending direction of the bit line BL, and the Z-axis corresponds to the vertical direction with respect to the surface of the semiconductor substrate forming the semiconductor memory device 1. In the top view, in order to easily observe the drawing, shading is appropriately added. The shading added in the top view does not necessarily relate to the raw materials or characteristics of the components with shading. In the cross-sectional view, in order to easily observe the drawing, components such as insulator layers (interlayer insulating films), wirings, and contacts are appropriately omitted.

[0071] 1.1.3.1 Planar Layout

[0072] Figure 3 is a top view for explaining the planar layout of the memory cell array of the semiconductor memory device of the first embodiment. In Figure 3 , as an example, a cell region CA including a structure corresponding to string components SU0 to SU3 in a certain block BLK and a part of a wiring region HA for leading out contacts CC from the stacked wiring layers of each string component SU are shown.

[0073] As shown in Figure 3As shown, the memory cell array 10 includes, for example, a slit SHE, a plurality of slits SLT, memory columns MP, contacts CP and CC, bit lines BL, and a stacked wiring layer. The slit SHE includes a plurality of slits SHE_X and a slit SHE_Y. The plurality of stacked wiring layers include, for example, three selection gate lines SGD (including SGD0 to SGD3 and SGDX located on the same layer), seven word lines WL0 to WL7, and one selection gate line SGS. The plurality of memory columns MP, contacts CP, and bit lines BL are provided in the cell region CA, and the plurality of contacts CC are provided in the wiring region HA.

[0074] The plurality of stacked wiring layers are stacked along the Z axis in the order of the selection gate line SGS, the word lines WL0 to WL7, and the selection gate line SGD from the semiconductor substrate side.

[0075] The plurality of slits SLT each extend along a specified direction (the X axis in Figure 3 ), and are arranged along a direction intersecting the specified direction (the Y axis, which is orthogonal to the X axis in Figure 3 ). The plurality of slits SHE_X also each extend along the X axis and are arranged in the Y direction between adjacent slits SLT. The slit SHE_Y extends along the Y axis, and both ends reach adjacent slits SLT. The width of the slit SLT is, for example, larger than the width of the slit SHE. The slit SLT, and SHE_X and SHE_Y include insulators. The slit SLT, for example, Figure 4 breaks the stacked wiring layers corresponding to the word lines WL, the selection gate lines SGD, and the selection gate line SGS, etc., which will be described below. That is, the slit SLT insulates and separates the string components SU0 to SU3 from other string components (not shown) adjacent to these string components SU0 to SU3. In addition, the slits SHE_X and SHE_Y break the stacked wiring layer corresponding to the selection gate line SGD into the selection gate lines SGD0 to SGD3 corresponding to the respective string components SU0 to SU3 and the selection gate line SGDX not corresponding to any string component SU, and insulate and separate them.

[0076] In this way, the regions separated by the slit SLT and SHE_X and SHE_Y constitute the respective string components SU0 to SU3. As a whole, the memory cell array 10 is repeatedly arranged along the Y axis in the same layout as Figure 3 shown.

[0077] In Figure 3In the cell region CA, a plurality of memory columns MP are arranged in a 16-column staggered pattern, for example, in the region between adjacent slits SLT. That is, in each string component SU0 to SU3, a plurality of memory columns MP are arranged in a 4-column staggered pattern. Each of the plurality of memory columns MP has a portion formed in the memory hole (lower column LP) and a portion formed in the SGD hole (upper column UP). The upper column UP is provided in a layer above the lower column LP. For example, the diameter of the upper column UP is smaller than that of the lower column LP.

[0078] That is, when looking down at the memory cell array plane from above, the corresponding upper column UP and the lower column LP have an overlapping portion. In this top view, the central axis of the corresponding upper column UP and the central axis of the lower column LP may or may not overlap. In addition, here, the central axis is defined as the axis passing through the center of any XY cross-section of the upper column UP and the lower column LP along the Z-axis. Any XY cross-section is, for example, the surface where the upper column UP and the lower column LP are in contact. In Figure 3 the top view, the lower column LP is arranged so as not to overlap with the slit SHE_X. In addition, regarding the memory column MP arranged near the slit SHE_X or the slit SLT, the central axis of the upper column UP is arranged to be offset in a direction away from the nearby slit SHE_X or SLT with respect to the central axis of the lower column LP. In this way, in the semiconductor memory device 1 of the first embodiment, the slit SHE_X or SLT can be designed with a layout that avoids contact with the memory column MP.

[0079] A plurality of bit lines BL extend along the Y-axis and are arranged along the X-axis. In a top view, each bit line BL is arranged so as to overlap at least one upper column UP in each string component SU, and two bit lines BL overlap on each upper column UP. A contact CP is provided between one of the plurality of bit lines BL overlapping the upper column UP and the upper column UP. The string component SU is electrically connected to the corresponding bit line BL via the contact CP formed on the upper column UP.

[0080] In Figure 3 the wiring region HA, the portion corresponding to the selection gate line SGDX in the three-layer selection gate lines SGD is formed in a stepped shape along the X-axis in a direction away from the cell region CA. That is, in a top view, the lower the wiring layer among the three-layer stacked wiring layers constituting the selection gate line SGDX, the longer it is along the X-axis, and has a region that does not overlap with the upper wiring layer.

[0081] The group of word lines WL5 to WL7, the group of word lines WL2 to WL4, and the selection gate line SGS and the group of word lines WL0 to WL1 form a stepped shape along the X-axis. That is, in a top view, the group of word lines WL5 to WL7 is longer than the selection gate line SGD along the X-axis and has a region A that does not overlap with the selection gate line SGD. The group of word lines WL2 to WL4 is longer than the group of word lines WL5 to WL7 along the X-axis and has a region B that does not overlap with the region A of the group of word lines WL5 to WL7. The selection gate line SGS and the group of word lines WL0 to WL1 are longer than the group of word lines WL2 to WL4 along the X-axis and have a region C that does not overlap with the region B of the group of word lines WL2 to WL4.

[0082] In addition, the group of word lines WL5 to WL7, the group of word lines WL2 to WL4, and the selection gate line SGS and the group of word lines WL0 to WL1 further form a stepped shape along the Y-axis at the ends of the stepped shape along the X-axis. That is, in region A, word line WL6 has a region T_WL6 that does not overlap with the region T_WL7 of word line WL7, word line WL5 has a region T_WL5 that does not overlap with regions T_WL6 and T_WL7, and regions T_WL5 to T_WL7 are arranged along the Y-axis. In region B, word line WL3 has a region T_WL3 that does not overlap with the region T_WL4 of word line WL4, word line WL2 has a region T_WL2 that does not overlap with regions T_WL3 and T_WL4, and regions T_WL2 to T_WL4 are arranged along the Y-axis. In region C, word line WL0 has a region T_WL0 that does not overlap with the region T_WL1 of word line WL1, the selection gate line SGS has a region T_SGS that does not overlap with regions T_WL0 and T_WL1, and regions T_SGS, T_WL0, and T_WL1 are arranged along the Y-axis.

[0083] Contact points CC_SGD0 to CC_SGD3, CC_WL0 to CC_WL7, and CC_SGS are respectively provided on the selection gate lines SGD0 to SGD3, on the regions T_WL0 to T_WL7 of the word lines WL0 to WL7, and on the region T_SGS of the selection gate line SGS. The contact points CC_SGD0 to CC_SGD3 are respectively in contact with the upper surfaces of the respective layers of the three-layer stacked wiring layer of the selection gate lines SGD0 to SGD3. The diameter of the contact point CC_SGD on the upper surface of the uppermost layer of the selection gate line SGD is larger than the diameters of the contact points CC_WL and CC_SGS. Regarding the diameter of the contact point CC_SGD, it is described in detail in Figure 8 is described in detail.

[0084] In addition, the planar layout of the memory cell array 10 described above is only an example and is not limited to this. For example, the number of slits SHE arranged between adjacent slits SLT or the number of string components SU can be designed arbitrarily. In addition, the number and arrangement of memory columns MP, or the bit lines BL connected to the memory columns MP, etc. can also be designed arbitrarily. In addition, the number of steps of the step shape along the Y axis in the arrangement of the regions T_SGS and T_WL0~W_TL7 can also be designed arbitrarily, and the step difference can also be not set along the Y axis.

[0085] 1.1.3.2 Unit area

[0086] Figure 4 It means that along the IV-IV line Figure 3 An example of a cross-sectional structure obtained by cutting the memory cell array 10 of the semiconductor memory device according to the first embodiment. Figure 4 As shown, a conductive layer 21 is provided above the semiconductor substrate 20 via an insulator layer (not shown). A circuit such as the sense amplifier module 16 can be provided on the insulator layer. The conductive layer 21 is formed, for example, in a plate shape extending along the XY plane, and serves as a source line SL. The conductive layer 21 includes, for example, silicon (Si).

[0087] A conductive layer 22 is provided above the conductive layer 21 via an insulating layer (not shown). The conductive layer 22 serves as a selection gate line SGS.

[0088] A plurality of insulating layers (not shown) and conductive layers 23 are alternately stacked on the conductive layer 22. The conductive layers 23 are used as word lines WL0 to WL7 in order from the semiconductor substrate 20. The conductive layers 22 and 23 are formed in a plate shape extending along the XY plane, for example, and contain tungsten (W).

[0089] On top of the conductor layer 23 stacked on the top layer, multiple layers of insulator layers (not shown) and conductor layers 24 are alternately stacked. The Z-direction spacing between the top conductor layer 23 and the bottom conductor layer 24 is greater than the Z-direction spacing between adjacent conductor layers 23 or between conductor layers 24. In other words, the thickness of the insulator layer (INS, not shown) between the top conductor layer 23 and the bottom conductor layer 24 is thicker than the thickness of the insulator layer between adjacent conductor layers 23 or between conductor layers 24. The stacked multiple conductor layers 24 are used as selection gate lines SGDa, SGDb, and SGDc in order from the semiconductor substrate 20 side, and the selection transistor ST1 is provided in the portion of the upper pillar UP corresponding to the selection gate lines SGDa to SGDc. The conductor layer 24 is formed, for example, in a plate shape extending along the XY plane, and contains, for example, tungsten (W).

[0090] Above the conductor layer 24 laminated on the uppermost layer, a conductor layer 25 is provided with an intervening insulator layer (not shown). For example, the conductor layer 25 extends along the Y axis, and a plurality of conductors are arranged linearly along the X axis and each serves as a bit line BL. The conductor layer 25 contains, for example, copper (Cu).

[0091] The memory pillar MP is provided to extend along the Z axis. Specifically, the lower pillar LP in the memory pillar MP penetrates the conductor layers 22 and 23, and the bottom contacts the conductor layer 21. The upper pillar UP in the memory pillar MP penetrates the conductor layer 24 and contacts the lower pillar LP.

[0092] In addition, the lower pillar LP in the memory pillar MP contains, for example, a core component 30, a semiconductor layer 31, a laminated film 32, and a semiconductor portion 33, and the upper pillar UP contains, for example, a core component 40, a semiconductor layer 41, a semiconductor layer 42, a laminated film 43, and a semiconductor portion 44. The upper pillar UP is formed such that a part of the semiconductor layer 41 is embedded in the upper end of the lower pillar LP, whereby good electrical connection with the lower pillar LP can be achieved.

[0093] The core component 30 of the lower pillar LP extends along the Z axis, and its upper end is, for example, located above the uppermost conductor layer 23, and the lower end of the core component 30 of the upper pillar UP is, for example, located within the layer of the conductor layer 21. The core component 30 contains, for example, an insulator such as silicon dioxide (SiO2).

[0094] The semiconductor layer 31 covers the bottom surface and side surface of the core component 30 and, for example, includes a cylindrical portion. The lower end of the semiconductor layer 31 contacts the conductor layer 21, and its upper end is located above the uppermost conductor layer 23.

[0095] The laminated film 32 covers the side surface and bottom surface of the semiconductor layer 31, except for the portion where the conductor layer 21 contacts the semiconductor layer 31, and, for example, includes a cylindrical portion. Regarding the layer structure of the laminated film 32, detailed description is given by using Figure 5 the description.

[0096] The semiconductor portion 33 covers the upper surface of the core component 30 and contacts the inner wall portion of the semiconductor layer 31 above the core component 30 and the lower end of the semiconductor layer 41 formed directly above the semiconductor portion 33. The semiconductor portion 33 is, for example, cylindrical.

[0097] The core component 40 is provided to extend along the Z axis. The lower end of the core component 40 is located between the uppermost conductor layer 23 and the lowermost conductor layer 24. The upper end of the core component 40 is located above the layer where the uppermost conductor layer 24 is provided.

[0098] The semiconductor layer 41 covers the side and bottom surfaces of the core component 40 and includes, for example, a cylindrical portion. The lower end of the semiconductor layer 41 is in contact with the semiconductor portion 33 to electrically connect it to the lower column LP, and its upper end is located above the uppermost conductor layer 24.

[0099] The semiconductor layer 42 includes a cylindrical portion that covers the side surface of at least the portion of the semiconductor layer 41 that crosses the conductor layer 24.

[0100] The stacked film 43 is a gate insulating film of the select transistor, covers the side surface of the semiconductor layer 42, and includes a cylindrical portion. Regarding the layer structure of the stacked film 43, detailed description will be given using Figure 7 the description.

[0101] The semiconductor portion 44 covers the upper surface of the core component 40 and is in contact with the inner wall of the portion of the semiconductor layer 41 that is disposed above the core component 40. The semiconductor portion 44 is, for example, formed in a cylindrical shape and reaches the upper end of the upper column UP.

[0102] Columnar contacts CP are provided on the upper surfaces of the semiconductor layer 41, the semiconductor layer 42, and the semiconductor portion 44 within the memory column MP. In Figure 4 the cross-sectional view, the contacts CP corresponding to two of the four memory columns MP are shown. The remaining two memory columns MP where the contacts CP are not shown are provided with contacts CP on Figure 4 the cross-section on the depth side or the front side. The upper surface of each contact CP is in contact with and electrically connected to a corresponding one of the conductor layers 25 (bit lines BL).

[0103] The slit SLT is formed, for example, by extending in a plate shape along the XZ plane and interrupts the conductor layers 22 - 24 in the Y direction. The upper end of the slit SLT is located between the conductor layer 24 and the conductor layer 25. The lower end of the slit SLT is, for example, located in the layer where the conductor layer 21 is provided. The slit SLT includes, for example, an insulator such as silicon oxide.

[0104] The slit SHE_X is formed, for example, by extending in a plate shape along the XZ plane and interrupts the conductor layer 24 in the Y direction. The upper end of the slit SHE_X is located between the conductor layer 24 and the conductor layer 25. The lower end of the slit SHE_X is, for example, located between the layer where the uppermost conductor layer 23 is provided and the layer where the conductor layer 24 is provided. The slit SHE_X includes, for example, an insulator such as silicon oxide.

[0105] The upper end of the slit SLT, the upper end of the slit SHE_X, and the upper end of the memory column MP may or may not be aligned.

[0106] Figure 5 is along the V - V line of Figure 4An XY cross-sectional view obtained by cutting the memory column MP shows an example of the cross-sectional structure of the conductive layer 23 including the lower column LP and its periphery.

[0107] As Figure 5 shown, the core component 30 is disposed at approximately the center of the lower column LP. Further, around the core component 30, a semiconductor layer 31 and a stacked film 32 are disposed in concentric circles. That is, the semiconductor layer 31 and the stacked film 32 are formed along the Z direction so as to surround the entire side surface of the core component 30. The stacked film 32 is a film in which a tunnel insulating film 35, an insulating film 36, and a barrier insulating film 37 are stacked in this order.

[0108] The tunnel insulating film 35 and the barrier insulating film 37 each contain, for example, silicon oxide, and the insulating film 36 contains, for example, silicon nitride (SiN).

[0109] Figure 6 is an XY cross-sectional view obtained by cutting the Figure 4 memory column MP along the line VI-VI, showing an example of the cross-sectional structure of the upper column UP.

[0110] As Figure 6 shown, the core component 40 is disposed at approximately the center of the upper column UP. Further, around the core component 40, a semiconductor layer 41, a semiconductor layer 42, and a stacked film 43 are disposed in concentric circles. That is, the semiconductor layer 41, the semiconductor layer 42, and the stacked film 43 are formed along the Z direction so as to surround the entire side surface of the core component 40. The stacked film 43 is a film in which a tunnel insulating film 45, an insulating film 46, and a barrier insulating film 47 are stacked in this order.

[0111] The tunnel insulating film 45 and the barrier insulating film 47 each contain, for example, silicon oxide, and the insulating film 46 contains, for example, silicon nitride (SiN).

[0112] In the structure of the memory column MP described above, the portion where the memory column MP intersects with the conductive layer 22 functions as the selection transistor ST2. The portion where the memory column MP intersects with the conductive layer 23 functions as the memory cell transistor MT. The portion where the memory column MP intersects with the conductive layer 24 functions as the selection transistor ST1.

[0113] That is, the semiconductor layer 31 serves as the channel for each of the memory cell transistor MT and the selection transistor ST2. The insulating film 36 serves as the charge accumulation layer for the memory cell transistor MT and the selection transistor ST2. The semiconductor layer 41 serves as the channel for the selection transistor ST1 and the electrical connection portion between the upper column UP and the lower column LP. The insulating film 46 serves as the charge accumulation layer for the selection transistor ST1. Thus, the memory column MP functions as, for example, one NAND string NS.

[0114] In addition, the structure of the memory cell array 10 described above is only an example, and the memory cell array 10 may have other structures. For example, the number of conductor layers 23 is designed based on the number of word lines WL. The number of select gate lines SGD is not limited to three layers and can be designed to any number of layers. Multiple conductor layers 22 arranged in multiple layers can also be assigned to the select gate line SGS. When the select gate line SGS is arranged in multiple layers, conductors different from the conductor layer 22 can also be used. The memory cell pillar MP and the conductor layer 25 can be electrically connected via two or more contacts, or can be electrically connected via other wirings. A variety of insulators can also be included in the slit SLT.

[0115] 1.1.3.3 Wiring Area

[0116] Figure 7 Shows an example of a cross-sectional structure obtained by cutting the memory cell array 10 of the semiconductor memory device of the first embodiment along line VII-VII. As Figure 3 shown, the conductor layers 21 to 24 extend along the X axis and reach the wiring area HA. Figure 7 As shown, the conductor layers 21 to 24 extend along the X axis and reach the wiring area HA.

[0117] Columnar contacts CC_WL1, CC_WL4, and CC_WL7 are respectively provided on the upper surfaces of the conductor layers 23 serving as the word lines WL1, WL4, and WL7. The upper surfaces of the contacts CC_WL1, CC_WL4, and CC_WL7 are respectively in contact with and electrically connected to the corresponding one conductor layer 80_1, 80_4, and 80_7. In addition, on the upper surfaces of the conductor layers 23 of the word lines WL0, WL3, and WL6 among the remaining word lines WL of the contact CC_WL (not shown), in Figure 7 the cross-section near the front side, contacts CC_WL0, CC_WL3, and CC_WL6 are respectively provided. In addition, on the upper surfaces of the conductor layer 22 serving as the select gate line SGS and the conductor layers 23 serving as the word lines WL2 and WL5, in the cross-section closer to the front side of the cross-section where the contacts CC_WL0, CC_WL3, and CC_WL6 are provided, contacts CC_SGS, CC_WL2, and CC_WL5 are respectively provided.

[0118] Columnar contacts CC_SGD are provided in contact with the upper surfaces of the three-layer conductor layers 24 serving as the select gate lines SGDa, SGDb, and SGDc. In Figure 7 the cross-sectional view, the contact CC_SGD0 corresponding to the string component SU0 among the four contacts CC_SGD is shown. The remaining three contacts CC_SGD1 to CC_SGD3 (not shown) are provided in Figure 7 the cross-section near the front side. The upper surface of each contact CC_SGD is in contact with and electrically connected to the corresponding one conductor layer 81.

[0119] The contact CC_SGD has a cross-section with a diameter Δ1 along the lower surface of the selection gate line SGDb of the second layer from the bottom, a cross-section with a diameter Δ1 + 2Δ2 greater than the diameter Δ1 along the lower surface of the selection gate line SGDc of the third layer (uppermost layer) from the bottom, and a diameter Δ3 greater than the diameter Δ1 + 2Δ2 along the upper surface of the uppermost selection gate line SGDc. The XY cross-section of the contact CC_SGD on the lower surface of the selection gate line SGDb is similar to the XY cross-section of the contact CC_SGD on the lower surface of the selection gate line SGDc and is centered in a plan view.

[0120] The slit SHE_Y is formed, for example, by extending in a plate shape along the YZ plane and divides the conductor layer 24 in the X direction. The slit SHE_Y has, for example, an upper end and a lower end at the same height as the slit SHE_X and contains an insulator such as silicon oxide, like the slit SHE_X.

[0121] The three-layer conductor layer 24 is divided by the slit SHE_Y into a portion including the selection gate lines SGDa to SGDc and a portion including the selection gate line SGDX. In the portion including the selection gate line SGDX, the lowermost conductor layer 24 is only longer than the conductor layer 24 of the second layer from the bottom by a difference δ1 along the X axis, and the conductor layer 24 of the second layer from the bottom is only longer than the uppermost conductor layer 24 by a difference Δ2 along the X axis. In this way, the difference Δ2 in the length along the X axis between the conductor layer 24 of the second layer from the bottom and the uppermost conductor layer 24 corresponds to the difference (2Δ2) in the diameter of the contact CC_SGD along the lower surface of the conductor layer 24 of the second layer from the bottom and the diameter of the contact CC_SGD along the lower surface of the uppermost conductor layer 24. In addition, the difference δ1 can also be "0" (that is, the lowermost conductor layer 24 and the conductor layer 24 of the second layer from the bottom can also have the same length along the X axis).

[0122] Figure 8 Shows an example of a plan view of the enlarged area VIII of the three-layer selection gate line SGD in the first embodiment and viewed from above. In Figure 3 the contact CC_SGD and the interlayer insulator layer are omitted, and the outer edge of the surface with the diameter Δ3 of the contact CC_SGD in contact with the upper surface of the uppermost conductor layer 24 is indicated by a single-dot chain line. Figure 8

[0123] As Figure 8 ​As shown, through holes with a diameter of Δ1 + 2Δ2 are formed in the topmost conductor layer 24 serving as the selection gate line SGDc. Through holes with a diameter of Δ1 are formed in the second layer from the bottom of the conductor layer 24 serving as the selection gate line SGDb. The through holes with a diameter of Δ1 + 2Δ2 are similar in shape to the through holes with a diameter of Δ1, and in a top view, the centers of the through holes with a diameter of Δ1 + 2Δ2 coincide with the centers of the through holes with a diameter of Δ1.

[0124] In Figure 8 the example of, the case where the through holes with a diameter of Δ1 and the through holes with a diameter of Δ1 + 2Δ2 are circular has been described, but it is not limited thereto. For example, the through holes with a diameter of Δ1 and the through holes with a diameter of Δ1 + 2Δ2 can take any shape such as a rectangle. In addition, in Figure 8 , the outer edge of the surface of the contact CC_SGD in contact with the upper surface of the topmost conductor layer 24 can take any shape within the range including the through holes with a diameter of Δ1 + 2Δ2, but it does not necessarily need to be the same as the shapes of the through holes with a diameter of Δ1 and the through holes with a diameter of Δ1 + 2Δ2, nor does it need to coincide with their centers.

[0125] 1.2 Method for manufacturing a semiconductor memory device

[0126] Hereinafter, an example of a series of manufacturing steps from the formation of the stacked structure corresponding to the word line WL to the formation of the contact CC_SGD corresponding to the selection gate line SGD of the semiconductor memory device according to the first embodiment will be described. Figures 9 - 24 FIGS. respectively show an example of the cross-sectional structure of a structure including a structure corresponding to a memory cell array in the manufacturing steps of the semiconductor memory device according to the first embodiment. In addition, in the cross-sectional views of the manufacturing steps referred to below, a cross-section perpendicular to the surface of the semiconductor substrate 20 is included. In addition, the regions shown in the cross-sectional views of each manufacturing step include the regions where the contacts CC_WL1, CC_WL4, CC_WL7, CC_SGD0 and the slit SHE_Y in the wiring region HA, and one memory cell pillar MP in the cell region CA are formed.

[0127] First, as Figure 9 shown, after stacking the sacrificial material 52 corresponding to the selection gate line SGS and the sacrificial material 53 corresponding to the word line WL, a stepped structure is formed in the portions of the wiring region HA corresponding to regions A to C.

[0128] Specifically, first, an insulator layer 50 and a conductor layer 21 are sequentially stacked on the semiconductor substrate 20. An insulator layer 51 and a sacrificial material 52 are stacked on the conductor layer 21, and the insulator layer 51 and the sacrificial material 53 are alternately stacked multiple times on the sacrificial material 52.

[0129] Subsequently, a mask (not shown) is provided on the upper surface of the sacrificial material 53, and a pattern is formed in a portion of the mask corresponding to regions A to C by photolithography. Thereafter, the following operations are repeatedly performed in sequence: anisotropic etching of the stacked structures of the sacrificial materials 52 and 53 and the insulator layer 51 based on the obtained pattern; and removal of a part of the mask pattern by thinning the mask pattern. Thus, etching can be performed such that portions corresponding to regions A to C in the stacked structure become stepped in the X direction and the Y direction. The anisotropic etching in this step is, for example, RIE (Reactive Ion Etching).

[0130] Thereafter, the stepped structure is embedded up to the position of the uppermost sacrificial material 53 by the insulator layer 54, and the insulator layer 55 is stacked on the insulator layer 54 and the uppermost sacrificial material 53. The insulator layers 51, 54, and 55 contain, for example, silicon oxide (SiO2). The number of formed layers of the sacrificial materials 52 and 53 corresponds to the number of the selected gate lines SGS and word lines WL stacked. The sacrificial materials 52 and 53 contain, for example, silicon nitride (SiN).

[0131] Next, as Figure 10 shown, memory holes H0 corresponding to the lower pillars LP are formed. Specifically, first, a mask having an opening in a region corresponding to the memory holes H0 is formed by photolithography. Then, the memory holes H0 are formed by anisotropic etching using the formed mask.

[0132] The memory holes H0 formed in this step penetrate through the insulator layer 51, the sacrificial materials 52 and 53, and the insulator layer 55, and reach the conductor layer 21. The anisotropic etching in this step is, for example, RIE.

[0133] Next, as Figure 11 shown, a stacked structure in the memory holes H0, i.e., the lower pillars LP, is formed.

[0134] Specifically, a stacked film 32 is formed by sequentially forming a barrier insulating film 37, an insulating film 36, and a tunnel insulating film 35 on the side surface and the bottom surface of the memory holes H0 and on the upper surface of the insulator layer 55. Then, after removing the stacked film 32 at the bottom of the memory holes H0, a semiconductor layer 31 and a core component 30 are sequentially formed to fill the memory holes H0. Thereafter, the core component 30 from the upper end of the memory holes H0 to a specified depth and the portion remaining above the insulator layer 54 are removed together.

[0135] Subsequently, a semiconductor portion 33 is formed to fill the memory holes H0. Thereafter, the semiconductor portion 33, the semiconductor layer 31, and the stacked film 32 remaining above the insulator layer 54 are removed. Thus, the lower pillars LP are formed.

[0136] Next, as Figure 12 shown, after forming the insulator layer 56 on the upper surfaces of the lower pillar LP and the insulator layer 55, the sacrificial material 57 corresponding to the select gate line SGD and the insulator layer 58 are alternately laminated. An insulator layer 59 is formed on the upper layer of the topmost sacrificial material 57. The insulator layers 56, 58, and 59 contain silicon oxide, and the sacrificial material 57 contains silicon nitride.

[0137] Next, as Figure 13 shown, the insulator layer 59 and the topmost sacrificial material 57 corresponding to the regions A to C are removed. Specifically, a mask (not shown) is provided on the upper surface of the insulator layer 59, and the portions corresponding to the regions A to C in the mask are removed by photolithography. Thereafter, anisotropic etching is performed on the insulator layer 59 and the sacrificial material 57 based on the obtained mask. The position of the end portion of the sacrificial material 57 extending along the Y axis formed by this step corresponds to the position of the end portion of the lowermost conductor layer 24.

[0138] Next, as Figures 14 - 16 shown, a stepped shape is formed at the end portions of the three-layer sacrificial material 57 in the wiring region HA, and a hole for allowing the contact CC_SGD to reach the lowermost conductor layer 24 is formed.

[0139] Specifically, as Figure 14 shown, a mask pattern is formed by photolithography, and the mask pattern removes the portions corresponding to the regions within δ1 from the end of the sacrificial material 57 along the X axis and the portion corresponding to the region of the predetermined diameter Δ1 on the upper surface of the lowermost conductor layer 24 that is contacted by the contact CC_SGD among the masks formed by the steps described in Figure 13 . Thereafter, anisotropic etching is performed on the insulator layer 59 and the sacrificial material 57 based on the obtained mask pattern. As a result, the end portion of the topmost sacrificial material 57 is shortened by only δ1 along the X axis. In addition, a hole H1 including a through hole having a diameter Δ1 is formed in the topmost sacrificial material 57. The anisotropic etching in this step is, for example, RIE.

[0140] Subsequently, as Figure 15As shown, by refining the mask pattern on the insulator layer 59, the portion of the mask pattern corresponding to the region within Δ2 from the end of the uppermost sacrificial material 57 along the X-axis and the portion corresponding to the region isotropically expanded by only Δ2 from the outer edge of the hole H1 are removed. Thereafter, anisotropic etching is performed on the insulator layer 59 and the sacrificial material 57 based on the obtained mask pattern. As a result, the end of the uppermost sacrificial material 57 is further shortened by only Δ2 along the X-axis, and the end of the sacrificial material 57 in the second layer from the bottom is shortened by only δ1 along the X-axis. In addition, a hole H2 is formed, which includes a through hole with a diameter of Δ1 + 2Δ2 formed in the uppermost sacrificial material 57 and a through hole with a diameter of Δ1 formed in the sacrificial material 57 in the second layer from the bottom. The anisotropic etching in this step is, for example, RIE.

[0141] Subsequently, as Figure 16 shown, the sacrificial material 57 removed by the steps described in Figure 14 and Figure 15 and the portions of the insulator layers 58 and 59 are embedded in the insulator layer 60.

[0142] Next, as Figure 17 shown, an SGD hole H3 corresponding to the upper pillar UP is formed. Specifically, first, a mask that opens the region corresponding to the SGD hole H3 is formed by photolithography. Then, the SGD hole H3 is formed by anisotropic etching using the formed mask.

[0143] The SGD hole H3 penetrates the insulator layers 59, 58, and 56, and the sacrificial material 57, and reaches the semiconductor portion 33 of the lower pillar LP. The anisotropic etching in this step is, for example, RIE.

[0144] Next, as Figure 18 shown, a laminated structure within the SGD hole H3 is formed. Specifically, first, a laminated film 43 is formed by sequentially forming a barrier insulating film 47, an insulating film 46, and a tunnel insulating film 45, and then a semiconductor layer 42 is formed. Then, the semiconductor layer 42 and the laminated film 43 at the bottom of the SGD hole H3 are removed by anisotropic etching (e.g., RIE) to expose the upper surface of the semiconductor portion 33.

[0145] Subsequently, a semiconductor layer 41 is formed within the SGD hole H3 and is connected to the semiconductor portion 33. Thus, the semiconductor layer 31 and the semiconductor layer 41 become a current path (channel path) for the cell current flowing through the memory pillar MP via the semiconductor portion 33.

[0146] Subsequently, the core component 40 is formed on the semiconductor layer 41 and within the SGD hole H3. Thereafter, a part of the core component 40 above the SGD hole H3 is removed, and the semiconductor portion 44 is embedded in this space. The stacked film 43, semiconductor layer 42, semiconductor layer 41, core component 40, and semiconductor portion 44 remaining in the layer above the insulator layer 59 are removed by, for example, CMP (Chemical Mechanical Polishing). Thus, the upper pillar UP is formed within the SGD hole H3.

[0147] Next, as Figure 19 shown, the sacrificial materials 52, 53, and 57 are respectively replaced with the conductor layers 22 to 24.

[0148] Specifically, first, holes (not shown) corresponding to the slit SLT are formed. The holes formed in this step divide the insulator layer 51, sacrificial materials 52 and 53, insulator layers 55 and 56, sacrificial material 57, and insulator layers 58 and 59 respectively. Subsequently, the surface of the conductor layer 21 exposed within the holes is oxidized to form an oxidation protection film (not shown). Thereafter, the sacrificial materials 52, 53, and 57 are selectively removed, for example, by wet etching using hot phosphoric acid. The structure after removing the sacrificial materials 52, 53, and 57 is maintained in its three-dimensional structure by a plurality of memory pillars MP or the like.

[0149] Subsequently, after embedding a conductor into the space from which the sacrificial materials 52, 53, and 56 have been removed via the holes, an insulator layer corresponding to the slit SLT is formed within the holes. In this step, for example, CVD (Chemical Vapor Deposition) is used. The portions of the conductor formed inside the holes and on the upper surface of the insulator layer 59 are removed by etch-back processing. Thus, the conductors formed in the adjacent wiring layers are separated to form the conductor layer 22, a plurality of conductor layers 23, and a plurality of conductor layers 24. The conductor layers 22, 23, and 24 formed in this step may also include barrier metals. In this case, in the formation of the conductor after removing the sacrificial materials 52, 53, and 57, for example, titanium nitride (TiN) is formed as a barrier metal and then tungsten is formed.

[0150] Next, as Figure 20 shown, holes H4 corresponding to the slits SHE_X and SHE_Y are formed. In addition, in Figure 20In [description], a part of the hole H4 corresponding to the slit SHE_Y is shown. Specifically, first, a mask with openings in regions corresponding to the slits SHE_X and SHE_Y is formed by photolithography. Then, the hole H4 is formed by anisotropic etching (e.g., RIE) using the formed mask. The hole H4 formed in this step divides the insulator layers 59 and 58, and the conductor layer 24, and reaches the insulator layer 56.

[0151] Next, as Figure 21 shown, on the insulator layers 59 and 60, an insulator layer 61 corresponding to the slits SHE_X and SHE_Y is formed so as to fill the hole H4. Then, the insulator layer 61 formed on a layer above the insulator layers 59 and 60 is removed, for example, by etch-back processing. The insulator layer 61 contains, for example, silicon oxide.

[0152] Next, as Figure 22 shown, while forming a conductor layer 62 on the upper surface of the semiconductor portion 44 of the memory column MP and forming a conductor layer 25 on the upper surface of the conductor layer 62, an insulator layer 63 is formed so as to embed them over the entire surface.

[0153] Next, as Figure 23 shown, a plurality of holes H5 corresponding to the contacts CC_SGD0 to CC_SGD3, and a plurality of holes H6 corresponding to the contacts CC_SGS and CC_WL0 to CC_WL7 are formed. In Figure 23 [description], one hole H5 corresponding to the contact CC_SGD0, and three holes H6 corresponding to the contacts CC_WL1, CC_WL4, and CC_WL7 are shown.

[0154] Specifically, first, a mask with openings in regions corresponding to the holes H5 and H6 is formed by photolithography. Then, the holes H5 and H6 are formed by anisotropic etching using the formed mask. In addition, with respect to the opening corresponding to the hole H6, a through hole having a diameter of Δ1 + 2Δ2 including the conductor layer 24 formed on the uppermost layer is formed.

[0155] The anisotropic etching in this step is, for example, RIE, and conditions are selected such that oxides and nitrides are selectively removed on one side while the conductor layers 22 to 24 are hardly etched. As a result, the hole H5 reaches the upper surfaces of the uppermost conductor layer 24, the second-layer conductor layer 24, and the lowermost conductor layer 24, respectively. The hole H5 has a diameter Δ3 on the upper surface of the uppermost conductor layer 24, a diameter Δ1 + 2Δ2 on the upper surface of the second-layer conductor layer 24 from the bottom, and a diameter Δ1 on the upper surface of the lowermost conductor layer 24. The hole H6 penetrates the insulator layers 63, 60, 56, and 55 and reaches the uppermost conductor layer 23, and further penetrates the insulator layer 54 and reaches the other conductor layers 23 and the conductor layer 22.

[0156] Next, as Figure 24 shown, conductor layers 64 and 65 are formed to fill the holes H5 and H6, respectively. After that, the conductor layers 64 and 65 remaining above the insulator layer 63 are removed.

[0157] Through the manufacturing steps of the semiconductor memory device according to the first embodiment described above, memory columns MP, source lines SL connected to the memory columns MP, word lines WL, select gate lines SGS and SGD, and contacts CC_SGS, CC_WL0 to CC_WL7, and CC_SGD0 to CC_SGD3 are formed, respectively. In addition, the manufacturing steps described above are merely examples, and other processes may be inserted between the respective manufacturing steps, or the order of the manufacturing steps may be changed within a range where no problem occurs.

[0158] 1.3 Effects of this embodiment

[0159] According to the configuration of the first embodiment, the select gate line SGD and the contact CC_SGD can be well connected. More specifically, the contact CC_SGD and the multiple conductor layers 24 that function as the select gate line SGD are in contact with each other on their respective upper surfaces, so that the contact area with any of the conductor layers 24 can be sufficiently ensured. Therefore, an increase in the resistance of the connection portion can be suppressed.

[0160] In addition, all the multiple conductor layers 24 can be electrically connected by one contact CC_SGD, so there is no need to separately provide a stepped area for forming the contact CC_SGD for the multiple conductor layers 24. Therefore, the length of the select gate line SGD along the X-axis can be shortened.

[0161] In addition, in order to form the contact CC_SGD as described above, the step of etching based on the mask pattern formed by refinement is appropriately repeated according to the number of stacked layers of the select gate line SGD. As a result, through holes having diameters that gradually decrease toward the lower layer are formed in the multi-layer sacrificial material 57, and a stepped shape in which the step width corresponds to the diameter of the through hole is formed. Further, the difference Δ2 in the diameter between the through hole of the second sacrificial material 57 from the bottom and the through hole of the uppermost sacrificial material 57 is consistent with the difference Δ2 in the length along the X-axis between the second sacrificial material 57 from the bottom and the uppermost sacrificial material 57.

[0162] In addition, according to the configuration of the first embodiment, the slit SHE includes, in addition to the slit SHE_X extending along the X-axis, a slit SHE_Y extending along the Y-axis. As a result, the select gate line SGD is divided into select gate lines SGD0 to SDG3 respectively corresponding to the string components SU0 to SU3, and a select gate line SGDX that does not correspond to any string component SU and is located at the end of the select gate line SGD along the X-axis. Therefore, the slit SHE_X can insulate and separate the select gate line SGD in units of string components SU without completely dividing the select gate line SGD along the X-axis (by dividing up to the slit SHE_Y).

[0163] Regarding the effects of this configuration, further use Figure 25 and Figure 26 will be described. Figure 25 is a comparative example for explaining the effects of the semiconductor memory device of the first embodiment, and corresponds to Figure 3 in the first embodiment, Figure 26 is a cross-sectional view taken along line XXVI-XXVI of Figure 25 . In the comparative examples of Figure 25 and Figure 26 , a plurality of slits SHE_X each extend along the X-axis longer than the plurality of conductor layers 24. As a result, the slit SHE_X divides the wiring layers corresponding to the select gate line SGD into select gate lines SGD0 to SGD3 and insulates and separates them, without forming the select gate line SGDX. Consequently, there is no insulator layer corresponding to the slit SHE_Y that divides the three-layer conductor layer 24 in the Y direction in the wiring region HA. In addition, in the comparative examples of Figure 25 and Figure 26 , the contact CC_SGDp extends upward from the upper surface of the lowermost conductor layer 24 and abuts against the side surfaces of the other conductor layers 24.

[0164] It can also be understood from Figure 25 that in the case where the slit SHE_Y is not formed, the slit SHE_X reaches the region OEA that does not include the three-layer conductor layer 24 in a top view. In addition, from Figure 26It is also known that in the region OEA, up to the depth of the conductor layer 23, a stacked structure is formed of an oxide or a nitride and does not include a metal layer.

[0165] Under the etching conditions applied when forming the hole H4 corresponding to the slit SHE_X, in the stacked structure formed of an oxide and a nitride, etching progresses rapidly, but etching hardly progresses in the metal layer. Therefore, when forming the hole H4, in the region OEA, over-etching may reach up to the depth of the conductor layer 23. In this case, the conductor layer 23 may be etched into a deformed shape, resulting in unexpected leakage current or the like.

[0166] According to the first embodiment, by forming the slit SHE_Y, the slit SHE_X does not reach the region OEA. Thus, the layer structure etched when forming the hole H4 is limited to the region including the three conductor layers 24 in plan view. Therefore, it is possible to prevent the etching of the hole H4 from progressing to the conductor layer 23. Accordingly, it is possible to suppress the slit SHE_X and the conductor layer 23 from becoming deformed shapes, and it is possible to suppress the generation of unexpected leakage current in the conductor layer 23.

[0167] 1.4 Variation

[0168] In addition, various variations can be made to the first embodiment.

[0169] 1.4.1 First Variation

[0170] In the first embodiment, the case where the contact CC_SGD is in contact with the upper surfaces of the plurality of conductor layers 24 has been described, but it is not limited thereto. For example, through holes having a sufficient contact area with the side surfaces of the plurality of conductor layers 24 may be formed, and contacts may be formed on the upper surfaces of the through holes. In the following description, the description of the configurations and manufacturing methods equivalent to those of the first embodiment is omitted, and mainly the configurations and manufacturing methods different from those of the first embodiment are described.

[0171] Figure 27 It is a plan view showing the planar layout of the memory cell array of the semiconductor memory device for explaining the first variation of the first embodiment, corresponding to that in the first embodiment Figure 3 Corresponding.

[0172] As Figure 27 shown, the through holes CV_SGD0 to CV_SGD3 are respectively provided in contact with the selection gate lines SGD0 to SGD3. The contacts CC'_SGD0 to CC'_SGD3 are respectively provided on the upper surfaces of the through holes CV_SGD0 to CV_SGD3. The diameter of the through hole CV_SGD is larger than the diameter of the contact CC'_SGD.

[0173] Figure 28 shows an example of a cross-sectional structure obtained by cutting the memory cell array 10 described in Figure 27 along line XXVIII-XXVIII, corresponding to that in the first embodiment. As Figure 7 shown, the via hole CV_SGD is provided on the upper surface of the lowermost conductive layer 24 and extends along the Z-axis in other conductive layers 24 (in the example of Figure 28 , the second layer from the bottom and the uppermost conductive layer 24) except for the lowermost conductive layer 24. That is, the via hole CV_SGD is in contact with the upper surface of the lowermost conductive layer 24 at the upper surface of the lowermost conductive layer 24 and is in contact with the other plurality of conductive layers 24 at the side surfaces of the other plurality of conductive layers 24. Figure 28 As described above, since the diameter of the via hole CV_SGD is larger than the diameter of the contact CC'_SGD, a sufficient contact area with the conductive layer 24 in contact at the side surface can also be ensured. Thereby, an increase in the contact resistance between the select gate line SGD and the contact CC'_SGD can be suppressed.

[0174] In addition, each of the plurality of conductive layers 24 is electrically connected to the contact CC'_SGD through one via hole CV_SGD. Therefore, there is no need to form the plurality of conductive layers 24 in a stepped shape in order to form a plurality of contacts corresponding to the plurality of conductive layers 24 respectively. Thereby, compared with the case where the contacts CC'_SGD are formed for the plurality of conductive layers 24 respectively, the area for forming the contacts CC'_SGD can be reduced. In addition, accordingly, the following configuration can be applied in the same manner as in the first embodiment: the plurality of conductive layers 24 are divided into portions corresponding to the select gate lines SGD0 to SGD3 and portions corresponding to the select gate line SGDX by the slits SHE_X and SHE_Y. Therefore, an abnormal shape of the conductive layer 23 due to over-etching when forming the slit SHE_X can be suppressed.

[0175] In addition, in the first modification, the via hole CV_SGD does not adopt a structure in contact with the upper surfaces of the plurality of conductive layers 24 respectively. Therefore, in the first modification, different from the first embodiment, there is no need to repeatedly perform the step of etching the multi-layer sacrificial material 57 using a mask pattern formed by refinement. Therefore, the ends of the plurality of conductive layers 24 along the -X direction do not become a stepped shape and can be in the same length and aligned shape.

[0176] 1.4.2 Second modification

[0177] 1.4.2 Second modification

[0178] In addition, in the first variation, the case where the selection gate line SGD and the contact CC_SGD are shunted by the through hole CV_SGD is described, but it is not limited to this. In the following description, the description of the same structure and manufacturing method as the first variation of the first embodiment is omitted, and the description is mainly about the structure and manufacturing method different from the first variation of the first embodiment.

[0179] Figure 29 1 is a top view for explaining the plan layout of a memory cell array of a semiconductor memory device according to a second variation of the first embodiment, which is similar to the plan layout of the first variation of the first embodiment. Figure 27 correspond.

[0180] like Figure 29 As shown, the contact points CC"_SGD0~CC"_SGD3 are respectively set in a manner connected to the selection gate lines SGD0~SGD3.

[0181] Figure 30 It means that along the XXX-XXX line Figure 29 An example of a cross-sectional structure obtained by cutting the memory cell array 10 described in the first embodiment is similar to that in the first variation of the first embodiment. Figure 28 Corresponding. Figure 30 As shown, the contact CC"_SGD is arranged on the upper surface of the bottom conductor layer 24, and the other conductor layers 24 (in Figure 30 In the example, the contact CC"_SGD extends along the Z axis within the second layer from the bottom and the top conductor layer 24. That is, the contact CC"_SGD is in contact with the bottom conductor layer 24 on the upper surface of the bottom conductor layer 24, and is in contact with the other multiple conductor layers 24 on the side surfaces of the other multiple conductor layers 24. The diameter of the contact CC"_SGD is, for example, the same as the diameter of the contact CC_WL.

[0182] As described above, when there is a margin for the restriction of the contact resistance, the same effect as that of the first embodiment and the first variation of the first embodiment can be achieved by a configuration in which the side surface of the selection gate line SGD is directly in contact with the contact CC_SGD.

[0183] 2. Second Implementation Method

[0184] Next, the semiconductor memory device of the second embodiment will be described. In the second embodiment, the hole for forming the contact CC_SGD connected to the select gate line SGD and the hole for forming the slit SHE are formed simultaneously. This is mainly different from the second variation of the first embodiment in this aspect. In the following description, the description of the configuration and manufacturing method equivalent to the second variation of the first embodiment will be omitted, and the configuration and manufacturing method different from the second variation of the first embodiment will be mainly described.

[0185] 2.1 Configuration of the Semiconductor Memory Device

[0186] Figure 31 It is a cross-sectional view for explaining the wiring area of the memory cell array of the semiconductor memory device of the second embodiment, corresponding to that in the second variation of the first embodiment. Figure 30 Corresponding.

[0187] As Figure 31 shown, the contact CC2_SGD extends along the Z-axis in a plurality of conductor layers 24, and its lower end is located below the lower surface of the lowermost conductor layer 24. The lower ends and upper ends of the slit SHE2_Y (and the slit SHE2_X not shown) and the lower end of the contact CC2_SGD are located at substantially the same height along the Z direction. That is, the length L from the lower end to the upper end of the slits SHE2_X and SHE2_Y is substantially the same as the length L from the lower end to the upper end of the contact CC2_SGD.

[0188] 2.2 Manufacturing Method of the Semiconductor Memory Device

[0189] Hereinafter, an example of a series of manufacturing steps of the semiconductor memory device of the second embodiment from the formation of the stacked structure corresponding to the word line WL to the formation of the contact CC_SGD corresponding to the select gate line SGD will be described. Figures 32 - 43 These respectively show an example of the cross-sectional structure of the structure including the structure corresponding to the memory cell array in the manufacturing steps of the semiconductor memory device of the second embodiment.

[0190] First, through the same steps as those Figures 9 - 12 shown in the first embodiment, an insulator layer 50 and a conductor layer 21 are sequentially formed on the semiconductor substrate 20. An insulator layer 51 and a sacrificial material 52 are stacked on the conductor layer 21, and the insulator layer 51 and the sacrificial material 53 are alternately stacked on the sacrificial material 52 multiple times. Then, after forming a stepped structure in the wiring area HA of this stacked structure, a lower pillar LP is formed in the cell area. Subsequently, an insulator layer 56 is formed on this stacked structure, and then the sacrificial material 57 corresponding to the select gate line SGD and the insulator layer 58 are alternately stacked. An insulator layer 59 is formed on the upper layer of the uppermost sacrificial material 57.

[0191] Next, as Figure 33 and Figure 34 shown, an SGD hole H3 corresponding to the upper column UP is formed, and a stacked structure corresponding to the upper column UP is formed within the SGD hole H3.

[0192] Next, a hole (not shown) corresponding to the slit SLT is formed. Then, as Figure 35 shown, the sacrificial materials 52, 53, and 56 are respectively replaced with the conductive layers 22 to 24 through this hole. An insulator layer (not shown) is embedded within the hole used in this replacement step to form the slit SLT.

[0193] Next, as Figure 36 shown, while forming a conductive layer 62 on the upper surface of the semiconductor portion 44 of the memory column MP and forming a conductive layer 25 on the upper surface of the conductive layer 62, an insulator layer 63 is formed in such a manner that they are embedded over the entire surface.

[0194] Next, as Figure 37 shown, holes H11 corresponding to the slits SHE2_X and SHE2_Y, and a hole H12 corresponding to the contact CC2_SGD are formed. In addition, Figure 37 shows a portion of the hole H11 corresponding to the slit SHE2_Y among the holes H11. Specifically, first, a mask that opens regions corresponding to the slits SHE2_X and SHE2_Y, and the contact CC2_SGD is formed by photolithography. Then, the holes H11 and H12 are formed by anisotropic etching (e.g., RIE) using the formed mask.

[0195] The holes H11 and H12 formed in this step divide the insulator layers 63, 59, and 58, and the conductive layer 24, and reach the insulator layer 56. The depths of the holes H11 and H12 are substantially equal to each other and are substantially consistent with the length L in Figure 31 .

[0196] Next, as Figure 38 shown, insulator layers 72 and 73 are formed to fill the holes H11 and H12 respectively. After that, the insulator layers 72 and 73 remaining above the insulator layer 63 are removed. The insulator layers 72 and 73 contain, for example, silicon nitride.

[0197] Next, as Figure 39 shown, the insulator layer 72 is selectively removed to reform the hole H11. Specifically, for example, after forming a resist (not shown) on the insulator layer 73 to protect the insulator layer 73, the insulator layer 72 is removed by wet etching that selectively removes silicon nitride.

[0198] Next, as Figure 40As shown, an insulator layer 74 is formed and the inside of the hole H11 is filled again. After that, the insulator layer 74 remaining above the insulator layer 63 is removed. The insulator layer 74 contains, for example, silicon oxide.

[0199] Next, as Figure 41 shown, a plurality of holes H13 corresponding to the contacts CC_SGS and CC_WL0 to CC_WL7 are formed. Specifically, first, a mask with an opening in the region corresponding to the hole H13 is formed by photolithography. Then, the hole H13 is formed by anisotropic etching using the formed mask.

[0200] Next, as Figure 42 shown, the insulator layer 73 is selectively removed by wet etching that selectively removes silicon nitride or the like, and the hole H12 is formed again.

[0201] Next, as Figure 43 shown, conductor layers 64A and 65 are formed and the inside of the holes H12 and H13 are filled respectively. After that, the conductor layers 64A and 65 remaining above the insulator layer 63 are removed.

[0202] Through the manufacturing steps of the semiconductor memory device of the second embodiment described above, slits SHE2_X and SHE2_Y and contacts CC2_SGD0 to CC2_SGD3 whose lower ends and upper ends are substantially aligned with each other are formed. In addition, the manufacturing steps described above are only examples, and other processes can be inserted between the manufacturing steps, and the order of the manufacturing steps can be changed within a range where no problems occur.

[0203] 2.3 Effects of this Embodiment

[0204] According to the second embodiment, the contact CC2_SGD is in contact with the side surfaces of the respective conductor layers 24. Accordingly, it is not necessary to form a contact for each of the plurality of conductor layers 24, and thus it is not necessary to form a stepped region for the contact for each of the plurality of conductor layers 24. Therefore, with respect to the plurality of conductor layers 24, the stepped shape along the -X direction can be omitted, and thus the chip area can be reduced.

[0205] In addition, the hole H13 corresponding to the contact CC_WL and the hole H12 corresponding to the contact CC2_SGD are formed by different steps. Accordingly, the difference in the etching depth of the holes formed in the same etching step can be reduced.

[0206] Supplementary note: In the case where holes H12 and H13 are formed by the same steps, the deepest hole among the formed holes is hole H13 that reaches the conductor layer 22, and the shallowest hole is hole H12 that reaches the uppermost conductor layer 24. On the other hand, in the case where holes H12 and H13 are formed by different steps, the deepest hole among the formed holes is hole H13 that reaches the lowermost conductor layer 22, and in contrast, the shallowest hole is hole H13 that reaches the uppermost conductor layer 23. Therefore, the difference in etching depth between the deepest hole and the shallowest hole can be reduced, the risk of over-etching the conductor layer 24 corresponding to the shallower hole can be alleviated, and thus the generation of unexpected leakage current can be suppressed.

[0207] In addition, hole H12 formed by different steps from hole H13 and hole H11 corresponding to slits SHE2_X and SHE2_Y are formed by the same steps. Thereby, an increase in manufacturing steps can be suppressed. In addition, accordingly, contact CC2_SGD and slits SHE2_X and SHE2_Y have a structure in which their lower ends and upper ends are located at substantially the same height along the Z direction.

[0208] 3. Others

[0209] In addition, various changes can be made to the first embodiment and the second embodiment.

[0210] For example, in the first embodiment and the second embodiment, the case where the memory column MP is formed of a separately manufactured upper column UP and lower column LP has been described, but it is not limited thereto. For example, the memory column MP may also have an integrally formed structure including a semiconductor layer extending along the Z axis in the conductor layers 22 to 24 and a charge accumulation layer disposed between the conductor layers 22 to 24 and the semiconductor layer.

[0211] In addition, in the first embodiment and the second embodiment, for example, the stacked film 43 includes a tunnel insulating film 45, an insulating film 46, and a barrier insulating film 47, and thus is configured to be able to adjust the threshold voltage of the selection transistor ST2, and this case has been described as an example, but it is not limited thereto. For example, the stacked film 43 may also have a configuration that does not include the tunnel insulating film 45 and the insulating film 46.

[0212] In addition, in the first and second embodiments, the semiconductor memory device 1 has a structure in which circuits such as the sense amplifier module 16 are provided under the memory cell array 10, and this case has been described as an example, but it is not limited thereto. For example, the semiconductor memory device 1 may also have a structure in which the memory cell array 10 and the sense amplifier module 16 are formed on the semiconductor substrate 20. In addition, the semiconductor memory device 1 may also have a structure in which a chip provided with the sense amplifier module 16 or the like is bonded to a chip provided with the memory cell array 10.

[0213] In addition, in the first and second embodiments, a structure in which the word line WL is adjacent to the selection gate line SGS and the word line WL is adjacent to the selection gate line SGD has been described, but it is not limited thereto. For example, dummy word lines may be provided between the uppermost word line WL and the selection gate line SGD. Similarly, dummy word lines may be provided between the lowermost word line WL and the selection gate line SGS. In addition, in the case where it is a structure formed by connecting a plurality of columns, the conductor layer near the connection portion may also be used as a dummy word line.

[0214] In addition, in the first and second embodiments, the case where the semiconductor layer 31 and the conductor layer 21 are electrically connected via the bottom of the memory column MP has been illustrated, but it is not limited thereto. The semiconductor layer 31 and the conductor layer 21 may also be electrically connected via the side surface of the memory column MP. In this case, the following structure is formed: a part of the laminated film 32 formed on the side surface of the memory column MP is removed, and the semiconductor layer 31 and the conductor layer 21 are brought into contact via this part.

[0215] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments or their variations are included in the scope or gist of the invention and are included in the invention described in the claims and its equivalents.

[0216] [Description of Reference Numerals]

[0217] 1 Semiconductor memory device

[0218] 2 Memory controller

[0219] 10 Memory cell array

[0220] 11 Command register

[0221] 12 Address register

[0222] 13 Sequencer

[0223] 14 Driver Module

[0224] 15 Row Decoder Module

[0225] 16 Sense Amplifier Module

[0226] 20 Semiconductor Substrate

[0227] 21 - 25, 62, 64, 64A, 65, 80, 81 Conductor Layers

[0228] 30, 40 Core Components

[0229] 31, 41, 42 Semiconductor Layers

[0230] 32, 43 Stacked Films

[0231] 33, 44 Semiconductor Parts

[0232] 35, 45 Tunnel Insulating Films

[0233] 36, 46 Insulating Films

[0234] 37, 47 Barrier Insulating Films

[0235] 50, 51, 54, 55, 56, 58, 59, 60, 61, 63, 71, 72, 73, 74 Insulator Layers

[0236] 52, 53, 57 Sacrificial Materials

[0237] BLK Block

[0238] SU String Component

[0239] MT Memory Cell Transistor

[0240] ST1, ST2 Selection Transistors

[0241] BL Bit Line

[0242] WL Word Line

[0243] SGD Selection Gate Line

Claims

1. A semiconductor memory device comprising: A plurality of first conductor layers laminated in a first direction; A first semiconductor layer extending in the first direction within the plurality of first conductor layers; A first charge accumulation layer provided between the plurality of first conductor layers and the first semiconductor layer; A plurality of second conductor layers laminated in the first direction above the uppermost layer among the plurality of first conductor layers; And A third conductor layer extending in the first direction from the upper surface of the lowermost layer among the plurality of second conductor layers and within one or more layers other than the lowermost layer among the plurality of second conductor layers, and in contact with the upper surfaces of the plurality of second conductors respectively.

2. The semiconductor memory device according to claim 1, wherein A first cross-section of the third conductor layer along the lower surface of the upper one of two adjacent ones among the plurality of second conductor layers in the first direction is similar to a second cross-section of the third conductor layer along the lower surface of the lower one of the two adjacent ones.

3. The semiconductor memory device according to claim 2, wherein The difference between the diameter of the first cross-section and the diameter of the second cross-section corresponds to the difference in the length along a second direction intersecting the first direction of the two adjacent second conductor layers.

4. The semiconductor memory device according to claim 2, wherein When viewed from the first direction, the outer edge of the first cross-section is located at an equal interval width from the outer edge of the second cross-section.

5. The semiconductor memory device according to claim 1, which Further comprises a first insulator layer, and The first insulator layer includes: A first portion extending in a second direction intersecting the first direction, dividing the plurality of second conductor layers into a first region and a second region arranged in a third direction intersecting the first direction and the second direction; and A second portion extending in the third direction, dividing the first region into a third region and a fourth region arranged in the second direction.

6. The semiconductor memory device according to claim 5, wherein The third conductor layer is provided in the third region or the fourth region of the plurality of second conductor layers.

7. The semiconductor memory device according to claim 1, wherein The first semiconductor layer further extends in the first direction within the plurality of second conductor layers, And the first charge accumulation layer is further provided between the plurality of second conductor layers and the first semiconductor layer.

8. The semiconductor memory device according to claim 1, which further comprises: A second semiconductor layer extending in the first direction within the plurality of second conductor layers; and A second insulator layer provided between the plurality of second conductor layers and the second semiconductor layer.

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