Low-temperature polycrystalline oxide array substrate and manufacturing method thereof

Abstract

The present invention provides a low-temperature polycrystalline oxide array substrate and a manufacturing method thereof. The low-temperature polycrystalline oxide array substrate provided by the present invention includes a substrate, a first light-shielding layer, a second light-shielding layer, a first thin-film transistor, and a second thin-film transistor. The first light-shielding layer and the second light-shielding layer are disposed on the substrate at intervals, and the first thin-film transistor and the second thin-film transistor are respectively disposed above the first light-shielding layer and the second light-shielding layer along the stacking direction of the array substrate. The first thin-film transistor includes a first semiconductor pattern, a first source electrode, a first drain electrode, and a first gate electrode. The second thin-film transistor includes a second semiconductor pattern, a second source electrode, a second drain electrode, and a second gate electrode. Among them, the first semiconductor pattern is a polysilicon semiconductor pattern, and the second semiconductor pattern is a metal oxide semiconductor pattern. The array substrate provided by the present invention can reduce the power consumption of the display panel while meeting the requirements of high resolution.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a low-temperature polycrystalline oxide array substrate and a manufacturing method thereof. Background Art

[0002] Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) have the characteristics of small size, low power consumption, and no radiation, and occupy a dominant position in the current flat panel display market. In recent years, with the rapid development of TFT-LCDs, especially the development of liquid crystal televisions has been even more rapid, and large-size and high-resolution liquid crystal televisions have become the mainstream of TFT-LCD development.

[0003] Traditional TFT-LCDs usually adopt polysilicon thin film transistors, which have a relatively high mobility, with a mobility greater than 30 cm 2 / V·s. Polysilicon thin film transistors are generally fabricated by an Excimer Laser Annealing (ELA) process. However, during laser annealing, due to the limitation of the laser pulse width, the formed polysilicon has poor uniformity, which directly affects the uniformity of the thin film transistors and makes them unsuitable for large-size liquid crystal panels; in addition, although polysilicon thin film transistors have a high mobility, their off-state current is large, and the power consumption is relatively high when driving pixel electrodes. Currently, TFT-LCDs also adopt metal oxide thin film transistors, which also have a relatively high mobility, generally around 10 - 30 cm 2 / V·s. Although the mobility is slightly lower than that of polysilicon thin film transistors, it can fully meet the driving requirements of the pixel region, and the off-state current of metal oxide thin film transistors is much smaller than that of polysilicon thin film transistors. Using them to drive pixel electrodes can reduce the power consumption of the display panel.

[0004] However, with the development of display products towards large size and high resolution, the existing thin film transistor structures cannot fully meet the requirements, and the power consumption of the display panel is increased. Summary of the Invention

[0005] The present invention provides a low-temperature polycrystalline oxide array substrate and a manufacturing method thereof. While meeting the requirements of high resolution, the array substrate can reduce the power consumption of the display panel.

[0006] One aspect of the present invention provides a low-temperature polycrystalline oxide array substrate, which includes a substrate, a first light-shielding layer, a second light-shielding layer, a first thin-film transistor, and a second thin-film transistor. The first light-shielding layer and the second light-shielding layer are disposed on the substrate at intervals, and the first thin-film transistor and the second thin-film transistor are respectively disposed above the first light-shielding layer and the second light-shielding layer along the stacking direction of the array substrate;

[0007] The first thin-film transistor includes a first semiconductor pattern located above the first light-shielding layer, a first source electrode and a first drain electrode respectively connected to both sides of the first semiconductor pattern, and a first gate electrode disposed above the first semiconductor pattern at intervals; the second thin-film transistor includes a second semiconductor pattern located above the second light-shielding layer, a second source electrode and a second drain electrode respectively connected to both sides of the second semiconductor pattern, and a second gate electrode disposed above the second semiconductor pattern at intervals; wherein, the first semiconductor pattern is a polysilicon semiconductor pattern, and the second semiconductor pattern is a metal oxide semiconductor pattern;

[0008] It further includes a buffer layer and a gate insulating layer. The buffer layer is disposed on the substrate and covers the first light-shielding layer and the second light-shielding layer, and the first semiconductor pattern and the second semiconductor pattern are disposed on the buffer layer;

[0009] The gate insulating layer is disposed on the buffer layer and covers the first semiconductor pattern and the second semiconductor pattern, and the first gate electrode and the second gate electrode are disposed on the gate insulating layer;

[0010] A first contact hole and a second contact hole are provided through the gate insulating layer and the buffer layer. The first gate electrode contacts the first light-shielding layer through the first contact hole, and the second gate electrode contacts the second light-shielding layer through the second contact hole.

[0011] In a possible implementation manner, the orthographic projection of the first semiconductor pattern on the substrate is located within the coverage of the first light-shielding layer, and the orthographic projection of the second semiconductor pattern on the substrate is located within the coverage of the second light-shielding layer.

[0012] In a possible implementation manner, the buffer layer includes a first buffer layer and a second buffer layer stacked on the substrate in sequence; wherein, the first buffer layer is a silicon nitride layer, and the second buffer layer is a silicon oxide layer.

[0013] In a possible implementation manner, the gate insulating layer includes a first silicon oxide layer and a second silicon oxide layer stacked on the buffer layer in sequence, and the density of the first silicon oxide layer is higher than that of the second silicon oxide layer.

[0014] In a possible implementation manner, the array substrate further includes a gate protection layer, and the gate protection layer is disposed on the gate insulating layer and covers the first gate electrode and the second gate electrode.

[0015] In a possible implementation, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are disposed on the gate protection layer. Through holes including a third contact hole, a fourth contact hole, a fifth contact hole, and a sixth contact hole are formed in the gate protection layer and the gate insulating layer. The first source electrode and the first drain electrode are respectively in contact with the first semiconductor pattern through the third contact hole and the fourth contact hole, and the second source electrode and the second drain electrode are respectively in contact with the second semiconductor pattern through the fifth contact hole and the sixth contact hole.

[0016] In a possible implementation, the array substrate further includes a passivation layer and a pixel electrode. The passivation layer is disposed on the gate protection layer and covers the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode. The pixel electrode is disposed on the passivation layer. A conductive via hole is formed in the passivation layer, and the second drain electrode is in contact with the second drain electrode through the conductive via hole.

[0017] Another aspect of the present invention provides a method for manufacturing a low-temperature polycrystalline oxide array substrate for manufacturing the low-temperature polycrystalline oxide array substrate as described in any one of the above. The manufacturing method includes the following steps:

[0018] Form spaced-apart first light-shielding layers and second light-shielding layers on a substrate substrate;

[0019] Form a first semiconductor pattern and a second semiconductor pattern above the first light-shielding layer and the second light-shielding layer respectively; wherein, the first semiconductor pattern is a polysilicon semiconductor pattern, and the second semiconductor pattern is a metal oxide semiconductor pattern;

[0020] Form a first gate and a second gate above the first semiconductor pattern and the second semiconductor pattern respectively;

[0021] Simultaneously form a first source electrode, a first drain electrode connected to both sides of the first semiconductor pattern, a second source electrode, and a second drain electrode connected to both sides of the second semiconductor pattern above the first gate and the second gate; and make the first gate in contact with the first light-shielding layer through a first contact hole, and the second gate in contact with the second light-shielding layer through a second contact hole.

[0022] In a possible implementation, forming a first semiconductor pattern and a second semiconductor pattern above the first light-shielding layer and the second light-shielding layer respectively specifically includes the following steps:

[0023] Deposit and form a buffer layer on the substrate substrate, and the buffer layer covers the first light-shielding layer and the second light-shielding layer;

[0024] Deposit and form an amorphous silicon layer on the buffer layer;

[0025] Perform an annealing process on the amorphous silicon layer to form a polysilicon layer;

[0026] Perform a photolithography process on the polysilicon layer to form the first semiconductor pattern;

[0027] A metal oxide semiconductor layer is deposited on the buffer layer, and the metal oxide semiconductor layer covers the first semiconductor pattern;

[0028] A photolithography process is performed on the metal oxide semiconductor layer to form a second semiconductor pattern.

[0029] In a possible implementation manner, a first gate and a second gate are respectively formed above the first semiconductor pattern and the second semiconductor pattern, and the specific steps are as follows:

[0030] A gate insulating layer is deposited on the buffer layer, and the gate insulating layer covers the first semiconductor pattern and the second semiconductor pattern;

[0031] A first contact hole and a second contact hole that penetrate are formed in the gate insulating layer and the buffer layer;

[0032] A gate metal layer is deposited on the gate insulating layer;

[0033] A photolithography process is performed on the gate metal layer to form a first gate and a second gate; wherein, the first gate is in contact with the first light-shielding layer through the first contact hole, and the second gate is in contact with the second light-shielding layer through the second contact hole.

[0034] In a possible implementation manner, a first source electrode, a first drain electrode connected to both sides of the first semiconductor pattern, a second source electrode, and a second drain electrode connected to both sides of the second semiconductor pattern are simultaneously formed above the first gate and the second gate, and the specific steps are as follows:

[0035] A gate protection layer is deposited on the gate insulating layer, and the gate protection layer covers the first gate and the second gate;

[0036] A third contact hole, a fourth contact hole, a fifth contact hole, and a sixth contact hole that penetrate are formed in the gate protection layer and the gate insulating layer;

[0037] A source-drain metal layer is deposited on the gate protection layer;

[0038] A photolithography process is performed on the source-drain metal layer once to form a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode; wherein, the first source electrode and the first drain electrode are respectively in contact with the first semiconductor pattern through the third contact hole and the fourth contact hole, and the second source electrode and the second drain electrode are respectively in contact with the second semiconductor pattern through the fifth contact hole and the sixth contact hole.

[0039] In a possible implementation manner, after a first source electrode, a first drain electrode connected to both sides of the first semiconductor pattern, a second source electrode, and a second drain electrode connected to both sides of the second semiconductor pattern are simultaneously formed above the first gate and the second gate, the following steps are further included:

[0040] A passivation layer is deposited on the gate protection layer, and the passivation layer covers the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode;

[0041] A through conductive via is formed at a position corresponding to the second drain electrode in the passivation layer;

[0042] A transparent conductive layer is deposited on the passivation layer;

[0043] A photolithography process is performed on the transparent conductive layer to form a pixel electrode, and the pixel electrode is in contact with the second drain electrode through the conductive via.

[0044] The present invention provides a low-temperature polycrystalline oxide array substrate and a manufacturing method thereof. The array substrate is provided with a first thin-film transistor and a second thin-film transistor on a substrate. The first semiconductor pattern of the first thin-film transistor is a polysilicon semiconductor pattern, and the second semiconductor pattern of the second thin-film transistor is a metal oxide semiconductor pattern, that is, the first thin-film transistor is a polysilicon TFT, and the second thin-film transistor is a metal oxide TFT. In practical applications, the high mobility characteristic of the polysilicon TFT can be utilized to drive the peripheral circuit, and the characteristic of the metal oxide TFT with a small off-state current can be utilized to drive the pixel electrode. The first thin-film transistor and the second thin-film transistor act together on each pixel of the array substrate, which can meet the high-resolution requirements of a large-size display panel and reduce the power consumption of the display panel. Among them, by respectively providing a first light-shielding layer and a second light-shielding layer at positions corresponding to the first semiconductor pattern and the second semiconductor pattern on the substrate, light irradiation on the first semiconductor pattern and the second semiconductor pattern can be avoided, so as not to affect the stability of the first thin-film transistor and the second thin-film transistor.

[0045] The LTPO (Low Temperature Polycrystalline Oxide) thin-film transistor array substrate integrates two devices, namely low-temperature poly-silicon (LTPS) TFT and oxide (Oxide) TFT, in one sub-pixel. The LTPO panel technology combines the advantages of the strong driving ability of the LTPS TFT process and the small leakage current and low power consumption of the Oxide TFT process. The LTPS TFT is used to drive the display, and the Oxide TFT is used for switching, so the power consumption of the display panel can be effectively reduced. Description of the Drawings

[0046] To more clearly illustrate the technical solutions of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0047] Figure 1 Schematic structural diagram of a low-temperature polycrystalline oxide array substrate provided in Embodiment 1 of the present invention;

[0048] Figure 2 Top view structural diagram of forming a first contact hole and a second contact hole in a gate insulating layer and a buffer layer provided in Embodiment 1 of the present invention;

[0049] Figure 3 Schematic flow chart of a manufacturing method of a low-temperature polycrystalline oxide array substrate provided in Embodiment 2 of the present invention;

[0050] Figure 4 Schematic structural diagram of forming spaced first light-shielding layer and second light-shielding layer on a substrate provided in Embodiment 2 of the present invention;

[0051] Figure 5 Schematic flow chart of forming a first semiconductor pattern and a second semiconductor pattern on the first light-shielding layer and the second light-shielding layer respectively provided in Embodiment 2 of the present invention;

[0052] Figure 6 Schematic structural diagram of forming a buffer layer on a substrate provided in Embodiment 2 of the present invention;

[0053] Figure 7 Schematic structural diagram of forming a first semiconductor pattern on a buffer layer provided in Embodiment 2 of the present invention;

[0054] Figure 8 Schematic structural diagram of forming a second semiconductor pattern on a buffer layer provided in Embodiment 2 of the present invention;

[0055] Figure 9 Schematic flow chart of forming a first gate and a second gate above the first semiconductor pattern and the second semiconductor pattern respectively provided in Embodiment 2 of the present invention;

[0056] Figure 10 Schematic structural diagram of forming a gate insulating layer on a buffer layer provided in Embodiment 2 of the present invention;

[0057] Figure 11 Schematic structural diagram of forming a first gate and a second gate on a gate insulating layer provided in Embodiment 2 of the present invention;

[0058] Figure 12Schematic flowchart of forming a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode provided in the second embodiment of the present invention;

[0059] Figure 13 Schematic structural diagram of forming a gate protection layer on a gate insulating layer provided in the second embodiment of the present invention;

[0060] Figure 14 Schematic structural diagram of forming a third contact hole, a fourth contact hole, a fifth contact hole, and a sixth contact hole in a gate protection layer and a gate insulating layer provided in the second embodiment of the present invention;

[0061] Figure 15 Schematic structural diagram of forming a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode on a gate protection layer provided in the second embodiment of the present invention;

[0062] Figure 16 Schematic structural diagram of forming a passivation layer and a pixel electrode on a gate protection layer provided in the second embodiment of the present invention.

[0063] Description of reference numerals:

[0064] 1 - Substrate; 21 - First light-shielding layer; 22 - Second light-shielding layer; 3 - First thin-film transistor; 31 - First semiconductor pattern; 32 - First source electrode; 33 - First drain electrode; 34 - First gate; 4 - Second thin-film transistor; 41 - Second semiconductor pattern; 42 - Second source electrode; 43 - Second drain electrode; 44 - Second gate; 5 - Buffer layer; 51 - First buffer layer; 52 - Second buffer layer; 6 - Gate insulating layer; 61 - First silicon oxide layer; 62 - Second silicon oxide layer; 7 - Gate protection layer; 8 - Passivation layer; 81 - Conductive via; 9 - Pixel electrode;

[0065] a - First contact hole; b - Second contact hole; c - Third contact hole; d - Fourth contact hole; e - Fifth contact hole; f - Sixth contact hole. Detailed description of the invention

[0066] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without making creative efforts based on the embodiments of the present invention belong to the scope of protection of the present invention.

[0067] In recent years, Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) have developed rapidly. Especially for liquid crystal televisions, their size and resolution have been continuously increasing. Currently, the largest liquid crystal television in the world has exceeded 100 inches.

[0068] Currently, most of the thin-film transistors (TFTs) in TFT-LCDs are polysilicon TFTs with relatively high mobility. Polysilicon TFTs are usually fabricated using the Excimer Laser Annealing (ELA) process. Due to the limitation of the laser pulse width, the formed polysilicon has poor uniformity, which directly affects the uniformity of the TFTs and severely restricts their applications. TFTs are generally only applicable to display panels below 6G (1200*1800mm) and are not suitable for large-size display panels.

[0069] In addition, although polysilicon TFTs have relatively high mobility, the off-state current of polysilicon TFTs is large, and when used to drive pixel electrodes, the power consumption is relatively high. Therefore, in the prior art, metal oxide TFTs are used to replace polysilicon TFTs. The mobility of metal oxide TFTs is also relatively high (slightly lower than that of polysilicon TFTs), which can fully meet the pixel driving requirements. Moreover, metal oxide TFTs have a lower off-state current, and when used to drive pixel electrodes, the power consumption of the display panel can be reduced.

[0070] However, with the increase in the resolution of the display panel, neither polysilicon TFTs nor metal oxide TFTs can meet the high-resolution requirements of the display panel, and the power consumption of the display panel increases.

[0071] Therefore, this embodiment provides a low-temperature polycrystalline oxide array substrate and a manufacturing method thereof to reduce the power consumption of the display panel while meeting the high-resolution requirements of large-size display panels.

[0072] Among them, the Low Temperature Polycrystalline Oxide (LTPO) array substrate integrates two types of devices, namely low-temperature poly-silicon (LTPS) TFTs and oxide TFTs, within a single sub-pixel. The LTPO panel technology combines the advantages of the strong driving ability of the LTPS TFT process and the small leakage current and low power consumption of the Oxide TFT process. The LTPS TFTs are used to drive the display, and the Oxide TFTs are used for switching, thus effectively reducing the power consumption of the display panel.

[0073] Embodiment 1

[0074] Figure 1 This is a schematic structural diagram of the low-temperature polycrystalline oxide array substrate provided in the first embodiment of the present invention. As Figure 1 shown, this embodiment provides a low-temperature polycrystalline oxide array substrate, which can be applied and is not limited to the fields of OLED, Mini-LED, Micro-LED, and liquid crystal display.

[0075] The low-temperature polycrystalline oxide array substrate (hereinafter referred to as the array substrate) includes a substrate 1, a first light-shielding layer 21, a second light-shielding layer 22, a first thin-film transistor 3, and a second thin-film transistor 4. The first thin-film transistor 3 and the second thin-film transistor 4 are respectively disposed above the first light-shielding layer 21 and the second light-shielding layer 22 along the stacking direction of the array substrate.

[0076] As Figure 1 shown, the array substrate includes a substrate 1. The substrate 1 serves as the basic bearing structure of the array substrate, and the remaining hierarchical structures of the array substrate are all formed on the substrate 1. Among them, the substrate 1 can be selected from a glass substrate or an organic substrate. For example, the substrate 1 is made of materials such as polyimide (abbreviation: PI) or polyethylene terephthalate (abbreviation: PET).

[0077] The array substrate forms a pixel area for displaying images on the substrate 1. Multiple data lines and multiple scan lines are distributed in this pixel area. The multiple data lines and multiple scan lines divide the pixel area into multiple sub-pixels arranged in a matrix in the plane. At least one thin-film transistor (abbreviation: TFT) is disposed in each sub-pixel, and the display state of the corresponding sub-pixel is controlled by each TFT.

[0078] Specifically, the multiple data lines are parallel to each other and arranged at equal intervals, the multiple scan lines are parallel to each other and arranged at equal intervals, and the data lines and the scan lines are arranged in a horizontal and vertical staggered manner in space. For example, taking the shape of the array substrate as a rectangle, the data lines can extend along the width direction of the array substrate, and the scan lines can extend along the length direction of the array substrate, so as to divide the pixel area on the array substrate into multiple sub-pixels arranged in a matrix. For example, multiple sub-pixels with the same size and shape of a rectangle can be formed.

[0079] With the continuous increase in the size and resolution of TFT-LCDs, in order to improve the display quality, TFT-LCDs use higher-frequency drive circuits to drive pixels. The mobility of existing amorphous silicon TFTs is difficult to meet the requirements. The mobility of amorphous silicon TFTs is generally 0.5 cm2 / V.s or so. When the size of the liquid crystal display exceeds 80 inches and the driving frequency is 120 Hz, a mobility of more than 1 cm 2 / V.s is required, and the mobility of the existing amorphous silicon obviously cannot meet the requirement.

[0080] In this regard, as Figure 1 shown, the array substrate provided in this embodiment forms a thin-film transistor assembly by disposing a first thin-film transistor 3 and a second thin-film transistor 4 in each sub-pixel on the substrate 1. For a large-size and high-resolution display panel, the first thin-film transistor 3 and the second thin-film transistor 4 are used to jointly drive the sub-pixels, which can not only meet the driving requirements of the sub-pixels, but also improve the mobility of the thin-film transistor assembly and meet the high-resolution requirements.

[0081] In addition, with the improvement of the resolution, the more sub-pixels arranged in the array substrate, the smaller the area of each sub-pixel, the higher the frequency of the driving circuit of the display panel, and the greater the power consumption. In this embodiment, by disposing the first thin-film transistor 3 and the second thin-film transistor 4 above the first light-shielding layer 21 and the second light-shielding layer 22 on the substrate 1 respectively, and jointly driving the sub-pixels by the first thin-film transistor 3 and the second thin-film transistor 4, the power consumption of the display panel can be reduced on the basis of meeting the high-resolution requirements of the display panel.

[0082] Specifically, the first thin-film transistor 3 includes a first semiconductor pattern 31, a first source electrode 32, a first drain electrode 33, and a first gate electrode 34. The first semiconductor pattern 31 is located above the first light-shielding layer 21, the first source electrode 32 and the first drain electrode 33 are respectively connected to both sides of the first semiconductor pattern 31, and the first gate electrode 34 is disposed above the first semiconductor pattern 31 at an interval; the second thin-film transistor 4 is disposed in parallel with the first thin-film transistor 3. The second thin-film transistor 4 includes a second semiconductor pattern 41, a second source electrode 42, a second drain electrode 43, and a second gate electrode 44. The second semiconductor pattern 41 is located above the second light-shielding layer 22, the second source electrode 42 and the second drain electrode 43 are respectively connected to both sides of the second semiconductor pattern 41, and the second gate electrode 44 is disposed above the second semiconductor pattern 41 at an interval.

[0083] In a specific application, the first source electrode 32 and the second source electrode 42 are both connected to the data lines in the array substrate, and the first gate electrode 34 and the second gate electrode 44 are both connected to the scan lines in the array substrate. The data lines transfer data signals to the first source electrode 32 and the second source electrode 42, and the scan lines transfer scan signals to the first gate electrode 34 and the second gate electrode 44. The charged first gate electrode 34 and second gate electrode 44 can conductify the first semiconductor pattern 31 and the second semiconductor pattern 41 corresponding to them respectively. The conductified first semiconductor pattern 31 and second semiconductor pattern 41 transfer the signals of the first source electrode 32 and the second source electrode 42 to the first drain electrode 33 and the second drain electrode 43 respectively, thereby turning on the first thin film transistor 3 and the second thin film transistor 4. At this time, the first thin film transistor 3 and the second thin film transistor 4 can control the corresponding sub-pixels to display images.

[0084] In this embodiment, the first semiconductor pattern 31 in the first thin film transistor 3 is a polysilicon semiconductor pattern, and the second semiconductor pattern 41 in the second thin film transistor 4 is a metal oxide semiconductor pattern, that is, the first thin film transistor 3 is a polysilicon TFT, and the second thin film transistor 4 is a metal oxide TFT. Among them, the second semiconductor pattern 41 can be composed of indium gallium zinc oxide (abbreviation: IGZO) for example, or composed of Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In 2 O 3 :Sn, In 2 O 3 :Mo, Cd 2 SnO 4 、ZnO:Al, TiO 2 :Nb, Cd-Sn-O or other metal oxides.

[0085] By setting the polysilicon TFT as the first thin film transistor 3, the polysilicon TFT has a high mobility, and its mobility is usually greater than 30 cm 2 / V.s, which can meet the driving circuit with a relatively high frequency; by setting the metal oxide TFT as the second thin film transistor 4, although the mobility of the metal oxide TFT is slightly lower than that of the polysilicon TFT, its mobility is usually 10-30 cm 2 / V.s, but it can meet the driving requirements for sub-pixels, and the metal oxide TFT has good uniformity and high transparency, and the manufacturing process is simple, which can better meet the requirements of large-size liquid crystal displays and active organic electroluminescence, and can meet the requirements of LCDs and OLEDs with high refresh frequencies and high mobilities.

[0086] Since the mobility of the polysilicon TFT is relatively high and the off-state current of the metal oxide TFT is relatively small, in some embodiments, for the first thin film transistor 3 and the second thin film transistor 4 disposed within a sub-pixel, the polysilicon TFT serving as the first thin film transistor 3 can be used to drive its peripheral circuits. Since the integration degree of the peripheral region is high and the area is small, a higher mobility is required, and thus the polysilicon TFT with a high mobility can fully meet the requirements of the peripheral circuits; the metal oxide TFT serving as the second thin film transistor 4 can be used to drive the pixel electrode 9. The metal oxide TFT can meet the driving requirements of the sub-pixel and can effectively reduce the power consumption of the display panel.

[0087] Based on this, in this embodiment, by making full use of the performance of the polysilicon TFT and the metal oxide TFT, the polysilicon TFT and the metal oxide TFT are disposed in different regions within a sub-pixel to serve as the first thin film transistor 3 and the second thin film transistor 4 respectively, which can effectively solve the technical problem that the polysilicon TFT is not applicable to large-size display panels, and the use of the metal oxide TFT to drive the pixel electrode 9 can effectively reduce the power consumption of the display panel.

[0088] Among them, the off-state current of the TFT refers to the leakage current generated in the TFT when the TFT is in the off state.

[0089] It should be noted that for the same sub-pixel, the first source electrode 32 and the second source electrode 42 can be connected to the same data line, and signals are transmitted to the first source electrode 32 and the second source electrode 42 simultaneously by this data line; or, in the array substrate, there are different data lines respectively corresponding to and connected to the first source electrode 32 and the second source electrode 42, and signals are transmitted to the first source electrode 32 and the second source electrode 42 respectively through different data lines. For example, the data line corresponding to and connected to the first source electrode 32 is disposed on the same layer as the first source electrode 32, and the data line corresponding to and connected to the second source electrode 42 is disposed on the same layer as the second source electrode 42.

[0090] Similarly, for the same sub-pixel, the first gate electrode 34 and the second gate electrode 44 can be connected to the same scanning line, and signals are transmitted to the first gate electrode 34 and the second gate electrode 44 simultaneously by this scanning line; or, in the array substrate, there are different scanning lines respectively corresponding to and connected to the first gate electrode 34 and the second gate electrode 44, and signals are transmitted to the first gate electrode 34 and the second gate electrode 44 respectively through different scanning lines. The first gate electrode 34 and the second gate electrode 44 respectively independently control the states of the first semiconductor pattern 31 and the second semiconductor pattern 41 to achieve independent control of the first thin film transistor 3 and the second thin film transistor 4.

[0091] In this embodiment, the first semiconductor pattern 31 of the first thin-film transistor 3 and the second semiconductor pattern 41 of the second thin-film transistor 4 are both disposed close to the substrate 1, while on the contrary, the first gate 34 and the second gate 44 are disposed away from the substrate 1. Taking the array substrate applied to an LCD as an example, as Figure 1 shown, in order to prevent the light emitted by the backlight in the LCD from passing through the substrate 1 and irradiating the first semiconductor pattern 31 and the second semiconductor pattern 41, thereby generating photo-generated carriers on the first semiconductor pattern 31 and the second semiconductor pattern 41 and affecting the off-state current characteristics of the first thin-film transistor 3 and the second thin-film transistor 4, in this embodiment, a first light-shielding layer 21 and a second light-shielding layer 22 are disposed at intervals on the substrate 1, so as to prevent the light emitted by the backlight from affecting the stability of the first thin-film transistor 3 and the second thin-film transistor 4.

[0092] As Figure 1 shown, specifically, the first light-shielding layer 21 is correspondingly disposed below the first semiconductor pattern 31, and the second light-shielding layer 22 is correspondingly disposed below the second semiconductor pattern 41. Through the light-shielding effect of the first light-shielding layer 21 and the second light-shielding layer 22, the light emitted by the backlight can be prevented from irradiating the first semiconductor pattern 31 and the second semiconductor pattern 41, and further, the light can be avoided from affecting the semiconductor characteristics of the first semiconductor pattern 31 and the second semiconductor pattern 41, and the stability of the first thin-film transistor 3 and the second thin-film transistor 4 can be improved.

[0093] In order to ensure that the first semiconductor pattern 31 and the second semiconductor pattern 41 are completely not affected by the light emitted by the backlight, in a possible implementation manner, the orthographic projection of the first semiconductor pattern 31 on the substrate 1 may be located within the coverage range of the first light-shielding layer 21, and the orthographic projection of the second semiconductor pattern 41 on the substrate 1 may be located within the coverage range of the second light-shielding layer 22.

[0094] As Figure 1 shown, in this embodiment, the surface area of the first light-shielding layer 21 is larger than the surface area of the first semiconductor pattern 31, and the orthographic projection of the first semiconductor pattern 31 on the substrate 1 is located within the coverage range of the first light-shielding layer 21. The surface area of the second light-shielding layer 22 is larger than the surface area of the second semiconductor pattern 41, and the orthographic projection of the second semiconductor pattern 41 on the substrate 1 is located within the coverage range of the second light-shielding layer 22. In this way, the first light-shielding layer 21 can completely cover the first semiconductor pattern 31, and the second light-shielding layer 22 can completely cover the second semiconductor pattern 41, so as to protect all parts of the first semiconductor pattern 31 and the second semiconductor pattern 41 from being irradiated by the backlight, and further improve the stability of the first thin-film transistor 3 and the second thin-film transistor 4.

[0095] Specifically, the first light-shielding layer 21 and the second light-shielding layer 22 can be formed on the substrate 1 through the same process, and the thicknesses of the first light-shielding layer 21 and the second light-shielding layer 22 can be the same. Specifically, the thicknesses of the first light-shielding layer 21 and the second light-shielding layer 22 can be 300 to 1500 angstroms, and the first light-shielding layer 21 and the second light-shielding layer 22 can be made of metals or alloys with good thermal stability such as Cr, W, Ti, Ta, Mo, etc. Alternatively, the materials for fabricating the first light-shielding layer 21 and the second light-shielding layer 22 can also be selected from black organic resins or other light-impermeable materials.

[0096] It should be noted that materials with good thermal conductivity such as Al and Cu are generally not selected for the first light-shielding layer 21 and the second light-shielding layer 22, so as to prevent the heat generated during the high-temperature and high-heat process in the manufacturing process of the array substrate from affecting the performance of other structural layers of the array substrate due to the first light-shielding layer 21 and the second light-shielding layer 22.

[0097] As Figure 1 shown, in some embodiments, the array substrate may further include a buffer layer 5 and a gate insulating layer 6. The buffer layer 5 is disposed on the substrate 1 and covers the first light-shielding layer 21 and the second light-shielding layer 22. The first semiconductor pattern 31 and the second semiconductor pattern 41 are disposed on the buffer layer 5. The gate insulating layer 6 is disposed on the buffer layer 5 and covers the first semiconductor pattern 31 and the second semiconductor pattern 41. The first gate 34 and the second gate 44 are disposed on the gate insulating layer 6.

[0098] By providing the buffer layer 5 on the substrate 1, with the buffer layer 5 covering the first light-shielding layer 21 and the second light-shielding layer 22 and the first semiconductor pattern 31 and the second semiconductor pattern 41 being disposed on the buffer layer 5, the buffer layer 5 can protect the first semiconductor pattern 31 and the second semiconductor pattern 41, so as to protect the semiconductor performance of the first semiconductor pattern 31 and the second semiconductor pattern 41 from being affected.

[0099] In a specific embodiment, the buffer layer 5 may include a first buffer layer 51 and a second buffer layer 52 that are sequentially stacked on the substrate 1. By sequentially providing the first buffer layer 51 and the second buffer layer 52 on the substrate 1 and disposing the first semiconductor pattern 31 and the second semiconductor pattern 41 on the second buffer layer 52, the first buffer layer 51 and the second buffer layer 52 have a better protective effect on the first semiconductor pattern 31 and the second semiconductor pattern 41.

[0100] Specifically, the first buffer layer 51 may be a silicon nitride layer, and the second buffer layer 52 may be a silicon oxide layer. The silicon nitride layer, as the first buffer layer 51, is directly formed on the substrate 1, and it has a good effect of isolating water vapor, which can isolate the water vapor outside the array substrate or from the substrate 1 and prevent the water vapor from entering the first semiconductor pattern 31 and the second semiconductor pattern 41. The silicon oxide layer, as the second buffer layer 52, is in direct contact with the first semiconductor pattern 31 and the second semiconductor pattern 41. It has good compactness and contains a large number of oxygen atoms. These oxygen atoms can diffuse into the first semiconductor pattern 31 and the second semiconductor pattern 41 to supplement the oxygen atoms of the two, helping the first semiconductor pattern 31 and the second semiconductor pattern 41 maintain their semiconductor characteristics, so as to prevent the oxygen atoms in the first semiconductor pattern 31 (the second semiconductor pattern 41) from combining with the metal ions in the first source electrode 32 (the second source electrode 42) or the first drain electrode 33 (the second drain electrode 43) and causing them to lose their semiconductor characteristics.

[0101] Exemplarily, the thickness of the silicon nitride layer as the first buffer layer 51 may be 1000 - 4000 angstroms, and the thickness of the silicon oxide layer as the second buffer layer 52 may be 200 - 2000 angstroms.

[0102] As Figure 1 As shown, in this embodiment, the first semiconductor pattern 31 and the second semiconductor pattern 41 are disposed on the buffer layer 5, and a gate insulating layer 6 is further disposed on the buffer layer 5. The first gate 34 and the second gate 44 are disposed on the gate insulating layer 6. The gate insulating layer 6 covers the first semiconductor pattern 31 and the second semiconductor pattern 41. By providing the gate insulating layer 6 between the first gate 34 and the first semiconductor pattern 31, and between the second gate 44 and the second semiconductor pattern 41, on the one hand, the gate insulating layer 6 plays an insulating and spacing role. In this way, when an electrical signal is generated in the first gate 34 and the second gate 44, the first gate 34 (the second gate 44) can conduct the first semiconductor pattern 31 (the second semiconductor pattern 41) through the gate insulating layer 6, so that the first semiconductor pattern 31 (the second semiconductor pattern 41) can transfer the signal in the first source electrode 32 (the second source electrode 42) to the first drain electrode 33 (the second drain electrode 43). On the other hand, the gate insulating layer 6 can protect the first semiconductor pattern 31 (the second semiconductor pattern 41) from the influence of metal ion diffusion in the first gate 34 (the second gate 44), so that the first semiconductor pattern 31 (the second semiconductor pattern 41) maintains its semiconductor performance.

[0103] As Figure 1As shown, in a specific embodiment, the gate insulating layer 6 may include a first silicon oxide layer 61 and a second silicon oxide layer 62 that are sequentially stacked on the buffer layer 5, and the density of the first silicon oxide layer 61 is higher than that of the second silicon oxide layer 62. In this embodiment, the gate insulating layer 6 may be a silicon oxide layer, and the oxygen atoms rich in the silicon oxide layer can absorb the metal ions diffusing from the first gate 34 (second gate 44) to the first semiconductor pattern 31 (second semiconductor pattern 41), ensuring the semiconductor characteristics of the first semiconductor pattern 31 (second semiconductor pattern 41).

[0104] By setting the first silicon oxide layer 61 and the second silicon oxide layer 62 stacked in sequence as the gate insulating layer 6, when the metal ions in the first gate 34 (second gate 44) diffuse to the first semiconductor pattern 31 (second semiconductor pattern 41), they will first diffuse to the second silicon oxide layer 62, and the second silicon oxide layer 62 will absorb some or all of the metal ions. The remaining metal ions continue to diffuse to the first silicon oxide layer 61, and the first silicon oxide layer 61 can completely absorb the remaining metal ions. Therefore, by setting the two silicon oxide layers of the first silicon oxide layer 61 and the second silicon oxide layer 62, it can be ensured that the gate insulating layer 6 completely absorbs the diffused metal ions, effectively ensuring the semiconductor characteristics of the first semiconductor pattern 31 (second semiconductor pattern 41).

[0105] Among them, the density of the first silicon oxide layer 61 directly stacked on the first semiconductor pattern 31 (second semiconductor pattern 41) is higher than that of the second silicon oxide layer 62. Specifically, compared with the second silicon oxide layer 62, the first silicon oxide layer 61 can be deposited at a low speed and low temperature to form a more dense silicon oxide layer. The first silicon oxide layer 61 has good flatness and, as the interface of the polysilicon TFT, is conducive to the transmission of carriers, improving the mobility of the polysilicon TFT, and thus improving the driving ability of the polysilicon TFT.

[0106] In addition, the first silicon oxide layer 61 with better density can be set as a thinner silicon oxide layer, further reducing the thickness of the array substrate on the basis of ensuring that the first silicon oxide layer 61 and the second silicon oxide layer 62 can completely absorb the diffused metal ions. Exemplarily, the thickness of the first silicon oxide layer 61 can be 300 - 1500 angstroms, and the thickness of the second silicon oxide layer 62 can be 1000 - 8000 angstroms.

[0107] It should be noted that, as described above, the first gate 34 (second gate 44) controls the switching state of the first thin-film transistor 3 (second thin-film transistor 4) by generating induced charges in the first semiconductor pattern 31 (second semiconductor pattern 41) spaced from it. Since a first light-shielding layer 21 (second light-shielding layer 22) is also provided at an interval below the first gate 34 (second gate 44), when an electrical signal is generated in the first gate 34 (second gate 44), induced charges will also be generated in the first light-shielding layer 21 (second light-shielding layer 22), which will directly affect the stability of the first thin-film transistor 3 (second thin-film transistor 4).

[0108] In this regard, in order to prevent the generation of induced charges in the first light-shielding layer 21 (second light-shielding layer 22) from affecting the stability of the first thin-film transistor 3 (second thin-film transistor 4), in this embodiment, by electrically connecting the first light-shielding layer 21 (second light-shielding layer 22) to the first gate 34 (second gate 44), the first light-shielding layer 21 (second light-shielding layer 22) and the first gate 34 (second gate 44) are at the same potential, thereby avoiding the first light-shielding layer 21 (second light-shielding layer 22) from affecting the stability of the first thin-film transistor 3 (second thin-film transistor 4).

[0109] Specifically, in this embodiment, through holes, i.e., a first contact hole a and a second contact hole b, are provided in the gate insulating layer 6 and the buffer layer 5. The first gate 34 is in contact with the first light-shielding layer 21 through the first contact hole a, and the second gate 44 is in contact with the second light-shielding layer 22 through the second contact hole b.

[0110] Figure 2 It is a top view structural diagram of forming the first contact hole and the second contact hole in the gate insulating layer and the buffer layer provided in the first embodiment of the present invention. As Figure 2 shown, by opening through holes, i.e., a first contact hole a (second contact hole b), in the gate insulating layer 6 and the buffer layer 5 corresponding to the first gate 34 (second gate 44) and the first light-shielding layer 21 (second light-shielding layer 22), a partial area of the first light-shielding layer 21 (second light-shielding layer 22) is exposed in the first contact hole a (second contact hole b). In this way, when the first gate 34 (second gate 44) is formed on the gate insulating layer 6, the first gate 34 (second gate 44) can be in contact with the first light-shielding layer 21 (second light-shielding layer 22) through the first contact hole a (second contact hole b). Furthermore, the first gate 34 (second gate 44) and the first light-shielding layer 21 (second light-shielding layer 22) are at the same potential, and no induced charges will be generated in the first light-shielding layer 21 (second light-shielding layer 22), thus not affecting the stability of the first thin-film transistor 3 (second thin-film transistor 4).

[0111] As Figure 1As shown, the array substrate provided in this embodiment may further include a gate protection layer 7. The gate protection layer 7 is disposed on the gate insulating layer 6 and covers the first gate 34 and the second gate 44. The first source electrode 32, the first drain electrode 33, the second source electrode 42, and the second drain electrode 43 are disposed on the gate protection layer 7.

[0112] The first thin-film transistor 3 and the second thin-film transistor 4 are protected by the gate protection layer 7. The gate protection layer 7 can separate the first source electrode 32 (the second source electrode 42), the first drain electrode 33 (the second drain electrode 43) from the first gate 34 (the second gate 44) to prevent the metal ions among the three from diffusing into each other, which may cause the short-circuit failure of the first thin-film transistor 3 (the second thin-film transistor 4).

[0113] As Figure 1 shown, specifically, through holes, namely the third contact hole c, the fourth contact hole d, the fifth contact hole e, and the sixth contact hole f, are provided in the gate protection layer 7 and the gate insulating layer 6. The first source electrode 32 and the first drain electrode 33 are respectively in contact with the first semiconductor pattern 31 through the third contact hole c and the fourth contact hole d, and the second source electrode 42 and the second drain electrode 43 are respectively in contact with the second semiconductor pattern 41 through the fifth contact hole e and the sixth contact hole f.

[0114] By respectively providing the third contact hole c (the fifth contact hole e) and the fourth contact hole d (the sixth contact hole f) at the positions corresponding to both sides of the first semiconductor pattern 31 (the second semiconductor pattern 41) in the gate protection layer 7 and the gate insulating layer 6, when the first source electrode 32 (the second source electrode 42) and the first drain electrode 33 (the second drain electrode 43) are formed on the gate protection layer 7, the first source electrode 32 (the second source electrode 42) and the first drain electrode 33 (the second drain electrode 43) can be in contact with both sides of the first semiconductor pattern 31 (the second semiconductor pattern 41) through the third contact hole c (the fifth contact hole e) and the fourth contact hole d (the sixth contact hole f).

[0115] Among them, the first gate 34 (the second gate 44), the first source electrode 32 (the second source electrode 42), and the first drain electrode 33 (the second drain electrode 43) can be made of metals or alloys such as Cr, W, Ti, Ta, Mo, Al, Cu, etc.

[0116] In a possible implementation manner, the array substrate may further include a passivation layer 8 and a pixel electrode 9. The passivation layer 8 is disposed on the gate protection layer 7 and covers the first source electrode 32, the first drain electrode 33, the second source electrode 42, and the second drain electrode 43. The pixel electrode 9 is disposed on the passivation layer 8. A conductive via 81 is provided in the passivation layer 8, and the second drain electrode 43 is in contact with the second drain electrode 43 through the conductive via 81.

[0117] As Figure 1As shown, by providing a passivation layer 8 on the gate protection layer 7, the passivation layer 8 can protect the first source electrode 32, the first drain electrode 33, the second source electrode 42, and the second drain electrode 43 from damage. The passivation layer 8 can isolate external moisture and can play a role in planarizing the array substrate. Exemplarily, the passivation layer 8 can be an oxide layer, a nitride layer, or an oxynitride layer.

[0118] The pixel electrode 9 is provided on the passivation layer 8. A conductive via 81 penetrating the passivation layer 8 is formed at a position corresponding to the second drain electrode 43 in the passivation layer 8. The pixel electrode 9 is in contact with the second drain electrode 43 through the conductive via 81, so that the second thin-film transistor 4 can drive the pixel electrode 9. It should be noted that in this embodiment, the second semiconductor pattern 41 is a metal oxide semiconductor pattern, and the second thin-film transistor 4 is a metal oxide TFT. By driving the pixel electrode 9 with the metal oxide TFT, the power consumption of the display panel can be reduced; by using another polysilicon TFT as the first thin-film transistor 3 to drive the peripheral circuit, the requirement of the peripheral circuit for the TFT mobility can be met.

[0119] The array substrate provided in this embodiment is provided with a first thin-film transistor and a second thin-film transistor on the substrate. The first semiconductor pattern of the first thin-film transistor is a polysilicon semiconductor pattern, and the second semiconductor pattern of the second thin-film transistor is a metal oxide semiconductor pattern, that is, the first thin-film transistor is a polysilicon TFT, and the second thin-film transistor is a metal oxide TFT; in practical applications, the high mobility characteristic of the polysilicon TFT can be utilized to drive the peripheral circuit, and the characteristic of the small off-state current of the metal oxide TFT can be utilized to drive the pixel electrode. The first thin-film transistor and the second thin-film transistor act together on each pixel of the array substrate, which can meet the high-resolution requirement of the large-size display panel and can reduce the power consumption of the display panel; wherein, by providing a first light-shielding layer and a second light-shielding layer at positions corresponding to the first semiconductor pattern and the second semiconductor pattern on the substrate, light can be prevented from irradiating the first semiconductor pattern and the second semiconductor pattern, so as not to affect the stability of the first thin-film transistor and the second thin-film transistor.

[0120] Embodiment 2

[0121] Figure 3 is a schematic flow chart of the manufacturing method of the low-temperature polycrystalline oxide array substrate provided in the second embodiment of the present invention. As Figure 3 shown, this embodiment provides a manufacturing method of a low-temperature polycrystalline oxide array substrate, and this manufacturing method is used to manufacture the low-temperature polycrystalline oxide array substrate described in Embodiment 1. Among them, the structure, function, and working principle of the low-temperature polycrystalline oxide array substrate are introduced in detail in Embodiment 1, and will not be elaborated here.

[0122] As Figure 3As shown, the method for fabricating a low-temperature polycrystalline oxide array substrate includes the following steps:

[0123] S100. Form spaced first light-shielding layer 21 and second light-shielding layer 22 on substrate 1.

[0124] Figure 4 It is a schematic structural diagram of forming spaced first light-shielding layer and second light-shielding layer on a substrate provided in the second embodiment of the present invention. As Figure 4 shown, first deposit a light-shielding layer on substrate 1. Specifically, use sputtering or thermal evaporation to deposit a light-shielding layer with a thickness of about 300 - 1500 angstroms on substrate 1. The material for forming the light-shielding layer can be selected from metals or alloys with good thermal stability such as Cr, W, Ti, Ta, Mo, or black organic resin, or other light-impermeable materials.

[0125] Then perform a photolithography process on the light-shielding layer to form first light-shielding layer 21 and second light-shielding layer 22. After depositing and forming the light-shielding layer, through the first photolithography process, pattern the light-shielding layer to form spaced first light-shielding layer 21 and second light-shielding layer 22 on substrate 1.

[0126] It should be noted that the process of performing a photolithography process on the light-shielding layer to form first light-shielding layer 21 and second light-shielding layer 22 can be as follows: First, coat a photoresist layer on the light-shielding layer. Set a mask plate above the light-shielding layer. The mask plate is provided with a light-transmitting area and a light-impermeable area. Ultraviolet light irradiates the surface of the photoresist layer through the mask plate, causing a chemical reaction in the photoresist in the exposed area of the photoresist layer. Then, dissolve and remove the photoresist in the exposed area (positive photoresist) or the unexposed area (negative photoresist) through a developing technique; thus, the remaining photoresist in the photoresist layer only covers the areas corresponding to first light-shielding layer 21 and second light-shielding layer 22 in the light-shielding layer, and other areas of the light-shielding layer are exposed. At this time, etch the exposed areas of the light-shielding layer, and finally only first light-shielding layer 21 and second light-shielding layer 22 are retained. Finally, remove the photoresist covering first light-shielding layer 21 and second light-shielding layer 22, and first light-shielding layer 21 and second light-shielding layer 22 can be formed on substrate 1.

[0127] It can be understood that the exposure and developing process of using ultraviolet light to irradiate the photoresist layer through the mask plate to transfer the mask pattern on the mask plate to the photoresist layer to form a photoresist layer pattern, and the etching process of etching the area not covered by the photoresist layer after forming the photoresist layer pattern are the same as or similar to the above process flow. For the exposure, developing, and etching processes that appear after this embodiment, they will not be elaborated one by one.

[0128] S200. Form a first semiconductor pattern 31 and a second semiconductor pattern 41 on the first light-shielding layer 21 and the second light-shielding layer 22 respectively; wherein, the first semiconductor pattern 31 is a polysilicon semiconductor pattern, and the second semiconductor pattern 41 is a metal oxide semiconductor pattern.

[0129] Figure 5 It is a schematic flow chart of forming a first semiconductor pattern and a second semiconductor pattern on a first light-shielding layer and a second light-shielding layer provided in Embodiment 2 of the present invention; Figure 6 It is a schematic structural diagram of forming a buffer layer on a substrate provided in Embodiment 2 of the present invention; Figure 7 It is a schematic structural diagram of forming a first semiconductor pattern on a buffer layer provided in Embodiment 2 of the present invention; Figure 8 It is a schematic structural diagram of forming a second semiconductor pattern on a buffer layer provided in Embodiment 2 of the present invention.

[0130] As Figure 5 shown, step S200 specifically includes the following steps:

[0131] S210. Deposit and form a buffer layer 5 on the substrate 1, and the buffer layer 5 covers the first light-shielding layer 21 and the second light-shielding layer 22.

[0132] As Figure 6 shown, after forming the first light-shielding layer 21 and the second light-shielding layer 22 on the substrate 1, a buffer layer 5 with a thickness of 2000 - 15000 angstroms is continuously deposited on the substrate 1 by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process.

[0133] Among them, depositing the buffer layer 5 includes first depositing a silicon nitride layer with a thickness of 1000 - 4000 angstroms on the substrate 1 as the first buffer layer 51, and the reaction gases used for depositing the silicon nitride layer are SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 ; then depositing a silicon oxide layer with a thickness of 200 - 2000 angstroms on the silicon nitride layer as the second buffer layer 52, and the reaction gases used for depositing the silicon oxide layer are SiH 4 , N 2 O.

[0134] It should be noted that in this embodiment, the second buffer layer 52 in contact with the first semiconductor pattern 31 is made of a silicon oxide layer. If the second buffer layer 52 in direct contact with the first semiconductor pattern 31 is composed of silicon nitride or silicon oxynitride, since the H content in the second buffer layer 52 is relatively high, in order to improve the stability of the first thin film transistor 3, a high-temperature annealing process can be performed on the second buffer layer 52 to reduce the H in the second buffer layer 52. At the same time, it can avoid the H explosion in the ELA annealing process during the formation of the first semiconductor pattern 31 (polycrystalline semiconductor pattern). While improving the performance of the polycrystalline TFT, it can prevent the polycrystalline TFT from experiencing an H explosion.

[0135] S220. Deposit and form an amorphous silicon layer on the buffer layer 5.

[0136] S230. Perform an annealing process on the amorphous silicon layer to form a polycrystalline silicon layer.

[0137] S240. Perform a photolithography process on the polycrystalline silicon layer to form the first semiconductor pattern 31.

[0138] As Figure 7 shown, after forming the buffer layer 5, an amorphous silicon layer with a thickness of 200 - 800 angstroms is continuously deposited on the buffer layer 5 through the PECVD process. After forming the amorphous silicon layer, a high-temperature annealing is performed on the amorphous silicon layer. For example, using the ELA process for annealing, the amorphous silicon layer is melted within a short time and recrystallized to grow into a polycrystalline silicon layer; alternatively, a rapid annealing furnace can also be used for high-temperature annealing. For example, annealing at a temperature above 600 °C causes the amorphous silicon layer to melt and then grow into a polycrystalline silicon layer. After forming the polycrystalline silicon layer, through the second photolithography process, the polycrystalline silicon layer is patterned into the first semiconductor pattern 31.

[0139] S250. Deposit and form a metal oxide semiconductor layer on the buffer layer 5, and the metal oxide semiconductor layer covers the first semiconductor pattern 31.

[0140] S260. Perform a photolithography process on the metal oxide semiconductor layer to form the second semiconductor pattern 41.

[0141] As Figure 8 shown, after forming the first semiconductor pattern 31 on the buffer layer 5, a metal oxide semiconductor layer with a thickness of about 100 - 2000 angstroms is deposited on the buffer layer 5 by sputtering or thermal evaporation. The metal oxide semiconductor layer can be composed of indium gallium zinc oxide (abbreviation: IGZO), or composed of Ln - IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In 2 O 3 :Sn, In 2 O 3 :Mo, Cd2 SnO 4 , ZnO:Al, TiO 2 :Nb, Cd - Sn - O or other metal oxides. Then, through the third lithography process, the metal oxide semiconductor layer is patterned into the second semiconductor pattern 41.

[0142] S300. Form a first gate 34 and a second gate 44 above the first semiconductor pattern 31 and the second semiconductor pattern 41 respectively; wherein, the first gate 34 contacts the first light - shielding layer 21 through the first contact hole a, and the second gate 44 contacts the second light - shielding layer 22 through the second contact hole b.

[0143] Figure 9 It is a schematic flow chart for forming a first gate and a second gate above the first semiconductor pattern and the second semiconductor pattern respectively provided in the second embodiment of the present invention; Figure 10 It is a schematic structural diagram for forming a gate insulating layer on a buffer layer provided in the second embodiment of the present invention; Figure 11 It is a schematic structural diagram for forming a first gate and a second gate on the gate insulating layer provided in the second embodiment of the present invention.

[0144] As Figure 9 shown, step S300 specifically includes the following steps:

[0145] S310. Deposit and form a gate insulating layer 6 on the buffer layer 5, and the gate insulating layer 6 covers the first semiconductor pattern 31 and the second semiconductor pattern 41.

[0146] As Figure 10 shown, after forming the first semiconductor pattern 31 and the second semiconductor pattern 41 on the buffer layer 5, deposit the gate insulating layer 6 on the buffer layer 5 through the PECVD process. Specifically, depositing the gate insulating layer 6 includes sequentially depositing a first silicon oxide layer 61 and a second silicon oxide layer 62 on the buffer layer 5.

[0147] First, deposit a first silicon oxide layer 61 with a thickness of about 300 - 1500 Å on the buffer layer 5 at a low speed and low temperature. The reaction gas can be SiH 4 , N 2 O. The H content in the first silicon oxide layer 61 is less than 6%, for example, the H content is between 3% - 4%, which can reduce the influence of H on the second semiconductor pattern 41; then deposit a second silicon oxide layer 62 with a thickness of about 1000 - 8000 Å on the first silicon oxide layer 61 at a high speed and high temperature. The reaction gas can be SiH 4 , N 2 O.

[0148] S320. Form a through - first contact hole a and a through - second contact hole b in the gate insulating layer 6 and the buffer layer 5. Refer toFigure 2 As shown, first contact holes a and second contact holes b are respectively formed at positions corresponding to the first light-shielding layer 21 and the second light-shielding layer 22 in the gate insulating layer 6 and the buffer layer 5. For example, the first contact holes a and the second contact holes b can be formed by dry etching. In this way, when the first gate 34 and the second gate 44 are formed subsequently, the first gate 34 and the second gate 44 can be in contact with the first light-shielding layer 21 and the second light-shielding layer 22 through the first contact holes a and the second contact holes b respectively.

[0149] S330. Deposit and form a gate metal layer on the gate insulating layer 6.

[0150] S340. Perform a photolithography process on the gate metal layer to form the first gate 34 and the second gate 44; wherein, the first gate 34 is in contact with the first light-shielding layer 21 through the first contact hole a, and the second gate 44 is in contact with the second light-shielding layer 22 through the second contact hole b.

[0151] As Figure 11 shown, a gate metal layer with a thickness of about 500 - 4000 angstroms is continuously deposited on the gate insulating layer 6 by sputtering or thermal evaporation. The gate metal layer can be selected from metals or alloys such as Cr, W, Ti, Ta, Mo, Al, Cu, etc. Then, through the fourth photolithography process, the gate metal layer is patterned into the first gate 34 and the second gate 44.

[0152] S400. Simultaneously form a first source electrode 32 and a first drain electrode 33 connected to both sides of the first semiconductor pattern 31 and a second source electrode 42 and a second drain electrode 43 connected to both sides of the second semiconductor pattern 41 above the first gate 34 and the second gate 44.

[0153] Figure 12 It is a schematic flow chart for forming the first source electrode, the first drain electrode, the second source electrode and the second drain electrode provided by the second embodiment of the present invention; Figure 13 It is a schematic structural diagram for forming a gate protection layer on the gate insulating layer provided by the second embodiment of the present invention; Figure 14 It is a schematic structural diagram for forming third contact holes, fourth contact holes, fifth contact holes and sixth contact holes in the gate protection layer and the gate insulating layer provided by the second embodiment of the present invention; Figure 15 It is a schematic structural diagram for forming the first source electrode, the first drain electrode, the second source electrode and the second drain electrode on the gate protection layer provided by the second embodiment of the present invention.

[0154] As Figure 12 shown, step S400 specifically includes the following steps:

[0155] S410. Deposit and form a gate protection layer 7 on the gate insulating layer 6, and the gate protection layer 7 covers the first gate 34 and the second gate 44.

[0156] AsFigure 13 As shown, after the first gate 34 and the second gate 44 are formed on the gate insulating layer 6, a gate protection layer 7 with a thickness of about 2000 - 10000 angstroms is deposited on the gate insulating layer 6 through the PECVD process. The gate protection layer 7 can be selected from oxides, nitrides or oxynitrides. Among them, the reaction gas corresponding to the oxide of silicon can be SiH 4 、N 2 O, and the reaction gases corresponding to nitrides or oxynitrides can be SiH 4 、NH 3 、N 2 or SiH 2 Cl 2 、NH 3 、N 2 .

[0157] S420. Third contact holes c, fourth contact holes d, fifth contact holes e and sixth contact holes f that penetrate through are formed in the gate protection layer 7 and the gate insulating layer 6.

[0158] As Figure 14 shown, after the gate protection layer 7 is formed, through the fifth photolithography process, the third contact holes c and the fourth contact holes d are respectively formed in the parts of the gate protection layer 7 and the gate insulating layer 6 corresponding to both sides of the first semiconductor pattern 31, and the fifth contact holes e and the sixth contact holes f are respectively formed in the parts corresponding to both sides of the second semiconductor pattern 41.

[0159] S430. A source-drain metal layer is deposited and formed on the gate protection layer 7.

[0160] S440. A photolithography process is performed on the source-drain metal layer to form a first source 32, a first drain 33, a second source 42 and a second drain 43. Among them, the first source 32 and the first drain 33 are respectively in contact with the first semiconductor pattern 31 through the third contact holes c and the fourth contact holes d, and the second source 42 and the second drain 43 are respectively in contact with the second semiconductor pattern 41 through the fifth contact holes e and the sixth contact holes f.

[0161] As Figure 15 shown, after step S420 is completed, a source-drain metal layer with a thickness of about 500 - 4000 angstroms is continuously deposited on the gate protection layer 7 by sputtering or thermal evaporation. The material for forming the source-drain metal layer can be selected from metals or alloys such as Cr, W, Ti, Ta, Mo, Al, Cu, etc. Then, through the sixth photolithography process, the source-drain metal layer is patterned into the first source 32, the first drain 33, the second source 42 and the second drain 43.

[0162] In a possible implementation manner, after the first source 32, the first drain 33, the second source 42 and the second drain 43 are formed, the following steps may further be included:

[0163] S500. Form a passivation layer 8 and a pixel electrode 9 on the gate protection layer 7.

[0164] Figure 16 This is a schematic structural diagram of forming a passivation layer and a pixel electrode on the gate protection layer provided in the second embodiment of the present invention. As Figure 16 shown, S500 specifically includes the following steps:

[0165] First, deposit and form a passivation layer 8 on the gate protection layer 7. The passivation layer 8 can be selected from oxides, nitrides or oxynitrides. Among them, the reaction gas corresponding to the oxide of silicon can be SiH 4 , N 2 O, and the reaction gas corresponding to the nitride or oxynitride can be SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 . The formed passivation layer 8 covers the first source electrode 32, the first drain electrode 33, the second source electrode 42 and the second drain electrode 43.

[0166] Then, form a through conductive via 81 at the position corresponding to the second drain electrode 43 in the passivation layer 8. Specifically, the conductive via 81 can be etched in the passivation layer 8 by means of dry etching. After that, deposit and form a transparent conductive layer on the passivation layer 8. The transparent conductive layer can be, for example, an indium tin oxide (ITO) layer. The transparent conductive layer is in contact with the second drain electrode 43 through the conductive via 81. Finally, pattern the transparent conductive layer into a pixel electrode 9 through a photolithography process.

[0167] This embodiment also provides a display panel. The display panel includes a color filter substrate, a liquid crystal layer and an array substrate. The color filter substrate and the array substrate are disposed opposite to each other, and the liquid crystal layer is sandwiched between the color filter substrate and the array substrate. By applying an electric field between the array substrate and the color filter substrate, the voltage in the electric field can control the arrangement state of the liquid crystal molecules in the liquid crystal layer, so as to achieve the purpose of blocking light and transmitting light, and enable the display panel to display an image.

[0168] Among them, the structure, function and working principle of the array substrate are introduced in detail in the first embodiment, and will not be elaborated here.

[0169] On the other hand, this embodiment also provides a display device. The display device includes the above display panel. Exemplarily, in this embodiment, the display device can be a liquid crystal TV, a notebook computer, a tablet computer, an electronic paper, etc.

[0170] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-temperature polycrystalline oxide array substrate, characterized in that, it includes a substrate, a first light-shielding layer, a second light-shielding layer, a first thin-film transistor, and a second thin-film transistor. The first light-shielding layer and the second light-shielding layer are arranged at intervals on the substrate. The substrate is a glass substrate or an organic substrate. The first thin-film transistor and the second thin-film transistor are respectively arranged above the first light-shielding layer and the second light-shielding layer along the stacking direction of the array substrate; the first thin-film transistor includes a first semiconductor pattern above the first light-shielding layer, a first source electrode and a first drain electrode respectively connected to both sides of the first semiconductor pattern, and a first gate electrode arranged at intervals above the first semiconductor pattern; the second thin-film transistor includes a second semiconductor pattern above the second light-shielding layer, a second source electrode and a second drain electrode respectively connected to both sides of the second semiconductor pattern, and a second gate electrode arranged at intervals above the second semiconductor pattern; wherein, the first semiconductor pattern is a polycrystalline silicon semiconductor pattern, and the second semiconductor pattern is a metal oxide semiconductor pattern; it further includes a buffer layer and a gate insulating layer. The buffer layer is arranged on the substrate and covers the first light-shielding layer and the second light-shielding layer. The first semiconductor pattern and the second semiconductor pattern are arranged on the buffer layer; the gate insulating layer is arranged on the buffer layer and covers the first semiconductor pattern and the second semiconductor pattern. The first gate electrode and the second gate electrode are arranged on the gate insulating layer; through first contact holes and second contact holes are provided in the gate insulating layer and the buffer layer. The first gate electrode contacts the first light-shielding layer through the first contact hole, and the second gate electrode contacts the second light-shielding layer through the second contact hole.

2. The low-temperature polycrystalline oxide array substrate according to claim 1, characterized in that, the orthographic projection of the first semiconductor pattern on the substrate is located within the coverage of the first light-shielding layer, and the orthographic projection of the second semiconductor pattern on the substrate is located within the coverage of the second light-shielding layer.

3. The low-temperature polycrystalline oxide array substrate according to claim 1, characterized in that, the buffer layer includes a first buffer layer and a second buffer layer stacked in sequence on the substrate; wherein, the first buffer layer is a silicon nitride layer, and the second buffer layer is a silicon oxide layer.

4. The low-temperature polycrystalline oxide array substrate according to any one of claims 1-3, characterized in that, the gate insulating layer includes a first silicon oxide layer and a second silicon oxide layer stacked in sequence on the buffer layer, and the density of the first silicon oxide layer is higher than that of the second silicon oxide layer.

5. The low-temperature polycrystalline oxide array substrate according to any one of claims 1-3, characterized in that, it further includes a gate protection layer. The gate protection layer is arranged on the gate insulating layer and covers the first gate electrode and the second gate electrode.

6. The low-temperature polycrystalline oxide array substrate according to claim 5, characterized in that, The first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are disposed on the gate protection layer. Through holes including a third contact hole, a fourth contact hole, a fifth contact hole, and a sixth contact hole are formed in the gate protection layer and the gate insulating layer. The first source electrode and the first drain electrode are respectively in contact with the first semiconductor pattern through the third contact hole and the fourth contact hole, and the second source electrode and the second drain electrode are respectively in contact with the second semiconductor pattern through the fifth contact hole and the sixth contact hole.

7. The low-temperature polycrystalline oxide array substrate according to claim 6, wherein, it further includes a passivation layer and a pixel electrode. The passivation layer is disposed on the gate protection layer and covers the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode. The pixel electrode is disposed on the passivation layer. A conductive via hole is formed in the passivation layer, and the second drain electrode is in contact with the second drain electrode through the conductive via hole.

8. A method for manufacturing a low-temperature polycrystalline oxide array substrate, which is used to manufacture the low-temperature polycrystalline oxide array substrate according to any one of claims 1-7, wherein, it includes the following steps: forming spaced-apart first and second light-shielding layers on a substrate; forming a first semiconductor pattern and a second semiconductor pattern above the first light-shielding layer and the second light-shielding layer respectively; wherein, the first semiconductor pattern is a polycrystalline silicon semiconductor pattern, and the second semiconductor pattern is a metal oxide semiconductor pattern; forming a first gate and a second gate above the first semiconductor pattern and the second semiconductor pattern respectively; simultaneously forming a first source electrode, a first drain electrode connected to both sides of the first semiconductor pattern and a second source electrode, a second drain electrode connected to both sides of the second semiconductor pattern above the first gate and the second gate; and making the first gate in contact with the first light-shielding layer through a first contact hole, and the second gate in contact with the second light-shielding layer through a second contact hole.

9. The method for manufacturing a low-temperature polycrystalline oxide array substrate according to claim 8, wherein, the forming of the first semiconductor pattern and the second semiconductor pattern above the first light-shielding layer and the second light-shielding layer respectively specifically includes the following steps: depositing and forming a buffer layer on the substrate, the buffer layer covering the first light-shielding layer and the second light-shielding layer; depositing and forming an amorphous silicon layer on the buffer layer; performing an annealing process on the amorphous silicon layer to form a polycrystalline silicon layer; performing a photolithography process on the polycrystalline silicon layer to form the first semiconductor pattern; depositing and forming a metal oxide semiconductor layer on the buffer layer, the metal oxide semiconductor layer covering the first semiconductor pattern; performing a photolithography process on the metal oxide semiconductor layer to form the second semiconductor pattern.

10. The method for manufacturing a low-temperature polycrystalline oxide array substrate according to claim 9, wherein, the forming of the first gate and the second gate above the first semiconductor pattern and the second semiconductor pattern respectively specifically includes the following steps: A gate insulating layer is deposited on the buffer layer, and the gate insulating layer covers the first semiconductor pattern and the second semiconductor pattern; A through first contact hole and a second contact hole are formed in the gate insulating layer and the buffer layer; A gate metal layer is deposited on the gate insulating layer; A photolithography process is performed on the gate metal layer to form the first gate and the second gate; wherein, the first gate contacts the first light-shielding layer through the first contact hole, and the second gate contacts the second light-shielding layer through the second contact hole.

11. The method for manufacturing a low-temperature polycrystalline oxide array substrate according to claim 10, characterized in that, The steps of simultaneously forming a first source electrode, a first drain electrode connected to both sides of the first semiconductor pattern and a second source electrode and a second drain electrode connected to both sides of the second semiconductor pattern above the first gate and the second gate specifically include the following steps: A gate protection layer is deposited on the gate insulating layer, and the gate protection layer covers the first gate and the second gate; A through third contact hole, a fourth contact hole, a fifth contact hole and a sixth contact hole are formed in the gate protection layer and the gate insulating layer; A source-drain metal layer is deposited on the gate protection layer; A first photolithography process is performed on the source-drain metal layer to form the first source electrode, the first drain electrode, the second source electrode and the second drain electrode; wherein, the first source electrode and the first drain electrode contact the first semiconductor pattern through the third contact hole and the fourth contact hole respectively, and the second source electrode and the second drain electrode contact the second semiconductor pattern through the fifth contact hole and the sixth contact hole respectively.

12. The method for manufacturing a low-temperature polycrystalline oxide array substrate according to claim 11, characterized in that, After simultaneously forming a first source electrode, a first drain electrode connected to both sides of the first semiconductor pattern and a second source electrode and a second drain electrode connected to both sides of the second semiconductor pattern above the first gate and the second gate, the following steps are further included: A passivation layer is deposited on the gate protection layer, and the passivation layer covers the first source electrode, the first drain electrode, the second source electrode and the second drain electrode; A through conductive via is formed in a portion of the passivation layer corresponding to the second drain electrode; A transparent conductive layer is deposited on the passivation layer; A photolithography process is performed on the transparent conductive layer to form a pixel electrode, and the pixel electrode contacts the second drain electrode through the conductive via.

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