A chip layout structure

Abstract

The embodiment of the present invention provides a chip layout structure, which includes a non-copyable functional unit matrix, namely a PUF unit matrix, a peripheral circuit unit and a grounding protection groove; the peripheral circuit unit is arranged around the PUF unit matrix; the grounding protection groove is arranged between the PUF unit matrix and the peripheral circuit unit. By arranging the grounding protection groove between the PUF unit matrix and the peripheral circuit unit, the instability caused by the peripheral circuit affecting the function mapping of the PUF unit matrix is ​​overcome, and the failure of the PUF chip caused by the instability is avoided; this layout design method is suitable for all types of PUF chips.

Description

Technical Field

[0001] The invention belongs to the field of electricity, and in particular relates to a chip layout structure. Background Art

[0002] Unclonable function chips (PUF chips) have been proven to be used for identification, authentication, and encryption / decryption functions in the Internet of Things and other terminal devices. PUF chips are physically unclonable functions. The function mapping relationship between input (challenge) / output (response) is implemented by physical or simulation methods. Unlike the function mapping relationship in computers and mathematics, the function mapping relationship of PUF chips will be affected by external parameters such as temperature and bias voltage. The same input (challenge) and output (response) will be slightly different, which causes trouble for PUF chips in identification, authentication and encryption applications. In particular, when the response stability of the PUF chip exceeds a certain level, the PUF chip will fail and become completely unusable.

[0003] The key component inside the PUF chip is the matrix composed of PUF units. This PUF unit outputs a 1-bit response for a 1-bit challenge. The existing PUF matrix is ​​composed of 16×16, 8×16, or 32×16, etc. This is the key component of the PUF chip. It utilizes the performance fluctuations of each component in the microelectronics manufacturing process, resulting in a random functional relationship between the challenge / response of each unit. However, we hope that it is stable, and this functional mapping relationship remains stable at different times and in different working environments.

[0004] However, in addition to the PUF unit matrix, the PUF chip needs to be equipped with other peripheral circuits such as readout circuits and power bias circuits around the PUF unit matrix. These peripheral circuits will inevitably introduce noise during operation, and will also introduce bias voltage unevenness through substrate crosstalk, which will cause the electrical characteristics of the PUF unit matrix to be uneven, and this unevenness is unstable, which will cause the function mapping characteristics of the PUF unit matrix to fail. Especially for the peripheral units of the PUF unit matrix, the impact is even greater. These peripheral PUF units account for more than 10% of the entire PUF unit matrix. Taking 32×16 as an example, 48 / 512≈10%. This can easily lead to the failure of more than 10% of the PUF unit matrix. Summary of the invention

[0005] The embodiment of the present invention provides a chip layout structure to overcome the PUF chip failure caused by the instability of PUF unit matrix function mapping due to the influence of peripheral circuits. This layout design structure is suitable for all types of PUF chips.

[0006] To achieve the above object, an embodiment of the present invention provides a chip layout structure, which includes a non-copyable functional unit matrix, namely a PUF unit matrix, a peripheral circuit unit and a ground protection groove;

[0007] Arrange the peripheral circuit unit around the PUF unit matrix;

[0008] The ground protection groove is arranged between the PUF unit matrix and the peripheral circuit unit.

[0009] The above technical solution has the following beneficial effects: by adopting the biased layout method of the peripheral units of the PUF unit matrix, that is, by setting a grounding protection groove between the PUF unit matrix and the peripheral circuit unit, the instability of the PUF unit matrix function mapping caused by the influence of the peripheral circuit is overcome, and the failure of the PUF chip caused by the instability is avoided; this layout design method is suitable for all types of PUF chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0011] Figure 1 is a schematic diagram of a chip layout structure according to an embodiment of the present invention;

[0012] Figure 2 is a cross-sectional view of a ground protection trench according to an embodiment of the present invention. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0014] like Figure 1 , which is a schematic diagram of a chip layout structure according to an embodiment of the present invention, wherein the structure includes a non-copyable functional unit matrix 10, namely, a PUF unit matrix 10, a peripheral circuit unit and a ground protection groove 20;

[0015] The peripheral circuit unit is arranged around the PUF unit matrix 10;

[0016] The ground protection groove 20 is disposed between the PUF unit matrix 10 and the peripheral circuit unit.

[0017] Figure 1 The PUF unit matrix 10 located in the center will be affected by the peripheral readout circuit 34, the site selection circuit 31, the control circuit 32 and the bias circuit 33. The function mapping characteristics of the PUF unit matrix 10 are not only affected by the microelectronics manufacturing process, but also by these peripheral circuits. The influence of the peripheral circuits is unstable and undesirable. The method of shielding the influence of these peripheral circuits is to protect the PUF unit matrix by grounding.

[0018] The ground protection groove 20 can effectively shield the influence of these peripheral circuits on the PUF unit matrix 10 .

[0019] Furthermore, the grounding protection groove 20 is a groove structure, and the PUF unit matrix 10 is arranged in the groove of the grounding protection groove 30 .

[0020] The arrangement of the groove structure can effectively shield the influence of the peripheral circuit units on the PUF unit matrix 10 .

[0021] Further, the distance between the edge of the PUF unit matrix 10 and the ground protection groove 20 is set in the range of 0.5 micrometers to 2 micrometers.

[0022] The distance between the edge of the PUF unit matrix 10 and the grounding protection groove 20 is set in the range of 0.5 micrometers to 2 micrometers, so that the grounding protection effect can be achieved well while ensuring the integrity and feasibility of the structural design.

[0023] Furthermore, the ground protection trench 20 is composed of a highly doped P-type layer 21 , a ground metal 22 and a silicon substrate 23 .

[0024] Furthermore, an ohmic contact is provided between the grounding metal 22 and the highly doped P-type layer 21 .

[0025] The entire PMOS and NMOS unit 11 is surrounded by a P+ type doped region, i.e., a highly doped P-type layer 21, and a peripheral metal wiring, i.e., a grounding metal 22, in contact with the highly doped P-type layer 21. The metal wiring in contact with the highly doped P-type layer 21 is grounded. The PMOS and NMOS in the middle constitute a PUF unit.

[0026] Furthermore, the outer ring PUF cells of the PUF cell matrix 10 are PUF cells in a virtual state.

[0027] Furthermore, the outer two circles of PUF units in the PUF unit matrix 10 are PUF units in a virtual state.

[0028] Set all peripheral PUF units in the PUF unit matrix 10 to a Dummy virtual state;

[0029] Taking a 32×16 PUF unit matrix as an example, if 32×16=512 PUF unit matrices are required, they should be set to 33×17=561 PUF unit matrices or 34×18=612 during design. Set one or two circles of PUF units in the periphery to the Dummy state to protect the stability of the function mapping characteristics of the 32×16=512 PUF unit matrix in the inner circle.

[0030] Furthermore, an oxidation isolation layer 12 is provided between the PUF units 11 of the PUF unit matrix 10 .

[0031] Adding ground protection slots and dummy PUF units will not increase the cost of the PUF chip, and the silicon chip area occupied by the added ground protection slots and dummy PUF units is negligible, but it improves the stability and reliability of the PUF chip, greatly reduces the error correction requirements in the PUF, and improves the yield rate of the PUF chip.

[0032] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of protection of the present disclosure. The attached method claims present the elements of the various steps in an exemplary order and are not intended to be limited to the specific order or hierarchy described.

[0033] In the above detailed description, various features are grouped together in a single embodiment to simplify the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the embodiments of the claimed subject matter require more features than are clearly stated in each claim. On the contrary, as reflected in the appended claims, the invention is in a state of having less than all the features of the disclosed individual embodiments. Therefore, the appended claims are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment of the invention.

[0034] The disclosed embodiments are described above to enable any person skilled in the art to implement or use the present invention. Various modifications of these embodiments are obvious to those skilled in the art, and the general principles defined herein may also be applied to other embodiments without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is not limited to the embodiments given herein, but is consistent with the broadest scope of the principles and novel features disclosed in this application.

[0035] The above description includes examples of one or more embodiments. Of course, it is impossible to describe all possible combinations of components or methods for the purpose of describing the above embodiments, but it should be recognized by those skilled in the art that the various embodiments may be further combined and arranged. Therefore, the embodiments described herein are intended to cover all such changes, modifications and variations that fall within the scope of protection of the appended claims. In addition, with respect to the term "comprising" used in the specification or claims, the word is covered in a manner similar to the term "including", just as "including," is explained as a transitional word in the claims. In addition, any term "or" used in the specification of the claims is intended to mean "non-exclusive or".

[0036] Those skilled in the art may also understand that the various illustrative logical blocks, units, and steps listed in the embodiments of the present invention may be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly demonstrate the interchangeability of hardware and software, the various illustrative components, units, and steps described above have generally described their functions. Whether such functions are implemented by hardware or software depends on the specific application and the design requirements of the entire system. Those skilled in the art may use various methods to implement the described functions for each specific application, but such implementation should not be understood as exceeding the scope of protection of the embodiments of the present invention.

[0037] The various illustrative logic blocks or units described in the embodiments of the present invention can be implemented or operated by a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field programmable gate array or other programmable logic device, a discrete gate or transistor logic, a discrete hardware component, or any combination of the above. The general-purpose processor can be a microprocessor, and optionally, the general-purpose processor can also be any conventional processor, controller, microcontroller or state machine. The processor can also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a digital signal processor core, or any other similar configuration.

[0038] The steps of the method or algorithm described in the embodiments of the present invention can be directly embedded in hardware, a software module executed by a processor, or a combination of the two. The software module can be stored in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or other storage media of any form in the art. Exemplarily, the storage medium can be connected to the processor so that the processor can read information from the storage medium and can write information to the storage medium. Optionally, the storage medium can also be integrated into the processor. The processor and the storage medium can be arranged in an ASIC, and the ASIC can be arranged in a user terminal. Optionally, the processor and the storage medium can also be arranged in different components in the user terminal.

[0039] In one or more exemplary designs, the above functions described in the embodiments of the present invention can be implemented in hardware, software, firmware or any combination of the three. If implemented in software, these functions can be stored on a computer-readable medium, or transmitted in the form of one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media that facilitate the transfer of computer programs from one place to another. The storage medium can be any available medium that can be accessed by any general or special computer. For example, such computer-readable media can include but are not limited to RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage or other magnetic storage devices, or any other medium that can be used to carry or store program codes in the form of instructions or data structures and other forms that can be read by general or special computers, or general or special processors. In addition, any connection can be appropriately defined as a computer-readable medium, for example, if the software is transmitted from a website site, server or other remote resource through a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wirelessly, such as infrared, wireless and microwave, it is also included in the defined computer-readable medium. The disk and disc include compact disk, laser disk, optical disk, DVD, floppy disk and blue-ray disk. Disks usually copy data magnetically, while discs usually copy data optically with lasers. The above combination can also be included in computer readable media.

[0040] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A chip layout structure, characterized in that: The structure includes a non-copyable functional unit matrix, namely a PUF unit matrix, a peripheral circuit unit and a ground protection groove; Arrange the peripheral circuit unit around the PUF unit matrix; The ground protection groove is arranged between the PUF unit matrix and the peripheral circuit unit; The ground protection groove is a groove structure, and the PUF unit matrix is ​​arranged in the groove of the ground protection groove; The distance between the edge of the PUF unit matrix and the ground protection groove is set in the range of 0.5 microns to 2 microns; The ground protection groove is composed of a highly doped P-type layer, a grounding metal and a silicon substrate; The grounding metal and the highly doped P-type layer are arranged in ohmic contact; The outer circle PUF units of the PUF unit matrix are PUF units in a virtual state; The peripheral circuit unit includes: a readout circuit, an address selection circuit, a control circuit and a bias circuit.

2. The chip layout structure according to claim 1, characterized in that: The outer two circles of PUF units in the PUF unit matrix are PUF units in a virtual state.

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