Phase-locked loop for analog-to-digital converter based on continuous-time delta-sigma modulator

Abstract

The present invention discloses a phase-locked loop, which includes a first oscillator, which provides a first oscillator signal having a first jitter component; and a second oscillator, which provides a second oscillator signal having a second jitter component. The second jitter component is higher than the first jitter component. A selector circuit selects the first oscillator signal or the second oscillator signal as a phase-locked loop output signal. The first oscillator signal and the second oscillator signal can have different frequencies, and the signal with a lower frequency has a larger jitter. The oscillator that produces a signal with less jitter consumes more power. A continuous time delta-sigma modulator analog-to-digital converter (ADC) receives the phase-locked loop output signal as an input clock signal. A high gain setting of an amplifier that provides an input signal to the ADC selects a lower jitter signal input clock signal, and a lower gain setting selects a higher jitter input clock signal.

Description

Technical Field

[0001] The present disclosure relates to generating clock signals, and more particularly, to generating clock signals in a phased-locked loop (PLL) with different power and jitter settings. Background Art

[0002] Analog to digital converters (ADCs) based on continuous-time delta-sigma modulators are widely used in radio frequency (RF) receiver (RX) applications. Typically, a high-order delta-sigma modulator-based ADC using a reference clock (e.g., a crystal oscillator) or a less complex low-order delta-sigma ADC with a higher clock rate is used. For the second case, in one solution, the clock of the ADC is generated by a divided local oscillator (LO) clock. However, the LO clock signal may change based on the tuning channel, resulting in changes in the ADC sampling frequency, complicating the design of the modem. Another approach is to use a phased-locked loop (PLL) circuit as a clock multiplier unit for the ADC. Typically, these PLLs are not optimized for delta-sigma ADCs, and therefore, these PLLs consume high power and occupy a large die area, increasing the cost. Summary of the invention

[0003] A phase-locked loop (PLL) can be used to independently provide a fixed-rate clock to the ADC in the RX signal chain, thus simplifying the modem design.

[0004] In one embodiment, a device includes a phase-locked loop (PLL) that provides a PLL output signal. The PLL includes: a first oscillator that provides a first oscillator signal having a first jitter component; and a second oscillator that provides a second oscillator signal having a second jitter component. The second jitter component is greater than the first jitter component. A selector circuit selects the first oscillator signal or the second oscillator signal as the PLL output signal.

[0005] In one embodiment, the first oscillator is selected to provide a PLL output signal having a first frequency, and the second oscillator is selected to provide a PLL output signal having a second frequency, the first frequency being higher than the second frequency.

[0006] In one embodiment, the first oscillator provides a first oscillator signal as a PLL output signal using a first power amount; and the second oscillator provides a second oscillator signal as a PLL output signal using a second power amount, the first power amount being greater than the second power amount.

[0007] In one embodiment, a delta-sigma modulator analog-to-digital converter (ADC) receives the PLL output signal as an input clock signal.

[0008] In another embodiment, a method includes selecting in a selector circuit a first oscillator output signal from a first oscillator or a second oscillator output signal from a second oscillator to provide as a phase-locked loop (PLL) output signal, the first oscillator output signal having a lower jitter component than the second oscillator output signal.

[0009] In one embodiment, when the first oscillator output signal is provided as the PLL output signal, the first oscillator output signal has a first frequency, and when the second oscillator output signal is provided as the PLL output signal, the second oscillator output signal has a second frequency, and the first frequency is higher than the second frequency. In one embodiment, the first oscillator uses a first amount of power to provide the PLL output signal at the first frequency, and the second oscillator uses a second amount of power to provide the PLL output signal at the second frequency, and the first amount of power is greater than the second amount of power.

[0010] In one embodiment, the PLL output signal is provided as an input clock signal to a continuous time delta-sigma modulator analog-to-digital converter (ADC). In one embodiment, the first oscillator or the second oscillator is selected based on the frequency requirement of the input clock signal.

[0011] In one embodiment, a first oscillator is selected in response to a first gain setting of an amplifier used in a radio frequency (RF) receive signal chain including a delta-sigma modulator ADC. A second oscillator is selected in response to a second gain setting of the amplifier, the first gain setting being higher than the second gain setting.

[0012] In another embodiment, a device includes an amplifier coupled to receive an input signal and to provide an amplifier output signal amplified according to a gain setting. A delta-sigma modulator analog-to-digital converter (ADC) is coupled to the amplifier output signal. A phase-locked loop (PLL) provides a PLL output signal. The PLL includes a charge pump and a loop filter that provides an oscillator control signal. A first oscillator is coupled to the oscillator control signal and is configured to provide a first oscillator signal having a first jitter component. A second oscillator is coupled to the oscillator control signal and is configured to provide a second oscillator signal having a second jitter component. A selector circuit selects the first oscillator signal or the second oscillator signal as the PLL output signal based on a selection signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0014] Figure 1a A PLL is shown providing a clock signal to the ADC operating in full rate mode.

[0015] Figure 1b A PLL is shown providing a clock signal to an ADC operating in less than full rate mode.

[0016] Figure 2a A PLL with a full-rate voltage control oscillator (VCO) is shown providing a full-rate clock signal to the ADC.

[0017] Figure 2b A PLL with a full rate VCO and a divider on the PLL output to provide a lower rate clock signal to the ADC is shown.

[0018] Figure 2c A PLL with a lower rate VCO is shown, which provides a lower rate clock signal to the ADC without using a divider.

[0019] Figure 3a An RX signal chain including an amplifier and an ADC is shown, wherein the PLL providing the clock signal to the ADC is configured to set the amplifier gain to a maximum value.

[0020] Figure 3b An RX signal chain including an amplifier and an ADC is shown, wherein a PLL providing a clock signal to the ADC is configured to set the amplifier gain to less than a maximum value.

[0021] Figure 4A block diagram of a PLL with multiple VCOs according to one embodiment is shown.

[0022] Figure 5 A portion of a PLL is shown showing control signals for a plurality of VCOs.

[0023] Figure 6a Shown is a block diagram of one of the PLL VCOs implemented as a ring oscillator in accordance with an embodiment.

[0024] Figure 6b A block diagram of another one of the PLL VCOs implemented as a ring oscillator according to an embodiment is shown.

[0025] Figure 7 Shows Figure 6a and 6b Various possible settings of the VCO are shown.

[0026] Figure 8 A conventional loop filter topology is shown.

[0027] Figure 9a A passive loop filter is shown.

[0028] Figure 9b An active loop filter is shown.

[0029] Fig.10a A conventional charge pump is shown.

[0030] Fig.10b The charge pump and active loop filter are shown.

[0031] Fig.11 A charge pump and loop filter topology with a shared unity gain buffer is shown in accordance with an embodiment.

[0032] Fig.12 The use of a charge pump and loop filter topology in an embodiment of a PLL with multiple VCOs is shown.

[0033] Fig.13 The use of a charge pump and loop filter topology in an embodiment of a PLL with a single VCO is shown.

[0034] The use of the same reference numbers in different drawings indicates similar or identical items. Specific embodiments

[0035] Embodiments described herein provide a phase-locked loop (PLL) specifically for clock generation of a continuous time delta-sigma modulator ADC in a radio frequency receiver (RF RX) signal chain. For a given power budget, the PLL minimizes far-end phase noise at the expense of a looser closure in phase noise. The PLL may also be used for other applications. Embodiments provide a variable power consumption PLL, wherein the PLL power consumption is selected based on the requirements of the ADC. For example, the PLL power may be scaled based on the input signal strength to the RX signal chain and / or based on the clock rate required by the ADC. Embodiments provide a fixed rate clock to the ADC, thereby avoiding the complexity of using a divided LO clock, thereby simplifying the design of the modem.

[0036] In one embodiment, for the case of 2 MHz bandwidth, the ADC clock rate is about 307.2 MHz. The integrated 2 MHz ADC noise bandwidth is primarily used for Zigbee applications. The ADC clock rate of about 153.6 MHz for a bandwidth of about 1 MHz is primarily used for Bluetooth applications, but both bandwidth settings can generally be used over a wide range of data rates, for example, 100 kbps to 2 Mbps FSK modulated signals or lower. Some embodiments assume a crystal frequency of 38.4 MHz. Due to high frequency jitter, the jitter limited signal to noise ratio (SNR) depends primarily on the in-band quantization noise folding. As is known in the art, jitter is the deviation of the clock signal edge from its ideal position. Higher clock rates require lower jitter in the PLL (e.g., twice the frequency requires less than a factor of two reduction in jitter, assuming that the shape of the noise transfer function (NTF) is simply scaled with frequency, for example, by doubling the size of the loop filter capacitor, the NTF is reduced by a factor of 2). Note that for a PLL used for clock generation of a continuous time delta-sigma modulator, minimizing the PLL high frequency jitter is more important than optimizing the overall jitter, and therefore, embodiments may focus on an efficient voltage controlled oscillator (VCO) design, keeping the charging pump (CP), loop filter, phase frequency detector (PFD), and feedback divider area and / or power consumption low. Therefore, embodiments are urged to reduce high frequency jitter because low frequency jitter is not as important for certain applications. Embodiments use a clock frequency scaling scheme for full rate and half rate ADC operations. In half rate mode, the ADC clock frequency is scaled by a factor of two compared to full rate mode. However, the frequency adjustment is not done by the VCO output divider. Instead, the feedback division ratio is reduced by a factor of two, and a lower power VCO is used instead of the VCO for full rate operation. Since the jitter requirements of the ADC are relaxed in half rate mode, this method results in lower overall total power consumption.

[0037] In addition, in principle, the jitter number can be relaxed when the input signal power is higher, for example, detected by RX gain compensation. Low jitter is required especially when the input signal level is close to the sensitivity level. The sensitivity level is the level at which acceptable signal detection occurs. For larger input signals (higher SNR), the allowed jitter may be higher. Therefore, an embodiment uses a PLL power scaling technique based on the received signal power. When the signal chain gain retreats from its maximum value to or below the threshold gain setting, the full-rate VCO will be replaced by a low-power version (which has higher jitter). When the signal power is higher, power can be saved by using a lower-power VCO with higher jitter.

[0038] If the ADC noise transfer function scales 1-1 when the clock frequency is reduced (e.g., fclk=320MHz to fclk=160MHz), the jitter specification can be relaxed by the same or similar amount. That is, twice as much jitter can be tolerated at the lower clock frequency. This allows the use of a lower power PLL to produce an output signal with higher jitter content. See Figure 1a Assuming that ADC101 is in full rate state, PLL 103 (which is also called clock multiplier unit (CMU) because it scales up the input reference clock) has a power utilization of P1 and a jitter specification of Jitter1, and PLL 103 provides ADC clock 105 with a frequency of fclk1. PLL 103 multiplies the reference clock signal CLKin with a frequency of fref to obtain the ADC clock 105 with a frequency of fclk1. PLL multiplies the reference clock CLKin by N based on the feedback divider. Therefore, the frequency of the ADC clock (fclk) = N×fref. Reference Figure 1b , if the clock frequency requirement of ADC 107 is reduced (for example, from 320 MHz to 160 MHz), the lower power PLL 109 provides an ADC clock 111 (ADCclk2) having a frequency of fclk2. PLL 109 multiplies the reference clock signal CLKin having a frequency of fref to obtain an ADC clock 111 having a frequency of fclk2. PLL 109 has a power utilization of P2 and a jitter specification of Jitter2 (jitter 2). Frequency fclk2 < fclk1, power utilization P2 < P1. Therefore, a lower power PLL can be used, which provides a lower frequency ADC clock with a higher jitter component. As described above, the jitter still meets the ADC requirements.

[0039] Reference Figure 2a, the illustrated embodiment utilizes a PLL 201 with a full-rate VCO to provide a full-rate ADC clock (ADCclk1) 203 to an ADC 205 . Figure 2b It is shown that the output divider 207 can be used in conjunction with the PLL 201 having a full-rate VCO to provide an ADC clock (ADclk2) 209 having a lower frequency than the ADC clock (ADCclk1) 203. However, Figure 2b The method requires the use of PLL 201 and divider 207 with a full-rate VCO, which consumes unnecessary power. Figure 2c An embodiment is shown in which a lower rate clock 215 is provided to ADC 217 directly from PLL 219 using a lower rate VCO. PLL 219 uses a lower power VCO specifically designed to provide a lower rate ADC clock. PLL 219 uses less power than PLL 201 and is Figure 2c In the illustrated embodiment, the divider 207 is omitted entirely, thereby saving additional power.

[0040] In an embodiment, PLL power scaling is performed based on the power of the input signal. Figure 3a , PLL 301 and ADC 303 are used as part of the RX signal chain. The signal chain includes a receive amplifier 305, whose gain setting is set by a gain control signal 307. Note that the gain block 305 represents various gain blocks (e.g., the gains of the front-end passive network, low noise amplifier (LNA), and programmable gain amplifier (PGA)) in a typical receiver as a single block for illustration. The gain setting provides information indicating whether the power level of the input signal 309 is close to the sensitivity level Psens. That is, if the input signal power Pin causes the input signal to be close to the minimum signal power sensitivity level Psens required to accurately sense the input signal, the gain setting of the amplifier 301 is set to the maximum gain factor G1 (G1=Gmax). When the gain factor is set to G1 (which corresponds to the maximum gain), the system consumes power P1 using PLL 301 and generates a clock signal with jitter Jitter1.

[0041] However, if Pin>Psens (e.g., at least a few dB greater), the amplifier gain signal 307 is decreased to reduce the gain of the amplifier 305. The decreased gain setting indicates that the jitter specification can be relaxed as the overall quantization + thermal noise limited SNR increases. This means that the ADC can tolerate a clock signal with a larger jitter component. In this case, the system will switch to a lower power VCO. Reference Figure 3b, if the gain of amplifier 305 is set to G2<Gmax, the system uses PLL 315, whose power utilization is P2, and the jitter is equal to Jitter2, Jitter2>Jitter1. In addition, the power of the input signal Pin2>Pin1, which allows a smaller gain factor G2<Gmax. The smaller gain factor means that PLL 315 can use a VCO that generates a clock signal with a higher jitter component. Therefore, PLL 315 provides a clock signal with a higher jitter component than clock signal 311 ( Figure 3a ) but with greater jitter. Using a higher jitter clock signal allows a lower power PLL to be used.

[0042] Figure 4 A block diagram of a PLL (or CMU) 400 according to an embodiment is shown. The PLL 400 includes a phase and frequency detector (PFD) 401, which compares a reference clock 403 with a feedback clock 405 and provides an UP or DN signal to a charge pump 407 based on the comparison. The charge pump provides a loop filter 409, which provides an oscillator control signal 411 to a low jitter oscillator (VCO1) 415 and a low power oscillator (VCO2) 417. A selector circuit 419 selects the output of VCO1 415 or VCO2 417 as the output clock signal 421 of the PLL 400. Thus, a single PLL is selected between the VCOs to achieve the desired power and jitter, rather than using separate PLLs. The output clock signal 421 is fed back to the PFD 401 through a feedback divider 423. The feedback divider 423 divides the PLL output signal by N and provides the divided signal 405 to the PFD 401. The choice of VCO1 415 or VCO2 417 as the output clock signal depends on the proximity of the input signal power to the sensitivity level and / or whether the ADC is running at half rate or full rate.

[0043] Despite Figure 4 In the embodiment shown in FIG. 1 , two VCOs are shown, but other embodiments may use additional VCOs. For example, in one embodiment, a third VCO has power consumption and jitter specifications between VCO1 and VCO2. For example, when the input signal power is above a predetermined level, but the dB above the sensitivity level (sufficiently high SNR) is not enough to warrant higher jitter in the low power VCO2, but can still withstand higher jitter than the low jitter VCO1, the third VCO is selected, thereby achieving some power savings. For example, in an embodiment where the ADC runs at a rate between full rate and half rate, the third VCO is also selected. In an embodiment, one or more VCOs that are not in use are powered off. For example, when VCO2 is used, VCO1 is powered off, and when VCO1 is used, VCO2 is powered off.

[0044] Figure 5 A high level block diagram of a portion of a PLL 500 is shown in accordance with one embodiment. The loop filter provides an oscillator control signal 501 to VCO1 515 and VCO2 517. A selector circuit 519 selects an output signal from one of the plurality of VCOs as the PLL output signal based on a select signal Sel 520. The oscillators receive a mode signal 531, VCO1 receives a select signal Sel 532, and VCO2 receives the inverse of Sel 533. The select signals 532 and 533 may be independent of or related to the select signal 520. Although in Figure 5 Two VCOs are shown in FIG, but other embodiments may use other numbers of VCOs to suit a particular application. Thus, an embodiment may select between three VCOs with different power and jitter specifications.

[0045] Figure 6a An exemplary block diagram of VCO1 515 is shown. Oscillator 515 is a ring oscillator based VCO having a programmable number of inverting stages. Mode signal 531 selects the delay through the ring oscillator by selecting the number of inverting stages. In the case where the mode signal is 1, the N1 stage is selected by multiplexer 601. In the case where the mode signal is 0, the N2 stage is selected, where N1 and N2 are integers. For a given control voltage Vctl, the number of stages selected by the mode signal determines the frequency of the output signal provided by VCO1. Select signal 532 determines whether the ring oscillator is activated. If the select signal is zero, the NAND gate 602 prevents the oscillator from oscillating. If the select signal is 1, the feedback signal controls the output of the NAND gate 602 and the ring oscillator oscillates.

[0046] VCO1 utilizes an inverter chain with a larger device aspect ratio (width / length (W / L)) to provide lower jitter / phase noise. Using an inverter with a larger W / L aspect ratio causes VCO1 to consume more power compared to VCO2. VCO1 is used for higher ADC clock rate modes and lower jitter. For a given ADC SNR requirement, lower jitter is required for high rate (full rate) ADC mode. VCO1 515 is also selected when the RX chain input power approaches the sensitivity level.

[0047] Figure 6bAn exemplary block diagram of an oscillator VCO2 517 is shown. Oscillator 517 is a ring oscillator based VCO with a programmable number of inverting stages. A mode signal 531 selects a certain number of inverting stages. In the case where the mode signal is 1, the M1 stage is selected by multiplexer 603. In the case where the mode signal is 0, the M2 stage is selected, where M1 and M2 are different integers. Note that depending on the specific embodiment, M1 and N1 can be the same or different, and M2 and N2 can be the same or different. For a given control voltage Vctl, the number of stages selected by the mode signal determines the frequency of the output signal provided by VCO2. Signal 533 (selb) determines whether the ring oscillator is activated. signal is zero, then NAND gate 604 prevents the oscillator from oscillating. Note that if signal is zero, select 532 is 1, thus enabling VCO1. The feedback signal controls the output of NAND gate 604 and the ring oscillator oscillates if the signal is 1. In one embodiment, the unused oscillator is powered down to save power, rather than just preventing the oscillator from oscillating.

[0048] Compared to VCO1, VCO2 utilizes an inverter chain with a smaller device aspect ratio W / L, consuming less power than VCO1, but at the expense of higher jitter. VCO2 is used in lower clock rate ADC modes. For a given ADC SNR requirement, higher jitter can be tolerated at lower clock rates. Therefore, VCO2 517 is used in half-rate ADC mode when higher jitter can be tolerated and a lower power VCO can be utilized. VCO2 517 is also used when the RX chain input power is higher (dB threshold number above the sensitivity level).

[0049] although Figure 6a and 6b A ring oscillator is shown, but other embodiments may use different types of oscillators for VCO1 and VCO 2. For example, in another embodiment, the oscillators are LC oscillators, which provide different power consumption and jitter levels.

[0050] Figure 7 Shows Figure 6a and 6bVarious possible settings of the VCO are shown. The selection signal (Sel) 532 is determined to select VCO1. In the case of mode = 0, VCO1 is configured to have more phase inversion stages, resulting in a lower oscillation frequency for a given control voltage Vctl. When a low rate is selected, the control voltage variation between two different frequency settings can be reduced by increasing the number of phase inversion stages. The mode and selection setting (1, 0) are suitable for low-rate, low-jitter applications. The mode and selection setting (1, 1) selects fewer phase inversion stages for VCO1 and is suitable for high-rate, low-jitter applications. The selection signal (Sel) 532 is not determined to select VCO2. In the case of mode = 0, VCO2 selects more phase inversion stages, resulting in a lower oscillation frequency at a given control voltage Vctl. The increase in the number of stages keeps the control voltage offset between the two oscillation frequencies very small. The mode and selection setting (0, 0) are suitable for low-rate, low-power, and higher-jitter applications. The mode and select settings (0, 1) configure VCO2 to have a smaller inversion stage (higher frequency) and is suitable for high-rate, higher-jitter, low-power applications. For example, if the input power is sufficiently above the sensitivity level, a higher jitter level can be tolerated and a low-power VCO can be used.

[0051] Reference back Figure 4 , components of PLL 400 include a charge pump 407 and a loop filter 409 . Figure 8 A conventional loop filter topology for a Type II PLL is shown, which also includes higher order electrodes. The area of ​​capacitor Cz 801 is typically larger, and therefore occupies a larger area. Additional circuitry 803 is included to provide higher order filtering.

[0052] Figure 9a shows an input impedance Passive loop filter 900. Figure 9b An active loop filter 902 with capacitor multiplication is shown, which reduces the size of capacitor Cz by a factor of N. The size of resistor 903 is set to R1=NRz, where Rz is Figure 9a The active loop filter 902 further includes a unit gain buffer 905. The unit gain buffer is an amplifier for making the output voltage equal to the input voltage, that is, the unit gain buffer is an amplifier with a gain of 1. In the active filter 902, the size of the resistor 907 is set to The active loop filter and the passive loop filter have the same input impedance. That is, the active loop filter also has an input impedance Using an active loop filter reduces the size of capacitor Cz to Cz / N. Therefore, the effective capacitance of the active loop filter with capacitor C increases by For active filter implementations, larger N (e.g., N=10) requires smaller capacitors, resulting in significant savings in capacitor area at the expense of additional area and power consumption caused by the unity gain buffer, additional resistor 907, and larger resistor 903. However, since the area of ​​the resistors in the loop filter implementation is much smaller than the area of ​​capacitor Cz, the additional area penalty for the resistors is small. In various embodiments, PLL 400 includes loop filter 800 ( Figure 8 ), loop filter 900, or loop filter 902, or any suitable loop filter, to generate a control signal to control the VCO according to the requirements of a specific application.

[0053] In addition to the loop filter, Figure 4 The illustrated PLL 400 also includes a charge pump 407 . Fig.10a FIG. 1 shows a conventional implementation of a push-pull charge pump 1000 used in an embodiment of PLL 400. Current sources 1001 and 1003 increase or decrease the charge provided according to the UP and DN signals provided from PFD 401 (see FIG. 1 ). Figure 4 ). The UP signal and the DN signal and their complements are provided as dnb, dn, up, and upb, respectively, to control transistors M1, M2, M3, and M4, respectively. Transistors M4 and M2 control the charging or discharging of the charge stored in the loop filter capacitor of the loop filter 900, respectively. It should be noted that the transistor pair M4 and M3 are PMOS transistors controlled by an active low gate control signal. The transistor pair M1 and M2 are NMOS transistors controlled by a higher active gate control signal. When one transistor in the pair is turned off, the other in the pair is turned on. Thus, for example, when both upb are high and dn are low, and upb is low and dnb is high, transistors M3 and M1 are turned on, thereby providing a path between nodes 1002 and 1004. When only upb (active low) is asserted, the loop filter capacitor Cz is charged through M4, and transistor M1 is turned on, thereby providing a path between nodes 1006 and 1004. When only dn is asserted, the loop filter capacitor Cz discharges through M2 and transistor M3 turns on to provide a path between nodes 1002 and 1006. Unity gain buffer 1005 forces the voltage Vx at node 1006 to follow the voltage on CPout node 1007, thereby helping to minimize the offset current. Fig.10a A simple passive loop filter 900 is shown, but other embodiments use higher order loop filters (e.g., Figure 8 Although a passive loop filter is used in various embodiments, Fig.10bAn embodiment is shown where an active loop filter 1011 is used in conjunction with a unity gain buffer 1015. This allows for the use of smaller capacitors (Cz / N).

[0054] Fig.11 An embodiment with a new charge pump and active loop filter topology 1100 is shown that has a lower overhead in power and area. The topology can be used in various embodiments described herein, but can also be used in PLLs intended for other applications to save area and power. The new charge pump and loop filter implementation can reduce the area of ​​the loop filter while keeping the overall charge pump and active loop filter current low due to the shared use of unity gain buffers, as described below. Fig.11 The embodiment in the embodiment includes a charge pump and an active loop filter 1100, wherein a unity gain buffer 1105 is shared by the charge pump and the loop filter, thereby reducing the area required for the charge pump and the loop filter and the power consumed. In the charge pump and loop filter 1100 (also refer to Figure 9b and 10b ), resistor 1133 is used as loop filter resistor R1 = NRz. Resistor 1135 is used as resistor and capacitor 1131 is Cz / N. Thus, the unity gain amplifier 1105 acts as part of an active loop filter, thereby allowing a reduction in the capacitance area of ​​capacitor 1131 compared to a passive loop filter implementation. The unity gain buffer 1105 also forces the voltage at node 1137 to follow the output voltage CPout on node 1134, thereby minimizing the offset current in the charge pump. Note that Fig.11 and Fig.10b For example, in Fig.10b In FIG. 1 , there is no series resistor (e.g., resistor 1133) between the passive input of the unity gain buffer and CPout. However, for the intended purpose (node ​​1137 follows node 1134), Fig.11 The circuit is valid. At DC, the capacitor is an open circuit, so at low frequencies the two methods are the same. The average Vx (node ​​1137) needs to follow the output (CPout, node 1134), which is Fig.11 can be realized in.

[0055] Fig.12 An embodiment of a PLL 1250 is shown, wherein: Figure 4The charge pump 407 and loop filter 409 of FIG. 1 are replaced by a charge pump / loop filter topology 1200 with a shared unity gain buffer 1201. Filter 1200 is identical to charge pump / loop filter 1100 except that current sources 1203 and 1205 are more symbolically shown in charge pump / loop filter 1200. Fig.12 In an embodiment of the present invention, the loop filter includes a higher order filtering component 1260. The charge pump / loop filter 1200 provides a VCO control signal 1209 to VCOs 1215 and 1217, and a multiplier 1221 selects one of the VCOs 1215 and 1217 to provide a PLL output signal.

[0056] Fig.13 An embodiment is shown in which a charge pump / loop filter 1300 with a shared unity gain buffer 1301 controls a single VCO 1315 in a PLL 1350 .

[0057] Thus, various aspects have been described in connection with a PLL that utilizes a VCO with different jitter and power specifications. The description of the invention herein is illustrative and is not intended to limit the scope of the invention as set forth in the appended claims. Other changes and modifications may be made to the embodiments disclosed herein based on the description set forth herein without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A device comprising: A phase-locked loop, which provides a phase-locked loop output signal, the phase-locked loop comprising: a first oscillator providing a first oscillator signal; a second oscillator providing a second oscillator signal; A selector circuit for selecting the first oscillator signal or the second oscillator signal as a phase-locked loop output signal; a continuous-time delta-sigma modulator analog-to-digital converter coupled to receive the phase-locked loop output signal as an input clock signal; an amplifier circuit coupled to receive an input signal and to provide an amplifier output signal to the delta-sigma modulator analog-to-digital converter; a gain control signal connected to the amplifier circuit to control the gain of the amplifier circuit; and Therein, the first oscillator is selected in response to a first value of the gain control signal, and the second oscillator is selected according to a second value of the gain control signal.

2. The device according to claim 1, wherein: The first oscillator signal has a first jitter component, the second oscillator signal has a second jitter component, and the second jitter component is greater than the first jitter component.

3. The device according to claim 1 or 2, in, The first value of the gain control signal is higher than the second value of the gain control signal; wherein the first oscillator uses a first amount of power to provide a first oscillator signal as a phase-locked loop output signal; and The second oscillator uses a second power amount to provide a second oscillator signal as a phase-locked loop output signal, and the first power amount is greater than the second power amount.

4. The device according to claim 1 or 2, in, The first oscillator is a ring oscillator and the first oscillator includes an inverter having a transistor having a first width to length aspect ratio; as well as wherein the second oscillator is a ring oscillator, and the second oscillator includes an inverter having a transistor having a second width to length aspect ratio, the second width to length aspect ratio being less than the first width to length aspect ratio; And wherein the first oscillator consumes more power than the second oscillator.

5. The device according to claim 4, wherein: The respective number of inverter stages in the first oscillator and the second oscillator is selectable.

6. The apparatus of claim 1 or 2, further comprising a loop filter coupled to the first oscillator and the second oscillator.

7. A method comprising: selecting in a selector circuit either a first oscillator output signal from the first oscillator or a second oscillator output signal from the second oscillator to provide as a phase locked loop output signal; providing the phase-locked loop output signal as an input clock signal to a continuous-time delta-sigma modulator analog-to-digital converter; selecting a first oscillator responsive to a first gain setting of an amplifier for use in a radio frequency receive signal chain including a delta-sigma modulator analog-to-digital converter; as well as A second oscillator is selected in response to a second gain setting for the amplifier, the first gain setting being higher than the second gain setting.

8. The method according to claim 7, further comprising: in, The first oscillator output signal has a lower jitter component than the second oscillator output signal.

9. The method according to any one of claims 7 or 8, further comprising: The first oscillator provides a phase-locked loop output signal using a first amount of power; as well as The second oscillator provides a phase locked loop output signal using a second amount of power, the first amount of power being greater than the second amount of power.

10. The method according to any one of claims 7 or 8, further comprising: providing an inverter in said first oscillator with a transistor having a first width to length aspect ratio; as well as Transistors having a second width-to-length aspect ratio are provided for inverters in the second oscillator, the second width-to-length aspect ratio being smaller than the first width-to-length aspect ratio.

11. The method according to any one of claims 7 or 8, further comprising: The output of the loop filter is provided to the first oscillator and the second oscillator.

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