Dry etching process on a metal oxide etch stop layer above a metal layer and structure formed thereby

Abstract

The present application discloses a microelectronic device (300), which includes a metal layer (304) on a first dielectric layer (302). An etch stop layer (306) is disposed above the metal layer (304) and on the first dielectric layer (302) directly adjacent to the metal layer (304). The etch stop layer (306) includes a metal oxide and has a thickness of less than 10 nanometers. A second dielectric layer (308) is disposed above the etch stop layer (306). The second dielectric layer (308) is removed from an etch region (310) extending downward to the etch stop layer (306). The etch region (310) extends at least partially above the metal layer (304). In one version of the microelectronic device (300), the etch stop layer (306) may extend above the metal layer (304) in the etch region (310). In another version, the etch stop layer (306) may be removed in the etch region (310). The microelectronic device (300) is formed by etching the second dielectric layer (308) using a plasma etching process and stopping on the etch stop layer (306).

Description

Technical Field

[0001] The present application relates generally to microelectronics and, more particularly, to metal layers in integrated circuits. Background Art

[0002] Microelectronic devices often include metal layers of platinum, gold, etc. The metal layer can be used in sensors such as thermistors, ion sensitive field effect transistors (ISFETs), etc. The manufacture of microelectronic devices often requires etching through an overlying dielectric layer comprising silicon dioxide, silicon nitride, etc. to expose the metal layer. It is challenging to etch silicon dioxide and silicon nitride and then stop on the metal layer. Wet etching processes lack lateral dimensional control due to undercutting of the etch mask. Dry etching (such as reactive ion etching (RIE)) tends to remove a portion of the metal layer and redeposit the metal on the overlying dielectric layer and the sidewalls of the etch mask, thereby complicating the removal of the etch mask and possibly contaminating the etching equipment. In addition, the adhesion of the dielectric layer to metals such as platinum and gold is generally unreliable. Summary of the invention

[0003] The microelectronic device includes a first dielectric layer and a metal layer on the first dielectric layer. An etch stop layer is disposed above the metal layer and the first dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide and has a thickness of less than 10 nanometers. A second dielectric layer is disposed above the etch stop layer. The second dielectric layer is removed from an etch region extending at least partially above the metal layer. In one aspect, the etch stop layer may extend above the metal layer in the etch region. In another aspect, the etch stop layer may be removed in the etch region. The microelectronic device is formed by etching the second dielectric layer using a plasma etching process and stopping on the etch stop layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a cross-section of an example microelectronic device including a metal layer.

[0005] FIG. 2A to FIG. 2H is a cross-section of a microelectronic device including a metal layer depicted at a stage in an example formation method.

[0006] Figure 3 is a cross-section of another example microelectronic device including a metal layer.

[0007] FIG. 4A to FIG. 4E is a cross-section of a microelectronic device including a metal layer depicted at a stage in another example formation method.

[0008] Figure 5 is a cross-section of another example microelectronic device including a metal layer.

[0009] FIG. 6A to FIG. 6Dis a cross-section of a microelectronic device including a metal layer depicted at a stage in a further example formation method.

[0010] Figure 7 is a cross-section of another example microelectronic device including a metal layer.

[0011] FIG. 8A to FIG. 8D is a cross-section of a microelectronic device including a metal layer depicted at a stage in another example formation method. DETAILED DESCRIPTION

[0012] These drawings are not drawn to scale. This specification is not limited by the illustrated order of actions or events, because some actions or events can occur in different orders and / or simultaneously with other actions or events. In addition, some illustrated actions or events are optional for implementing the method according to this specification.

[0013] A microelectronic device includes a first dielectric layer and a metal layer on the first dielectric layer. An etch stop layer is disposed above the metal layer and a dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide and has a thickness of less than 10 nanometers. A second dielectric layer is disposed above the etch stop layer. The second dielectric layer is removed from an etch region that extends from a top surface of the second dielectric layer to a top surface of the etch stop layer and extends laterally at least partially above the metal layer. In one aspect, the etch stop layer may extend above the metal layer in the etch region. In another aspect, the etch stop layer may be removed in the etch region. A microelectronic device is formed by etching the second dielectric layer using a plasma etching process and stopping on the etch stop layer.

[0014] For the purpose of this description, the term "lateral" refers to a direction parallel to a plane of the top surface of a microelectronic device. Terms such as top, above, over, upward, below, and below may be used in this specification. These terms should not be interpreted as limiting the position or orientation of structures or elements, but should be used to provide spatial relationships between structures or elements.

[0015] For the purpose of description, if an element is referred to as being adjacent to another element, the element may be directly adjacent to the other element, or intervening elements may be present. If an element is referred to as being directly adjacent to another element, there are no other intentionally disposed intervening elements.

[0016] Figure 1 1 is a cross-section of an example microelectronic device including a metal layer. Microelectronic device 100 includes a first dielectric layer 102. First dielectric layer 102 may include, for example, silicon dioxide, organic silicon glass (OSG), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), silicon oxynitride, silicon nitride, silicon oxynitride carbon, glass, or sapphire. First dielectric layer 102 may be a thermally grown silicon dioxide layer over a silicon substrate.

[0017] The metal layer 104 is disposed on the first dielectric layer 102. The metal layer 104 may include, for example, platinum, gold, iridium, silver, palladium, rhodium, ruthenium, rhenium nickel, copper, or a combination thereof. Other metals in the metal layer 104 are within the scope of this example. The metal layer 104 may have a thickness of, for example, 10 nanometers to 1 micrometer. In this example, as shown in FIG. Figure 1 As depicted, the metal layer 104 may be disposed on a planar surface of the first dielectric layer 102 .

[0018] The etch stop layer 106 is disposed over the metal layer 104 and over the first dielectric layer 102 directly adjacent to the metal layer 104. The etch stop layer 106 may optionally extend completely across the first dielectric layer 102. The thickness of the etch stop layer 106 is less than 10 nanometers. The etch stop layer 106 includes at least one metal oxide, such as aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, vanadium oxide, or tantalum oxide. The etch stop layer 106 has a composition different from that of the first dielectric layer 102.

[0019] A second dielectric layer 108 is disposed over the etch stop layer 106. The second dielectric layer 108 may include, for example, silicon dioxide, silicon nitride, or silicon oxynitride. The second dielectric layer 108 has a composition different from that of the etch stop layer 106. The second dielectric layer 108 has a thickness of at least 100 nanometers in order to adequately protect the microelectronic device 100 from contamination or mechanical damage.

[0020] The microelectronic device 100 is free of the second dielectric layer 108 in the etch region 110. The etch region 110 extends upward from the top surface 114 of the etch stop layer 106 to the top surface 112 of the second dielectric layer 108 and extends laterally over at least a portion of the metal layer 104. Figure 1 As depicted, etch region 110 may extend over the entire metal layer 104. Figure 1 As depicted, the etch stop layer 106 may optionally be present in the etch region 110 and extend across the etch region 110. Alternatively, a portion or all of the etch region 110 may be free of the etch stop layer 106. The side surface 116 of the second dielectric layer 108 facing the etch region 110 may be straight, which is not easily obtained by a wet etching process and indicates that the etch region 110 is formed by a plasma process. The wet etching process generally produces a curved side surface. The side surface 116 of the second dielectric layer 108 facing the etch region 110 may be substantially vertical, as shown in FIG. Figure 1 depicted, or at an angle, such as up to 20 degrees, from vertical.

[0021] The metal layer 104 of this example may be contacted by one or more electrical connectors 118. In this example, the electrical connectors 118 may be located in the first dielectric layer 102. The electrical connectors 118 of this example may include, for example, vias 120 and interconnects 122. Other configurations of the electrical connectors 118, optionally along with other components, are within the scope of this example.

[0022] The metal layer 104 can provide a sensing element for a sensor such as a thermistor. Leaving the etched region 110 free of the second dielectric layer 108 can advantageously achieve physical coupling between the metal layer 104 and the environment in contact with the microelectronic device 100. During operation of the microelectronic device 100 in some environments, such as in an oxidizing environment or at high temperatures above 100° C., the etch stop layer 106 can reduce the loss of the metal layer 104. Making the thickness of the etch stop layer 106 less than 10 nanometers can advantageously provide a desired level of physical coupling between the metal layer 104 and the environment.

[0023] FIG. 2A to FIG. 2H is a cross-section of a microelectronic device including a metal layer depicted at a stage in an example formation method. Figure 2A , the microelectronic device 200 includes a first dielectric layer 202, which may have a reference Figure 1 In the case where the first dielectric layer 202 is formed on a silicon substrate, the first dielectric layer 202 may be formed, for example, by a plasma enhanced chemical vapor deposition (PECVD) process, a low pressure chemical vapor deposition (LPCVD) process, a spin coating process using hydrogen silsesquioxane (HSQ), or a thermal oxidation process.

[0024] The microelectronic device 200 may include an electrical connection 218 in or through the first dielectric layer 202. The electrical connection 218 may include a via 220 extending to a surface of the first dielectric layer 202, and an interconnect 222 contacting the via 220.

[0025] A metal film 224 is formed on the first dielectric layer 202. The metal film 224 may include a reference Figure 1 The metal film 224 may be formed by an evaporation process, a sputtering process, or a metal organic chemical vapor deposition (MOCVD) process. The metal film 224 may have a thickness of, for example, 10 nanometers to 1 micrometer. The metal film 224 may contact the electrical connector 218 so that an electrical signal may be sent through the metal film 224 using the electrical connector 218.

[0026] A first etching mask 226 is formed over the metal film 224 to cover the area of ​​the subsequently formed metal layer. The first etching mask 226 may include, for example, a photoresist and an anti-reflective layer. The first etching mask 226 may be formed by a photolithography process. Other methods of forming the first etching mask 226, such as an additive process, are within the scope of this example.

[0027] Reference Figure 2B , is removed at the location exposed by the first etching mask 226 Figure 2A The metal film 224 is formed by a first etching mask 226 to form the metal layer 204. For example, the metal film 224 can be removed by a wet etching process. Due to the undercut by the wet etching process, the metal layer 204 can be recessed from the lateral edge of the first etching mask 226. Other methods of removing the metal film 224, such as a plasma process, are within the scope of this example.

[0028] The first etching mask 226 is then removed. The photoresist and the organic anti-reflective material in the first etching mask 226 may be removed, for example, by an ashing process followed by a wet cleaning process.

[0029] Reference Figure 2C , the microelectronic device 200 is exposed to a metal-containing agent, Figure 2C The metal reagent is marked as Figure 2E 2 is a diagram showing a portion of an atomic layer deposition (ALD) process for an etch stop layer 206. The metal-containing reagent forms a metal-containing layer 228 over the metal layer 204 and over the first dielectric layer 202 directly adjacent to the metal layer 204. The metal-containing layer 228 may extend completely over the first dielectric layer 202. The metal-containing layer 228 may have a thickness of approximately one molecular layer.

[0030] The metal-containing reagent may include aluminum, such as trimethylaluminum. The metal-containing reagent may include titanium, such as isopropoxy titanium or tetrakis(dimethylamino)titanium. The metal-containing reagent may include tantalum, such as ethoxide tantalum. The metal-containing reagent may include zirconium, such as tetrakis(dimethylamino)zirconium, tetrakis(ethylmethylamino)zirconium or tetrakis(diethylamino)zirconium. The metal-containing reagent may include hafnium, such as tetrakis(dimethylamino)hafnium, tetrakis(ethylmethylamino)hafnium or tetrakis(diethylamino)hafnium. The metal-containing reagent may include vanadium, such as tetrakis(dimethylamino)vanadium. Other ingredients for the metal-containing reagent are within the scope of this example.

[0031] The microelectronic device 200 may be heated during the ALD process to provide a desired stoichiometry and density for the etch stop layer 206. Heating the microelectronic device 200 may also provide a desired low hydrogen content in the etch stop layer 206. The microelectronic device 200 may be heated to, for example, 50°C to 300°C.

[0032] After forming the metal-containing layer 228, the flow of the metal-containing reagent is stopped. The environment above the microelectronic device 200 is purged, such as by another gas (eg, argon), to remove any remaining metal-containing reagent.

[0033] Reference Figure 2D , the microelectronic device 200 is exposed to an oxygen-containing agent, Figure 2D The oxygen reagent is marked as Figure 2E The oxygen-containing reagent forms an oxygen-containing layer 230 on the metal-containing layer 228. The oxygen-containing layer 230 may have a thickness of about one molecular layer. The oxygen-containing reagent may include, for example, water vapor, ozone, or atomic oxygen provided by an oxygen plasma.

[0034] The oxygen in the oxygen-containing layer 230 reacts with the metal in the metal-containing layer 228 to form a metal oxide layer of the etch stop layer 206. The organic functional groups in the metal-containing layer 228 are desorbed from the microelectronic device 200.

[0035] The flow of the oxygen-containing reagent is then stopped. The environment above the microelectronic device 200 is purged to remove any residual oxygen-containing reagent.

[0036] Reference Figure 2E , by sequentially repeating the reference Figure 2C and Figure 2D The steps described above form the etch stop layer 206, thereby adding a metal oxide layer to the etch stop layer 206. For example, the formation of aluminum oxide with a thickness of 4 nanometers using trimethylaluminum and ozone can be achieved by referring to Figure 2C and Figure 2D The described sequence is completed with about 40 iterations. The etch stop layer 206 may include reference Figure 1 The etch stop layer 106 is described as any metal oxide.

[0037] Reference Figure 2F , a second dielectric layer 208 is formed over the etch stop layer 206. The second dielectric layer 208 may include a single layer of dielectric material, or two or more sub-layers of dielectric material. The second dielectric layer 208 may include silicon dioxide, silicon nitride, silicon oxynitride, or any combination thereof. The thickness of the second dielectric layer 208 may be at least 100 nanometers to provide the desired protection for the microelectronic device 200. The second dielectric layer 208 may be formed, for example, by a PECVD process, an LPCVD process, or a spin coating process. The etch stop layer 206 may advantageously provide better adhesion to the metal layer 204 than the adhesion provided by forming the second dielectric layer 208 directly on the metal layer 204. In a version of this example, where the metal layer 204 primarily includes platinum or gold, the metal oxide in the etch stop layer 206 may provide better adhesion than other dielectric materials.

[0038] A second etch mask 232 is formed over the second dielectric layer 208, exposing an area for etching the region 210. The area for etching the region 210 extends over at least a portion of the metal layer 204. The second etch mask 232 may include a photoresist formed by a photolithography process, which may advantageously reduce the manufacturing cost of the microelectronic device 200 compared to forming an etch mask using a hard mask material such as hard carbon.

[0039] Reference Figure 2G , the second dielectric layer 208 is removed from the etch region 210 by a plasma process using fluorine, stopping on the etch stop layer 206 . Figure 2G Depicts a partially completed plasma process. The plasma process causes the fluorine-containing reagent (in Figure 2G A plasma process (depicted as "fluorine reagent") is flowed over the microelectronic device 200. The fluorine-containing reagent may include a combination of one or more fluorine-containing gases, such as tetrafluoromethane (CF4) and trifluoromethane (CHF3). A carrier gas, such as nitrogen, may also flow over the microelectronic device 200. Radio frequency (RF) power is applied to the fluorine-containing reagent to form a plasma that provides fluorine radicals, including fluorine ions, to remove the second dielectric layer 208 from the etch region 210. The thickness of the second dielectric layer 208 is at least 10 times the thickness of the etch stop layer 206, so the etching rate of the plasma process on the etch stop layer 206 must be a much lower rate than the etching rate of the plasma process on the second dielectric layer 208. This etching rate condition is achieved by making the plasma process substantially free of gases that tend to provide a sputtering etching mechanism, that is, gases such as rare gases (i.e., helium, neon, argon, or xenon). It has been demonstrated that the use of fluorine without argon to remove the second dielectric layer 208 in a plasma process has a sufficiently lower etch rate than an etch stop layer 206 comprising aluminum oxide to be able to stop on an embodiment of the etch stop layer 206 having a thickness of 4 nanometers after removing an embodiment of the second dielectric layer 208 having a thickness of 500 nanometers. The term "stopping on the etch stop layer 206" includes removing a first portion of the etch stop layer 206 during the plasma process, thereby retaining a second portion of the etch stop layer 206 after the plasma process is completed. Eliminating the noble gas from the plasma process can reduce the etch rate of the second dielectric layer 208, thereby extending the etching time. In order to reduce degradation of the second etch mask 232, the gas above the microelectronic device 200 can be substantially free of oxygen. In the context of a plasma process to remove the second dielectric layer 208 from the etch region 210, the term "substantially free" means that the relevant gas (noble gas or oxygen) is not intentionally introduced into the plasma process.

[0040] Reference Figure 2HAfter the etch stop layer 206 is exposed from the entire etch region 210, the plasma process for removing the second dielectric layer 208 from the etch region 210 can be continued, which is generally referred to as over-etching. The over-etching step can be continued for half the time required to remove the second dielectric layer 208 from the etch region 210. At least a portion of the etch stop layer 206 can remain after the over-etching step is completed, so that the over-etching step can advantageously provide complete removal of the second dielectric layer 208 across a workpiece (such as a wafer) containing the microelectronic device 200, and can also provide complete removal of the second dielectric layer 208 from wafer to wafer, taking into account the variation in the thickness of the second dielectric layer 208 between wafers. The etch region 210 extends upward from the top surface 214 of the etch stop layer 206 to the top surface 212 of the second dielectric layer 208.

[0041] The second etch mask 232 is then removed, leaving the etch stop layer 206 in place in the etched region 210 to provide a similar Figure 1 The second etch mask 232 may be removed by an ashing process (eg, a barrel ashing process or a downstream ashing process) to reduce ion damage to the etch stop layer 206. Alternatively, a wet photoresist removal process using a commercial photoresist stripper may be used.

[0042] Figure 3 3 is a cross-section of another example microelectronic device including a metal layer. Microelectronic device 300 includes a first dielectric layer 302. First dielectric layer 302 may include reference Figure 1 The metal layer 304 is disposed on the first dielectric layer 302. The metal layer 304 may include any dielectric material described with reference to Figure 1 In this example, the metal layer 104 may be any metal described. Figure 3 As depicted, metal layer 304 is disposed in the trenches of first dielectric layer 302 .

[0043] The etch stop layer 306 is disposed over the metal layer 304 and over the first dielectric layer 302 directly adjacent to the metal layer 304. The thickness of the etch stop layer 306 is less than 10 nanometers. The etch stop layer 306 includes a Figure 1 The etch stop layer 306 may be at least one metal oxide of any of the metal oxides described for the etch stop layer 106. The etch stop layer 306 may have a composition different from that of the first dielectric layer 302.

[0044] The second dielectric layer 308 is disposed over the etch stop layer 306. The second dielectric layer 308 may include a reference Figure 1The second dielectric layer 308 may be any dielectric material described above for the second dielectric layer 108. The second dielectric layer 308 has a composition that is different from the composition of the etch stop layer 306. The second dielectric layer 308 has a thickness 334 of at least 100 nanometers.

[0045] The microelectronic device 300 is free of the second dielectric layer 308 in the etch region 310. The etch region 310 extends upward from the top surface 314 of the etch stop layer 306 to the top surface 312 of the second dielectric layer 308 and extends laterally over at least a portion of the metal layer 304. Figure 3 As indicated, the etched region 310 may be discontinuous. Figure 3 As depicted, the etch stop layer 306 may optionally be present in the etch region 310 and extend across the etch region 310. Alternatively, a portion or all of the etch region 310 may be free of the etch stop layer 306. The side surface 316 of the second dielectric layer 308 facing the etch region 310 may be straight, which is not easily obtained by a wet etching process and indicates that the etch region 310 is formed by a plasma process. The width 336 of the etch region 310 between two adjacent portions of the second dielectric layer 308 may be less than the thickness 334 of the second dielectric layer 308, which is not easily obtained by a wet etching process and also indicates that the etch region 310 is formed by a plasma process. The width 336 of the etch region 310 having the straight side surface 316 and being less than the thickness 334 of the second dielectric layer 308 may make the area for the component having the metal layer 304 smaller, thereby advantageously reducing the size and manufacturing cost of the microelectronic device 300.

[0046] The metal layer 304 of this example may be contacted by one or more electrical connections 318. In this example, the electrical connections 318 may include wire bonds on the metal layer 304 through the etch stop layer 306. The thickness of the etch stop layer 306 being less than 10 nanometers may advantageously enable reliable wire bonds to be formed to the metal layer 304 without removing the etch stop layer 306. The etch region 310 and the etch stop layer 306 may provide a reference Figure 1 Advantages of the microelectronic device 100 are described.

[0047] FIG. 4A to FIG. 4E is a cross-section of a microelectronic device including a metal layer depicted at a stage in another example formation method. Figure 4A , the microelectronic device 400 includes a first dielectric layer 402, which may have a dielectric layer as shown in FIG. Figure 1 The first dielectric layer 402 may be formed by referring to Figure 2A The first dielectric layer 202 may be formed by any of the processes described above.

[0048] A metal layer 404 is formed on the first dielectric layer 402. In this example, Figure 4A As depicted, metal layer 404 is formed in a trench in first dielectric layer 402. The trench may be formed by an etching process before forming the metal. Metal layer 404 may be formed by forming a metal film extending into the trench on first dielectric layer 402. The metal film may be formed by referring to Figure 2A The metal film 224 is formed by any process described above. The metal film is then removed from the outside of the trench, such as by a chemical mechanical polishing (CMP) process. The metal layer 404 may include reference Figure 1 The metal layer 104 may be any metal as described.

[0049] Reference Figure 4B , an etch stop layer 406 is formed on the metal layer 404 and on the first dielectric layer 402 directly adjacent to the metal layer 404. The etch stop layer 406 includes a metal oxide and has a thickness of less than 10 nanometers. The etch stop layer can be formed by, for example, referring to FIG. 2C to FIG. 2E The ALD process described is formed.

[0050] Reference Figure 4C , a second dielectric layer 408 is formed over the etch stop layer 406. The second dielectric layer 408 may include a reference Figure 2F The second dielectric layer 208 may be made of any dielectric material described herein and may be made by reference to Figure 2F The second dielectric layer 208 may be formed by any of the processes described above. The thickness of the second dielectric layer 408 may be at least 100 nanometers.

[0051] An etch mask 432 is formed over the second dielectric layer 408, exposing areas for etching the regions 410. Figure 4C As shown in FIG. 4 , the area for etching region 410 extends over at least a portion of metal layer 404 and may optionally be discontinuous. Etching mask 432 may include a photoresist formed by a photolithography process having a reference Figure 2F The advantages of the second etching mask 232 are described.

[0052] Reference Figure 4D , by using a fluorinated reagent (in Figure 4D The plasma process (labeled as "fluorine agent" in FIG. 1 ) removes the second dielectric layer 408 from the etched area 410, stopping on the etch stop layer 406. A carrier gas may also be used in the plasma process. RF power (at Figure 4D RF power) is applied to the fluorine-containing reagent to form a plasma. The plasma process can be substantially free of noble gases and oxygen, with reference to Figure 2G and Figure 2HAdvantages discussed. Due to the undercut by the wet etching process, the plasma process can enable the formation of an etched region 410 with a smaller geometry than can be easily obtained by the wet etching process. The plasma process can produce a substantially straight profile of the side surface 416 of the second dielectric layer 408. In addition, the width 436 of the etched region 410 between two adjacent portions of the second dielectric layer 408 can be less than the thickness 434 of the second dielectric layer 408. The etched region 410 extends upward from the top surface 414 of the etch stop layer 406 to the top surface 412 of the second dielectric layer 408.

[0053] The etch mask 432 is then removed. The etch mask 432 may be removed, such as by a plasma process using oxygen, a wet cleaning process, or a combination thereof.

[0054] Reference Figure 4E , an electrical connection 418, which in this example is implemented as a wire bond 418, is formed on the metal layer 404 in the etched area 410 using a wire bonding tool 438. In this example, the wire bond 418 can be formed through the etch stop layer 406 by an ultrasonic bonding process, advantageously eliminating the patterning or removal of the etch stop layer 406. The thickness of the etch stop layer 406 less than 10 nanometers can advantageously enable the formation of the wire bond 418 to the metal layer 404 with desired mechanical integrity and reliability.

[0055] Figure 5 5 is a cross-section of another example microelectronic device including a metal layer. Microelectronic device 500 includes a first dielectric layer 502. First dielectric layer 502 may include reference Figure 1 The first dielectric layer 102 may be any dielectric material as described above. The metal layer 504 is disposed on the first dielectric layer 502. The metal layer 504 may include reference Figure 1 Any metal described in the metal layer 104. Figure 5 As depicted, the metal layer 504 can be disposed in a trench in the first dielectric layer 502 , or in another configuration it can be disposed on the first dielectric layer 502 .

[0056] In this example, an etch stop layer 506 is partially disposed over the metal layer 504 and over the first dielectric layer 502 directly adjacent to the metal layer 504. The thickness of the etch stop layer 506 is less than 10 nanometers. The etch stop layer 506 includes a dielectric layer such as the dielectric layer 502 shown in FIG. Figure 1 The etch stop layer 506 may be at least one metal oxide of any of the metal oxides described for the etch stop layer 106. The etch stop layer 506 may have a composition different from that of the first dielectric layer 502.

[0057] The second dielectric layer 508 is disposed over the etch stop layer 506. The second dielectric layer 508 may include a reference Figure 1The second dielectric layer 508 may be any dielectric material as described above for the second dielectric layer 108. The second dielectric layer 508 has a composition different from the composition of the etch stop layer 506. The second dielectric layer 508 has a thickness of at least 100 nanometers.

[0058] In this example, the microelectronic device 500 can include a third dielectric layer 540 below the first dielectric layer 502. The third dielectric layer 540 can have a composition different from that of the first dielectric layer 502. For example, the first dielectric layer 502 can include primarily silicon dioxide, and the third dielectric layer 540 can include a sublayer of primarily silicon nitride above a thin sublayer of thermal oxide. The microelectronic device 500 can further include a semiconductor region 542 below the third dielectric layer 540.

[0059] The microelectronic device 500 is free of the second dielectric layer 508 in the etch region 510. The etch region 510 of this example extends upward from the top surface 514 of the etch stop layer 506 to the top surface 512 of the second dielectric layer 508 and extends laterally over a portion of the metal layer 504. Figure 5 As shown, the etch region 510 can further extend below the etch stop layer 506 to the third dielectric layer 540, so that the microelectronic device 500 is also free of the first dielectric layer 502 in the etch region 510. Figure 5 As depicted, a portion of metal layer 504 may be exposed at etch region 510 .

[0060] The semiconductor region 542 may have a first conductivity type such as a p-type under the etch region 510. The semiconductor region 542 may further include a source and drain region 544 extending partially under the etch region 510. The source and drain region 544 has a conductivity type opposite to that of the semiconductor region 542 under the etch region 510. In the case where the semiconductor region 542 under the etch region 510 is a p-type, the source and drain region 544 may be an n-type.

[0061] The metal layer 504, the etched region 510, the third dielectric layer 540, the semiconductor region 542 below the etched region 510, and the source and drain regions 544 can provide an ISFET 546 of the microelectronic device 500. During operation of the microelectronic device 500, a fluid such as an aqueous solution is allowed to enter the etched region 510 so that the fluid contacts the metal layer 504 and the third dielectric layer 540. A potential can be provided to the metal layer 504 while a current is measured between the source and drain regions 544. The relationship between the potential applied to the metal layer 504 and the current between the source and drain regions 544 can provide information about the fluid (e.g., the concentration of ions or the pH of the fluid). Compared to other ISFET configurations integrated into the microelectronic device, the ISFET 546 can have a small area, thereby advantageously improving the sensitivity of the ISFET 546, which can be proportional to the ratio of the channel width to the channel length, and reducing the size and manufacturing cost of the microelectronic device 500. The ISFET 546 can enable the microelectronic device 500 to sample small amounts of fluid (such as less than one picoliter of fluid) compared to other ISFET configurations, advantageously allowing the microelectronic device 500 to be used in a wider range of applications.

[0062] FIG. 6A to FIG. 6D is a cross-section of a microelectronic device including a metal layer depicted at a stage further illustrating a formation method. Fig. 6A , the microelectronic device 600 of this example may include a semiconductor region 642 having a first conductivity type. Fig. 6A As shown, the first conductivity type may be a p-type. Source and drain regions 644 having a second opposite conductivity type may be formed in the semiconductor region 642. Fig. 6A As shown, the second conductivity type can be n-type. Source and drain regions 644 can be formed by implanting dopants of the second conductivity type (such as phosphorus and arsenic) into the semiconductor region 642. The microelectronic device 600 of this example can further include a third dielectric layer 640 above the semiconductor region 642. The third dielectric layer 640 can include a thin sublayer of thermal oxide on the semiconductor region 642, and a sublayer of another dielectric material such as silicon nitride on the thin layer of thermal oxide. The thermal oxide in the third dielectric layer 640 can be formed by thermal oxidation of silicon at the top surface of the semiconductor region 642. The silicon nitride in the third dielectric layer 640 can be formed by a LPCVD process. Other compositions, structures, and formation methods of the third dielectric layer 640 are within the scope of this example.

[0063] The microelectronic device 600 includes a first dielectric layer 602 above a third dielectric layer 640. The first dielectric layer 602 can have a different composition than the top sublayer of the third dielectric layer 640 to provide a desired selectivity to a subsequent etching process for removing a portion of the first dielectric layer and stopping in or on the third dielectric layer 640. For example, the first dielectric layer 602 can primarily include silicon dioxide or a silicon dioxide-based dielectric material, such as OSG. The first dielectric layer 602 can be formed by referring to Figure 2A The first dielectric layer 202 may be formed by any of the processes described above.

[0064] A metal layer 604 is formed on the first dielectric layer 602. In this example, Fig. 6A As depicted, the metal layer 604 can be formed in a trench in the first dielectric layer 602. Figure 4A The grooves and metal layer 604 are formed as described above for the metal layer 404. Alternatively, the first dielectric layer 602 may have a planar top surface, and the metal layer 604 may be formed on the planar top surface. In this case, the metal layer 604 may be formed by referring to Figure 2A Any other configuration of the metal layer 604 on the first dielectric layer 602 is within the scope of this example. The metal layer 604 may include reference Figure 1 The metal layer 104 may be any metal as described.

[0065] An etch stop layer 606 is formed on the metal layer 604 and on the first dielectric layer 602 directly adjacent to the metal layer 604. The etch stop layer 606 includes a metal oxide and has a thickness of less than 10 nanometers. The etch stop layer may be formed by, for example, FIG. 2C to FIG. 2E A second dielectric layer 608 is formed over the etch stop layer 606 by the ALD process described herein. The second dielectric layer 608 may have a composition different from that of the first dielectric layer. For example, the second dielectric layer 608 may primarily include silicon nitride or silicon oxynitride. The thickness of the second dielectric layer 608 may be at least 100 nanometers.

[0066] An upper etching mask 632 is formed on the second dielectric layer 608, which exposes a portion of the area for etching the area 610. As shown in FIG. 6, the area for etching the area 610 extends over a portion of the metal layer 604 and over a portion of the first dielectric layer directly adjacent to the metal layer 604. The etching mask 632 may include a photoresist formed by a photolithography process, which has a reference Figure 2F The advantages of the second etching mask 232 are described.

[0067] Reference Figure 6B , by using a fluorinated reagent (in Figure 6BThe second dielectric layer 608 is removed from a portion of the etched region 610 above the etch stop layer 606 by a plasma process using a fluorine-containing agent (labeled as "fluorine agent" in FIG. 1 ) and optionally a carrier gas. RF power is applied to the fluorine-containing agent to form a plasma. The plasma process may be substantially free of noble gases and oxygen, with reference to Figure 2G and Figure 2H Advantages discussed.

[0068] Reference Figure 6C , the etch stop layer 606 is removed at the locations exposed in the etched area 610 without removing a substantial amount of the metal layer 604. The etch stop layer 606 may be removed in a timed process of a few seconds, such as by an ion milling process using argon ions 648. The ion milling process is sometimes referred to as a sputter etching process. Alternatively, the etch stop layer 606 may be removed by a wet etching process using an aqueous solution of a mixture of phosphoric acid, hydrofluoric acid, buffered hydrofluoric acid, ammonium hydroxide and hydrogen peroxide, or acetic acid and ammonium fluoride. Other methods of removing the etch stop layer 606 without removing a substantial amount of the metal layer 604, such as a short plasma etch using chlorine, are within the scope of this example.

[0069] Reference Fig.6D , removing the first dielectric layer 602 from the second portion of the etched region 610, thereby exposing a portion of the third dielectric layer 640 above the semiconductor region 642 between the source and drain regions 644. The first dielectric layer 602 can be removed, for example, by a downstream etching process that uses a fluorine-containing reagent (labeled "fluorine reagent" in FIG. 6) and RF power (at Fig.6D 608, and extends laterally over a portion of the metal layer 604, and further extends below the etch stop layer 606 to the third dielectric layer 640.

[0070] The etch mask 632 is then removed. The exemplary method may provide an ISFET 646 or similar sensor for use in the microelectronic device 600.

[0071] Figure 7 700 includes a first dielectric layer 702. In this example, the first dielectric layer 702 can include silicon dioxide or a silicon dioxide-based dielectric material. The first dielectric layer 702 can be part of an interconnect dielectric layer stack of the microelectronic device 700.

[0072] The metal layer 704 is located above the first dielectric layer 702. Figure 7 As depicted, metal layer 704 can be the top metal layer of a bonding pad 750 of microelectronic device 700. Bond pad 750 can optionally include a lower metal layer 752 below metal layer 704. Lower metal layer 752 can include a sublayer of a metal such as an adhesion sublayer, a barrier sublayer, or a fill sublayer. Metal layer 704 provides a bonding surface for bonding pad 750. Metal layer 704 can include, for example, gold, platinum, aluminum, or other metal suitable for wire bonding.

[0073] The bonding pad 750 can be electrically coupled to an interconnect 754 of the microelectronic device 700. The interconnect 754 can be located in the first dielectric layer 702. The interconnect 754 can include, for example, aluminum or copper. Figure 7 The depicted one is directly on interconnect 754, or may be electrically coupled to interconnect 754 through a via or other conductive structure not shown.

[0074] The etch stop layer 706 is disposed over a portion of the metal layer 704 and over the first dielectric layer 702 directly adjacent to the metal layer 704. The thickness of the etch stop layer 706 is less than 10 nanometers. The etch stop layer 706 includes a Figure 1 The etch stop layer 706 may be at least one metal oxide of any of the metal oxides described. The etch stop layer 706 may have a composition different from that of the first dielectric layer 702 .

[0075] A second dielectric layer 708 is disposed over the etch stop layer 706. The second dielectric layer 708 of this example may be a protective overcoat (PO) of the microelectronic device 700, and thus may include, for example, silicon dioxide, silicon nitride, silicon oxynitride, or any combination thereof. The second dielectric layer 708 has a composition different from that of the etch stop layer 706. The second dielectric layer 708 has a thickness of at least 100 nanometers. The etch stop layer 706 may advantageously provide better adhesion to the metal layer 704 than the second dielectric layer 708 would provide. In a version of this example, where the metal layer 704 primarily includes platinum or gold, and where the second dielectric layer 708 includes silicon dioxide, silicon nitride, or silicon oxynitride, the metal oxide in the etch stop layer 706 may provide superior adhesion than the second dielectric layer 708 would provide, which may advantageously improve the reliability of the microelectronic device 700.

[0076] The microelectronic device 700 is free of the second dielectric layer 708 in the etched region 710. The etched region 710 extends upward from the top surface 712 of the second dielectric layer 708 to the top surface 714 of the etch stop layer 706 and extends laterally over at least a portion of the metal layer 704 to expose an area for wire bonding 718. Figure 7 As depicted, the etch region 710 may optionally be free of the etch stop layer 706. Alternatively, a portion or all of the etch stop layer 706 may be present in the etch region 710, and the wire bond 718 may optionally be made through the etch stop layer 706 that may be present. The advantage of the metal oxide in the etch stop layer 706 is demonstrated by the fact that the etch stop layer 706 may be thick enough to prevent etching of the first dielectric layer 702 during etching of the etch region 710, and may be thin enough to enable the wire bond 718 to be formed through the etch stop layer 706. The side surface 716 of the second dielectric layer 708 facing the etch region 710 may be straight, which is not easily obtained by a wet etching process, and indicates that the etch region 710 is formed by a plasma process. The wire bond 718 contacts the metal layer 704 at the location exposed by the etch region 710, and provides an electrical connection to the interconnect 754 through the bonding pad 750. Since the etching stop layer 706 is formed, the side surface 716 of the second dielectric layer 708 facing the etching region 710 may be free of metal residues from the metal layer 704 , which advantageously reduces potential contamination of the microelectronic device 700 .

[0077] FIG. 8A to FIG. 8D is a cross-section of a microelectronic device including a metal layer depicted at a stage in another example formation method. Fig. 8A , the microelectronic device 800 includes a first dielectric layer 802, which can be part of an interconnect dielectric layer stack of the microelectronic device 800. The first dielectric layer 802 can include, for example, silicon dioxide or a silicon dioxide-based dielectric material. The interconnect 854 can be formed in or below the first dielectric layer 802. In one version of this example, the interconnect 854 can include aluminum and can be formed by etching the aluminum layer using an RIE process. In another version, the interconnect 854 can include copper and be formed by a damascene process. Other compositions and formation methods for the interconnect 854 are within the scope of this example.

[0078] A bond pad 850 is formed to make an electrical connection to an interconnect 854. The bond pad 850 includes a metal layer 804 extending to the top of the bond pad 850. In one version of this example, the bond pad 850 may be formed by etching a bond pad opening in the first dielectric layer 802 to expose a portion of the interconnect 854, then plating a lower metal layer 852, and then plating the metal layer 804 on the lower metal layer 852. In another version, the bond pad 850 may be formed by etching a bond pad opening in the first dielectric layer 802 to expose a portion of the interconnect 854, then forming a metal layer including an adhesion metal sublayer and an aluminum layer on the first dielectric layer 802, extending into the bond pad opening, and then etching the metal layer outside the bond pad opening so that the aluminum layer provides the metal layer 804. Other methods of forming the bond pad 850 are within the scope of this example.

[0079] Reference Figure 8B , an etch stop layer 806 is formed on the metal layer 804 and on the first dielectric layer 802 directly adjacent to the metal layer 804. The etch stop layer 806 includes a metal oxide and has a thickness of less than 10 nanometers. The etch stop layer can be formed by, for example, referring to FIG. 2C to FIG. 2E A second dielectric layer 808 is formed over the etch stop layer 806. The second dielectric layer 808 may include Figure 7 The second dielectric layer 708 may be any dielectric material as described above. Figure 2F The second dielectric layer 808 may be formed by any of the processes described for the second dielectric layer 208 of FIG. The thickness of the second dielectric layer 808 may be at least 100 nanometers. The etch stop layer 806 may advantageously provide better adhesion to the metal layer 804 than the second dielectric layer 808 would provide, particularly when the metal layer 804 comprises primarily platinum or gold, as described with reference to FIG. Figure 7 As described, improved reliability is advantageously provided.

[0080] Reference Figure 8C , an etching mask 832 is formed over the second dielectric layer 808, which exposes an area for etching the area 810. The area for etching the area 810 extends over at least a portion of the metal layer 804. The etching mask 832 may include a photoresist formed by a photolithography process, which has a reference Figure 2F The advantages of the second etching mask 232 are described.

[0081] Subsequently, by using a fluorine-containing reagent (in Figure 8C The plasma process (labeled as "fluorine agent" in FIG. 1 ) removes the second dielectric layer 808 from the etched area 810, stopping on the etch stop layer 806. A carrier gas may also be used in the plasma process. RF power (at Figure 8CRF power) is applied to the fluorine-containing reagent to form a plasma. The plasma process can be substantially free of noble gases and oxygen, with reference to Figure 2G and Figure 2H The advantages discussed. The plasma process can produce a substantially straight profile of the side surface 816 of the second dielectric layer 808. The etch region 810 extends upward from the top surface 814 of the etch stop layer 806 to the top surface 812 of the second dielectric layer 808. The plasma process can be continued after the etch stop layer 806 in the over-etch step to advantageously provide complete removal of the second dielectric layer 808 in the etch region 810. The metal oxide in the etch stop layer 806 advantageously prevents removal of dielectric material from the first dielectric layer 802 during the over-etch step.

[0082] The etch mask 832 is then removed. The etch mask 832 may be removed, such as by a plasma process using oxygen, a wet cleaning process, or a combination thereof.

[0083] Reference Fig.8D , the etch stop layer 806 may be optionally removed at locations exposed by the second dielectric layer 808. The etch stop layer 806 may be removed to facilitate subsequent wire bonding operations. Fig.8D As depicted, the etch stop layer 806 can be removed by a wet etching solution 856. The wet etching solution 856 can include, for example, an aqueous solution of a mixture of phosphoric acid, hydrofluoric acid, buffered hydrofluoric acid, ammonium hydroxide and hydrogen peroxide, or acetic acid and ammonium fluoride. Other formulations of the wet etching solution 856 are within the scope of this example. The wet etching solution 856 is formulated to remove little or substantially no first dielectric layer 802 or second dielectric layer 808. In another version of this example, the etch stop layer 806 can be removed by a dry process, such as a dry process as described with reference to FIG. Figure 6C Alternatively, the etch stop layer 806 may be left in place, advantageously reducing the manufacturing cost and complexity of the microelectronic device 800.

[0084] The formation of the microelectronic device 800 can continue by forming wire bonds, not shown, on the metal layer 804. Forming the microelectronic device 800 by the method of this example can provide a clean surface for wire bonding on the metal layer 804 compared to other methods without the etch stop layer 806. In the version of this example, where the etch stop layer 806 is not removed at the location exposed by the second dielectric layer 808, wire bonds can be made through the etch stop layer 806 to the metal layer 804. The metal oxide in the etch stop layer 806 can advantageously provide effective protection for the first dielectric layer 802, and can also enable the formation of wire bonds through the etch stop layer 806.

[0085] Various features of the examples described herein may be combined in other manifestations of the example integrated circuits. For example, a microelectronic device may have Figure 1 , Figure 3 , Figure 5 or Figure 7 Any structure described on the first dielectric layer as described with respect to Figure 1 , Figure 3 , Figure 5 or Figure 7 Any structure described in the metal layer, and as described in relation to Figure 1 , Figure 3 , Figure 5 or Figure 7 Similarly, a microelectronic device can be formed by: forming an etch stop layer as described in reference Figure 2A and Figure 2B As described, as referenced Figure 4A As described, as referenced Fig. 6A as described or as referenced Fig. 8A The metal layer is formed as described in reference FIG. 2C to FIG. 2E The etching stop layer is formed as described, and as described in reference Figure 2H or Figure 4E The etch stop layer is left in the etched area as described, or as described with reference to Figure 6C or Fig.8D The etch stop layer is removed as described, and further combined with the reference Figures 2F to 2H As described, as referenced Figure 4C and Figure 4D As described, as referenced FIG. 6A to FIG. 6D Described or referred to Figure 8C The etched regions are formed as described.

[0086] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. A microelectronic device comprising: a first dielectric layer; a metal layer over the first dielectric layer; an etch stop layer on the first dielectric layer and on a portion of the metal layer, the etch stop layer comprising a metal oxide, the etch stop layer having a thickness less than 10 nanometers; as well as a second dielectric layer on the etch stop layer, wherein an etch region extends upward from a top surface of the etch stop layer to a top surface of the second dielectric layer and extends laterally partially above and beyond the metal layer such that at least one sidewall surface and a bottom surface of the metal layer are exposed to a cavity formed by the etch region, the etch region being free of the second dielectric layer. 2 . The microelectronic device of claim 1 , wherein the etch region is free of the etch stop layer.

3. The microelectronic device of claim 1, wherein the metal layer comprises a metal selected from the group consisting of platinum, gold, iridium, silver, palladium, rhodium, ruthenium, rhenium nickel, aluminum, and copper.

4. The microelectronic device of claim 1, wherein the metal oxide is selected from the group consisting of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, vanadium oxide, and tantalum oxide. 5 . The microelectronic device of claim 1 , wherein the etch region extends below a portion of the etch stop layer to expose a bottom surface of the portion of the etch stop layer to the cavity, and wherein the etch region is free of the first dielectric layer.

6. The microelectronic device of claim 1, further comprising an electrical connection to the metal layer, the electrical connection being located in the first dielectric layer.

7. The microelectronic device of claim 1, further comprising an electrical connection to the metal layer, the electrical connection comprising a wire bond through the etch stop layer to the metal layer, wherein the wire bond contacts the etch stop layer.

8. The microelectronic device of claim 1, wherein a width of the etched region is less than a thickness of the second dielectric layer. 9 . The microelectronic device according to claim 1 , wherein a side surface of the second dielectric layer facing the etching region is straight.

10. The microelectronic device of claim 1, wherein the metal layer is disposed in a trench in the first dielectric layer.

11. The microelectronic device of claim 1, wherein the first dielectric layer comprises a dielectric material selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride, and the second dielectric layer comprises a dielectric material selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride.

12. A method of forming a microelectronic device, comprising: forming a first dielectric layer; forming a metal layer over the first dielectric layer; forming an etch stop layer over the metal layer and the first dielectric layer directly adjacent to the metal layer, the etch stop layer comprising a metal oxide, the etch stop layer having a thickness of less than 10 nanometers; forming a second dielectric layer over the etch stop layer; and The second dielectric layer is removed from an etched region by a plasma etching process that stops on the etch stop layer, the etched region extending upward from a top surface of the etch stop layer to a top surface of the second dielectric layer and extending laterally at least partially above the metal layer, wherein the plasma etching process uses a fluorine-containing reagent and is free of noble gases and oxygen. 13 . The method of claim 12 , wherein forming the etch stop layer comprises forming the metal oxide by an atomic layer deposition (ALD) process.

14. The method of claim 12, wherein the metal oxide is selected from the group consisting of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, vanadium oxide, and tantalum oxide.

15. The method of claim 12, wherein the metal layer comprises a metal selected from the group consisting of platinum, gold, iridium, silver, palladium, rhodium, ruthenium, rhenium nickel, aluminum, and copper.

16. The method of claim 12, further comprising removing the etch stop layer in the etch region. 17 . The method of claim 12 , further comprising removing a portion of the first dielectric layer such that the etch region extends below the etch stop layer.

18. The method of claim 12, further comprising forming a wire bond through the etch stop layer to the metal layer in the etch region.

19. A microelectronic device comprising: Dielectric layer; a bonding pad over the dielectric layer, the bonding pad comprising a surface layer comprising platinum; an etch stop layer on the dielectric layer and the bonding pad, the etch stop layer comprising aluminum oxide, the etch stop layer having a thickness of less than 10 nanometers; a protective overcoat layer on the etch stop layer, wherein the protective overcoat layer includes an opening over the bond pad; as well as A wire bond extends through the etch stop layer to the bond pad and contacts the etch stop layer.

20. A method of forming a microelectronic device, comprising: forming a dielectric layer; forming a bond pad over the dielectric layer, the bond pad comprising platinum; forming an etch stop layer on the dielectric layer and the bonding pad, the etch stop layer comprising aluminum oxide formed by atomic layer deposition, the etch stop layer having a thickness of less than 10 nanometers; forming a protective overcoat layer on the etch stop layer; plasma etching an opening in the protective overcoat layer over the bond pad, the opening exposing the etch stop layer, the plasma etching using a fluorine-containing reagent and being free of noble gases and oxygen; and With the etch stop layer covering the bond pad, a wire bond is formed through the etch stop layer to the bond pad.

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