A protection circuit and method for railway products or non-type flash memory

Abstract

The present invention relates to the field of digital circuit design, and more specifically, to a protection circuit and method for a railway product NOR Flash memory. The protection circuit for a railway product NOR Flash memory proposed by the present invention includes a central processing unit, which is connected to a NOR Flash memory and a programmable logic device, reads and writes data to the NOR Flash memory, sends configuration instructions and / or work instructions to the NOR Flash memory, and sends control instructions to the programmable logic device; the programmable logic device is connected to the central processing unit and the NOR Flash memory, receives the control instructions of the central processing unit, and sends reset and / or write protection instructions to the NOR Flash memory according to the control instructions of the central processing unit. The railway product NOR Flash protection circuit and method proposed by the present invention improve the anti-interference ability of the NOR Flash, protect the integrity of key data, and thus improve the stability and reliability of the product.

Description

Technical Field

[0001] The present invention relates to the field of digital circuit design, and more specifically to a protection circuit and method for railway products or non-flash memory. Background Art

[0002] NOR Flash (or non-volatile flash memory) is a non-volatile flash memory technology created by Intel in 1988. In railway locomotive electronic products, NOR Flash plays a very important role and is a very important data and program carrier. It can be used to store Boot Loader system startup code, kernel, file system and application program, and can also be used as a medium for storing key information parameters and important data.

[0003] The partitions in NOR flash store the core data of the device or system. Whether the data stored in it can be read and written normally is directly related to the reliability and availability of the entire device and even the system.

[0004] The NOR Flash circuit of traditional railway locomotive electronic products is relatively simple, and in many cases, there is no hardware circuit protection for NOR Flash. Once the important data stored in NOR Flash is damaged, it will endanger the safety of the entire system.

[0005] In actual product use, the key data stored in NOR Flash may be lost, tampered, illegally accessed, etc. due to the lack of data protection function, which may eventually cause the system to fail to operate. Even the system cannot start after power-on or reset due to the loss or tampering of the boot code in NOR Flash, and it is completely paralyzed.

[0006] If a problem occurs in the NOR Flash that lacks effective protection, the system cannot start and the equipment fails. The equipment can only be returned to the factory for repair, which causes a huge waste of manpower and material resources, and there are uncertain risks in the equipment.

[0007] The NOR Flash protection method and circuit in the prior art generally adopt the following two solutions:

[0008] One is to control whether to perform write protection control on NOR Flash by using a jumper sleeve connected to the write protection control pin of NOR Flash. The jumper sleeve is a conductor. When connected to two pins, the pin circuit is short-circuited. When removed, the two pin circuits are disconnected.

[0009] The second is to connect a resistor-capacitor circuit to the write protection control pin of the NOR Flash to achieve the purpose of write protection during the startup process by delaying the reset.

[0010] In the above solution 1, manual operation of the circuit board is required, which has certain risks and is very inconvenient in the later maintenance stage, especially when used on some equipment that disassembles and assembles the circuit board;

[0011] In the above solution 2, the NOR Flash after the device is powered on cannot be protected, and there is a risk that the NOR Flash protection is not in place and the data is modified. Summary of the invention

[0012] The purpose of the present invention is to provide a protection circuit and method for railway products or NOR flash memory, so as to solve the problems of low protection degree and poor anti-interference ability of NOR Flash in the prior art.

[0013] In order to achieve the above object, the present invention provides a protection circuit for railway products or non-type flash memory, including a central processing unit and a programmable logic device:

[0014] The central processing unit is connected to the NOR-type flash memory and the programmable logic device, reads and writes data to the NOR-type flash memory, sends configuration instructions and / or work instructions to the NOR-type flash memory, and sends control instructions to the programmable logic device;

[0015] The programmable logic device is connected to the central processing unit and the NOR type flash memory, receives the control instruction of the central processing unit, and sends a reset and / or write protection instruction to the NOR type flash memory according to the control instruction of the central processing unit.

[0016] In one embodiment, the protection circuit is in an overall powered-on state:

[0017] The programmable logic device outputs a write protection enable signal and a reset enable signal to a write protection pin and a reset pin of the NOR type flash memory, and controls the NOR type flash memory to work in a write protection state and a reset state.

[0018] In one embodiment, the protection circuit is in a boot program loading state:

[0019] The programmable logic device outputs a write protection enable signal to a write protection pin of the NOR type flash memory, so as to control the NOR type flash memory to work in a write protection state;

[0020] The programmable logic device outputs a reset disable signal to a reset pin of the NOR type flash memory, and controls the NOR type flash memory to work in a reset disable state.

[0021] In one embodiment, the protection circuit is in a content update state:

[0022] The central processing unit outputs a chip selection signal to the NOR-type flash memory to select the corresponding NOR-type flash memory;

[0023] The central processing unit outputs a write enable signal to the NOR type flash memory to control the NOR type flash memory to work in a write state;

[0024] The programmable logic device outputs a write protection disable signal to the write protection pin of the NOR type flash memory according to the control instruction of the central processing unit, and controls the NOR type flash memory to work in a write protection disable state;

[0025] The central processing unit performs a write-modify operation on the data content of the NOR-type flash memory.

[0026] In one embodiment, the programmable logic device is a parallel port device, and the NOR type flash memory is a parallel port device.

[0027] In one embodiment, the programmable logic device is a field programmable gate array.

[0028] In one embodiment, the programmable logic device is connected to the central processing unit via a parallel bus.

[0029] In order to achieve the above object, the present invention provides a method for protecting a railway product or non-type flash memory, comprising the following steps:

[0030] S1, the protection circuit is powered on as a whole, and the programmable logic device outputs a write protection enable signal and a reset enable signal to the write protection pin and reset pin of the NOR type flash memory, and controls the NOR type flash memory to work in the write protection state and the reset state;

[0031] S2, determine whether the protection circuit loads the boot program normally, if yes, proceed to step S3;

[0032] S3, the protection circuit loads the boot program, the programmable logic device outputs a write protection enable signal to the write protection pin of the NOR type flash memory, controls the NOR type flash memory to work in a write protection state, and the programmable logic device outputs a reset disable signal to the reset pin of the NOR type flash memory, controls the NOR type flash memory to work in a reset disable state;

[0033] S4, determine whether the protection circuit loads the operating system and application program normally, if yes, proceed to step S5;

[0034] S5. The protection circuit operates normally, the programmable logic device outputs a write protection enable signal to the write protection pin of the NOR type flash memory, and controls the NOR type flash memory to work in a write protection state. The programmable logic device outputs a reset disable signal to the reset pin of the NOR type flash memory, and controls the NOR type flash memory to work in a reset disabled state.

[0035] In one embodiment, the step S2 further includes determining whether the protection circuit loads the boot program normally, if not, proceeding to step S6;

[0036] The step S6, updating the boot program of the protection circuit, comprises the following steps:

[0037] S601, the central processing unit outputs a chip selection signal to the NOR type flash memory to select the corresponding NOR type flash memory;

[0038] S602, the central processing unit outputs a write enable signal to the NOR type flash memory to control the NOR type flash memory to work in a write state;

[0039] S603, the programmable logic device outputs a write protection disable signal to the write protection pin of the NOR type flash memory according to the control instruction of the central processing unit, and controls the NOR type flash memory to work in a write protection disable state;

[0040] S604, the programmable logic device outputs a reset disable signal to the reset pin of the NOR type flash memory according to the control instruction of the central processing unit, and controls the NOR type flash memory to work in a reset disabled state;

[0041] S605: The central processing unit performs a write-modification operation on the boot program of the NOR-type flash memory.

[0042] In one embodiment, the step S4 further includes determining whether the protection circuit loads the operating system and the application program normally, if not, proceeding to step S7;

[0043] The step S7, in which the protection circuit updates the operating system or application, comprises the following steps:

[0044] S701, the central processing unit outputs a chip selection signal to the NOR type flash memory to select the corresponding NOR type flash memory;

[0045] S702, the central processing unit outputs a write enable signal to the NOR type flash memory to control the NOR type flash memory to work in a write state;

[0046] S703, the programmable logic device outputs a write protection disable signal to the reset pin of the NOR type flash memory according to the control instruction of the central processing unit, and controls the NOR type flash memory to work in a write protection disable state;

[0047] S704, the programmable logic device outputs a reset disable signal to the reset pin of the NOR type flash memory according to the control instruction of the central processing unit, and controls the NOR type flash memory to work in a reset disabled state;

[0048] S705: The central processing unit performs a write-modification operation on the operating system or application program of the NOR-type flash memory.

[0049] The railway product NOR Flash protection circuit and method proposed in the present invention have the following beneficial effects:

[0050] 1) Write protection control is performed on NOR Flash during the entire cycle of product startup, operation, and data modification, and the NOR Flash device is protected when no write operation is required on the NOR Flash;

[0051] 2) When the NOR Flash data needs to be updated, it is controlled by the FPGA device without human intervention, which is very convenient for updating application programs during equipment production debugging and after-sales process. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The above and other features, properties and advantages of the present invention will become more apparent through the following description in conjunction with the accompanying drawings and embodiments, in which the same reference numerals always represent the same features, wherein:

[0053] Figure 1 A schematic diagram of the principle of a protection circuit for a railway product or non-flash memory according to an embodiment of the present invention is disclosed;

[0054] Figure 2 A flow chart of a method for protecting a railway product or non-flash memory according to an embodiment of the present invention is disclosed. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the invention and are not used to limit the invention.

[0056] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0057] The present invention proposes a NOR flash protection circuit and method for railway locomotive electronic products, realizing a reliable write protection strategy for NOR flash and improving the reliability and stability of equipment and systems.

[0058] In view of the defects existing in the prior art, the present invention provides a protection method and circuit for NOR Flash specifically for railway locomotive electronic products, which improves the anti-interference ability of NOR Flash and protects the integrity of key data, thereby improving the stability and reliability of the product. The present invention is applicable to NOR Flash including a write protection control pin and a reset pin.

[0059] The present invention provides a railway product NOR Flash protection circuit, comprising a central processing unit and a programmable logic device:

[0060] The central processing unit is connected to the NOR-type flash memory and the programmable logic device, reads and writes data to the NOR-type flash memory, sends configuration instructions and / or work instructions to the NOR-type flash memory, and sends control instructions to the programmable logic device;

[0061] The programmable logic device is connected to the central processing unit and the NOR type flash memory, receives the control instruction of the central processing unit, and sends a reset and / or write protection instruction to the NOR type flash memory according to the control instruction of the central processing unit.

[0062] The present invention adopts software to control NOR Flash write protection, and also adds hardware write protection logic circuit, that is, programmable logic device. Software write protection is a method of software control instruction, which refers to a method of writing protection of NOR Flash input control instruction through CPU chip.

[0063] In the NOR Flash protection circuit provided by the present invention, the programmable logic device can be a field programmable gate array (FPGA) or a complex programmable logic device (CPLD).

[0064] FPGA (Field Programmable Gate Array) emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASICs), which not only solves the shortcomings of custom circuits, but also overcomes the disadvantage of the limited number of gate circuits of the original programmable devices.

[0065] Optionally, the FPGA chip may be a Virtex series chip from Xilinx.

[0066] CPLD (Complex Programmable Logic Device) belongs to the category of large-scale integrated circuits. It is a digital integrated circuit in which users construct their own logical functions according to their needs.

[0067] Optionally, the CPLD chip may be an EPM7128S device.

[0068] exist Figure 1In the illustrated embodiment, the programmable logic device specifically adopts a field programmable gate array (FPGA), and the central processing unit specifically adopts a CPU chip.

[0069] Figure 1 The schematic diagram of the protection circuit of a railway product or non-flash memory according to an embodiment of the present invention is disclosed. Figure 1 As shown, the present invention proposes a protection circuit for NOR Flash of railway products, including a CPU chip and an FPGA chip:

[0070] The CPU chip is a core control device, which is connected to the NOR Flash and FPGA chip, reads and writes data from the NOR Flash, issues configuration instructions and work instructions to the NOR Flash, and sends control instructions to the FPGA chip.

[0071] Connect the chip select signal CS0 of NOR Flash to the pin of CPU chip, and connect the write enable WE and read enable RD signals on the parallel bus of NOR Flash to the pin of CPU chip;

[0072] The FPGA chip is a core control device, connected to the NOR Flash and the CPU chip, receives control instructions from the CPU chip, and sends reset and / or write protection instructions to the NOR Flash according to the control instructions from the CPU chip.

[0073] Connect the write enable WE and read enable RD signals on the NOR Flash parallel bus to the FPGA chip pins;

[0074] The FPGA chip is also connected to the CPU chip parallel bus through a parallel bus, as another parallel port device, and CS1 serves as the chip select signal of the FPGA chip.

[0075] Furthermore, NOR Flash is a parallel port device and FPGA chip is a parallel port device.

[0076] The FPGA chip outputs two control signals to control the operation of the NOR Flash chip:

[0077] The write protection enable WP signal of the FPGA chip is connected to the write protection pin of the NOR Flash to control the NOR Flash to work in the write protection state;

[0078] The reset enable RESET signal of the FPGA chip is connected to the reset pin of the NOR Flash to control the NOR Flash to work in the reset state.

[0079] When the write protection pin of NOR Flash receives the write protection signal, it will not allow write operations to the protected BLOCK in NOR Flash. BLOCK can generally be set through configuration.

[0080] The RESET pin of NOR Flash will not work after receiving the reset signal, and the device will not be allowed to read or write, thereby protecting critical data from being tampered with.

[0081] The protection circuit of the invention can effectively protect each working state of NOR Flash. The following is a detailed description of each working stage of the specific embodiment.

[0082] 1) The protection circuit is in the overall power-on state

[0083] When the entire device system is started, the CPU and some circuit states are not completely stable, some key signal levels are not established, and the data stored in the NOR Flash may be modified.

[0084] The boot process is often when the FLASH is easily damaged. Therefore, during the power-on process of the protection circuit, the write protection enable WP signal from the FPGA chip to the NOR Flash is low, and the NOR Flash is in a write protection state.

[0085] At the same time, the FPGA chip gives the NOR Flash control logic signal a reset enable signal RESET, controlling the NOR Flash to always work in a reset and data-unwritten protection state, ensuring that the NOR Flash data is stable and not modified.

[0086] 2) The protection circuit is in the boot program loading state

[0087] After the delay of the reset enable signal RESET sent by the FPGA chip to the control logic signal of the NOR Flash, the FPGA chip sends a reset disable signal to the control logic signal of the NOR Flash, and the NOR Flash recovers to the reset disable state and starts working;

[0088] The write protection enable WP signal from the FPGA chip to the NOR Flash is still at a low level, and the NOR Flash is in a write protection state. At this time, the data in the NOR Flash can only be read but not written, so it will not affect the startup of the device system.

[0089] After the core of the entire CPU chip is started, that is, in normal operation, the FPGA chip always outputs a low-level write protection enable WP to the write protection pin of NORFlash.

[0090] 3) The protection circuit is in the content update state

[0091] When the data content in the NOR Flash needs to be updated, the protection circuit performs the following actions:

[0092] The CPU chip outputs the chip select signal to the NOR Flash, pulls the CS0 chip select signal of the NOR Flash low, and selects the corresponding NOR Flash;

[0093] The CPU chip outputs a write enable signal WE to the NOR Flash, pulls the WE signal low, and controls the NOR Flash to work in the write state;

[0094] After the FPGA chip obtains the bus control instruction from the CPU to the NOR Flash, it outputs a write protection disable signal to the NOR Flash, pulls up the write protection pin level of the NOR Flash, and releases the write protection state;

[0095] After the FPGA chip obtains the bus control instruction from the CPU to the NOR Flash, it outputs a reset disable signal to the NORFlash, pulls the reset pin level of the NOR Flash high, and releases the reset state;

[0096] The CPU chip writes and modifies the data content in the NOR Flash, wherein the data content includes: the underlying uboot, the kernel file system, or the application program.

[0097] The protection circuit of the present invention uses an FPGA chip to control the write protection and reset of NOR Flash, instead of directly using a CPU chip to control NOR Flash, because the CPU chip is a von Neumann structure, and it decodes and executes instructions, and it also has an operating system, and the stability time after startup is relatively long. The FPGA chip is a programmable logic gate circuit, has no instructions, and starts faster and more stably. NOR Flash is the easiest to be tampered with during the power on and off process, therefore, the FPGA chip can better protect NOR Flash than the CPU chip during the power on and off process.

[0098] Furthermore, since the FPGA chip may be unstable during the power-on process, the protection circuit of the present invention has a default write protection enabled, that is, the write protection pin is pulled low by the default pull-down resistor.

[0099] Figure 2 A flowchart of a method for protecting a railway product or non-flash memory according to an embodiment of the present invention is disclosed. Figure 2 In the illustrated embodiment, the programmable logic device specifically adopts a field programmable gate array (FPGA), and the central processing unit specifically adopts a CPU chip.

[0100] like Figure 2 As shown, the protection method of railway product NOR Flash proposed by the present invention comprises the following steps:

[0101] S1. The protection circuit is powered on as a whole. The FPGA chip outputs a write protection enable signal and a reset enable signal to the write protection pin and reset pin of the NOR Flash, controls the NOR Flash to work in the write protection state and the reset state, and the NOR Flash write protection pin is pulled down to the ground by a resistor. The FPGA controls the NOR Flash write protection pin to output a low level when powered on.

[0102] S2, determine whether the protection circuit loads the boot program normally, if yes, proceed to step S3;

[0103] S3, the protection circuit loads the boot program, the FPGA chip outputs a write protection enable signal to the write protection pin of the NOR Flash, and controls the NOR Flash to work in a write protection state, and the FPGA chip outputs a reset disable signal to the reset pin of the NOR Flash, and controls the NOR Flash to work in a reset disable state;

[0104] S4, determine whether the protection circuit loads the operating system and application program normally, if yes, proceed to step S5;

[0105] S5: The protection circuit operates normally, and the FPGA chip outputs a write protection enable signal to the write protection pin of the NOR Flash, controlling the NOR Flash to operate in a write protection state.

[0106] The step S2 further includes determining whether the protection circuit loads the boot program normally, if not, proceeding to step S6;

[0107] The step S6, updating the boot program of the protection circuit, comprises the following steps:

[0108] S601, the CPU chip outputs a chip select signal to the NOR Flash, and selects the corresponding NOR Flash;

[0109] S602, the CPU chip outputs a write enable signal to the NOR Flash to control the NOR Flash to work in a write state;

[0110] S603, the FPGA chip outputs a write protection disable signal to the write protection pin of the NOR Flash according to the control instruction of the CPU chip, and controls the NOR Flash to work in a write protection disable state;

[0111] S604, the FPGA chip outputs a reset disable signal to the reset pin of the NOR Flash according to the control instruction of the CPU chip, and controls the NOR Flash to work in a reset disable state;

[0112] S605, the CPU chip writes and modifies the boot program of the NOR Flash. The boot program includes data such as environment variables.

[0113] The step S4 further includes determining whether the protection circuit loads the operating system and the application program normally, if not, proceeding to step S7;

[0114] The step S7, in which the protection circuit updates the operating system or application, comprises the following steps:

[0115] S701, the CPU chip outputs a chip select signal to the NOR Flash, and selects the corresponding NOR Flash;

[0116] S702, the CPU chip outputs a write enable signal to the NOR Flash to control the NOR Flash to work in a write state;

[0117] S703, the FPGA chip outputs a write protection disable signal to the reset pin of the NOR Flash according to the control instruction of the CPU chip, and controls the NOR Flash to work in a write protection disable state;

[0118] S704, the FPGA chip outputs a reset disable signal to the reset pin of the NOR Flash according to the control instruction of the CPU chip, and controls the NOR Flash to work in a reset disable state;

[0119] S705: The CPU chip writes and modifies the operating system or application program of the NOR Flash.

[0120] The present invention proposes a railway product NOR Flash protection circuit and method, which utilizes an FPGA programmable logic device to control a write protection pin and a reset pin of the NOR Flash. The circuit modification is simple and the logic implementation is also easy to implement. The shortcomings of the traditional solution using a jumper sleeve and a resistor and capacitor are improved. The jumper sleeve is not used, which reduces the repeated operations of the operator and the risk of the jumper sleeve falling on the locomotive. At the same time, the anti-interference ability of the NOR Flash is improved, and the integrity of key data is protected, thereby improving the stability and reliability of the product.

[0121] The railway product NOR Flash protection circuit and method proposed in the present invention have the following beneficial effects:

[0122] 1) Write protection control is performed on NOR Flash during the entire cycle of product startup, operation, and data modification, and the NOR Flash device is protected when no write operation is required on the NOR Flash;

[0123] 2) When the NOR Flash data needs to be updated, it is controlled by the FPGA device without human intervention, which is very convenient for updating application programs during equipment production debugging and after-sales process.

[0124] Although the above methods are illustrated and described as a series of actions for simplicity of explanation, it should be understood and appreciated that these methods are not limited by the order of the actions, because according to one or more embodiments, some actions may occur in a different order and / or concurrently with other actions from those illustrated and described herein or not illustrated and described herein but understandable to those skilled in the art.

[0125] As shown in this application and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and / or "the" do not refer to the singular and may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0126] The above embodiments are provided for persons familiar with the art to implement or use the present invention. Persons familiar with the art can make various modifications or changes to the above embodiments without departing from the inventive concept of the present invention. Therefore, the protection scope of the present invention is not limited to the above embodiments, but should be the maximum scope of the innovative features mentioned in the claims.

Claims

1. A protection circuit for railway products or non-flash memory, characterized in that, Including central processing unit and programmable logic device: The central processing unit is connected to the NOR-type flash memory and the programmable logic device, reads and writes data to the NOR-type flash memory, sends configuration instructions and / or work instructions to the NOR-type flash memory, and sends control instructions to the programmable logic device; The programmable logic device is connected to the central processing unit and the NOR-type flash memory, receives the control instruction of the central processing unit, and sends a reset and / or write protection instruction to the NOR-type flash memory according to the control instruction of the central processing unit; Among them, the protection circuit is in the content update state: The central processing unit outputs a chip selection signal to the NOR-type flash memory to select the corresponding NOR-type flash memory; The central processing unit outputs a write enable signal to the NOR type flash memory to control the NOR type flash memory to work in a write state; The programmable logic device outputs a write protection disable signal to the write protection pin of the NOR type flash memory according to the control instruction of the central processing unit, and controls the NOR type flash memory to work in a write protection disable state; The central processing unit performs a write-modify operation on the data content of the NOR-type flash memory.

2. The protection circuit of railway products or non-type flash memory according to claim 1, characterized in that: The protection circuit is in the overall powered-on state: The programmable logic device outputs a write protection enable signal and a reset enable signal to a write protection pin and a reset pin of the NOR type flash memory, and controls the NOR type flash memory to work in a write protection state and a reset state.

3. The protection circuit of railway products or non-type flash memory according to claim 1, characterized in that: The protection circuit is in the boot program loading state: The programmable logic device outputs a write protection enable signal to a write protection pin of the NOR type flash memory, so as to control the NOR type flash memory to work in a write protection state; The programmable logic device outputs a reset disable signal to a reset pin of the NOR type flash memory, and controls the NOR type flash memory to work in a reset disable state.

4. The protection circuit of railway products or non-type flash memory according to claim 1, characterized in that: The programmable logic device is a parallel port device, and the NOR type flash memory is a parallel port device.

5. The protection circuit of railway products or non-type flash memory according to claim 1, characterized in that: The programmable logic device is a field programmable gate array.

6. A method for protecting a railway product or non-type flash memory, characterized in that: The following steps are involved: S1, the protection circuit is powered on as a whole, and the programmable logic device outputs a write protection enable signal and a reset enable signal to the write protection pin and reset pin of the NOR type flash memory, and controls the NOR type flash memory to work in the write protection state and the reset state; S2, determine whether the protection circuit loads the boot program normally, if yes, proceed to step S3; S3, the protection circuit loads the boot program, the programmable logic device outputs a write protection enable signal to the write protection pin of the NOR type flash memory, controls the NOR type flash memory to work in a write protection state, and the programmable logic device outputs a reset disable signal to the reset pin of the NOR type flash memory, controls the NOR type flash memory to work in a reset disable state; S4, determine whether the protection circuit loads the operating system and application program normally, if yes, proceed to step S5; S5, the protection circuit operates normally, the programmable logic device outputs a write protection enable signal to the write protection pin of the NOR type flash memory, and controls the NOR type flash memory to work in a write protection state; Wherein, the step S4 further includes determining whether the protection circuit loads the operating system and the application program normally, if not, proceeding to step S7; The step S7, in which the protection circuit updates the operating system or application, comprises the following steps: S701, the central processing unit outputs a chip selection signal to the NOR type flash memory to select the corresponding NOR type flash memory; S702, the central processing unit outputs a write enable signal to the NOR type flash memory to control the NOR type flash memory to work in a write state; S703, the programmable logic device outputs a write protection disable signal to the reset pin of the NOR type flash memory according to the control instruction of the central processing unit, and controls the NOR type flash memory to work in a write protection disable state; S704, the programmable logic device outputs a reset disable signal to the reset pin of the NOR type flash memory according to the control instruction of the central processing unit, and controls the NOR type flash memory to work in a reset disabled state; S705: The central processing unit performs a write-modification operation on the operating system or application program of the NOR-type flash memory.

7. The method for protecting railway products or non-type flash memory according to claim 6, characterized in that: The step S2 further includes determining whether the protection circuit loads the boot program normally, if not, proceeding to step S6; The step S6, updating the boot program of the protection circuit, comprises the following steps: S601, the central processing unit outputs a chip selection signal to the NOR type flash memory to select the corresponding NOR type flash memory; S602, the central processing unit outputs a write enable signal to the NOR type flash memory to control the NOR type flash memory to work in a write state; S603, the programmable logic device outputs a write protection disable signal to the write protection pin of the NOR type flash memory according to the control instruction of the central processing unit, and controls the NOR type flash memory to work in a write protection disable state; S604, the programmable logic device outputs a reset disable signal to the reset pin of the NOR type flash memory according to the control instruction of the central processing unit, and controls the NOR type flash memory to work in a reset disabled state; S605: The central processing unit performs a write-modification operation on the boot program of the NOR-type flash memory.

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