Gate drive circuit and gate driver

Abstract

The present application provides a gate drive circuit and a gate driver, wherein the gate drive circuit includes an N-level sub-drive circuit, wherein the N-level sub-drive circuit includes: a pull-up control module, a pull-down module, and a high-level module, wherein the transistor in the pull-up control module is a low-temperature polysilicon transistor, and the transistor in the pull-down module is a metal oxide transistor. The present application utilizes the high mobility of the low-temperature polysilicon transistor to enhance the driving capability of the N-level sub-drive circuit, because the leakage current of the low-temperature polysilicon transistor is large, in order to avoid the problem of high power consumption and low charging efficiency caused by the N-level sub-drive circuit being charged and discharged at the same time, the transistor in the pull-down module of the present application is a metal oxide transistor, because the leakage current of the metal oxide transistor is small, so the transistor in the pull-down module can be completely turned off to improve the charging efficiency and reduce the power consumption.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of liquid crystal displays, and in particular to a gate driving circuit and a gate driver. Background Art

[0002] The gate driver on array (GOA) is a gate driver circuit integrated on the thin film transistor (TFT) array, which is used to drive the gate signal line (Gate line) to scan line by line. GOA has the advantages of saving gate ICs, and has been widely used in panel design. As the size of display panels continues to increase, the load resistance and capacitance of the gate scan line also increase, and the delay of the gate signal becomes serious. The driving capability of the GOA circuit is particularly important.

[0003] The current technical solution can enhance the driving capability of the GOA circuit by increasing the size of the TFT, but the size of the TFT is limited by the allowable size of the panel, and the increase in the size of the TFT will also cause an increase in the parasitic capacitance in the gate drive circuit, thereby increasing the power consumption of the gate drive circuit and affecting the quality of the output signal of the gate drive circuit. Summary of the invention

[0004] The embodiments of the present application provide a gate driving circuit and a gate driver, which can improve the driving capability of a GOA circuit.

[0005] In a first aspect, an embodiment of the present application provides a gate drive circuit, which includes N levels of sub-drive circuits, and the Nth level sub-drive circuit includes: a pull-up control module, a pull-down module and a high-level module, the pull-up control module is connected to the N-2th level sub-drive circuit or the initial signal source, the pull-up control module is also connected to the pull-down module and the pull-up PU signal point of the Nth level sub-drive circuit, the pull-down module is connected to the high-level module, and N is an integer greater than or equal to 3; wherein the transistor in the pull-up control module is a low-temperature polysilicon transistor, and the transistor in the pull-down module is a metal oxide transistor.

[0006] In a possible implementation, the N-2th stage sub-driving circuit or the initial signal source is used to output a low-level signal.

[0007] In a possible implementation, the pull-up control module includes a first low-temperature polysilicon transistor, the pull-down module includes a first metal oxide transistor, the gate drive circuit further includes a high-level module, and the Nth-stage sub-drive circuit further includes: a first clock signal generator;

[0008] The gate and source of the first low-temperature polysilicon transistor are both connected to the N-2th sub-driving circuit or the initial signal source, the drain of the first low-temperature polysilicon transistor is respectively connected to the source of the first metal oxide transistor and the pull-up PU signal point of the Nth sub-driving circuit, the gate of the first metal oxide transistor is connected to the first clock signal generator, and the drain of the first metal oxide transistor is connected to the high-level module.

[0009] In a possible implementation, the Nth stage sub-driving circuit further includes: a horizontal scan line, and the pull-down module further includes a second metal oxide transistor;

[0010] The gate of the second metal oxide transistor is connected to the first clock signal generator, the source of the second metal oxide transistor is connected to the horizontal scan line, and the drain of the second metal oxide transistor is connected to the high level module.

[0011] In a possible implementation, the Nth-stage sub-driving circuit further includes: a pull-up module, the pull-up module is connected to the pull-up control module; and the transistor in the pull-up module is a low-temperature polysilicon transistor.

[0012] In a possible implementation, the pull-up module includes: a second low-temperature polysilicon transistor, and the Nth-stage sub-driving circuit further includes: a second clock signal generator;

[0013] The gate of the second low-temperature polysilicon transistor is connected to the PU signal point of the N-th sub-driving circuit, the source of the second low-temperature polysilicon transistor is connected to the second clock signal generator, and the drain of the second low-temperature polysilicon transistor is connected to the horizontal scan line of the N-th sub-driving circuit.

[0014] In a possible implementation, the Nth stage sub-driving circuit further includes: a pull-down maintaining module, the pull-down maintaining module is connected to the pull-up module and the pull-down module respectively, and the transistor in the pull-down maintaining module is a low-temperature polysilicon transistor.

[0015] In a possible implementation, the Nth stage sub-driving circuit further includes: a pull-down maintaining module, the pull-down maintaining module is connected to the pull-up module and the pull-down module respectively, and the transistor in the pull-down maintaining module is a metal oxide transistor.

[0016] In a possible implementation, the pull-down maintenance module includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, and the Nth-stage sub-driving circuit also includes: a third clock signal generator, a fourth clock signal generator and a bootstrap capacitor;

[0017] The gate of the first transistor and the source of the first transistor are connected to the third clock signal generator, the source of the first transistor and the source of the second transistor are connected to the pull-down PD signal point of the N-th sub-driving circuit, the gate of the second transistor is connected to the PU signal point of the N-th sub-driving circuit, the drain of the second transistor is connected to the high-level module, the gate of the third transistor is connected to the PD signal point, the source of the third transistor is connected to the PU signal point, the drain of the third transistor is connected to the high-level module, the gate of the fourth transistor is connected to the gate of the third transistor, the source of the fourth transistor is connected to the horizontal scan line of the N-th sub-driving circuit, and the drain of the fourth transistor is connected to the high-level module. The gate of the fifth transistor is connected to the fourth clock signal generator, the source of the fifth transistor is connected to the PD signal point, the drain of the fifth transistor is connected to the high level module, the gate of the sixth transistor is connected to the gate of the seventh transistor, and the gate of the sixth transistor and the gate of the seventh transistor are both connected to the reset point Reset of the Nth level sub-driving circuit, the source of the sixth transistor is connected to the PU signal point, the drain of the sixth transistor is connected to the high level module, the source of the seventh transistor is connected to the horizontal scan line, the drain of the seventh transistor is connected to the high level module, the first end of the bootstrap capacitor is connected to the PU signal point, and the second end of the bootstrap capacitor is connected to the horizontal scan line.

[0018] In a second aspect, an embodiment of the present application provides a gate driver, which may include the gate driving circuit in the above-mentioned first aspect and various possible implementations.

[0019] In a third aspect, an embodiment of the present application provides a display, which may include the gate driver of the second aspect described above.

[0020] The embodiment of the present application provides a gate drive circuit and a gate driver. The embodiment of the present application utilizes the advantages of the high mobility of the low-temperature polysilicon transistor to enhance the driving capability of the N-th level sub-drive circuit. Because the leakage current of the low-temperature polysilicon transistor is large, in order to prevent the N-th level sub-drive circuit from charging and discharging at the same time, resulting in high power consumption and low charging efficiency, the transistor in the pull-down module in the embodiment of the present application is a metal oxide transistor. Because the leakage current of the metal oxide transistor is small, the transistor in the pull-down module can be completely turned off, thereby improving the charging efficiency and reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0022] Figure 1 A schematic diagram of a structure of an N-th stage sub-driving circuit provided in an embodiment of the present application;

[0023] Figure 2 Another structural schematic diagram of the Nth stage sub-driving circuit provided in an embodiment of the present application;

[0024] Figure 3 Another structural schematic diagram of the Nth stage sub-driving circuit provided in an embodiment of the present application;

[0025] Figure 4 Another structural schematic diagram of the Nth stage sub-driving circuit provided in an embodiment of the present application.

[0026] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the embodiments of the present application.

[0028] The embodiments of the embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the embodiments of the present application, and cannot be understood as limiting the embodiments of the present application. In addition, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the embodiments of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly defined and specifically defined. In the embodiments of the present application, unless otherwise clearly defined and defined, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection; it can be directly connected, or it can be indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined.

[0029] In the description of the embodiments of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradicting each other.

[0030] LED stands for light-emitting diode (LED). LED display can include a backlight and a liquid crystal display. The backlight can emit light according to the light-emitting diode set thereon, and then serve as the backlight source of the liquid crystal display. The structure of the LED display is complicated. Because the material itself does not emit light, it is necessary to use the backlight to achieve light emission. If the display screen of the LED display is to be displayed as black, it is necessary to block the light through the movement of the liquid crystal molecules in the liquid crystal display, but there is always some light that will leak out, which will cause the liquid crystal display to turn gray when displaying a pure black picture, thereby causing light leakage. Compared with LED displays, organic light-emitting diode (OLED) displays do not have the above problems. OLED displays emit light by driving organic thin films with current. The organic thin films in OLED displays can emit light, so OLED displays do not need to set up additional backlight sources, which can simplify the structure of OLED displays. In addition, OLED displays can realize direct control of each pixel point, so the light emission of the pixel point can be directly turned off, so when displaying a pure black picture, it is pure black and will not leak light. And OLED has great advantages over LED in preparing flexible display screens, so OLED is rapidly developing in the display field. It should be understood that the gate driving circuit in the embodiment of the present application can be applied to OLED displays or other displays that require improved driving capabilities.

[0031] In order to enhance the driving capability of the GOA circuit, an embodiment of the present application provides a gate drive circuit, which improves the driving capability of the GOA circuit by adopting a low-temperature polysilicon transistor with high mobility in the pull-up control module of the gate drive circuit. At the same time, in order to prevent the high power consumption of the low-temperature polysilicon transistor due to leakage current, a metal oxide transistor with low leakage current can be used in the pull-down module of the gate drive circuit to reduce the leakage current of the gate drive circuit, thereby reducing power consumption. The low-temperature polysilicon transistor itself has the advantage of a low aspect ratio, so the area occupied by the gate drive circuit can be reduced to achieve a narrow border of the display screen.

[0032] The gate drive circuit provided in the embodiment of the present application is described below in conjunction with specific embodiments. The following embodiments can be combined with each other, and the same concepts will not be described in detail. It should be understood that the gate drive circuit in the embodiment of the present application may include N-level sub-drive circuits in cascade. The manner in which the N-level sub-drive circuits are cascaded is not described in detail here. For details, please refer to the relevant description of the current technical solution. In the embodiment of the present application, each level of sub-drive circuit is described by taking the N-th level sub-drive circuit in the N-level sub-drive circuit as an example. It should be understood that the structure of each level of sub-drive circuit can be the same. Among them, the N-th level sub-drive circuit can be connected to the initial signal source or the upper-level sub-drive circuit. In the embodiment of the present application, the N-th level sub-drive circuit is connected to the initial signal source or the N-2-th level sub-drive circuit as an example for description.

[0033] Figure 1 A schematic diagram of the structure of the Nth stage sub-driving circuit provided in the embodiment of the present application. Figure 1 As shown, the N-th sub-driving circuit includes: a pull-up control module (pull-up control part), a pull-down module (pull-down Part) and a high-level module. In the embodiment of the present application, the pull-up control module is connected to the N-2-th sub-driving circuit or the initial signal source, and the pull-up control module is also connected to the pull-down module and the pull-up PU signal point of the N-th sub-driving circuit, and the pull-down module is connected to the high-level module. It should be understood that the PU signal point can also be called a pull-up node, which is a connection point of each module for pulling up the signal of the N-th sub-driving circuit.

[0034] The N-2-th level sub-driving circuit or the initial signal source can transmit the downlink signal or the gate Gate signal to the pull-up control module. Among them, the pull-up control module is responsible for controlling the opening time of the transistor in the pull-up module (pull-up part) in the N-th level sub-driving circuit. The pull-down module is responsible for pulling the gate of the transistor down to a low potential at the first time, that is, turning off the transistor. The high-level module is used to output a high-level signal, which can be a high voltage. The pull-up module is mainly responsible for outputting the clock signal (Clock) generated by the clock signal generator as a gate signal. The pull-up module is described in detail in the following embodiments, and the specific embodiments can be referred to in the following embodiments.

[0035] In the current technical solution, the types of transistors included in the pull-up control module and the pull-down module are the same, such as the transistors included in the pull-up control module and the pull-down module are all metal oxide semiconductor field effect transistors (metallic oxide semiconductor field effect transistors, MOSFET) (which can be referred to as metal oxide transistors), or the transistors included in the pull-up control module and the pull-down module are all low temperature polysilicon transistors (low temperature poly-silicon, LTPS TFT). Among them, because the mobility of metal oxide transistors is generally greater than 8cm2 / V·S, but it is much lower than the mobility of low temperature polysilicon transistors 80cm2 / V·S, the driving capability of low temperature polysilicon transistors is about 10 times that of metal oxide transistors. Therefore, when the transistors in the pull-up control module are metal oxide transistors, their driving capability is weak. However, if all the transistors included in the pull-up control module and the pull-down module are replaced with low temperature polysilicon transistors with high mobility, although the driving capability is stronger than that of metal oxide transistors, due to the large leakage current of low temperature polysilicon transistors, the power consumption of low temperature polysilicon transistors is large.

[0036] Therefore, in the embodiment of the present application, the transistors included in the pull-up control module and the pull-down module are a combination of low-temperature polysilicon transistors and metal oxide transistors, making full use of the advantages of the two types of transistors to improve the driving capability of the gate drive circuit without increasing the power consumption of the gate drive circuit. Among them, the transistors in the pull-up control module in the embodiment of the present application are low-temperature polysilicon transistors, and the transistors in the pull-down module are metal oxide transistors.

[0037] It should be understood that the transistor in the pull-up control module in the embodiment of the present application is a low-temperature polysilicon transistor, which can make full use of the high mobility of the low-temperature polysilicon transistor to enhance the driving ability of the N-th sub-driving circuit. When the low-temperature polysilicon transistor in the pull-up control module is in the driving circuit, if the transistor in the pull-down module is also a low-temperature polysilicon transistor, it is equivalent to the N-th sub-driving circuit being charged and discharged. In order to prevent the problem of increasing the power consumption of the N-th sub-driving circuit due to the large leakage current of the low-temperature polysilicon transistor, the transistor in the pull-down module in the embodiment of the present application is a metal oxide transistor, because the leakage current of the metal oxide transistor is small, that is, the transistor in the pull-down module can be completely turned off, thereby avoiding the problem of low charging efficiency and high power consumption caused by the N-th sub-driving circuit charging and discharging at the same time.

[0038] In view of the fact that the transistors in the pull-up module in the embodiment of the present application are low-temperature polysilicon transistors, which are P-type transistors, the N-2-stage sub-driving circuit or the initial signal source can output a low-level signal, that is, can turn on the low-temperature polysilicon transistor, and then drive the N-stage sub-driving circuit. Therefore, the N-stage sub-driving circuit in the embodiment of the present application can be driven by a low-level signal, which can further reduce the power consumption of the N-stage sub-driving circuit.

[0039] The gate drive circuit provided in the embodiment of the present application includes an N-level sub-drive circuit, and the N-level sub-drive circuit includes: a pull-up control module and a pull-down module, wherein the pull-up control module is connected to the N-2-level sub-drive circuit or the initial signal source, and the pull-up control module is also connected to the pull-down module, and N is an integer greater than or equal to 3; wherein the transistor in the pull-up control module is a low-temperature polysilicon transistor, and the transistor in the pull-down module is a metal oxide transistor. In the embodiment of the present application, the high mobility advantage of the low-temperature polysilicon transistor is utilized to enhance the driving capability of the N-level sub-drive circuit, and because the leakage current of the low-temperature polysilicon transistor is large, in order to prevent the N-level sub-drive circuit from charging and discharging at the same time, causing high power consumption and low charging efficiency, the transistor in the pull-down module in the embodiment of the present application is a metal oxide transistor, because the leakage current of the metal oxide transistor is small, that is, the transistor in the pull-down module can be completely turned off, thereby improving the charging efficiency and reducing power consumption.

[0040] Based on the above embodiments, Figure 2 Another structural diagram of the Nth stage sub-driving circuit provided in the embodiment of the present application. Figure 2 As shown, the N-th stage sub-driving circuit in the embodiment of the present application further includes: a pull-up module, the pull-up module is connected to the pull-up control module, wherein the transistor in the pull-up module is a low temperature polysilicon transistor.

[0041] It should be understood that the pull-up module in the embodiment of the present application can transmit a downlink signal to the next-level sub-drive circuit, so the pull-up module can also play the role of outputting a signal, and the pull-up module can also be called a downlink module. It is conceivable that an additional downlink module can be provided in the embodiment of the present application, and the downlink module is used to transmit a downlink signal to the next-level sub-drive circuit. In the embodiment of the present application, the pull-up module can transmit a downlink signal to the next-level sub-drive circuit as an example for explanation. Because the transistors in the pull-up module are low-temperature polysilicon transistors, because the width-to-length ratio of low-temperature polysilicon transistors can be 120:5um, which is much smaller than the width-to-length ratio of metal oxide transistors (which can be 1200:5um), the output unit (pull-up module) in the embodiment of the present application uses a low-temperature polysilicon transistor, which can effectively reduce the area of ​​the pull-up module, thereby helping to reduce the area of ​​the Nth-level sub-drive circuit, thereby helping to achieve a narrow frame of the display screen.

[0042] Among them, the N-th sub-driving circuit in the embodiment of the present application also includes a pull-down holding module (pull-down holding part) and a bootstrap capacitor (Boast). Among them, the pull-down holding module is responsible for holding the output signal of the Gate line and the Gate signal generated by the pull-up module (usually referred to as the pull-up PU signal point) in a closed state. The bootstrap capacitor is responsible for the secondary lifting of the PU signal point, which is conducive to the output of the signal of the pull-up module.

[0043] In the embodiment of the present application, the pull-down maintenance module is connected to the pull-up module and the pull-down module respectively, wherein the transistor in the pull-down maintenance module may be a low-temperature polysilicon transistor. When the transistor in the pull-down maintenance module is a low-temperature polysilicon transistor, due to the advantage of the low aspect ratio of the low-temperature polysilicon transistor, the area of ​​the transistor can be further reduced, thereby reducing the area of ​​the Nth-level sub-driving circuit. Or,

[0044] The pull-down maintenance module in the embodiment of the present application needs to have good shut-off performance to fully maintain the proper potential of the PU signal point, thereby preventing the PU signal point from generating leakage current. In this case, the transistor in the pull-down maintenance module in the embodiment of the present application is a metal oxide transistor. Because the leakage current of the metal oxide transistor is small, the transistor can be completely turned off to prevent the voltage of the PU signal point from leaking and maintain the potential of the PU signal point. It should be understood that the PU signal point in the embodiment of the present application can be the connection point between the pull-up control module and the pull-up module. Correspondingly, the Nth-level sub-drive circuit also includes a pull-down PD signal point. It should be understood that the PD signal point can also be called a pull-down node, which is the connection point of each module used to pull down the signal of the Nth-level sub-drive circuit.

[0045] In an embodiment of the present application, the N-th level sub-driving circuit may include an output module (pull-up module) and a pull-down maintaining module, wherein the transistor in the output module may be a low-temperature polysilicon transistor, which can effectively reduce the area of ​​the pull-up module, thereby facilitating the reduction of the area of ​​the N-th level sub-driving circuit, thereby facilitating the realization of a narrow edge of the display screen. The transistor in the pull-down maintaining module may be a metal oxide transistor or a low-temperature polysilicon transistor. When the transistor in the pull-down maintaining module is a low-temperature polysilicon transistor, the area of ​​the transistor can be further reduced due to the advantage of the low aspect ratio of the low-temperature polysilicon transistor, thereby reducing the area of ​​the N-th level sub-driving circuit. When the transistor in the pull-down maintaining module is a metal oxide transistor, because the leakage current of the metal oxide transistor is small, the transistor can be completely turned off to prevent the voltage of the PU signal point from leaking and maintain the potential of the PU signal point.

[0046] Each module in the Nth-stage sub-driving circuit in the embodiment of the present application is composed of transistors. The following embodiment describes the Nth-stage sub-driving circuit provided in the embodiment of the present application with a specific circuit structure. Figure 3 Another structural diagram of the N-th sub-driving circuit provided in the embodiment of the present application. The N-th sub-driving circuit also includes: a horizontal scan line G(N), a first clock signal generator CK1, a second clock signal generator CK2, a third clock signal generator CK3, and a fourth clock signal generator CK4. Among them, the horizontal scan line G(N) is used to output the signal of the N-th sub-driving circuit, the clock signal generator is used to generate a high level or a low level signal, and the high level module V gh Used to output high voltage.

[0047] like Figure 3 As shown, the pull-up control module in the embodiment of the present application includes a first low-temperature polysilicon transistor T1, and the pull-down module includes a first metal oxide transistor T2. Among them, the gate of the first low-temperature polysilicon transistor T1 and the source of the first low-temperature polysilicon transistor T1 are connected to the N-2-stage sub-driving circuit or the initial signal source, the drain of the first low-temperature polysilicon transistor T1 is respectively connected to the source of the first metal oxide transistor T2 and the pull-up PU signal point of the N-stage sub-driving circuit, the gate of the first metal oxide transistor T2 is connected to the first clock signal generator CK1, and the drain of the first metal oxide transistor T2 is connected to the high level module V gh connect.

[0048] The pull-down module also includes a second metal oxide transistor T3. The gate of the second metal oxide transistor T3 is connected to the first clock signal generator CK1, the source of the second metal oxide transistor T3 is connected to the horizontal scan line G(N), and the drain of the second metal oxide transistor T3 is connected to the high level module V gh connect.

[0049] As mentioned above Figure 3 As shown, the pull-up module includes: a second low-temperature polysilicon transistor T4. The gate of the second low-temperature polysilicon transistor T4 is connected to the PU signal point of the N-th sub-driving circuit, the source of the second low-temperature polysilicon transistor T4 is connected to the second clock signal generator CK2, and the drain of the second low-temperature polysilicon transistor T4 is connected to the horizontal scanning line G(N) of the N-th sub-driving circuit.

[0050] in, Figure 3The pull-down maintenance module is described by taking the example that all transistors in the pull-down maintenance module are metal oxide transistors. The pull-down maintenance module includes: a first transistor T5, a second transistor T6, a third transistor T7, a fourth transistor T8, a fifth transistor T9, a sixth transistor T10 and a seventh transistor T11. Because the transistors in the pull-down maintenance module can also be low-temperature polysilicon transistors, it is not written here what type of transistors the first transistor T5 to the seventh transistor T11 are. Among them, Figure 4 Another structural schematic diagram of the Nth stage sub-driving circuit provided in an embodiment of the present application. Figure 4 The transistors in the pull-down maintenance module are all low-temperature polysilicon transistors. Figure 3 The circuit connection relationship of the transistors in the pull-down holding circuit will be described. Figure 4 The circuit connection relationship of the transistor in the pull-down holding circuit is Figure 3 same.

[0051] The gate of the first transistor T5 and the source of the first transistor T5 are connected to the third clock signal generator CK3, the source of the first transistor T5 and the source of the second transistor T6 are connected to the pull-down PD signal point of the N-th sub-driving circuit, the gate of the second transistor T6 is connected to the PU signal point of the N-th sub-driving circuit, and the drain of the second transistor T6 is connected to the high level module V gh The gate of the third transistor T7 is connected to the PD signal point, the source of the third transistor T7 is connected to the PU signal point, and the drain of the third transistor T7 is connected to the high level module V gh The gate of the fourth transistor T8 is connected to the gate of the third transistor T7, the source of the fourth transistor T8 is connected to the horizontal scanning line G(N) of the N-th sub-driving circuit, and the drain of the fourth transistor T8 is connected to the high level module V gh The gate of the fifth transistor T9 is connected to the fourth clock signal generator CK3, the source of the fifth transistor T9 is connected to the PD signal point, and the drain of the fifth transistor T9 is connected to the high level module V gh The gate of the sixth transistor T10 is connected to the gate of the seventh transistor T11, and the gate of the sixth transistor T10 and the gate of the seventh transistor T11 are both connected to the reset point Reset of the N-th sub-driving circuit, the source of the sixth transistor T10 is connected to the PU signal point, and the drain of the sixth transistor T10 is connected to the high level module V gh The source of the seventh transistor T11 is connected to the horizontal scanning line G(N), and the drain of the seventh transistor T11 is connected to the high level module V ghThe first end of the bootstrap capacitor C is connected to the PU signal point, and the second end of the bootstrap capacitor C is connected to the horizontal scan line G(N). It should be understood that the reset point Reset of the Nth sub-driving circuit can be understood as the reset switch of the Nth sub-driving circuit, that is, the gate of the sixth transistor T10 and the gate of the seventh transistor T11 are both connected to the reset switch of the Nth sub-driving circuit.

[0052] In the N-th sub-driving circuit in the embodiment of the present application, low-temperature polysilicon transistors are used to make full use of the high driving capability and high stability of low-temperature polysilicon transistors, improve the driving capability and stability of the N-th sub-driving circuit, and realize a narrow frame design. In addition, T3 and T4 use metal oxide transistors. In the pull-up and output stages, the low leakage current performance of metal oxide transistors is fully utilized to maintain the potential of the PU signal point and G(N), which can improve the pull-up speed and stabilize the output potential. The embodiment of the present application also has the same technical effects as the above-mentioned embodiment, and the relevant description in the above-mentioned embodiment can be referred to for details.

[0053] The present application also provides a gate driver, which may include a gate driving circuit as in the embodiment. It should be understood that the gate driver has the same technical effect as the Nth sub-driving circuit in the above embodiment, and will not be described in detail here.

[0054] The embodiment of the present application may also provide a display, which may include the above-mentioned gate driver.

[0055] It should be noted that, for transistors in the field of liquid crystal displays, there is no clear distinction between the drain and the source, so the source of the transistor mentioned in this application can be the drain of the transistor, and the drain of the transistor can also be the source of the transistor.

[0056] In the several embodiments provided in the present application, it should be understood that the disclosed modules can be implemented in other ways. For example, the module embodiments described above are only schematic, for example, the division of modules is only a logical function division, and there may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0057] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0058] In addition, each functional module in each embodiment of the present application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, rather than to limit them. Although the embodiments of the present application have been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate drive circuit, characterized in that: The gate driving circuit includes N-level sub-driving circuits, and the N-level sub-driving circuit includes: a pull-up control module, a pull-down module and a high-level module, the pull-up control module is connected to the N-2-level sub-driving circuit or the initial signal source, the pull-up control module is also connected to the pull-down module and the pull-up PU signal point of the N-level sub-driving circuit, the pull-down module is connected to the high-level module, and N is an integer greater than or equal to 3; Wherein, the transistor in the pull-up control module is a low-temperature polysilicon transistor, and the transistor in the pull-down module is a metal oxide transistor; The N-th stage sub-driving circuit further includes: a pull-up module, the pull-up module is connected to the pull-up control module; the transistor in the pull-up module is a low-temperature polysilicon transistor; The N-th stage sub-driving circuit further includes: a pull-down maintaining module, the pull-down maintaining module is connected to the pull-up module and the pull-down module respectively, and the transistor in the pull-down maintaining module is a low-temperature polysilicon transistor or a metal oxide transistor; The pull-down maintenance module includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, and the N-th stage sub-driving circuit also includes: a third clock signal generator, a fourth clock signal generator and a bootstrap capacitor; The gate of the first transistor and the source of the first transistor are connected to the third clock signal generator, the source of the first transistor and the source of the second transistor are connected to the pull-down PD signal point of the N-th sub-driving circuit, the gate of the second transistor is connected to the PU signal point, the drain of the second transistor is connected to the high level module, the gate of the third transistor is connected to the PD signal point, the source of the third transistor is connected to the PU signal point, the drain of the third transistor is connected to the high level module, the gate of the fourth transistor is connected to the gate of the third transistor, the source of the fourth transistor is connected to the horizontal scan line of the N-th sub-driving circuit, the drain of the fourth transistor is connected to the high level module, and the The gate of the fifth transistor is connected to the fourth clock signal generator, the source of the fifth transistor is connected to the PD signal point, the drain of the fifth transistor is connected to the high level module, the gate of the sixth transistor is connected to the gate of the seventh transistor, and the gate of the sixth transistor and the gate of the seventh transistor are both connected to the reset point Reset of the Nth level sub-driving circuit, the source of the sixth transistor is connected to the PU signal point, the drain of the sixth transistor is connected to the high level module, the source of the seventh transistor is connected to the horizontal scan line, the drain of the seventh transistor is connected to the high level module, the first end of the bootstrap capacitor is connected to the PU signal point, and the second end of the bootstrap capacitor is connected to the horizontal scan line.

2. The gate driving circuit according to claim 1, characterized in that: The N-2th level sub-driving circuit or initial signal source is used to output a low level signal.

3. The gate drive circuit according to claim 1 or 2, characterized in that: The pull-up control module includes a first low-temperature polysilicon transistor, the pull-down module includes a first metal oxide transistor, and the Nth-stage sub-driving circuit further includes: a first clock signal generator; The gate and source of the first low-temperature polysilicon transistor are both connected to the N-2th sub-driving circuit or the initial signal source, the drain of the first low-temperature polysilicon transistor is respectively connected to the source of the first metal oxide transistor and the pull-up PU signal point of the Nth sub-driving circuit, the gate of the first metal oxide transistor is connected to the first clock signal generator, and the drain of the first metal oxide transistor is connected to the high-level module.

4. The gate driving circuit according to claim 3, characterized in that: The Nth stage sub-driving circuit further includes: a horizontal scanning line, and the pull-down module further includes a second metal oxide transistor; The gate of the second metal oxide transistor is connected to the first clock signal generator, the source of the second metal oxide transistor is connected to the horizontal scan line, and the drain of the second metal oxide transistor is connected to the high level module.

5. The gate driving circuit according to claim 1, characterized in that: The pull-up module includes: a second low-temperature polysilicon transistor, and the Nth-stage sub-driving circuit also includes: a second clock signal generator; The gate of the second low-temperature polysilicon transistor is connected to the PU signal point, the source of the second low-temperature polysilicon transistor is connected to the second clock signal generator, and the drain of the second low-temperature polysilicon transistor is connected to the horizontal scan line of the Nth level sub-driving circuit.

6. A gate driver, characterized in that: The gate driving circuit comprises the gate driving circuit as claimed in any one of claims 1 to 5.

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