Dynamic voltage supply circuit and non-volatile memory device including the same

Abstract

The present application discloses a dynamic voltage supply circuit and a non-volatile memory device including the same. The dynamic voltage supply circuit of the non-volatile memory device includes a voltage amplification / output circuit and a dynamic voltage output circuit. The voltage amplification / output circuit receives a first clock signal and a second clock signal to generate a dynamic supply voltage greater than the supply voltage when the first clock signal has a "low" level. The dynamic voltage output circuit outputs the dynamic supply voltage when the first clock signal has a "low" level and outputs a ground voltage when the first clock signal has a "high" level.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0040377, filed on April 5, 2019, the entire contents of which are incorporated herein by reference. Technical field

[0003] Various embodiments of the present disclosure generally relate to non - volatile memory devices, and more particularly, to a dynamic voltage supply circuit and a non - volatile memory device including the dynamic voltage supply circuit. Background art

[0004] Semiconductor memory devices are generally classified as random access memory (RAM) devices or read - only memory (ROM) devices according to their data volatility. RAM devices are volatile memory devices that lose the stored data when the power is interrupted. In contrast, ROM devices are non - volatile memory devices that retain the stored data even when their power is interrupted. According to the data input method, i.e., the data programming method, ROM devices can also be classified as programmable ROM (PROM) devices or mask ROM devices. PROM devices can be manufactured and sold without programming and can be directly programmed by a customer (i.e., a user) after manufacturing. During the manufacture of mask ROM devices, the mask ROM devices can be programmed using an implantation mask manufactured based on data requested by the user. PROM devices can include: one - time programmable ROM (OTPROM) devices, erasable programmable ROM (EPROM) devices, and electrically erasable programmable ROM (EEPROM) devices. Once an OTPROM device is programmed, the data in the programmed OTPROM device cannot be changed.

[0005] An NMOS transistor or a PMOS transistor can be used as a cell transistor of a non-volatile memory device (e.g., an OTPROM device). When a PMOS transistor is used as a cell transistor of a non-volatile memory device, the PMOS cell transistor can have an off state as its initial state and can have an on state as its programmed state. A read operation of the PMOS cell transistor can be performed by sensing a voltage level of a bit line connected to any one selected from PMOS cell transistors. In this case, the voltage level of the bit line can be determined by a ratio of a resistance value of a load resistor coupled between a power supply voltage line and the bit line to an equivalent resistance value of the selected PMOS cell transistor. As electronic systems are scaled down and classified into more types of systems, more power supply voltage levels are required to operate non-volatile memory devices used in the electronic systems. Specifically, if a non-volatile memory device is embedded in a portable device, the operating range of the non-volatile memory device can be limited by reducing the magnitude of the power supply voltage according to the power consumption of the battery of the portable device. SUMMARY OF THE INVENTION

[0006] According to an embodiment, a dynamic voltage supply circuit includes a voltage amplification / output circuit and a dynamic voltage output circuit. The voltage amplification / output circuit receives a first clock signal and a second clock signal to generate a dynamic supply voltage greater than a supply voltage when the first clock signal has a "low" level. The dynamic voltage output circuit outputs the dynamic supply voltage when the first clock signal has a "low" level and outputs a ground voltage when the first clock signal has a "high" level.

[0007] According to another embodiment, a non-volatile memory device includes a dynamic voltage supply circuit, non-volatile memory cells, and a sense amplifier circuit. The dynamic voltage supply circuit is configured to include a voltage amplification / output circuit and a dynamic voltage output circuit. The voltage amplification / output circuit receives a first clock signal and a second clock signal to generate a dynamic supply voltage greater than a supply voltage when the first clock signal has a "low" level. The dynamic voltage output circuit outputs the dynamic supply voltage when the first clock signal has a "low" level and outputs a ground voltage when the first clock signal has a "high" level. The non-volatile memory cells are coupled between a bit line connected to a dynamic voltage supply line having the dynamic supply voltage and a ground voltage terminal. The sense amplifier circuit selectively outputs any one of the dynamic supply voltage and the ground voltage in response to a bit line voltage induced at the bit line.

[0008] According to another embodiment, a non-volatile storage device includes: a first terminal adapted to receive a supply voltage; a second terminal adapted to receive a first clock signal; a third terminal adapted to receive a second clock signal; a first output node and a second output node; a first transistor coupled between the first terminal and the first output node; a second transistor coupled between the first terminal and the second output node; a first capacitor coupled between the first output node and the second terminal; a second capacitor coupled between the second output node and the third terminal; and a dynamic voltage output circuit coupled between a selected one of the first output node and the second output node and a ground voltage terminal, adapted to generate a dynamic supply voltage greater than the supply voltage in response to a selected one of the first clock signal and the second clock signal, the selected clock signal corresponding to the unselected one of the first output node and the second output node. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In the drawings, for each separate view, the same reference numerals refer to the same or functionally similar elements. The drawings and the following detailed description are incorporated in and form a part of the specification, and are used to further illustrate embodiments including the novel concepts claimed, and to explain the various principles and advantages of those embodiments.

[0010] Figure 1 is a circuit diagram showing a read interference phenomenon caused by a reduced supply voltage during a read operation of a non-volatile storage device.

[0011] Figure 2 is a circuit diagram showing a dynamic voltage supply circuit of a non-volatile storage device according to an embodiment of the present disclosure.

[0012] Figure 3 is a timing diagram showing the operation of a dynamic voltage supply circuit according to an embodiment of the present disclosure.

[0013] Figures 4 to 12 shows Figure 2 the dynamic voltage supply circuit shown in Figure 3 at the time points of the timing diagram of

[0014] Figure 13 is a circuit diagram showing a dynamic voltage supply circuit of a non-volatile storage device according to an embodiment of the present disclosure.

[0015] Figure 14 is a timing diagram showing the operation of a dynamic voltage supply circuit according to an embodiment of the present disclosure.

[0016] Figure 15 is a circuit diagram showing a non-volatile storage device according to an embodiment of the present disclosure.

[0017] Figure 16 is a circuit diagram showing a sense amplifier circuit in a non-volatile memory device according to an embodiment of the present disclosure.

[0018] Figure 17 is a circuit diagram showing a non-volatile memory device according to an embodiment of the present disclosure. Detailed Description

[0019] For the following description of embodiments, it will be understood that the terms "first" and "second" are intended to identify elements and are not used to define the elements themselves or imply a specific order or hierarchy. Additionally, when an element is referred to as being "on", "above", "over", "under", or "beneath" another element, a relative positional relationship is indicated regardless of the presence or absence of intervening elements. Thus, terms such as "on", "above", "over", "under", or "beneath" as used herein are for the purpose of describing a particular embodiment only and are not intended to limit the scope of the present disclosure. Further, when elements are referred to as being "connected" or "coupled" to each other, these elements can be directly electrically or mechanically connected or coupled without the need for intervening elements or indirectly through intervening elements.

[0020] Various embodiments relate to a dynamic voltage supply circuit and a non-volatile memory device including the dynamic voltage supply circuit.

[0021] Figure 1 is a circuit diagram showing a read interference phenomenon caused by a reduced supply voltage during a read operation of the non-volatile memory device 100. Refer to Figure 1 , the non-volatile memory device 100 may include a non-volatile memory cell 110, a resistive load 120, and a sense amplifier circuit 130. The non-volatile memory cell 110 may include a first PMOS transistor PM1 corresponding to a cell transistor and a second PMOS transistor PM2 corresponding to a select transistor. The gate of the first PMOS transistor PM1 may be a floating gate, and the drain of the first PMOS transistor PM1 may be grounded. The source of the first PMOS transistor PM1 may be directly connected to the drain of the second PMOS transistor PM2. A first enable signal EN1 serving as a select signal may be input to the gate of the second PMOS transistor PM2. The source of the second PMOS transistor PM2 may be coupled to a first node NODE_A via a bit line BL.

[0022] The resistive load 120 may include a resistive load device coupled between a first node NODE_A and a supply voltage line 101. For example, the resistive load device may be a third PMOS transistor PM3. A second enable signal EN2 may be input to the gate of the third PMOS transistor PM3. The source and drain of the third PMOS transistor PM3 may be coupled to the supply voltage line 101 and the first node NODE_A, respectively. When the third PMOS transistor PM3 is turned on, the third PMOS transistor PM3 may function as a resistive element coupled between the supply voltage line 101 and the first node NODE_A.

[0023] The sense amplifier circuit 130 may be implemented using a complementary metal oxide semiconductor (CMOS) inverter including a first NMOS transistor NM1 and a fourth PMOS transistor PM4. The gates of the first NMOS transistor NM1 and the fourth PMOS transistor PM4 may receive a sense input signal SA_IN via a sense input line 102. The sense input line 102 may be coupled to the first node NODE_A. The source of the first NMOS transistor NM1 may be grounded. The drain of the first NMOS transistor NM1 may be coupled to the drain of the fourth PMOS transistor PM4. The source of the fourth PMOS transistor PM4 may be coupled to the supply voltage line 101 to which a supply voltage VDD is applied. The drain of the first NMOS transistor NM1 and the drain of the fourth PMOS transistor PM4 may be coupled to a sense output line 103. A sense output signal SA_OUT may be output from the sense amplifier circuit 130 via the sense output line 103.

[0024] The first PMOS transistor PM1 serving as a cell transistor may have an initial state or a programmed state. In this specification, the initial state refers to an off cell state in which the first PMOS transistor PM1 is turned off, and the programmed state refers to an on cell state in which the first PMOS transistor PM1 is turned on. To read data corresponding to the state of the first PMOS transistor PM1, a first enable signal EN1 may be applied to the gate of the second PMOS transistor PM2 to turn on the second PMOS transistor PM2, and a second enable signal EN2 may be applied to the gate of the third PMOS transistor PM3 to turn on the third PMOS transistor PM3. In this case, a bit line voltage obtained by reducing the voltage drop across the turned-on third PMOS transistor PM3 from the supply voltage VDD provided via the supply voltage line 101 may be applied to the first node NODE_A. The bit line voltage may correspond to the sense input signal SA_IN. The sense input signal SA_IN may be input to the sense amplifier circuit 130.

[0025] If the first PMOS transistor PM1 has an initial state corresponding to the off-cell state, the resistance value between the first node NODE_A and the ground voltage terminal can ideally be infinite. However, compared to the resistance value of the turned-on third PMOS transistor PM3, the resistance value between the first node NODE_A and the ground voltage terminal may not actually be infinite, but rather relatively high. Therefore, the voltage induced at the first node NODE_A, that is, the voltage of the sense input signal SA_IN can be approximately equal to the supply voltage VDD. When the sense input signal SA_IN having the supply voltage VDD is input to the sense amplifier circuit 130, the fourth PMOS transistor PM4 may not be turned on, while the first NMOS transistor NM1 is turned on. Since only the first NMOS transistor NM1 is turned on, the sense output signal SA_OUT output from the sense amplifier circuit 130 can approximately have the ground voltage. Thus, if the ground voltage is generated as the sense output signal SA_OUT, the first PMOS transistor PM1 corresponding to the cell transistor can be regarded as having the initial state.

[0026] If the first PMOS transistor PM1 has a programmed state corresponding to the on-cell state, the resistance value between the first node NODE_A and the ground voltage terminal can ideally be zero. However, compared to the resistance value of the turned-on third PMOS transistor PM3, the resistance value between the first node NODE_A and the ground voltage terminal may not actually be zero, but rather relatively low. Therefore, the voltage induced at the first node NODE_A, that is, the sense input voltage SA_IN can be approximately equal to the ground voltage. When the sense input voltage SA_IN of the ground voltage is input to the sense amplifier circuit 130, the first NMOS transistor NM1 may not be turned on, while the fourth PMOS transistor PM4 is turned on. Since only the fourth PMOS transistor PM4 is turned on, the sense output signal SA_OUT output from the sense amplifier circuit 130 can approximately have the supply voltage VDD. Thus, if the supply voltage VDD is generated as the sense output signal SA_OUT, the first PMOS transistor PM1 corresponding to the cell transistor can be regarded as having the programmed state.

[0027] If the supply voltage VDD is reduced to a relatively low level, the read operation of the first PMOS transistor PM1 may be abnormally executed. Specifically, in order for the first PMOS transistor PM1 to be regarded as having a programmed state, both the second PMOS transistor PM2, which serves as a selection transistor of the non-volatile memory cell 110, and the fourth PMOS transistor PM4 of the sense amplifier circuit 130 must be turned on. In order to turn on the second PMOS transistor PM2, the voltage applied between the gate and the source of the second PMOS transistor PM2 must be greater than the first threshold voltage Vth1 between the gate and the source of the second PMOS transistor PM2. Similarly, in order to turn on the fourth PMOS transistor PM4, the voltage applied between the gate and the source of the fourth PMOS transistor PM4 must be greater than the second threshold voltage Vth2 between the gate and the source of the fourth PMOS transistor PM4. Therefore, in order to turn on both the second PMOS transistor PM2 and the fourth PMOS transistor PM4, when the voltage drop across the third PMOS transistor PM3 is ignored, the supply voltage VDD must be greater than the sum of the first threshold voltage Vth1 of the second PMOS transistor PM2 and the second threshold voltage Vth2 of the fourth PMOS transistor PM4. That is, if the supply voltage VDD is less than the sum of the first threshold voltage Vth1 and the second threshold voltage Vth2, the read operation of the first PMOS transistor PM1 having a programmed state may not be correctly executed.

[0028] Figure 2 is a circuit diagram showing a dynamic voltage supply circuit 200 employed in a non-volatile memory device according to an embodiment of the present disclosure. Referring to Figure 2 , the dynamic voltage supply circuit 200 may include a voltage amplification and output (amplification / output) circuit 210 and a dynamic voltage output circuit 220. The voltage amplification / output circuit 210 may receive a first clock signal CK1 and a second clock signal CK2 to generate a dynamic supply voltage dVDD that is twice as large as the supply voltage VDD when the first clock signal CK1 has a voltage corresponding to a "low" level. The dynamic voltage output circuit 220 may output the dynamic supply voltage dVDD when the first clock signal CK1 has a voltage corresponding to a "low" level, and may output a ground voltage (i.e., 0 volts) when the first clock signal CK1 has a voltage corresponding to a "high" level.

[0029] Specifically, the voltage amplification / output circuit 210 may be configured to include a first capacitor C1, a second capacitor C2, a first NMOS transistor MN21, and a second NMOS transistor MN22. The first clock signal CK1 may be applied to one end of the first capacitor C1, and the other end of the first capacitor C1 may be coupled to the first node NODE_B. Thus, if the first clock signal CK1 having a supply voltage VDD is applied to one end of the first capacitor C1, the first node voltage VB induced at the first node NODE_B may rise to the supply voltage VDD. The second clock signal CK2 may be applied to one end of the second capacitor C2, and the other end of the second capacitor C2 may be coupled to the second node NODE_C. Thus, if the second clock signal CK2 having a supply voltage VDD is applied to one end of the second capacitor C2, the second node voltage VC induced at the second node NODE_C may rise to the supply voltage VDD.

[0030] The first NMOS transistor MN21 may be coupled between the terminal of the supply voltage VDD and the first node NODE_B. The gate of the first NMOS transistor MN21 may be coupled to the second node NODE_C. The drain and source of the first NMOS transistor MN21 may be coupled to the terminal of the supply voltage VDD and the first node NODE_B, respectively. Thus, if the gate-source voltage Vgs of the first NMOS transistor MN21 (i.e., the voltage value calculated by the equation "VC - VB") is greater than the threshold voltage of the first NMOS transistor MN21, the first NMOS transistor MN21 may be turned on. The second NMOS transistor MN22 may be coupled between the terminal of the supply voltage VDD and the second node NODE_C. The gate of the second NMOS transistor MN22 may be coupled to the first node NODE_B. The drain and source of the second NMOS transistor MN22 may be coupled to the terminal of the supply voltage VDD and the second node NODE_C, respectively. Thus, if the gate-source voltage Vgs of the second NMOS transistor MN22 (i.e., the voltage value of "VB minus VC") is greater than the threshold voltage of the second NMOS transistor MN22, the second NMOS transistor MN22 may be turned on.

[0031] The dynamic voltage output circuit 220 can be implemented using an inverter. In this case, the dynamic voltage output circuit 220 can be configured to include a first PMOS transistor MP21 and a third NMOS transistor MN23. The first PMOS transistor MP21 can be coupled between the second node NODE_C and the output line of the dynamic supply voltage dVDD. The first clock signal CK1 can be applied to the gate of the first PMOS transistor MP21. The source and drain of the first PMOS transistor MP21 can be coupled to the second node NODE_C and the output line of the dynamic supply voltage dVDD, respectively. The third NMOS transistor MN23 can be coupled between the output line of the dynamic supply voltage dVDD and the ground voltage terminal. The first clock signal CK1 can be applied to the gate of the third NMOS transistor MN23. The drain and source of the third NMOS transistor MN23 can be coupled to the output line of the dynamic supply voltage dVDD and the ground voltage terminal.

[0032] When the first clock signal CK1 has a "high" level (e.g., the supply voltage VDD), the first PMOS transistor MP21 can be turned off, while the third NMOS transistor MN23 can be turned on. Therefore, the dynamic supply voltage dVDD having the ground voltage can be output via the output line of the dynamic supply voltage dVDD. Conversely, when the first clock signal CK1 has a "low" level (e.g., the ground voltage), the first PMOS transistor MP21 can be turned on, while the third NMOS transistor MN23 can be turned off. Therefore, the dynamic supply voltage dVDD output via the output line of the dynamic supply voltage dVDD can have the second node voltage VC.

[0033] Figure 3 is a timing diagram showing the operation of a dynamic voltage supply circuit (e.g., Figure 2 the dynamic voltage supply circuit 200 shown in Figures 4 to 12 is a diagram showing Figure 2 the operation of the dynamic voltage supply circuit 200 shown in Figure 3 at the time points of the timing diagram according to Figure 3As shown, the "high" level of the first clock signal CK1 and the second clock signal CK2 represents the supply voltage VDD, while the "low" level of the first clock signal CK1 and the second clock signal CK2 represents the ground voltage. In this embodiment, the first clock signal CK1 and the second clock signal CK2 are such that the "high" level time period of the first clock signal CK1 does not overlap with the "high" level time period of the second clock signal CK2 in the timing diagram. Additionally, the first clock signal CK1 and the second clock signal CK2 can be set such that the "high" level time periods of the first clock signal CK1 and the second clock signal CK2 are generated alternately. For example, during the time period from the first time point "t1" to the second time point "t2", the second clock signal CK2 can have the ground voltage, while the first clock signal CK1 can have the supply voltage VDD. Furthermore, during the time period from the third time point "t3" to the fourth time point "t4", the second clock signal CK2 can have the supply voltage VDD, while the first clock signal CK1 can have the ground voltage. Moreover, during the time period from the fifth time point "t5" to the sixth time point "t6", the second clock signal CK2 can have the ground voltage, while the first clock signal CK1 can have the supply voltage VDD, and during the time period from the seventh time point "t7" to the eighth time point "t8", the second clock signal CK2 can have the supply voltage VDD, while the first clock signal CK1 has the ground voltage. Additionally, during the time period from the ninth time point "t9" to the tenth time point "t10", the second clock signal CK2 can have the ground voltage, while the first clock signal CK1 can have the supply voltage VDD.

[0034] As Figure 4 shown, during the time period from the first time point "t1" to the second time point "t2", the first clock signal CK1 can have the supply voltage VDD corresponding to the "high" level, while the second clock signal CK2 can have the ground voltage corresponding to the "low" level. Thus, as the level of the first clock signal CK1 changes from the ground voltage to the supply voltage VDD, the first node voltage VB can rise to the supply voltage VDD. As the first node voltage VB rises to the supply voltage VDD, the second NMOS transistor MN22 can be turned on. The second node voltage VC can rise from the ground voltage to reach the voltage level "VDD - Vth" remaining after subtracting the threshold voltage Vth of the second NMOS transistor MN22 from the supply voltage VDD. Since the first clock signal CK1 has the supply voltage VDD, the first PMOS transistor MP1 can be turned off and the third NMOS transistor MN23 can be turned on. Therefore, the dynamic supply voltage dVDD1 having the ground voltage can be output from the dynamic voltage supply circuit 200.

[0035] As Figure 5As shown, during the period from the second time point “t2” to the third time point “t3”, both the first clock signal CK1 and the second clock signal CK2 have a ground voltage corresponding to the “low” level, and as the level of the first clock signal CK1 changes from the supply voltage VDD to the ground voltage, the first node voltage VB can be reduced from the supply voltage VDD to the ground voltage. As the first node voltage VB is reduced from the supply voltage VDD to the ground voltage, the second NMOS transistor MN22 can be turned off. The second node voltage VC can maintain the previous voltage level “VDD-Vth”. Since the first clock signal CK1 has a ground voltage, the first PMOS transistor MP21 can be turned on and the third NMOS transistor MN23 can be turned off. Therefore, the dynamic supply voltage dVDD1 output from the dynamic voltage supply circuit 200 can have a voltage level “VDD-Vth” remaining after subtracting the threshold voltage Vth of the second NMOS transistor MN22 from the supply voltage VDD corresponding to the second node voltage VC.

[0036] As Figure 6 shown, during the period from the third time point “t3” to the fourth time point “t4”, the first clock signal CK1 can have a ground voltage corresponding to the “low” level, while the second clock signal CK2 can have the supply voltage VDD corresponding to the “high” level. Therefore, as the level of the second clock signal CK2 changes from the ground voltage to the supply voltage VDD, the second node voltage VC2 can rise from the previous voltage “VDD-Vth” to the supply voltage VDD to reach a voltage level “2×VDD-Vth” remaining after subtracting the threshold voltage Vth of the second NMOS transistor MN22 from twice the supply voltage VDD. As the second node voltage VC rises, the first NMOS transistor MN21 can be turned on. If the first NMOS transistor MN21 is turned on, the first node voltage VB can rise to the supply voltage VDD. In this case, since the first node voltage VB has the supply voltage VDD, the second NMOS transistor MN22 can still be turned off. Since the first clock signal CK1 has a ground voltage, the first PMOS transistor MP21 can be turned on and the third NMOS transistor MN23 can be turned off. As a result, the dynamic supply voltage dVDD1 output from the dynamic voltage supply circuit 200 can have a voltage level “2×VDD-Vth” remaining after subtracting the threshold voltage Vth of the second NMOS transistor MN22 from twice the supply voltage VDD.

[0037] As Figure 7As shown, during the period from the fourth time point "t4" to the fifth time point "t5", both the first clock signal CK1 and the second clock signal CK2 have a ground voltage corresponding to the "low" level. In this case, as the second clock signal CK2 changes from the supply voltage VDD to the ground voltage, the second node voltage VC can be reduced to have a voltage level of "VDD - Vth" remaining after subtracting the threshold voltage Vth of the second NMOS transistor MN22 from the supply voltage VDD. Since the first clock signal CK1 has a ground voltage, the first PMOS transistor MP21 can be turned on and the third NMOS transistor MN23 can be turned off. Therefore, the dynamic supply voltage dVDD1 output from the dynamic voltage supply circuit 200 can have a voltage level of "VDD - Vth" remaining after subtracting the threshold voltage Vth of the second NMOS transistor MN22 from the supply voltage corresponding to the second node voltage VC.

[0038] As Figure 8 shown, during the period from the fifth time point "t5" to the sixth time point "t6", the first clock signal CK1 can have the supply voltage VDD corresponding to the "high" level, while the second clock signal CK2 can have the ground voltage corresponding to the "low" level. Therefore, as the level of the first clock signal CK1 changes from the ground voltage to the supply voltage VDD, the first node voltage VB can rise to reach a voltage level of "2 × VDD". As the first node voltage VB rises to the voltage level of "2 × VDD", the first NMOS transistor MN21 can be turned off and the second NMOS transistor MN22 can be turned on. Since the first NMOS transistor MN21 is turned off, the first node voltage VB can maintain the voltage level of "2 × VDD", and the second node voltage VC can rise to reach the supply voltage VDD. Since the first clock signal CK1 has the supply voltage VDD, the first PMOS transistor MP21 can be turned off and the third NMOS transistor MN23 can be turned on. As a result, the dynamic supply voltage dVDD1 output from the dynamic voltage supply circuit 200 can have a ground voltage (i.e., 0 volts).

[0039] As Figure 9As shown, during the period from the sixth time point "t6" to the seventh time point "t7", both the first clock signal CK1 and the second clock signal CK2 have a ground voltage corresponding to the "low" level. In this case, as the first clock signal CK1 changes from the supply voltage VDD to the ground voltage, the first node voltage VB can decrease from the voltage level of "2×VDD" to the supply voltage VDD. The second node voltage VC can maintain the previous voltage level (i.e., the supply voltage VDD). Since the first clock signal CK1 has a ground voltage, the first PMOS transistor MP21 can be turned on, while the third NMOS transistor MN23 can be turned off. Therefore, the dynamic supply voltage dVDD1 output from the dynamic voltage supply circuit 200 can have the supply voltage VDD.

[0040] As Figure 10 shown, during the period from the seventh time point "t7" to the eighth time point "t8", the first clock signal CK1 can have a ground voltage corresponding to the "low" level, while the second clock signal CK2 can have the supply voltage VDD corresponding to the "high" level. Therefore, as the level of the second clock signal CK2 changes from the ground voltage to the supply voltage VDD, the second node voltage VC can increase from the supply voltage VDD by the supply voltage VDD to reach the voltage level of "2×VDD". As the second node voltage VC increases to have the voltage level of "2×VDD", the first NMOS transistor MN21 can be turned on. As the first NMOS transistor MN21 is turned on, the first node voltage VB can maintain the supply voltage VDD. In this case, since the first node voltage VB has the voltage level of the supply voltage VDD and the second node voltage VC has the voltage level of "2×VDD", the second NMOS transistor MN22 can be turned off to maintain the second node voltage VC having the voltage level of "2×VDD". Since the first clock signal CK1 has a ground voltage, the first PMOS transistor MP21 can be turned on, while the third NMOS transistor MN23 can be turned off. As a result, the dynamic supply voltage dVDD1 output from the dynamic voltage supply circuit 200 can have the voltage level "2×VDD" corresponding to the second node voltage VC.

[0041] As Figure 11As shown, during the period from the eighth time point “t8” to the ninth time point “t9”, both the first clock signal CK1 and the second clock signal CK2 have a ground voltage corresponding to the “low” level. In this case, as the second clock signal CK2 changes from the supply voltage VDD to the ground voltage, the second node voltage VC can be reduced from the voltage level of “2×VDD” to the supply voltage VDD. Since the first clock signal CK1 has a ground voltage, the first PMOS transistor MP21 can be turned on, while the third NMOS transistor MN23 can be turned off. Therefore, the dynamic supply voltage dVDD1 output from the dynamic voltage supply circuit 200 can have the supply voltage VDD corresponding to the second node voltage VC.

[0042] As Figure 12 shown, during the period from the ninth time point “t9” to the tenth time point “t10”, the first clock signal CK1 can have the supply voltage VDD corresponding to the “high” level, while the second clock signal CK2 can have the ground voltage corresponding to the “low” level. Therefore, as the level of the first clock signal CK1 changes from the ground voltage to the supply voltage VDD, the first node voltage VB can rise to reach the voltage level of “2×VDD”. As the first node voltage VB rises to the voltage level of “2×VDD”, the first NMOS transistor MN21 can be turned off, while the second NMOS transistor MN22 can be turned on. Since the first NMOS transistor MN21 is turned off, the first node voltage VB can maintain the voltage level of “2×VDD”, and since the second NMOS transistor MN22 is turned on, the second node voltage VC can maintain the supply voltage VDD. Since the first clock signal CK1 has the supply voltage VDD, the first PMOS transistor MP21 can be turned off, while the third NMOS transistor MN23 can be turned on. As a result, the dynamic supply voltage dVDD1 output from the dynamic voltage supply circuit 200 can have a ground voltage (i.e., 0 volts).

[0043] Subsequently, the execution with reference to Figures 7 to 12The described operation. Thus, from the second duration "t6 - t9" among the durations "t2 - t5" and "t6 - t9" during which the first clock signal CK1 has a "low" level, the dynamic supply voltage dVDD1 can be raised from the ground voltage to twice the supply voltage "2×VDD" to maintain the twice supply voltage "2×VDD" for a certain duration (e.g., when the second clock signal CK2 has a "high" level), and then can be reduced to have the supply voltage VDD. Conversely, during the durations "t1 - t2", "t5 - t6", and "t9 - t10" when the first clock signal CK1 has a "high" level, the dynamic supply voltage dVDD1 output from the dynamic voltage supply circuit 200 can have the ground voltage (i.e., 0 volts).

[0044] Figure 13 is a circuit diagram showing a dynamic voltage supply circuit 300 of a non - volatile memory device according to an embodiment of the present disclosure. In Figure 13 which, the same reference numerals or symbols as those used in Figure 2 represent the same elements. Referring to Figure 13 , the dynamic voltage supply circuit 300 can be different from the dynamic voltage supply circuit 200 in terms of the connection structure between the voltage amplification / output circuit 210 and the dynamic voltage output circuit 220. Specifically, the gates of the first PMOS transistor MP21 and the third NMOS transistor MN23 of the dynamic voltage supply circuit 300 can be coupled to one terminal of the second capacitor C2 to which the second clock signal CK2 is input. Additionally, the source of the first PMOS transistor MP21 of the dynamic voltage supply circuit 300 can be coupled to the first node NODE_B. As a result, when the second clock signal CK2 has a "low" level, the dynamic supply voltage dVDD2 output from the dynamic voltage supply circuit 300 can have the first node voltage VB, and when the second clock signal CK2 has a "high" level, the dynamic supply voltage dVDD2 output from the dynamic voltage supply circuit 300 can have the ground voltage (i.e., 0 volts).

[0045] Figure 14 is a timing diagram showing the operation of the dynamic voltage supply circuit 300 shown in Figure 13 which. Referring to Figure 14 , the first node voltage VB and the second node voltage VC of the dynamic voltage supply circuit 300 can have as shown in reference Figures 4 to 12A waveform identical to the described waveform. However, the output timing of the dynamic supply voltage dVDD2 with a supply voltage of "2×VDD" twice as high can be different from the output timing of the dynamic supply voltage dVDD1 with a supply voltage of "2×VDD" twice as high. Specifically, since the dynamic supply voltage dVDD2 has the first node voltage VB when the second clock signal CK2 has a "low" level (i.e., the ground voltage), the dynamic supply voltage dVDD2 output from the dynamic voltage supply circuit 300 can have the supply voltage VDD during the period from time point "t1" to time point "t3" (i.e., within the first duration when the second clock signal CK2 has a "low" level). However, the dynamic supply voltage dVDD2 output from the dynamic voltage supply circuit 300 can have a supply voltage of "2×VDD" twice as high during the period from time point "t4" to time point "t7" (i.e., within the second duration when the second clock signal CK2 has a "low" level). After time point "t7", whenever the second clock signal CK2 has a "low" level, the dynamic supply voltage dVDD2 output from the dynamic voltage supply circuit 300 can have a supply voltage of "2×VDD" twice as high.

[0046] Figure 15 is a circuit diagram showing an example of a non-volatile memory device 400 according to an embodiment of the present disclosure. Figure 16 is shown including Figure 15 an example of the sense amplifier circuit 430 included in the non-volatile memory device 400. Refer to Figure 15 , the non-volatile memory device 400 can be configured to include a dynamic voltage supply circuit 200, a non-volatile memory cell 410, a resistive load 420, and a sense amplifier circuit 430. The dynamic voltage supply circuit 200 can have the same configuration as described in reference to Figure 2 and Figure 3 . The non-volatile memory cell 410 can be configured to include a second PMOS transistor MP32 serving as a selection transistor and a third PMOS transistor MP33 serving as a cell transistor. The selection signal SG can be input to the gate of the second PMOS transistor MP32. The source of the second PMOS transistor MP32 can be coupled to the bit line BL, and the drain of the second PMOS transistor MP32 can be coupled to the source of the third PMOS transistor MP33. The gate of the third PMOS transistor MP33 can be a floating gate, and the drain of the third PMOS transistor MP33 can be grounded.

[0047] The resistive load 420 may include a resistive load device coupled between the dynamic voltage supply line 450 and the bit line BL. In one embodiment, the resistive load 420 may be the fourth PMOS transistor MP44. The read signal READb may be input to the gate of the fourth PMOS transistor MP44. The drain of the fourth PMOS transistor MP44 may be coupled to the bit line BL, and the source of the fourth PMOS transistor MP44 may be coupled to the dynamic voltage supply line 450. In this embodiment, the dynamic voltage supply line 450 may be defined as a signal line to which the output signal (i.e., the dynamic supply voltage dVDD1) of the dynamic voltage supply circuit 200 is applied. If the fourth PMOS transistor MP44 constituting the resistive load 420 is turned on, the fourth PMOS transistor MP44 may be used as a resistor coupled between the dynamic voltage supply line 450 and the bit line BL.

[0048] The sense amplifier circuit 430 may receive the bit line voltage VBL via the bit line BL, and may output the dynamic supply voltage dVDD1 induced at the dynamic voltage supply line 450 or the ground voltage as a sense output signal SA_OUT. As Figure 16 shown, according to one embodiment, the sense amplifier circuit 430 may be implemented using an inverter. In this case, the sense amplifier circuit 430 may be configured to include a fifth PMOS transistor MP65 and a fourth NMOS transistor MN64 coupled in series. The fifth PMOS transistor MP65 may be coupled between the dynamic voltage supply line 450 and the sense output signal line that outputs the sense output signal SA_OUT. The gate of the fifth PMOS transistor MP65 may be coupled to the bit line BL. The source and drain of the fifth PMOS transistor MP65 may be coupled to the dynamic voltage supply line 450 and the sense output signal line, respectively. The fourth NMOS transistor MN64 may be coupled between the sense output signal line and the ground voltage terminal. The gate of the fourth NMOS transistor MN64 may be coupled to the bit line BL. The drain and source of the fourth NMOS transistor MN64 may be coupled to the sense output signal line and the ground voltage terminal, respectively.

[0049] If the bit line voltage VBL has a "high" level, the fifth PMOS transistor MP65 may be turned off, while the fourth NMOS transistor MN64 may be turned on. Therefore, the sense output signal SA_OUT output via the sense output signal line may have the ground voltage. On the contrary, if the bit line voltage VBL has a "low" level, the fifth PMOS transistor MP65 may be turned on, while the fourth NMOS transistor MN64 may be turned off. Therefore, the sense output signal SA_OUT output via the sense output signal line may have the dynamic supply voltage dVDD1 applied to the dynamic voltage supply line 450.

[0050] Refer again toFigure 15 A read operation of the non-volatile memory cell 410 can be performed in response to a read signal READb. That is, in order to perform a read operation of the non-volatile memory cell 410, a read signal READb having a "low" level can be applied to the gate of the fourth PMOS transistor MP44, and a select signal SG having a "low" level can be applied to the gate of the second PMOS transistor MP32. The select signal SG can be generated to be synchronized with the read signal READb. Both the second PMOS transistor MP32 and the fourth PMOS transistor MP44 can be turned on by the read signal READb having a "low" level and the select signal SG having a "low" level. Accordingly, the bit line voltage VBL induced at the bit line BL can be determined according to whether the third PMOS transistor MP33 serving as the non-volatile memory cell has an on cell state or an off cell state.

[0051] If the third PMOS transistor MP33 has an on cell state corresponding to a programmed state, the bit line voltage VBL induced at the bit line BL can have a ground voltage corresponding to a "low" level. Accordingly, as described in reference to Figure 16 the sense amplifier circuit 430 can output a dynamic supply voltage dVDD1 applied to the dynamic voltage supply line 450 as a sense output signal SA_OUT. That is, if the sense output signal SA_OUT output from the sense amplifier circuit 430 has the dynamic supply voltage dVDD1, the third PMOS transistor MP33 serving as the non-volatile memory cell can be regarded as a programmed cell. On the contrary, if the third PMOS transistor MP33 has an off cell state corresponding to an initial state, the bit line voltage VBL induced at the bit line BL can have a dynamic supply voltage dVDD1 corresponding to a "high" level. Accordingly, as described in reference to Figure 16 the sense amplifier circuit 430 can output a ground voltage as the sense output signal SA_OUT. That is, if the sense output signal SA_OUT output from the sense amplifier circuit 430 has a ground voltage, the third PMOS transistor MP33 serving as the non-volatile memory cell can be regarded as an unprogrammed cell having an initial state.

[0052] In the non-volatile memory device 400, the "low" level period of the read signal READb can be synchronized with the "low" level period of the first clock signal CK1 after the first "low" level period of the first clock signal CK1. In this case, as described in reference to Figure 2 and Figure 3As described, the dynamic supply voltage dVDD1 loaded on the dynamic voltage supply line 450 may have a supply voltage of "2×VDD". Therefore, if the third PMOS transistor MP33 has a programmed state, during a read operation, the second PMOS transistor MP32 of the non-volatile memory cell 410 and the fifth PMOS transistor MP65 of the sense amplifier circuit 430 must be fully turned on. According to this embodiment, since the dynamic supply voltage dVDD1 with a double supply voltage of "2×VDD" is applied to the second PMOS transistor MP32 of the non-volatile memory cell 410 and the fifth PMOS transistor MP65 of the sense amplifier circuit 430, a read interference phenomenon caused by a low supply voltage, which is less than the sum of the threshold voltages of the second PMOS transistor MP32 and the fifth PMOS transistor MP65 during a read operation, can be suppressed.

[0053] Figure 17 FIG. is a circuit diagram showing a non-volatile memory device 500 according to another embodiment of the present disclosure. Referring to Figure 17 FIG., the non-volatile memory device 500 may be configured to include a dynamic voltage supply circuit 300, a non-volatile memory cell 410, a resistive load 420, and a sense amplifier circuit 430. The dynamic voltage supply circuit 300 may have the same configuration as described in reference to Figure 13 FIG. The non-volatile memory cell 410, the resistive load 420, and the sense amplifier circuit 430 may also have the same configurations as described in reference to Figure 15 and Figure 16 FIG. Therefore, the non-volatile memory device 500 may differ from the non-volatile memory device 400 shown in Figure 15 FIG. in terms of the characteristics of the dynamic supply voltage dVDD2 output from the dynamic voltage supply circuit 300 and provided via the dynamic voltage supply line 550. The dynamic voltage supply line 550 may be coupled to the source of the fourth PMOS transistor MP44 constituting the resistive load 420 and the source of the fifth PMOS transistor MP65 included in the sense amplifier circuit 430.

[0054] In the non-volatile memory device 500 according to an embodiment, the "low" period of the read signal READb may be synchronized with the "low" period of the second clock signal CK2 after the first "low" period of the second clock signal CK2. In this case, as described in reference to Figure 13 and Figure 14As described, the dynamic supply voltage dVDD2 supplied via the dynamic voltage supply line 550 may have a supply voltage of "2×VDD". Therefore, if the third PMOS transistor MP33 is in a programmed state, during a read operation, the second PMOS transistor MP32 of the non-volatile memory cell 410 and the fifth PMOS transistor MP65 of the sense amplifier circuit 430 must be fully turned on. According to this embodiment, since the dynamic supply voltage dVDD2 having a supply voltage of "2×VDD" is applied to the second PMOS transistor MP32 of the non-volatile memory cell 410 and the fifth PMOS transistor MP65 of the sense amplifier circuit 430, a read interference phenomenon caused by a low supply voltage can be suppressed, the low supply voltage being less than the sum of the threshold voltages of the second PMOS transistor MP32 and the fifth PMOS transistor MP65 during a read operation.

[0055] For illustrative purposes, embodiments of the present disclosure have been disclosed above. Those of ordinary skill in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and spirit of the present disclosure as disclosed in the appended claims.

Claims

1. A dynamic voltage supply circuit, comprising: A first capacitor coupled between a supply line of a first clock signal and a first node; A second capacitor coupled between a supply line of a second clock signal and a second node; A first NMOS transistor having a gate coupled to the second node, a drain coupled to a supply voltage terminal, and a source coupled to the first node; And A second NMOS transistor having a gate coupled to the first node, a drain coupled to the supply voltage terminal, and a source coupled to the second node; A first PMOS transistor having a gate coupled to the supply line of the first clock signal, a drain coupled to an output line of a dynamic supply voltage, and a source coupled to the second node; And A third NMOS transistor having a gate coupled to the supply line of the first clock signal, a drain coupled to the output line of the dynamic supply voltage, and a source coupled to a ground voltage terminal.

2. The dynamic voltage supply circuit according to claim 1, wherein, A high-level period of the first clock signal does not overlap with a high-level period of the second clock signal.

3. The dynamic voltage supply circuit according to claim 2, wherein, The high-level periods of the first clock signal and the second clock signal are alternately generated.

4. A dynamic voltage supply circuit, comprising: A first capacitor coupled between a supply line of a first clock signal and a first node; A second capacitor coupled between a supply line of a second clock signal and a second node; A first NMOS transistor having a gate coupled to the second node, a drain coupled to a supply voltage terminal, and a source coupled to the first node; And A second NMOS transistor having a gate coupled to the first node, a drain coupled to the supply voltage terminal, and a source coupled to the second node; A first PMOS transistor having a gate coupled to the supply line of the second clock signal, a drain coupled to an output line of a dynamic supply voltage, and a source coupled to the first node; And A third NMOS transistor having a gate coupled to the supply line of the second clock signal, a drain coupled to the output line of the dynamic supply voltage, and a source coupled to a ground voltage terminal.

5. A non-volatile memory device, comprising: A first capacitor coupled between a supply line of a first clock signal and a first node; A second capacitor coupled between a supply line of a second clock signal and a second node; A first NMOS transistor having a gate coupled to the second node, a drain coupled to a supply voltage terminal, and a source coupled to the first node; And A second NMOS transistor having a gate coupled to the first node, a drain coupled to the supply voltage terminal, and a source coupled to the second node; A first PMOS transistor having a gate coupled to the supply line of the first clock signal, a drain coupled to an output line of a dynamic supply voltage, and a source coupled to the second node; And A third NMOS transistor having a gate coupled to the supply line of the first clock signal, a drain coupled to the output line of the dynamic supply voltage, and a source coupled to a ground voltage terminal; A non-volatile memory cell coupled between a bit line connected to a dynamic voltage supply line having the dynamic supply voltage and a ground voltage terminal; And A sense amplifier circuit configured to selectively output either the dynamic supply voltage or the ground voltage in response to a bit line voltage induced at the bit line.

6. The non-volatile memory device according to claim 5, wherein, The high-level period of the first clock signal does not overlap with the high-level period of the second clock signal.

7. The non-volatile memory device according to claim 6, wherein, The high-level periods of the first clock signal and the second clock signal are alternately generated.

8. The non-volatile memory device according to claim 5, wherein, The read operation of the non-volatile memory cell is performed during the low-level period of the first clock signal after the first low-level period of the first clock signal.

9. The non-volatile memory device according to claim 5, wherein, The non-volatile memory cell includes a second PMOS transistor and a third PMOS transistor; Wherein, the second PMOS transistor has a select gate to which a select signal is applied, a drain coupled to the source of the third PMOS transistor, and a source coupled to the bit line; and Wherein, the third PMOS transistor has a floating gate, a drain coupled to the ground voltage terminal, and a source coupled to the drain of the second PMOS transistor.

10. The non-volatile memory device according to claim 5, further comprising a resistive load coupled between the dynamic voltage supply line and the bit line.

11. The non-volatile memory device according to claim 10, wherein, The resistive load includes a fourth PMOS transistor having a gate to which a read signal is applied, a drain coupled to the bit line, and a source coupled to the dynamic voltage supply line.

12. The non-volatile memory device according to claim 5, wherein, The sense amplifier circuit includes: A fifth PMOS transistor having a gate coupled to the bit line, a drain coupled to a sense output signal line, and a source coupled to the dynamic voltage supply line; and A fourth NMOS transistor having a gate coupled to the bit line, a drain coupled to the sense output signal line, and a source coupled to the ground voltage terminal.

13. A non-volatile memory device, comprising: A first capacitor coupled between a supply line of the first clock signal and a first node; A second capacitor coupled between a supply line of the second clock signal and a second node; A first NMOS transistor having a gate coupled to the second node, a drain coupled to a supply voltage terminal, and a source coupled to the first node; And A second NMOS transistor having a gate coupled to the first node, a drain coupled to the supply voltage terminal, and a source coupled to the second node; A first PMOS transistor having a gate coupled to the supply line of the second clock signal, a drain coupled to an output line of the dynamic supply voltage, and a source coupled to the first node; A third NMOS transistor having a gate coupled to the supply line of the second clock signal, a drain coupled to the output line of the dynamic supply voltage, and a source coupled to the ground voltage terminal; A non-volatile memory cell coupled between a bit line connected to a dynamic voltage supply line having the dynamic supply voltage and a ground voltage terminal; And A sense amplifier circuit configured to selectively output either the dynamic supply voltage or the ground voltage in response to a bit line voltage induced at the bit line.

14. The non-volatile memory device according to claim 13, wherein, The read operation of the non-volatile memory cell is performed during the low-level period of the second clock signal after the first low-level period of the second clock signal.

15. The non-volatile memory device according to claim 13, wherein, The non-volatile memory cell includes a second PMOS transistor and a third PMOS transistor; wherein, the second PMOS transistor has a select gate to which a select signal is applied, a drain coupled to the source of the third PMOS transistor, and a source coupled to the bit line; and wherein, the third PMOS transistor has a floating gate, a drain coupled to the ground voltage terminal, and a source coupled to the drain of the second PMOS transistor.

16. The non-volatile memory device according to claim 13, further comprising a resistive load coupled between the dynamic voltage supply line and the bit line.

17. The non-volatile memory device according to claim 16, wherein, The resistive load includes a fourth PMOS transistor, which has a gate to which a read signal is applied, a drain coupled to the bit line, and a source coupled to the dynamic voltage supply line.

18. The non-volatile memory device according to claim 13, wherein, The sense amplifier circuit includes: a fifth PMOS transistor, which has a gate coupled to the bit line, a drain coupled to the sense output signal line, and a source coupled to the dynamic voltage supply line; and a fourth NMOS transistor, which has a gate coupled to the bit line, a drain coupled to the sense output signal line, and a source coupled to the ground voltage terminal.

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