LDMOS with diode-coupled isolation ring

Abstract

A method for increasing the breakdown voltage of a laterally diffused metal oxide semiconductor (LDMOS) includes biasing a first well of a field effect transistor (FET) to a first voltage. The first well is laterally separated from a second well. In response to the first voltage exceeding the breakdown voltage of a diode connected between the isolation ring and the first well, the isolation ring is charged to a second voltage. The isolation ring laterally surrounds the FET and contacts a buried layer (BL) extending below the first and second wells. A substrate is biased to a third voltage less than or equal to the first voltage. The substrate laterally extends below and contacts the BL.

Description

Technical Field

[0001] The present disclosure relates generally to high voltage semiconductor devices, and more particularly to laterally diffused metal oxide semiconductors (LDMOS). Background Art

[0002] In automotive, industrial, and consumer applications, there is an increasing demand for integrated high-voltage devices operating at higher voltages. To achieve high-side capability at an acceptable breakdown voltage, these devices can be surrounded by an isolation trench region formed by n-type well implants on the sides of the device and an n-type buried layer (NBL) extending below the device. In such designs, the device breakdown voltage is typically limited by the vertical junction between the NBL and the isolated p-type above it. For example, the breakdown voltage in an n-type LDMOS is typically determined by the junction between the body region and the underlying NBL isolation layer. However, the junction formed by the p-type drift region and the NBL often determines the breakdown voltage in a p-type LDMOS.

[0003] For conventional LDMOS, increasing the epitaxial layer thickness to improve device breakdown voltage can, however, create numerous manufacturing challenges. For example, increasing the epitaxial layer thickness makes it more difficult to form a robust electrical connection between the isolation ring and the NBL, and may require expensive, high-energy implantation tools. Furthermore, increasing the epitaxial layer thickness can reduce alignment accuracy or even cause alignment issues. Summary of the Invention

[0004] As will be appreciated, the disclosed embodiments include at least the following. In one embodiment, an LDMOS includes a FET comprising a source terminal, a body terminal connected to a body region, and a drain terminal connected to a drift region. The body region is laterally separated from the drift region. An isolation ring is positioned to laterally surround the FET. A buried layer (BL) is located below the FET and in contact with the isolation ring. A diode includes an anode and a cathode. The anode is electrically coupled to the isolation ring, and the cathode is electrically coupled to a region of the FET.

[0005] An alternative embodiment of the LDMOS includes one of the following features or any combination thereof. The FET is a p-type FET and the region of the FET is the body region. The FET is an n-type FET and the region of the FET is the drift region. The region of the FET includes an upper portion formed by an n-type well implant, and a lower portion formed by a p-type well implant disposed between the upper portion and the BL. An n-type implant is formed in the cathode, wherein the n-type implant has a higher doping concentration than the upper portion of the region of the FET. The BL includes a first portion located below the region of the FET and a second portion located below the region of the FET, wherein the second portion has a lower doping concentration relative to the first portion. A first thickness between the first portion and a silicon surface proximate to a gate oxide of the FET is less than a second thickness between the second portion and the silicon surface. Deep trench isolation is disposed to laterally surround the isolation ring. A p-type implant is disposed between the body region and the isolation ring.

[0006] In another embodiment, an LDMOS includes a FET having a source terminal, a body terminal connected to a body region, and a drain terminal connected to a drift region. An isolation ring is positioned to laterally surround the FET. A BL is positioned below the FET and contacts the isolation ring. A diode includes an anode and a cathode. The anode is electrically coupled to the isolation ring using a metal interconnect, and the cathode is electrically coupled to a region of the FET.

[0007] Alternative embodiments of the LDMOS include one of the following features or any combination thereof. The region of the FET includes an upper portion formed by an n-type well implant, and a lower portion formed by a p-type well implant disposed between the upper portion and the BL. An n-type implant is formed in the cathode, wherein the n-type implant has a higher doping concentration than the region of the FET. The BL includes a first portion located below the region of the FET and a second portion located below the region of the FET, wherein the second portion has a lower doping concentration relative to the first portion. A first thickness between the first portion and a silicon surface proximate a gate oxide of the FET is less than a second thickness between the second portion and the silicon surface. Deep trench isolation is disposed to laterally surround the isolation ring. A p-type implant is disposed between the body region and the isolation ring.

[0008] In another embodiment, a method for increasing the breakdown voltage of an LDMOS includes biasing a first well of a FET to a first voltage. The first well is laterally separated from a second well. In response to the first voltage exceeding the breakdown voltage of a diode connected between the isolation ring and the first well, the isolation ring is charged to a second voltage. The isolation ring laterally surrounds the FET and contacts a barrier (BL) extending below the first and second wells. A substrate is biased to a third voltage less than or equal to the first voltage. The substrate laterally extends below and contacts the BL.

[0009] Alternative embodiments of the method for increasing the breakdown voltage of an LDMOS include one or any combination of the following features: the FET is a PFET, the first well is a body region of the PFET, the second well is a drift region of the PFET, and charging the isolation ring to the second voltage increases the breakdown voltage of the PFET across a vertical junction between the BL and the drift region. the FET is an NFET, the first well is a drift region of the NFET, the second well is a body region of the NFET, and charging the isolation ring to the second voltage increases the breakdown voltage of the NFET across a vertical junction between the BL and the body region. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

[0011] Figure 1 is a cross-sectional view of a p-type LDMOS according to an example embodiment of the present disclosure.

[0012] Figure 2 It shows Figure 1 Partial plan view of the placement of a subset of the LDMOS mask layer.

[0013] Figure 3 is a graphical view showing the breakdown voltage (BV) characteristics of a p-type LDMOS in an “off” state.

[0014] Figure 4 is a graphical view showing the BV characteristics of a p-type LDMOS in an “on” state.

[0015] Figure 5 It is to compare the DC safe operating area (SOA) of conventional p-type LDMOS with Figure 1 A graphical view of the p-type LDMOS for comparison.

[0016] Figure 6is a cross-sectional view of an n-type LDMOS according to an example embodiment of the present disclosure.

[0017] Figure 7 is a graphical view showing the BV characteristics of an n-type LDMOS in an “off” state.

[0018] Figure 8 is a graphical view showing the effect of drain current on the left axis and transconductance on the right axis, comparing conventional n-type LDMOS with Figure 6 n-type LDMOS.

[0019] Figure 9 is a graphical view showing the BV characteristics of an n-type LDMOS in an “on” state.

[0020] Figure 10 It is to combine the DC SOA of conventional n-type LDMOS with Figure 6 A graphical view comparing n-type LDMOS.

[0021] Figure 11 is a cross-sectional view of an n-type LDMOS according to an example embodiment of the present disclosure.

[0022] Figure 12 is a flowchart representation of a method for increasing the breakdown voltage of an LDMOS according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] Various embodiments described herein provide an LDMOS with an improved breakdown voltage by dynamically biasing the isolation tank region. The isolation tank region is formed by an isolation ring surrounding the LDMOS and connected to a buried layer extending below the LDMOS. The isolation ring of the LDMOS is electrically coupled to the anode of an integrated diode. This diode is positioned outside the device operating region and consists of a p+ active region and an n-type region (for example, a body region in a p-type LDMOS and a drift region in an n-type LDMOS, respectively, which are typically biased at a high potential during device operation). Such a configuration reduces the potential on the isolation ring by a value equal to or greater than the diode breakdown voltage, which results in an increase in the breakdown voltage of the LDMOS. The biased isolation tank region reduces the potential difference across the critical breakdown region between the buried layer and the well of the LDMOS disposed vertically above the buried layer. Other variations of the LDMOS embodiments described herein are achievable using similar diodes coupled to the isolation ring.

[0024] Figure 1An example embodiment 10 of a p-type LDMOS according to the present disclosure is shown. Embodiment 10 is formed on a p-type substrate 12. An N-type buried layer (NBL) 14 is formed above and in contact with p-type substrate 12. In one embodiment, p-type substrate 12 is grounded using a connection to a ground terminal (not shown), and the NBL is charged to a voltage equal to or greater than ground. In embodiment 10, a lightly doped NBL (LNBL) 16 is formed above and in contact with a portion of p-type substrate 12. An isolation ring is formed to surround the field effect transistor (FET) of embodiment 10 by forming a vertical structure including a deep n-well 18 on top of NBL 14 and an n-well 20 on top of deep n-well 18. The isolation ring, together with NBL 14 and LNBL 16, forms an isolation trench region to enable high voltage operation. In one embodiment, NBL 14 extends the entire width of the underlying p-type substrate 12, rather than forming LNBL 16. In another embodiment, deep trench isolation (DTI) (not shown) surrounds the isolation ring to increase integration density.

[0025] An n+ region 22, covered by silicide 24, is formed on n-well 20 to allow a low-impedance connection to the isolation ring. A p-type epitaxial layer 26 is formed above NBL 14 and LNBL 16, with a first thickness 27 between NBL 14 and the silicon surface near the gate oxide of the NFET being less than a second thickness 28 between LNLB 16 and the silicon surface. The body region of the FET is formed by a chain implant of an ultra-high voltage N-well (UHVNW) and includes an upper portion 30 (UHVNW-N) and a lower portion 32 (UHVNW-P). Lower portion 32 helps to vertically separate the body region, formed in part by upper portion 30, from the isolation trench region, which enables a different biasing of the body region from the isolation trench region.

[0026] The drift region of the FET is formed by an ultrahigh voltage P-well (UHVPW) 34. The LNBL 16 extends beneath the UHVPW 34. The region between the UHVPW 34 and the LNBL 16 forms a vertical junction, which is also the critical breakdown region of the FET. In various embodiments, the LNBL 16 is deeper and more lightly doped than the NBL 14, thereby increasing the breakdown voltage across the vertical junction between the UHVPW 34 and the LNBL 16.

[0027] The drift region of the FET is further limited by shallow trench isolation (STI) 36. A gate 40 is formed over a gate oxide 42 that extends across the body region and the drift region. The gate 40 is covered by silicide 44 to facilitate a low-impedance connection to the gate 40. Sidewall spacers 46 and 48 are formed on either side of the gate 40. The UHVPW 34 of the drift region is contacted by a p+ region 50 covered by silicide 52. In one embodiment, the drain terminal of the FET is connected to the silicide 52.

[0028] A p+ region 54 and an n+ region 56 are each formed to contact the upper portion 30 of the body region and are covered by silicide 58. In one embodiment, the source terminal of the FET is connected to the p+ region 54, and the body terminal of the FET is connected to the n+ region 56, where the source and body terminals are shorted together. In another embodiment, the source and body terminals are separated by STI or other isolation schemes. In another embodiment, a p-type lightly doped drain (PLDD) 60 and a p-type extension (PEXT) 62 are formed adjacent to the p+ region 54.

[0029] A p+ region 64 covered by silicide 66 is formed on a high voltage N-well (HVNW) region 68, thereby forming a diode. Specifically, p+ region 64 forms the anode of the diode, and HVNW region 68 forms the cathode of the diode. HVNW region 68 prevents depletion of upper portion 30 by providing a greater n-type doping concentration adjacent to p+ region 64. In another embodiment, HVNW region 68 is removed for simplicity, and a diode is formed using p-type region 64 and upper portion 30.

[0030] Metal interconnect 70 connects silicide region 24 of n+ region 22 (e.g., isolation trench region) to silicide region 66 of p+ region 64 (e.g., anode). The diode formed by p+ region 64 and HVNW region 68 is laterally displaced from the FET operating region (e.g., partially including n+ region 56, p+ region 54, and the region below gate 40) by STI 72, which forms a lateral extension of the body region. STI 74 separates the isolation ring (e.g., partially formed by n+ region 22) from the diode (e.g., partially formed by p+ region 64). In one embodiment, STI 76 is also formed adjacent to n+ region 22.

[0031] High voltage P-well (HVPW) 78 further provides isolation between the body region formed by upper portion 30 and the isolation ring, as the body region and the isolation ring can operate at different potentials. In another embodiment, one or more of STI regions 36, 72, 74, and 76 are replaced by a different isolation scheme, such as a silicide barrier layer.

[0032] Figure 2 Shown Figure 1 , to further illustrate the relationship between the isolation ring, the diode, and the FET device. Embodiment 90 includes a first drain 92 and a second drain 94. A source region 96 is connected to the source terminal using source contacts 98, 100, and 102. In one embodiment, each of the source contacts includes a body contact, wherein each source contact is electrically shorted to the corresponding body contact. A first transistor 104a is formed between source contact 98 and the first drain 92 using a first gate finger (not shown). A second transistor 104b is formed between source contact 100 and the first drain 92 using a second gate finger (not shown). A third transistor 104c is formed between source contact 100 and the second drain 94 using a third gate finger (not shown). A fourth transistor 104d is formed between source contact 102 and the second drain 94 using a fourth gate finger (not shown).

[0033] An isolation ring 106 laterally surrounds four transistors 104a, 104b, 104c, and 104d (collectively, 104). Isolation ring 106 is connected to the anodes of diodes formed by corresponding p+ regions 108a, 108b, 108c, and 108d (collectively, 108) via corresponding metal interconnects 110a, 110b, 110c, and 110d (collectively, 110). The total length of p+ regions 108 scales with device geometry (e.g., the width of transistor 104 and the number of gate fingers), which enhances the isolation ring's response to bulk voltage.

[0034] Figure 3 、 Figure 4 and Figure 5 The breakdown characteristics of the p-type LDMOS improved by the present disclosure are shown. Figure 3 The IV curves between the conventional structure 132 and the new p-type LDMOS 134 with an integrated diode coupling the body potential to the isolation ring (and thus to the isolation tank region) are compared. Figure 3 The IV curve is measured in the "off" state, where the gate is set equal to the source voltage (e.g., disconnected), and the vertical axis represents the leakage current between the source and the drain. The IV curve compares the drain current through the FET formed by the corresponding LDMOS structure with the voltage drop measured across the source and drain terminals of the FET. Figure 3 The IV curve of the enhanced LDMOS 134 is shown to have a breakdown voltage of 126V compared to 115V for the conventional structure 132, even though both structures have the same accumulation length, drift length, epitaxial layer 26, and similar polysilicon and metal stacks.

[0035] As reference Figure 1 and Figure 3 As shown, when a source voltage of 0V is applied to the body region via p+ region 54, the potential of the isolation trench region is initially defined by the ground potential of p-type substrate 12 and p-type epitaxial layer 26 above NBL 14. In other embodiments, p-type substrate 12 is biased to a low reference that is less than or equal to the lowest voltage applied to the body region. As the potential of the body region increases, the voltage difference between HVNW region 68 and p+ region 64 reaches or exceeds the reverse breakdown voltage of the diode formed therein, thereby maintaining the potential of the isolation trench region within one reverse diode drop of the body potential until the vertical junction between LNBL 16 and UHVPW drift region 34 breaks down. As a result, the new device exhibits a higher breakdown voltage, equivalent to the reverse diode breakdown voltage formed by p+ region 64 and HVNW region 68. Due to the lower threshold voltage of the new LDMOS 134, the device has slightly higher leakage current than the conventional LDMOS 132. The lower threshold voltage of the new LDMOS 134 is attributed to the different heavily doped shallow implants placed in the channel region on the source side.

[0036] The IV characteristics of the LDMOS in the "off" state are shown. Figure 3 compared to, Figure 4 The IV characteristics are shown in the "on" state, where the gate 40 is biased to form a channel between the source and drain. Figure 4 , curves 140, 142, 144, 146, and 148 are plotted for increasing absolute values ​​of gate bias for the conventional LDMOS. Curves 150, 152, 154, 156, and 158 are plotted for increasing values ​​of gate bias for the new LDMOS, each showing a higher breakdown voltage than the corresponding curve for the conventional LDMOS.

[0037] Figure 5 Shown Figure 4 The DC SOA for the conventional LDMOS 160 is compared to the DC SOA for the new LDMOS 162. For example, referring to Figure 4 and Figure 5 Both, Figure 4 Curve 146 for a conventional LDMOS in FIG shows a peak current occurring at 135 V just before vertical junction breakdown, which is similarly plotted in FIG. Figure 5 The new device exhibits improved DC SOA, especially at high gate voltages. The “on” state breakdown voltage also becomes less sensitive to gate potential.

[0038] Continue to refer Figure 1 , Figure 6 Another example embodiment 170 of an n-type LDMOS according to the present disclosure is shown. Figure 1 and Figure 6 The isolation trench region, p-type epitaxial layer, anode of the diode and the connections thereto are identical. Therefore, for the sake of brevity, their description will not be repeated. Figure 1 and Figure 6 Elements with the same element number between the two are similar in function, but it should be understood that the order in which these elements are formed is not determined by Figure 1 or Figure 6 hint.

[0039] The drift region of embodiment 170 is formed by a chain implant of UHVNW and includes an upper portion 172 (UHVNW-N) and a lower portion 174 (UHVNW-P). Lower portion 174 helps to vertically separate the drift region, which is partially formed by upper portion 172, from the isolation trench region, thereby achieving a different bias on the drift region from the isolation trench region. In one embodiment, lower portion 174 is a reduced surface field (RESURF) region.

[0040] The body region of embodiment 170 is formed by a p-type high voltage (PHV) implant 176. LNBL 16 extends beneath PHV 176. The region between PHV 176 and LNBL 16 forms a vertical junction, which is also the critical breakdown region for n-type FETs formed from n-type LDMOS. In various embodiments, LNBL 16 is deeper and more lightly doped than NBL 14, thereby increasing the breakdown voltage across the vertical junction between PHV 176 and LNBL 16. In another embodiment, NBL 14 extends across the entire width of p-type substrate 12, and LNBL 16 is not formed.

[0041] A gate 178 is formed over a gate oxide 180 that extends across the accumulation region and the bulk region. Gate 178 is covered by a silicide 182 to facilitate a low-impedance connection to gate 178. Sidewall spacers 184 and 186 are formed on either side of gate 178. The upper portion 172 of the drift region is contacted by an n+ region 190 covered by a silicide 192 and separated from the p+ region 64 (e.g., an anode) by STI 194. In one embodiment, the drain terminal of the n-type FET is connected to the silicide 192. The drift region of the n-type FET is further confined by shallow trench isolation (STI) 196.

[0042] A high voltage N-type lightly doped drain (HVNLDD) implant 198 is formed adjacent to the N+ region 200. The n+ region 200 is adjacent to the p+ region 202. The silicide extends across the n+ region 200 and the p+ region 202 to form a low impedance connection. In one embodiment, the source terminal of the n-type FET is connected to the n+ region 200, and the body terminal of the n-type FET is connected to the p+ region 202, where the source terminal and the body terminal are shorted together. In another embodiment, the source terminal and the body terminal are separated by STI or other isolation schemes. In another embodiment, one or more of the STI regions 74, 76, 194 and 196 are replaced by a different isolation scheme, such as a silicide barrier layer. In another embodiment, deep trench isolation (DTI) (not shown) surrounds the isolation ring to increase integration density.

[0043] Figure 7 、 Figure 9 and Figure 10 The breakdown characteristics of the n-type LDMOS improved by the present disclosure are shown. Figure 7 The IV curves are compared between a conventional structure 212 and an n-type LDMOS 214 with an integrated diode coupling the drain potential to the isolation ring. Figure 7 The IV curve is measured in the "off" state, where the gate is set equal to the source voltage (e.g., disconnected), and the vertical axis represents the leakage current between the source and the drain. The IV curve compares the drain current through the FET formed by the corresponding LDMOS structure with the voltage drop measured across the source and drain terminals of the FET. Figure 7 As shown, the IV curve of the enhanced LDMOS 214 has a breakdown voltage of 108 V compared to 85 V for the conventional structure 212 , even though both structures have the same accumulation length, drift length, epitaxial layer 26 , and similar polysilicon and metal stacks.

[0044] As reference Figure 6 and Figure 7 As shown, when the drain voltage applied to the drift region through n+ region 190 is initially 0V, the potential of the isolation trench region is initially defined by the ground potential of p-type substrate 12 and p-type epitaxial layer 26 above NBL 14. In other embodiments, p-type substrate 12 is biased to a low reference that is less than or equal to the lowest voltage applied to the drain region. As the potential of the drift region increases, the voltage difference between upper portion 172 and p+ region 64 reaches or exceeds the reverse breakdown voltage of the diode formed therein, thereby maintaining the potential of the isolation trench region within one reverse diode drop of the drift region potential until the vertical junction between LNBL 16 and PHV body region 176 breaks down. As a result, the new device exhibits a higher breakdown voltage that is equivalent to or greater than the breakdown voltage of the reverse diode formed by p+ region 64 and upper portion 172.

[0045] At moderate bias in the drift region, the isolation ring maintains a voltage equal to the reduced reverse diode breakdown voltage of the drift region. However, when the bias in the drift region is high, but low enough to prevent breakdown of the vertical junction, the n-type region of the upper portion 172 between the drain contact (formed by n+ region 190) and the anode (e.g., p+ region 64) is depleted by the adjacent p-type region. Consequently, an additional voltage drop occurs between the drain contact and the anode, further increasing the device breakdown voltage across the vertical junction.

[0046] Figure 8 The transconductance of the conventional n-type LDMOS 220 is compared with the transconductance of the new n-type LDMOS 222 shown on the right axis. Figure 8 Additionally, drain current is compared for conventional n-type LDMOS 224 and new n-type LDMOS 226, shown on the left axis. Both the drain current comparison and the transconductance comparison demonstrate that the "on" resistance from drain to source (eg, RDSon) is unaffected by the biasing configuration of the isolation ring.

[0047] The IV characteristics of the LDMOS in the "off" state are shown. Figure 8 compared to, Figure 9 The IV characteristics are shown in the "on" state, where the gate 178 is biased to form a channel between the source and drain. Figure 9 , curves 230, 232, 234, 236, and 238 are plotted for increasing values ​​of gate bias for the conventional LDMOS. Curves 240, 242, 244, 246, and 248 are plotted for increasing values ​​of gate bias for the new LDMOS, showing each curve having a higher breakdown voltage than the corresponding curve for the conventional LDMOS.

[0048] Figure 10 Shown Figure 9 The DC SOA for the conventional LDMOS 250 compared to the new LDMOS 252. For example, refer to Figure 9 and Figure 10 Both, Figure 9 Curve 240 for the new LDMOS in FIG shows a peak current occurring at 147 V just before vertical junction breakdown, which is similarly plotted at Figure 10 On curve 252.

[0049] Continue to refer Figure 6 , Figure 11 Another embodiment 260 of an n-type LDMOS according to the present disclosure is shown. The Kirk effect is known to deteriorate the SOA in many n-type LDMOS devices. To alleviate this problem, in some embodiments, a heavily doped n-type well implant HVNW 262 is added to the drain active region. Figure 11 A cross section of an n-type LDMOS is shown with a HVNW 262 implemented in the drain active area and around the p+ region 64 and in the region between the drain contact (n+ region 190) and the anode (p+ region 64). In this embodiment 260, depletion is no longer as Figure 6 As in the case of embodiment 170, the isolation ring is located along the n-type region between the drain contact and the anode. Therefore, the potential of the isolation ring is less than the drain voltage by a constant value equal to the reverse breakdown voltage of the diode. In this embodiment, the FET is isolated from the adjacent circuitry by NBL 14. In other embodiments, as Figure 6 The LNBL 16 or the combination of the NBL 14 and the LNBL 16 is shown to form the isolation trench region.

[0050] Figure 12 A method 270 for increasing the breakdown voltage of an LDMOS according to the present disclosure is shown. At 272, a first well of a FET is biased to a first voltage. In one example embodiment, the first well is Figure 1 in the upper portion 30 of the body region of the p-type FET or Figure 6 At 274, the isolation ring is charged to a second voltage via a diode connected between the isolation ring and the first well. The diode is connected to the upper portion 172 of the drift region of the n-type FET in FIG. Figure 1 The p+ region 64 and the HVNW region 68 are formed by Figure 6 The p+ region 64 and the upper portion 172 are formed. At 276, the substrate 12 is biased to a third voltage less than or equal to the first voltage. The substrate 12 contacts the buried layer NBL 14 and the LNBL 16 below the FET. The buried layer 14 contacts the isolation ring (e.g., formed in part by 18 and 20). The isolation ring increases the breakdown voltage between the buried layer LNBL 16 and the second well of the FET. In an example embodiment, the second well is Figure 1 The UHVPW region 34 in the drift region of the p-type FET or Figure 6 The PHV region 176 of the body region of the n-type FET.

[0051] Although the present invention has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the present invention as set forth in the claims below. Therefore, the specification and drawings should be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions described herein with respect to specific embodiments are not intended to be construed as a key, required, or essential feature or element of any or all the claims.

[0052] Unless stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Therefore, these terms are not necessarily intended to indicate temporal or other prioritization of these elements.

Claims

1. A laterally diffused metal oxide semiconductor (LDMOS), characterized in that: include: a field effect transistor (FET), the FET comprising a source terminal, a body terminal connected to a body region, and a drain terminal connected to a drift region, the body region being laterally separated from the drift region; an isolation ring positioned to laterally surround the FET; a buried layer BL, the BL being located below the FET and contacting the isolation ring; as well as A diode includes an anode and a cathode, the anode electrically coupled to the isolation ring and the cathode electrically coupled to the N-type well region of the FET; wherein the diode is laterally separated from the isolation ring by shallow trench isolation.

2. The LDMOS according to claim 1, wherein: The N-type well region of the FET includes an upper portion formed by an n-type well implant, and a lower portion formed by a p-type well implant disposed between the upper portion and the BL.

3. The LDMOS according to claim 1, wherein: The BL includes a first portion located below the N-type well region of the FET and a second portion located below the N-type well region of the FET, wherein the second portion has a lower doping concentration than the first portion.

4. A laterally diffused metal oxide semiconductor (LDMOS), characterized in that: include: a field effect transistor FET, the FET comprising a source terminal, a body terminal connected to the body region, and a drain terminal connected to the drift region; an isolation ring positioned to laterally surround the FET; a buried layer BL, the BL being located below the FET and contacting the isolation ring; as well as a diode comprising an anode and a cathode, the anode being electrically coupled to the isolation ring using a metal interconnect, and the cathode being electrically coupled to an N-type well region of the FET; The diode and the isolation ring are laterally separated by shallow trench isolation.

5. The LDMOS according to claim 4, wherein: The N-type well region of the FET includes an upper portion formed by an n-type well implant, and a lower portion formed by a p-type well implant disposed between the upper portion and the BL.

6. The LDMOS according to claim 4, wherein: The BL includes a first portion located below the N-type well region of the FET and a second portion located below the N-type well region of the FET, wherein the second portion has a lower doping concentration than the first portion.

7. The LDMOS according to claim 4, wherein: Additionally included is a p-type implant positioned between the N-well region of the FET and the isolation ring.

8. A method for increasing the breakdown voltage of a laterally diffused metal oxide semiconductor (LDMOS), characterized in that: include: biasing a first well of a field effect transistor FET to a first voltage, the first well being laterally separated from a second well; charging the isolation ring to a second voltage in response to the first voltage exceeding a breakdown voltage of a diode connected between the isolation ring and the first well and laterally separated from the isolation ring by shallow trench isolation, the isolation ring laterally surrounding the FET and contacting a buried layer BL extending below the first well and the second well; as well as A substrate is biased to a third voltage less than or equal to the first voltage, the substrate extending laterally below and contacting the BL.

9. The method according to claim 8, characterized in that The FET is a P-channel FET (PFET), the first well is a body region of the PFET, the second well is a drift region of the PFET, and charging the isolation ring to the second voltage increases a breakdown voltage of the PFET across a vertical junction between the BL and the drift region.

10. The method according to claim 8, characterized in that The FET is an N-channel FET (NFET), the first well is a drift region of the NFET, the second well is a body region of the NFET, and charging the isolation ring to the second voltage increases a breakdown voltage of the NFET across a vertical junction between the BL and the body region.

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