Data encoding on the serial bus

Abstract

The present disclosure relates to data encoding on a serial bus. A method for encoding a data value to be transmitted on an SPI serial bus includes an operation for modifying a status register of a memory according to all or part of the data value to be transmitted at least at a selected time.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of French patent application 1903929 filed on April 12, 2019, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present description relates generally to electronic circuits and, more particularly, to systems in which multiple circuits can communicate over a serial bus. Background Art

[0004] Serial buses have been widely implemented to allow multiple electronic circuits of the same system to communicate with each other. For example, in automobiles, computers often use serial buses to allow microprocessors to read or write information in non-volatile memory throughout the use of the vehicle.

[0005] There is a need to extend current communication capabilities via serial buses. It is particularly desirable to be able to exploit the existence of a serial bus to enable encoding of additional information that can be transmitted independently of the usual communication channel.

[0006] There is a need in the art to overcome all or some of the disadvantages of known methods for encoding data on a serial bus. Summary of the invention

[0007] One embodiment provides a method for encoding a data value to be transmitted on an SPI serial bus, wherein a status register of a memory is modified at least at a selected time according to all or part of the data value to be transmitted.

[0008] According to one embodiment, the memory is a reprogrammable non-volatile memory.

[0009] According to one embodiment, the status register is modified by inverting the state of a latch bit of the memory in write mode.

[0010] According to one embodiment, the status register is modified during a write cycle of the memory.

[0011] According to one embodiment, the status register is modified only once during a write cycle in the memory, the data value to be transmitted forming a bit.

[0012] According to one embodiment, the status register is modified a number of times during a write cycle in the memory, the data value to be transmitted forming a word comprising at least two bits.

[0013] According to one embodiment, during a write cycle in the memory, the number of modifications of the status register is related to the number of state transitions between successively transmitted bits of a word.

[0014] According to one embodiment, the data value to be transferred represents the wear of the memory.

[0015] According to one embodiment, the data value to be transmitted reflects the number of error corrections performed in the memory.

[0016] One embodiment provides a method comprising: starting writing in a memory; periodically sending a status register of the memory; modifying the status register of the memory at the given time to encode all or part of the data value to be transmitted; and stopping writing in the memory.

[0017] One embodiment provides an electronic circuit configured to implement the described method.

[0018] One embodiment provides a non-volatile memory comprising a state register configured to be modified by implementation of the described method. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above-mentioned features and advantages and other features and advantages will be described in detail in the following description of specific embodiments, which are given by way of example and not limitation, with reference to the accompanying drawings, in which:

[0020] Figure 1 An embodiment of an electronic circuit is shown very schematically in block diagram form;

[0021] Figure 2 An example of a status register of a memory is shown;

[0022] Figure 3 is a sequence diagram of an embodiment of operations associated with a data write cycle in a memory via a serial bus;

[0023] Figure 4 A mode of implementation of a method for encoding a data value to be transmitted via a serial bus is shown; and

[0024] Figure 5 A further mode of realization of a method for encoding a data value to be transmitted via a serial bus is shown. DETAILED DESCRIPTION

[0025] In the various drawings, similar features are represented by similar reference numerals. In particular, common structural and / or functional features between various embodiments may have the same reference numerals, and may be arranged with the same structure, dimensions, and material properties.

[0026] For the sake of clarity, only the operations and elements useful for understanding the embodiments described herein are shown and described in detail. In particular, the generation of signals according to the data to be transmitted on the serial bus and the reception of these signals by the receiving circuit are not described in detail, and the described embodiments and implementation modes are compatible with conventional transmissions between two or more circuits via a serial bus.

[0027] Unless otherwise specified, when referring to two elements being connected together, it means a direct connection without any intermediate elements other than conductors; and when referring to two elements being linked or coupled together, it means the two elements may be connected or may be linked or coupled via one or more other elements.

[0028] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers (such as terms "front", "back", "top", "bottom", "left", "right", etc.) or relative position qualifiers (such as terms "above", "below", "higher", "lower", etc.) or orientation qualifiers (such as "horizontal", "vertical", etc.), reference is made to the orientation shown in the figure.

[0029] Unless otherwise indicated, the expressions "about," "approximately," "substantially," and "approximately" mean within 10%, preferably within 5%.

[0030] Figure 1 An embodiment of an electronic circuit 1 of the type to which the described mode of implementation is applicable is shown very schematically in the form of a block diagram.

[0031] According to this embodiment, the electronic circuit 1 includes: one or more digital processing units (PUs) 11 of the type such as finite state machines, microprocessors, programmable logic circuits, etc.; one or more volatile (RAM) and / or non-volatile (NVM) storage memories 12, 13 for data and programs; one or more buses 14 for data, addresses and / or commands between various elements inside the electronic circuit 1; one or more input / output (I / O) interfaces 15 for communicating with the outside of the circuit; and Figure 1 Various other circuits in accordance with the functionality of the present application are represented by block 16 (FCT).

[0032] In most applications, the memory 13 may be used to record or store information, parameters, calculation results, etc. specific to the operation of the electronic circuit 1. The memory 13 is typically in communication with one or more other elements of the system, if applicable. Figure 1 In the example of , consider that the memory 13 exchanges data with the digital processing unit 11, which reads or writes information in the memory 13. For example, the memory 13 is an electrically erasable programmable read-only memory (EEPROM).

[0033] exist Figure 1 In the embodiment of the present invention, the bus 14 allows the transmission of data, in particular between the digital processing unit 11 and the memory 13. Thus, the digital processing unit 11 can communicate with the memory 13 by sending requests, instructions or operation codes (opcodes) via the bus 14. These operation codes are usually standardized according to the bus 14 selected to realize the data transmission. The bus 14 is usually a serial bus, for example a synchronous serial data bus of the SPI (Serial Peripheral Interface) type.

[0034] In the case where the bus 14 is an SPI bus, the digital processing unit 11 can specifically send an operation code denoted as "RDSR" to the memory. Due to the RDSR operation code, the digital processing unit 11 can read the status register of the memory 13. In response to the reception of the RDSR operation code, the content of the status register is returned by the memory 13 to the digital processing unit 11. The status register specifically indicates the operation that is allowed or in the process of being executed in the memory 13. For simplicity, unless otherwise stated, the register of the memory is compared to the content of the register hereinafter.

[0035] Figure 2 An example of a memory status register 2 is shown.

[0036] exist Figure 2 In the example of Figure 1 The status register (SR) 2 of the memory 13 in the example generally assumes the form of a byte consisting of the following eight bits: one bit 20 (WIP - Write In Progress) which is configured to indicate that a write operation is in progress in the memory; one bit 21 (WEL - Write Enable Latch) which is used to latch the memory in write mode; two bits 22 and 23 (BP0 - Block Protection 0 and BP1 - Block Protection 1) which in combination are configured to define an area, range or quadrant of the memory that is desired to be protected in write mode; three bits 24, 25 and 26 whose values ​​are arbitrarily set to 0 in this example; and one bit 27 (SRWD - Status Register Write Disable) which is configured to prohibit writing to the status register 2 of the memory.

[0037] It is usually undesirable that bits 22 to 27 of the status register 2 of a memory are modified during normal use of a product equipped with the memory. Therefore, a predefined value is usually assigned to each of bits 22 to 27 at the factory. Most of the time, the value of each of bits 22 to 27 is therefore "hardwired" by the device manufacturer that implements such a memory. As a specific exemplary application, in the automotive field, the manufacturer is, for example, a device manufacturer that supplies an on-board computer or an electronic control unit (ECU) to a vehicle manufacturer.

[0038] In contrast, bits 20 and 21 (WIP and WEL, respectively) of status register 2 have values ​​that typically need to be changed during normal use of a product equipped with such a memory. In particular, the values ​​of the WIP and WEL bits are modified throughout a write cycle performed on the memory.

[0039] By arbitrary convention, 0 or 1 represents the corresponding state of a bit, regardless of the levels represented by these states, for example, "high" and "low".

[0040] For example, assume that the values ​​of the WIP and WEL bits are initially equal to 0, and it is desired to perform a write cycle in the memory. The values ​​of the WIP and WEL bits of the status register 2 of the memory are then typically modified in the following manner: the WEL bit is set to state 1, which indicates that a write cycle in the memory has been authorized; from the beginning of the write cycle, the value of the WIP bit switches to state 1 to indicate that a write operation is in progress in the memory; during the write cycle in the memory, the WEL bit is set to state 0; and after the write cycle is completed, the WIP bit is set to state 0.

[0041] Figure 3 is a sequence diagram of an embodiment of operations associated with a data write cycle in a memory via a serial bus.

[0042] According to this embodiment, the digital processing unit ( Figure 1 11) through the serial bus ( Figure 1 14) coupled, preferably connected to a memory ( Figure 1 13 in ). Assume that the digital processing unit needs to write data in the memory, for example to save information, store calculation results, etc. For simplicity, we mainly look at the operations that occur on the memory side.

[0043] exist Figure 3 In the example of FIG. 1 , for a digital processing unit, a first step (block 301, memory selection) consists in selecting a memory in which one or more data values ​​are desired to be written. The memory then receives (block 311, receive WREN command) an operation code denoted as "WREN" from the digital processing unit. The operation code WREN preceding the actual write operation enables a write operation to be performed in the memory. The memory is then deselected by the digital processing unit (block 302, memory deselection). Then, in write mode, the WEL latch bit of the memory enters state 1 (block 321, WEL=1).

[0044] Then, the digital processing unit selects the memory again (block 303, memory selection). Once the memory is selected, the memory receives a write command sent by the digital processing unit (block 312, receive write command). For example, the write command includes: an operation code byte; two address bytes; and a certain number of bytes constituting one or more data values ​​to be written in the memory.

[0045] Next, the memory is deselected by the digital processing unit (block 304, memory deselection). The deselection of the memory leads to the start of the actual write cycle in the memory (block 331, start data writing). Then, the bit WIP enters state 1 (block 323, WIP=1). At the end of the actual write operation (block 333, end data writing), the bit WIP returns to state 0 (block 325, WIP=0).

[0046] According to a preferred embodiment, in parallel with the above-described write operation, that is to say, within the duration separating blocks 331 and 333, the memory is again selected by the digital processing unit (block 305, memory selection). The memory then receives (block 313, receive RDSR command) another operation code denoted as "RDSR" from the digital processing unit. The operation code RDSR constitutes a continuous transmission request from the status register of the memory. On receipt of the operation code RDSR, the memory, in return, starts to transmit its status register to the processing unit (block 351, SR byte output).

[0047] According to a preferred embodiment, the memory repeatedly sends (block 351) (at each clock event) its status register via the serial bus as long as the memory remains selected by the digital processing unit (or another circuit that selects the memory). This selection is de-correlated with the actual write operation (blocks 331, 323 and 333), the memory being selected by a binary signal distinct from the bus. Figure 3 In the example of , once the write operation is completed, that is, when the bit WIP returns to state 0 (block 325), the processing unit commands the deselection of the memory (block 306, memory deselection). The deselection of the memory interrupts the repeated transmission of the status register of the memory (block 353, end of SR byte output).

[0048] During the phase in which the bit WIP is in state 1 and the memory is selected, the memory therefore repeatedly sends its status register (block 351). In other words, the status register is sent cyclically or periodically while write cycles occur in the memory, while the memory is still selected by the processing unit (block 35). This therefore allows the digital processing unit to control the evolution of the status register.

[0049] According to a preferred embodiment, the status register of the memory is transmitted synchronously with respect to a synchronization signal or clock signal for controlling the timing of data transmission via the serial bus. For example, for a data transmission with a frequency of 1 MHz, a minimum duration of 8 μs separates each transmission by the memory of the bytes constituting the status register. Still according to this example, during a write cycle with a total duration of 3 ms, the status register can therefore theoretically be transmitted 375 times by the memory. Taking into account a write cycle between 1 ms and 4 ms, the status register can theoretically be transmitted at least 125 times and at most 500 times.

[0050] Typically, at any time during the execution of a data write operation, the bit WEL of the memory status register is reset. Figure 3 The updating of the status register of the memory and its reading by the digital processing unit during the entire write operation can indeed control the moment when the value of the WEL bit returns to 0.

[0051] An advantage of this embodiment is that it allows backward compatibility with existing communication circuits and methods using the SPI serial bus. In fact, the memory ( Figure 1 13) is compatible with standard applications. Figure 3 The described embodiments may thus be implemented in existing circuits without disrupting their operation.

[0052] Figure 4 A mode of realization of a method for encoding a data value to be transmitted via a serial bus is shown.

[0053] According to this implementation mode, if combined with Figure 3 As described, a write cycle is considered, during which the memory repeatedly sends its status register 2 as long as a write operation is in progress. For simplicity, only bits 20 (WIP) and 21 (WEL) of the byte forming the status register 2 of the memory are considered. In this example, it is considered that the values ​​of the other bits 22 to 27 do not undergo any other evolution throughout the write cycle, and bits 20 and 21 represent the least significant bits of the status register 2.

[0054] During the write operation, assume that the state register 2 of the memory is updated and sent n times. In other words, it is assumed that after the block 351 ( Figure 3 ) and box 353 ( Figure 3 ) separates the duration of the memory status register, the repeated transfer ( Figure 3 Box 351) is performed n times.

[0055] Still according to this example, the writing operation in the memory occurs between the first iteration stage 1 and the last iteration stage n. Figure 4 This leads to the fact that between these two iterations the value of the bit WIP remains equal to 1, which indicates that a write operation is being performed. After the last iteration stage n, the WIP bit is set to state 0. Figure 4 This constitutes the final step, stage n+1.

[0056] exist Figure 4 In the example of , for the sake of simplicity, only six intermediate iterations, stage 2, stage 3, stage k-1, stage k, stage k+1 and stage n-1, are considered. Still in this example, these six intermediate iterations are inserted continuously between the first iteration stage 1 and the last iteration stage n. Other iterations (not shown) can also be inserted between iteration stage 3 and stage k-1 on the one hand and / or between iteration stage k+1 and stage n-1 on the other hand. In other words, the iterations occur in the following order in time: stage 1, stage 2, stage 3, ..., stage k-1, stage k, stage k+1, ..., stage n-1 and stage n.

[0057] In each new iteration, the content of the state register 2 of the memory can be updated and sent by the memory to the serial bus. In this example, the state register 2 of the memory is updated and sent at least in the consecutive iterations of phase 1, phase 2, phase 3, phase k-1, phase k, phase k+1, phase n-1 and phase.

[0058] In a write cycle using the SPI bus, as previously combined Figure 2 As described above, the reset timing of bit WEL can occur at any time between the start and end of the write operation.

[0059] According to a preferred implementation, a reset of the control bit WEL is provided so that the reset occurs at a selected moment. Figure 4 In the example of , bit WEL is intentionally reset between iteration phase 2 and iteration phase 3 (where bit WEL is set to state 0). Still according to this example, for all subsequent iteration phases 3 to phase n, the value of bit WEL remains equal to 0.

[0060] The intentional or deterministic control of the resetting of bit WEL during a write operation here makes it possible to encode data bit 4 (B) or a binary data value. For example, bit WEL can be chosen to be reset: either before a certain iteration, for example before iteration stage k, in order to encode the low state of bit B; or after the same iteration stage k, in order to encode the high state of bit B.

[0061] Thus, for example, a bit B can be transmitted to a processing unit connected to the memory, the value of which is encoded relative to the moment when the bit WEL is set to the state 0 during the write cycle. If the bit WEL is reset before a certain iteration, a certain moment or a certain duration, this amounts to encoding a first state of the bit B. Conversely, if the bit WEL is reset after the same iteration or the same moment or the same duration, this amounts to encoding a second state of the bit B.

[0062] According to one mode of implementation, this control of the resetting of the bit WEL during a write cycle is used to send a bit B representative of the wear condition of the memory. For example, intervention is performed at the selected moment to put the bit WEL in state 0 so as to encode the bit B, for which: a high state makes it possible to indicate that one or more error correction operations have been carried out in the memory, which can indicate that the memory is worn, while a low state reflects the fact that no error correction has been carried out in the memory, which can indicate that the memory is not worn.

[0063] According to another mode of realization, it is considered that the value taken by bit WEL in iteration phase k or at a moment corresponding to iteration phase k determines the state of bit B. In other words, iteration phase k constitutes a reference for encoding bit B. Thus, for example, it can be considered that: if bit WEL is equal to 1 at iteration phase k, bit B is equal to 1; and if bit WEL is equal to 0 at iteration phase k, bit B is equal to 0.

[0064] Still according to this example, according to the value of the bit B that we wish to send on each new write cycle in the memory, during the cycle under consideration, the control bit WEL is set to the state 0 at the moment. Assuming that we wish to encode the state 0 of the bit B during the write cycle, during the iteration before iteration phase k (for example, during iteration phase 2), the bit WEL is set to the state 0. Next, the bit WEL is kept in the state 0 until the end of the write cycle, so that the value of the bit WEL is equal to 0 at iteration phase k.

[0065] Assuming that it is then desired to encode the state 1 of bit B during another write cycle, during the iteration after iteration phase k (e.g. during iteration phase n-1), bit WEL is set to state 0. Thus, bit WEL will remain in state 1 at least until iteration phase k.

[0066] From one write cycle to another, it may be decided to deterministically reset bit WEL (set it to state 0) within a range of iterations before or after iteration k taken as reference. For example, it may be decided to always set bit WEL to state 0: in iteration phase 2, in order to encode the value 0 of bit B; and in iteration phase n-1, in order to encode the value 1 of bit B.

[0067] In a variant, the bit WEL may be randomly reset within a range of iterations before or after the iteration k taken as a reference. For example, the state 0 of the bit B may be encoded by resetting the bit WEL in an iteration randomly selected from the iterations before the iteration stage k; and the state 1 of the bit B may be encoded by resetting the bit WEL only in an iteration randomly selected from the iterations after the iteration stage k.

[0068] Figure 5 A further mode of realization of a method for encoding a data value to be transmitted via a serial bus is shown.

[0069] According to this implementation mode, consider including such as combining Figure 4 The write cycle of n iterations described. For the sake of simplicity, only bits 20 (WIP) and 21 (WEL) of the byte forming the state register 2 of the memory will be considered. In this example, it is considered that the values ​​of the other bits 22 to 27 do not undergo any evolution during the entire write cycle. Still in this example, it is assumed that at least in the continuous iteration phase 1, phase 2, phase 3, phase k-1, phase k, phase k+1, phase n-1 and phase n, the state register 2 of the memory is updated and sent via the SPI bus.

[0070] In a write cycle using, for example, an SPI serial bus, the value of bit WEL can be modified multiple times during a write. Figure 4 The principle described for encoding one bit is extended to encoding a plurality of bits forming a data value or word 5 (DATA). To this end, in each new iteration of the loop, the value taken by bit WEL of status register 2 is controlled to update and transmit status register 2 of the memory.

[0071] exist Figure 5 In the example of , for each iteration included between phase 2 and phase n-1, the value of the bit WEL is applied. This makes it possible to encode, for each new iteration, a bit of the data value DATA whose value is equal to the value of the bit WEL in the iteration considered. Thus, in Figure 5 In the example, the data value DATA forms a word that specifically includes the following items: bit 50, whose value is equal to the value of bit WEL in iteration stage 2; bit 51, whose value is equal to the value of bit WEL in iteration stage 3; bit 52, whose value is equal to the value of bit WEL in iteration stage k-1; bit 53, whose value is equal to the value of bit WEL in iteration stage k; bit 54, whose value is equal to the value of bit WEL in iteration stage k+1; and bit 55, whose value is equal to the value of bit WEL in iteration stage n-1.

[0072] Therefore, for a transmission cycle in which the state register 2 of the memory is updated and transmitted n times, a data value DATA including up to n-2 bits can theoretically be sent via the serial bus. For example, in the memory, for a write cycle with a cadence frequency of 10 MHz and a duration extending 1 ms, a data value DATA of about 1000 bits (1 kb) can be sent via the serial bus. This is equivalent to creating a new data transmission channel on the serial bus.

[0073] exist Figure 5 In the example of , bits 50 to 55 of the data value DATA are sent in the order from the least significant bit (bit 50) to the most significant bit (bit 55), which is not mandatory. It is indeed possible to provide for sending bits 50 to 55 of the data value DATA in another order (e.g., in an order resulting from a permutation).

[0074] exist Figure 5 In the example of , during the same write cycle in the memory, the status register 2 undergoes a number of modifications related to the number of state transitions between successively transmitted bits of word 5.

[0075] Combined with the above Figure 4 and 5 The different implementation modes and variants described can be implemented as follows: by means of a circuit, for example, circuit 1 ( Figure 1 ); and / or via a non-volatile memory, such as memory 13 ( Figure 1 ), whose status register 2 is configured to be modified as described.

[0076] Various embodiments, implementation modes and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments, implementation modes and variations may be combined, and other variations will be apparent to those skilled in the art. In particular, the following may be repeated during consecutive write cycles: Figure 4 The encoding of bit B described above is performed in order to encode a plurality of bits B that together form one or more data values. Similarly, the encoding of bit B can be repeated during consecutive write cycles as in combination with Figure 5 An encoding of a data value DATA is described, for example in order to encode a plurality of data values ​​DATA which after recombining (for example after concatenation) form another data value which is not transferable within a single write cycle in the memory.

[0077] Finally, the practical implementation of the described embodiments, implementation modes and variants is within the capabilities of a person skilled in the art, given the functional indications provided above. In particular, the bit B and the data value DATA may represent any type of information or information portion, for example, information representing the wear of the memory or the number of error corrections performed within a determined duration.

Claims

1. A method for encoding a data value to be transmitted on an SPI serial bus, comprising: The status register of the memory is modified multiple times at selected times during a write cycle in the memory, depending on all or part of the data value to be transferred.

2. The method of claim 1, wherein the memory is a reprogrammable non-volatile memory. 3 . The method of claim 1 , wherein modifying the status register comprises performing a state inversion of a latch bit of the memory. The method of claim 1 , wherein the data value to be transmitted comprises a word having at least two bits. 5 . The method according to claim 4 , wherein the number of modifications of the state register performed during the write cycle in the memory is related to the number of state transitions between successively transmitted bits of the word. The method of claim 1 , wherein the data value to be transmitted represents a wear condition of the memory.

7. The method of claim 1, wherein the data value to be transmitted reflects a number of error corrections performed within the memory.

8. The method according to claim 1, comprising the steps of: Starting writing in said memory; periodically sending the content of the status register of the memory; modifying the status register of the memory at each selected moment to encode all or part of the data value to be transmitted; as well as Stop writing to the memory.

9. An electronic circuit comprising: SPI serial bus; A memory having a status register; as well as Circuitry is configured to encode a data value to be transmitted on the SPI serial bus by modifying the status register of the memory multiple times at multiple selected moments during a write cycle in the memory according to all or part of the data value to be transmitted on the SPI serial bus.

10. The electronic circuit of claim 9, wherein the memory is a reprogrammable non-volatile memory.

11. The electronic circuit of claim 9, wherein the circuit modifies the status register by performing a state inversion of a latched bit of the memory.

12. The electronic circuit of claim 9, wherein the data value to be transmitted comprises a word having at least two bits.

13. Electronic circuit according to claim 12, wherein the number of modifications of the state register performed during the write cycle in the memory is related to the number of state transitions between successively transmitted bits of the word.

14. The electronic circuit of claim 9, wherein the data value to be transmitted represents a wear condition of the memory.

15. The electronic circuit of claim 9, wherein the data value to be transmitted reflects a number of error corrections performed within the memory.

16. The electronic circuit of claim 9, wherein the circuit is configured to: Starting writing in said memory; periodically sending the content of the status register of the memory; modifying the status register of the memory at each selected moment to encode all or part of the data value to be transmitted; as well as Stop writing to the memory.

17. A memory circuit comprising: Non-volatile memory; as well as Status register; as well as Circuitry is configured to encode a data value by modifying a state register of the non-volatile memory multiple times according to all or part of the data value at multiple selected times during a write cycle in the memory.

18. The memory circuit of claim 17, wherein the circuit modifies the status register by performing a state inversion of a latched bit of the non-volatile memory.

19. The memory circuit of claim 17, wherein the data value comprises a word having at least two bits.

20. The memory circuit of claim 19, wherein the number of modifications of the state register performed during the write cycle in the non-volatile memory is related to the number of state transitions between successively transmitted bits of the word.

21. The memory circuit of claim 17, wherein the data value represents a wear condition of the non-volatile memory.

22. The memory circuit of claim 17, wherein the data value reflects a number of error corrections performed within the nonvolatile memory.

23. The memory circuit of claim 17, wherein the circuit is configured to: Starting writing in the non-volatile memory; periodically sending the content of the status register of the non-volatile memory; modifying the state register of the non-volatile memory at each selected time to encode all or part of the data value; as well as Writing in the non-volatile memory is stopped.

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