Component carrier and method for producing a component carrier
By embedding terminals made of a first conductive material into the stack of the component carrier and forming an interface structure and a conductive structure made of a second conductive material (such as copper) in the exposed portion of the terminal, the problem of difficulty in integrating the use of metallized components other than copper in the prior art is solved, and interconnection of any metal terminal is achieved, reducing costs and increasing flexibility.
Patent Information
- Application Number
- CN202010274104.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2019-04-10
- Filing Date
- 2020-04-09
- Publication Date
- 2025-05-13
- Estimated Expiration
- 2040-04-09
AI Technical Summary
Existing component carriers are difficult to effectively integrate metallized components other than copper, especially those of gold materials, because gold materials cannot be interconnected by wet copper processes.
The interconnection of any metal terminals is achieved by embedding terminals made of a first conductive material in the stack of the component carrier and forming an interface structure and a conductive structure at the exposed portion of the terminal, and depositing the conductive structure using a second conductive material (such as copper).
This method allows interconnecting any metal terminals with copper, reducing the cost of component manufacturing, increasing component flexibility, and reducing restrictions on manufacturers and customers.
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Figure CN111816637B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a component carrier and to a method for producing a component carrier. Background Art
[0002] Conventional component carriers include a stack with at least one conductive layer structure and / or at least one electrically insulating layer structure, wherein components are embedded in the stack. The components include terminals. The component carrier has a recess in the stack, which exposes the terminals. The material of the terminals is usually copper, so that the terminals can be interconnected by a so-called wet (electroplating) copper process. In the case of embedding components in a component carrier, copper is the preferred material for the terminals of the components.
[0003] However, semiconductor components are sometimes manufactured with terminal metallizations other than copper. Typically, the preferred surface metal is gold, which does not oxidize, is very resistant, and exhibits good wire bonding properties. Gold cannot be interconnected by wet (electroplated) copper processes. This fact significantly reduces the number of options for embedding such components directly in a component carrier. Summary of the invention
[0004] The object of the present invention is to provide a component carrier and a method for producing a component carrier, by which the integration of any components can be facilitated. To achieve the above defined objects, a component carrier and a method for producing a component carrier according to the present invention are provided.
[0005] According to an exemplary embodiment of the present invention, a component carrier is provided. The component carrier includes: a stacked part having at least one conductive layer structure and / or at least one electrically insulating layer structure; a component including a terminal made of a first conductive material and embedded in the stacked part; a recess located in the stacked part, the recess exposing at least a portion of the terminal; an interface structure located on the at least partially exposed terminal; and a conductive structure located on the interface structure made of a second conductive material.
[0006] According to another exemplary embodiment of the present invention, a method for manufacturing a component carrier is provided. The method includes: forming a stack including at least one conductive layer structure and / or at least one electrically insulating layer structure; embedding a component including a terminal made of a first conductive material into the stack; forming a recess in the stack to expose at least a portion of the terminal; forming an interface structure on the at least partially exposed terminal; and forming a conductive structure on the interface structure made of a second conductive material.
[0007] Detailed Description of Example Implementations
[0008] To deposit the interface structures and the conductive structures, metal deposition and sputtering processes (thin film deposition) can be used, such as HiPMS, plasma, PECVD, CVD, laser ablation, chemical deposition, etc. Thus, the surface of any terminal of the embedded component can be prepared for subsequent (e.g., electroplating) copper deposition. That is, any metal terminal other than copper can be contacted with conventional electroplated copper.
[0009] Since any terminals of a component can be interconnected, the cost of manufacturing the component can be reduced. A metallization process can also be included within the framework of the invention, so that the metallization process does not have to be done by the component manufacturer.
[0010] Due to the conductive structure on the interface structure, a copper seed layer such as copper foil is not required.
[0011] Through the present invention, the flexibility of embedding components is increased and the restrictions on component manufacturers and customers are reduced.
[0012] Hereinafter, other exemplary embodiments of the present invention will be explained.
[0013] In one embodiment, the second conductive material is different from the first material.
[0014] In one embodiment, the first conductive material is selected from aluminum, silver, titanium, copper, gold, Si, SiC, SiO2 and GaN. Therefore, the first conductive material can also be a semiconductor material.
[0015] In one embodiment, the second conductive material is copper.
[0016] In one embodiment, the interface structure comprises an adhesion promoter or the interface structure is an adhesion promoter, in particular, the adhesion promoter is one of titanium, copper nitride, tungsten, chromium and nickel. The adhesion promoter may have a thickness in the range between 20 nm and 100 nm.
[0017] In one embodiment, the interface structure comprises or is a diffusion barrier layer, in particular, the diffusion barrier layer is nickel. The diffusion barrier layer may have a thickness in the range between 150 nm and 500 nm.
[0018] In one embodiment, the component carrier comprises at least one of the following features: the component carrier comprises at least one component which is surface mounted and / or embedded in the component carrier, wherein the at least one component is in particular selected from: electronic components, non-conductive inlays and / or conductive inlays, heat transfer units, photoconductive elements, energy harvesting units, active electronic components, passive electronic components, electronic chips, storage devices, filters, integrated circuits, signal processing components, power management components, optoelectronic interface elements, voltage converters, cryptographic components, transmitters and / or receivers, electromechanical transducers, actuators, micro-electromechanical systems, microprocessors, capacitors, resistors, inductors, accumulators, switches, cameras, antennas, magnetic elements, further component carriers and logic chips; wherein the component carrier At least one of the conductive layer structures comprises at least one of copper, aluminum, nickel, silver, gold, palladium and tungsten, any of the mentioned materials being optionally coated with a superconducting material such as graphene; wherein the electrically insulating layer structure comprises at least one of the following: a resin, in particular a reinforced resin or a non-reinforced resin, such as an epoxy resin or a bismaleimide-triazine resin; FR-4; FR-5; cyanate ester; a polyphenylene derivative; glass; a prepreg; polyimide; polyamide; a liquid crystal polymer; an epoxy-based laminate film; polytetrafluoroethylene; ceramics and metal oxides; wherein the component carrier is formed as a plate; wherein the component carrier is constructed as one of a printed circuit board, a substrate and an interposer; wherein the component carrier is constructed as a laminated component carrier.
[0019] In an embodiment according to the method, the second electrically conductive material is different from the first electrically conductive material.
[0020] In an embodiment of the method, the first conductive material is selected from the group consisting of aluminum, silver, titanium, copper, gold, Si, SiC, SiO2 and GaN.
[0021] In an embodiment of the method, the second conductive material is copper.
[0022] In one embodiment of the method, the interface structure comprises an adhesion promoter or is an adhesion promoter, in particular, the adhesion promoter is one of titanium, copper nitride, tungsten, chromium and nickel. The adhesion promoter may have a thickness in the range between 20 nm and 100 nm.
[0023] In one embodiment of the method, the interface structure comprises or is a diffusion barrier layer, in particular the diffusion barrier layer is nickel. The diffusion barrier layer may have a thickness in the range between 150 nm and 500 nm.
[0024] In one embodiment of the method, forming the interface structure and the conductive structure is performed simultaneously with forming the interface structure and the conductive structure in a through hole of the stack. The through hole may be a via.
[0025] In an embodiment of the method, additional masking and photolithography steps may be performed before depositing the interface structure to pattern or structure the interface structure. For example, a very thin film may be used as a mask, and in combination with a sputtering process or a similar process, a copper structure with very small line spacing may be obtained. A stripping step may be performed after depositing the interface structure, in which the mask is stripped. Thereafter, a conductive structure may be deposited on the interface structure.
[0026] In an embodiment of the method, at least one of the interface structure and the conductive structure may be deposited by a deposition process such as thin film deposition, HiPMS (high power pulsed magnetron sputtering), CVD, PECVD, laser ablation or chemical deposition, or a sputtering process.
[0027] In the context of the present application, the term "component carrier" may particularly denote any supporting structure on which and / or in which one or more components can be accommodated to provide mechanical support and / or electrical connection. In other words, the component carrier may be configured as a mechanical carrier and / or an electronic carrier for the components. In particular, the component carrier may be one of a printed circuit board, an organic interposer and an IC (integrated circuit) substrate. The component carrier may also be a hybrid board combining different component carriers of the above-mentioned types of component carriers.
[0028] In one embodiment, the component carrier comprises a stack of at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier may be a laminate of the mentioned (one or more) electrically insulating layer structures and (one or more) electrically conductive layer structures, formed in particular by applying mechanical pressure and / or heat. The mentioned stack may provide a plate-like component carrier that is able to provide a large mounting surface for other components and yet is very thin and compact. The term "layer structure" may in particular denote a continuous layer, a patterned layer or a plurality of non-continuous islands in a common plane.
[0029] In one embodiment, the component carrier is formed as a plate. This facilitates a compact design, wherein the component carrier still provides a large base for mounting components thereon. Furthermore, in particular, bare dies as an example of embedded electronic components can be conveniently embedded in thin boards such as printed circuit boards due to their small thickness.
[0030] In one embodiment, the component carrier is configured as one of a printed circuit board, a substrate (in particular an IC substrate) and an interposer.
[0031] In the context of the present application, the term "printed circuit board" (PCB) may particularly denote a plate-like component carrier formed by combining several conductive layer structures with several electrically insulating layer structures, for example, by applying pressure and / or by supplying thermal energy. As a preferred material for PCB technology, the conductive layer structure is made of copper, while the electrically insulating layer structure may contain resin and / or glass fiber, so-called prepreg or FR4 material. The various conductive layer structures may be connected to each other in a desired manner by the following process: for example, through holes are formed through the laminate by laser drilling or mechanical drilling, and the through holes are filled with conductive material (particularly copper), thereby forming a via as a through-hole connection. In addition to being embedded in one or more components in the printed circuit board, the printed circuit board is generally configured to accommodate one or more components on one or two opposite surfaces of the plate-like printed circuit board. They may be connected to the corresponding main surface by welding. The dielectric part of the PCB may be composed of a resin with reinforcing fibers (such as glass fibers).
[0032] In the context of the present application, the term "substrate" may specifically refer to a small component carrier having substantially the same size as the components (especially electronic components) to be mounted thereon. More specifically, a substrate may be understood as a carrier for electrical connections or electrical networks and a component carrier comparable to a printed circuit board (PCB), but the substrate has a relatively high density of lateral and / or vertically arranged connections. The lateral connections are, for example, conductive paths, while the vertical connections may be, for example, drill holes. These lateral and / or vertical connections are arranged in the substrate and may be used to provide electrical and / or mechanical connections between accommodated components (especially IC chips) or unaccommodated components (such as bare dies) and a printed circuit board or an intermediate printed circuit board. Therefore, the term "substrate" may also include an "IC substrate". The dielectric portion of the substrate may be composed of a resin having reinforcing particles (such as reinforcing balls, especially glass balls).
[0033] The substrate or interposer may include: at least one layer of glass, silicon (Si) or a photoimageable organic material or a dry-etched organic material; or the substrate or interposer may be composed of at least one layer of glass, silicon (Si) or a photoimageable organic material or a dry-etched organic material, wherein the organic material is, for example, an epoxy-based laminated material (e.g., an epoxy-based laminated film) or a polymer composite such as polyimide, polybenzoxazole or benzocyclobutene.
[0034] In one embodiment, the at least one electrically insulating layer structure comprises at least one of the following: a resin (such as a reinforced resin or a non-reinforced resin, for example an epoxy resin or a bismaleimide-triazine resin), a cyanate resin, a polyphenylene derivative, a glass (particularly glass fiber, multilayer glass, a glass-like material), a prepreg (such as FR-4 or FR-5), a polyimide, a polyamide, a liquid crystal polymer (LCP), an epoxy-based laminated film, polytetrafluoroethylene (Teflon), a ceramic and a metal oxide. Reinforcement materials such as meshes, fibers or balls made of glass (multilayer glass) may also be used. Although prepregs, especially FR-4, are generally preferred for rigid PCBs, other materials, especially epoxy-based laminated films, may also be used for the substrate. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymers and / or cyanate resins, low-temperature co-fired ceramics (LTCC) or other low DK materials, lower DK materials, ultra-low DK materials may be applied in the component carrier as an electrically insulating layer structure.
[0035] In one embodiment, the at least one conductive layer structure may include at least one of copper, aluminum, nickel, silver, gold, palladium and tungsten. Although copper is generally preferred, other materials or their coating forms are also possible, in particular coated with superconducting materials such as graphene.
[0036] The at least one component may be selected from: a non-conductive inlay, a conductive inlay (such as a metal inlay, preferably comprising copper or aluminum), a heat transfer unit (such as a heat pipe), a photoconductive element (such as an optical waveguide or a photoconductor connector), an electronic component, or a combination thereof. For example, the component may be an active electronic component, a passive electronic component, an electronic chip, a storage device (such as a DRAM or other data storage), a filter, an integrated circuit, a signal processing component, a power management component, an optoelectronic interface element, a light emitting diode, an optocoupler, a voltage converter (such as a DC / DC converter or an AC / DC converter), a cryptographic component, a transmitter and / or a receiver, an electromechanical transducer, a sensor, an actuator, a microelectromechanical system (MEMS), a microprocessor, a capacitor, a resistor, an inductor, an accumulator, a switch, a camera, an antenna, a logic chip, and an energy harvesting unit. However, other components may be embedded in the component carrier. For example, a magnetic element may be used as a component. Such a magnetic element may be a permanent magnetic element (such as a ferromagnetic element, an antiferromagnetic element, a multiferroic element or a ferrimagnetic element, such as a ferrite core), or such a magnetic element may be a paramagnetic element. However, the component may also be a substrate, an interposer or another component carrier, for example in a board-in-board configuration. The component may be surface mounted on the component carrier and / or may be embedded inside the component carrier. Furthermore, other components may also be used as components, in particular those which generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment.
[0037] In one embodiment, the component carrier is a laminated component carrier. In such an embodiment, the component carrier is an assembly of multilayer structures that are stacked and connected together by applying pressure and / or heat.
[0038] The aspects defined above and further aspects of the invention will become apparent from the examples of embodiment to be described hereinafter and will be explained with reference to these examples of embodiment. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Figure 1 A cross-sectional view of a component carrier according to an exemplary embodiment of the invention is shown.
[0040] Figure 2 A method for producing a component carrier according to an exemplary embodiment of the invention is shown.
[0041] Figure 3 A method for producing a component carrier according to an exemplary embodiment of the invention is shown.
[0042] Figure 4 A method for producing a component carrier according to an exemplary embodiment of the invention is shown. DETAILED DESCRIPTION
[0043] The illustrations in the drawings are schematic. In different drawings, similar or identical elements are provided with the same reference numerals.
[0044] Figure 1 A cross-sectional view of a component carrier 1 according to an exemplary embodiment of the present invention is shown. The component carrier 1 is shaped as a plate. The component carrier 1 may be configured as one of a printed circuit board, a substrate and an interposer. The component carrier 1 may be configured as a laminated component carrier.
[0045] The component carrier 1 comprises a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure 2 .
[0046] The at least one electrically conductive layer structure of the component carrier 1 may comprise at least one of copper, aluminum, nickel, silver, gold, palladium and tungsten, any of the mentioned materials optionally being coated with a superconducting material such as graphene.
[0047] The electrically insulating layer structure 2 may include at least one of the following: a resin, in particular a reinforced resin or a non-reinforced resin, such as an epoxy resin or a bismaleimide-triazine resin; FR-4; FR-5; cyanate ester; polyphenylene derivatives; glass; prepreg; polyimide; polyamide; liquid crystal polymer; epoxy-based laminate film; polytetrafluoroethylene; ceramics and metal oxides.
[0048] Component 4 is embedded in the stack. Component 4 may be selected from: electronic components, non-conductive inlays and / or conductive inlays, heat transfer units, photoconductive elements, energy harvesting units, active electronic components, passive electronic components, electronic chips, storage devices, filters, integrated circuits, signal processing components, power management components, optoelectronic interface components, voltage converters, cryptographic components, transmitters and / or receivers, electromechanical transducers, actuators, micro-electromechanical systems, microprocessors, capacitors, resistors, inductors, accumulators, switches, cameras, antennas, magnetic elements, further component carriers and logic chips.
[0049] The component 4 comprises a terminal 5 made of a first electrically conductive material. The first electrically conductive material of the terminal 5 need not necessarily be copper.
[0050] A recess 6 is provided in the stack so that at least a portion of the terminal 5 is exposed. Note that the recess 6 may optionally expose not only a portion of the terminal 5 but also the terminal 5 completely. This is done to avoid possible weak adhesion between the terminal 5 and the surface of the electrically insulating layer structure 2. The adhesion between the terminal 5 and the electrically insulating layer structure 2 will only be based on the choice of material. This problem is basically applicable to all embodiments. An interface structure 7 is provided on the exposed terminal 5, and a conductive structure 8 made of a second conductive material is provided on the interface structure 7.
[0051] The second conductive material is different from the first conductive material. In particular, the first conductive material can be selected from aluminum, silver, titanium, copper, gold, Si, SiC, SiO2 and GaN, and the second conductive material can be copper.
[0052] The interface structure 7 may contain or may be an adhesion promoter, in particular, the adhesion promoter is one of titanium, copper nitride, tungsten, chromium and nickel. The adhesion promoter has a thickness in the range between 20 nm and 100 nm.
[0053] Additionally or alternatively, the interface structure 7 may comprise or may be a diffusion barrier layer, in particular, the diffusion barrier layer is nickel. The diffusion barrier layer has a thickness in the range between 150 nm and 500 nm.
[0054] Figure 2 A method for producing a component carrier 1 according to an exemplary embodiment of the invention is shown.
[0055] In step S1, a preform of a component carrier 1 is provided. The component carrier 1 is implemented as a PCB, which includes a stack having at least one electrically insulating layer structure 2 and optionally at least one conductive layer structure. The component carrier 1 also includes a component 4, which includes a terminal 5 made of a first conductive material. And the component 4 is embedded in the stack. The first conductive material of the terminal 5 does not have to be copper. In particular, the first conductive material can be selected from aluminum, silver, titanium, copper, gold, Si, SiC, SiO2 and GaN. The component carrier 1 also includes a recess 6 located in the stack, which exposes at least a portion of the terminal 5.
[0056] The recess 6 may be a laser drilled hole which serves as a connection between the outer surface of the component carrier 1 and the component 4. Once the laser hole 6 has been formed, the component carrier 1 may optionally be cleaned, for example in a chemical bath, thereby cleaning the laser hole 6 and the outer surface of the component carrier 1.
[0057] In step S2, an interface structure 7 is deposited on the exposed terminal 5. The interface structure 7 can be deposited by a metal deposition process or a sputtering process such as thin film deposition, HiPMS (high power pulsed magnetron sputtering), CVD, PECVD, laser ablation, chemical plating, etc. . Thus, the surface of the terminal 5 that is not made of copper is prepared for subsequent copper deposition. The interface structure 7 forms an adhesion promoter so that the copper material can be bonded to the terminal 5 of the component 4. The adhesion promoter can be selected from titanium, copper nitride, aluminum nitride (AIN), tungsten and chromium. More generally, other oxides, nitrides, metal alloys or metals can be used for the interface structure 7. The adhesion promoter can have a thickness in the range between 20nm and 100nm. The interface structure 7 can be deposited not only on the interface structure 7 of the terminal 5 of the component 4, but also on the outer surface of the component carrier 1.
[0058] Alternatively or in addition to the adhesion promoter, the interface structure 7 may form a diffusion barrier, in particular if nickel is used in the interface structure 7. The diffusion barrier may have a thickness in the range between 150 nm and 500 nm. The diffusion barrier may also be deposited by a deposition process such as thin film deposition, HiPMS (high power pulsed magnetron sputtering), CVD, PECVD, laser ablation, chemical deposition or a sputtering process.
[0059] Thus, the interface structure 7 may include an adhesion promoter, a diffusion barrier, or both an adhesion promoter and a diffusion barrier.
[0060] In step S3, a conductive structure 8 made of a second conductive material is deposited on the interface structure 7 and optionally also on the outer surface of the component carrier 1. The conductive structure 8 can be a copper film (Cu). The conductive structure 8 can also be deposited by a deposition process or sputtering process such as thin film deposition, HiPMS (high power pulsed magnetron sputtering), CVD, PECVD, laser ablation, chemical deposition, etc.
[0061] After step S3, the component carrier 1 can be processed by conventional PCB manufacturing steps. For example, a further copper layer can be applied on the conductive structure 8 by electroplating or electroless deposition. The copper layer can then be patterned conventionally by photolithography and etching processes. The recess 6 can also be (completely) filled with copper.
[0062] Figure 3 A method for manufacturing a component carrier 1 according to an exemplary embodiment of the invention is shown. In addition to the following differences, Figure 3 Methods and Figure 2 The method is similar to that of . The first conductive material of the terminal 5 is gold (Au). The interface structure 7 may include nickel (Ni) or titanium or a combination of nickel (Ni) and titanium as an adhesion promoter between the terminal 5 and the superimposed conductive structure 8 made of copper. In this case, a conventional acid combination can be used to construct the nickel layer as an adhesion promoter.
[0063] Figure 2 and Figure 3 The method can be modified by additional masking and photolithography steps implemented before step S2. Additional masking and photolithography steps are implemented so that the interface structure 7 is patterned or structured. The mask can be formed by a photoresist or a dry film. Very thin films can be used as masks, and in combination with a sputtering process, copper structures with very small line spacing can be obtained. A stripping step can be performed after step S2, in which the mask is stripped. Thereafter, step S3 can be implemented.
[0064] A stripping step may also be performed after step S3.
[0065] Figure 4A method for manufacturing a component carrier 1 according to an exemplary embodiment of the present invention is shown. In this embodiment, the terminals 5 of the embedded component 4 do not have an electrical contact surface metallization. This means that the embedded component 4 can initially be provided with bare Si, SiC, SiO2 or GaN material as exposed terminals 5. In other words, the contact surface area of the terminal 5 can directly expose the component material of the embedded component 4, in particular Si, SiC, SiO2 or GaN. This can reduce production costs because several steps of manufacturing the component 4, such as metallization, photolithography, cleaning, etc., can be omitted. The basic concept is to contact metallize the terminals 5 of the component 4 when the component 4 is already embedded in the electrically insulating layer structure 2. The laser process can be calibrated to stop drilling holes on the component surface (for example, on the doped Si or SiO2 surface). After this, the terminals 5 of the component 4 can be regularly metallized, for example by titanium and / or copper. After this, similar to the previous embodiment, the metallization process of the component carrier 1 will continue.
[0066] In step S10, a recess 6 is formed in the electrically insulating layer structure 2 by laser drilling. In this case, the upper surface of the component carrier 1 can be used as a stop layer for laser processing. An oxide layer can be formed on the component carrier 1 to protect the component carrier 1 (for example, if the component carrier 1 is made of silicon (Si), the oxide layer is a SiO2 layer). Masking and photolithography steps are performed so that the interface structure 7 is patterned or structured.
[0067] Steps S11 and S13 correspond to Figure 2 and 3 Steps S2 and S3 in .
[0068] In step S12 , a stripping process is performed in which the mask is stripped.
[0069] Can be modified by via filling step Figures 2 to 4 A method is provided in which vias (not shown) in the stack of component carriers 1 are filled in step S2 / S11 and / or step S3 / S13. The parameters of the via filling step are essentially the aspect ratio and the sputtering rate. For example, an additional layer of gold (Au) or silver (Ag) can be applied in the via filling step. Instead of copper as the second conductive material, gold, silver or any other metal can be used as the second conductive material. The process can also be extended to the entire surface of the component carrier 1.
[0070] exist Figures 2 to 4 In the method, the component 4 can be embedded at the panel level, wafer level or PCB level. Both central core embedding and asymmetric embedding are possible.
[0071] Furthermore, metallization by sputtering of the interface structures 7 and the conductive structures 8 will allow biocompatible metals, such as titanium (Ti) and gold (Au), to be implemented on the component carrier 1 at any stage.
[0072] It should be noted that the term "comprising" does not exclude other elements or steps and "a" or "an" does not exclude a plurality. Furthermore, elements described in association with different embodiments may be combined.
[0073] It should also be noted that reference signs in the claims should not be construed as limiting the scope of the claims.
[0074] The implementation of the invention is not limited to the preferred embodiments shown in the drawings and described above. On the contrary, the solutions shown and numerous variants of the principle according to the invention can be used, even in the case of fundamentally different embodiments.
Claims
1. A component carrier (1), the component carrier (1) being configured as one of an integrated circuit substrate, a printed circuit board and an interposer, the integrated circuit substrate being in the form of a carrier for electrical connections or electrical networks and having high-density lateral and / or vertically arranged connections, wherein: The component carrier (1) comprises: A stack comprising at least one electrically conductive layer structure and / or at least one electrically insulating layer structure (2); a component (4), the component (4) comprising a terminal (5) made of a first conductive material and the component being embedded in the stack; a notch (6) in the stack, the notch (6) exposing at least a portion of the terminal (5); an interface structure (7), the interface structure (7) being located on the surface of the terminal (5) which is at least partially exposed, wherein the interface structure (7) at least partially covers the sidewalls of the recess (6), and the interface structure (7) being deposited on the outer surface of the component carrier (1); a conductive structure (8), the conductive structure (8) being located on the surface of the interface structure (7) and being made of a second conductive material, wherein the second conductive material is different from the first conductive material, the conductive structure (8) at least covering the interface structure (7) located on the surface of the at least partially exposed terminal (5), Characterized in that the first conductive material is selected from aluminum, silver, titanium, gold, Si, SiC, SiO2 and GaN; The second conductive material is copper.
2. The component carrier (1) according to claim 1, wherein: The interface structure (7) contains an adhesion promoter, or the interface structure (7) is an adhesion promoter.
3. The component carrier (1) according to claim 2, wherein: The adhesion promoter is one of titanium, copper nitride, tungsten, chromium, and nickel.
4. The component carrier (1) according to claim 2, wherein: The adhesion promoter has a thickness in the range between 20 nm and 100 nm.
5. The component carrier (1) according to claim 1 or 2, wherein: The interface structure (7) comprises a diffusion barrier layer, or the interface structure (7) is a diffusion barrier layer.
6. The component carrier (1) according to claim 5, wherein: The diffusion barrier layer is nickel.
7. The component carrier (1) according to claim 5, wherein: The diffusion barrier layer has a thickness in a range between 150 nm and 500 nm.
8. The component carrier (1) according to claim 1 or 2, comprising at least one of the following features: The components are selected from: heat transfer units, transmitters and / or receivers, and further component carriers; wherein at least one of the electrically conductive layer structures of the component carrier (1) comprises at least one of copper, aluminum, nickel, silver, gold, palladium and tungsten; wherein the electrical insulating layer structure (2) comprises at least one of the following: resin; FR-4; FR-5; glass; prepreg; ceramic and metal oxide; in, The component carrier (1) is designed as a laminated component carrier.
9. The component carrier (1) according to claim 1 or 2, wherein: The component is an electronic component.
10. The component carrier (1) according to claim 1 or 2, wherein: The components are non-conductive inlays and / or conductive inlays.
11. The component carrier (1) according to claim 1 or 2, wherein: The component is a light guiding element.
12. The component carrier (1) according to claim 1 or 2, wherein: The component is an energy harvesting unit, a signal processing component or an electromechanical transducer.
13. The component carrier (1) according to claim 1 or 2, wherein: The components are active electronic components or passive electronic components.
14. The component carrier (1) according to claim 1 or 2, wherein: The component is an electronic chip.
15. The component carrier (1) according to claim 1 or 2, wherein: The component is a storage device, a power management component, a cryptographic component or a magnetic element.
16. The component carrier (1) according to claim 1 or 2, wherein: The component is a filter, an optoelectronic interface element, a voltage converter, an actuator, a switch, a camera or an antenna.
17. The component carrier (1) according to claim 1 or 2, wherein: The component is an integrated circuit.
18. The component carrier (1) according to claim 1 or 2, wherein: The component is a micro-electromechanical system.
19. The component carrier (1) according to claim 1 or 2, wherein: The component is a microprocessor.
20. The component carrier (1) according to claim 1 or 2, wherein: The component is a capacitor, a resistor, an inductor or an accumulator.
21. The component carrier (1) according to claim 1 or 2, wherein: The component is a logic chip.
22. The component carrier (1) according to claim 8, wherein: Any one of the copper, aluminum, nickel, silver, gold, palladium and tungsten is coated with a superconducting material.
23. The component carrier (1) according to claim 22, wherein: The superconducting material is graphene.
24. The component carrier (1) according to claim 8, wherein: The resin may be a reinforced or unreinforced resin.
25. The component carrier (1) according to claim 8, wherein: The resin is an epoxy resin or a bismaleimide-triazine resin.
26. A method for manufacturing a component carrier (1), the component carrier (1) being configured as one of an integrated circuit substrate, a printed circuit board and an interposer, the integrated circuit substrate being in the form of a carrier for electrical connections or electrical networks and having a high density of laterally and / or vertically arranged connections, wherein: The method comprises: forming a stack comprising at least one electrically conductive layer structure and / or at least one electrically insulating layer structure (2); embedding a component (4) comprising a terminal (5) made of a first conductive material into the stack; forming a notch (6) in the stacked member so as to expose at least a portion of the terminal (5); forming an interface structure (7) on the at least partially exposed surface of the terminal (5), wherein the interface structure (7) at least partially covers the sidewalls of the recess (6), and the interface structure (7) is deposited on the outer surface of the component carrier (1); forming a conductive structure (8) made of a second conductive material on the surface of the interface structure (7), wherein the conductive structure (8) at least covers the interface structure (7) located on the surface of the at least partially exposed terminal (5); wherein the second conductive material is different from the first conductive material, Characterized in that the first conductive material is selected from aluminum, silver, titanium, gold, Si, SiC, SiO2 and GaN; The second conductive material is copper.
27. The method according to claim 26, wherein: The interface structure (7) contains an adhesion promoter, or the interface structure (7) is an adhesion promoter.
28. The method according to claim 27, wherein: The adhesion promoter is one of titanium, copper nitride, tungsten, chromium, and nickel.
29. The method according to claim 26, wherein: The interface structure (7) comprises a diffusion barrier layer, or the interface structure (7) is a diffusion barrier layer.
30. The method of claim 29, wherein: The diffusion barrier layer is nickel.
31. The method of claim 26, wherein: The formation of the interface structure (7) and the conductive structure (8) is carried out simultaneously with the formation of the interface structure and the conductive structure in the through hole of the stack.
32. The method of claim 26, wherein: At least one of the interface structure (7) and the conductive structure (8) is deposited by thin film deposition.
33. The method of claim 32, wherein: The thin film deposition is high power pulsed magnetron sputtering or chemical deposition.
34. The method of claim 26, wherein: At least one of the interface structure (7) and the conductive structure (8) is deposited by PECVD.
35. The method of claim 26, wherein: At least one of the interface structure (7) and the conductive structure (8) is deposited by a deposition process.
36. The method of claim 35, wherein: The deposition process is a sputtering process.
Citation Information
Patent Citations
Multilayer printed circuit board
CN101098588A
Semiconductor Packages and Methods of Fabricating the Same
US20130267066A1